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Robofish 2026-02-04 02:48:44 +08:00
parent f0b9fdb003
commit 00451057cf
14 changed files with 899 additions and 556 deletions
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50
.mxproject
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File diff suppressed because one or more lines are too long

4
CMakeLists.txt
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@ -56,19 +56,19 @@ target_sources(${CMAKE_PROJECT_NAME} PRIVATE
User/bsp/uart.c User/bsp/uart.c
# User/component sources # User/component sources
User/component/QuaternionEKF.c
User/component/ahrs.c User/component/ahrs.c
User/component/crc16.c User/component/crc16.c
User/component/crc8.c User/component/crc8.c
User/component/error_detect.c User/component/error_detect.c
User/component/filter.c User/component/filter.c
User/component/freertos_cli.c User/component/freertos_cli.c
User/component/kalman_filter.c
User/component/limiter.c User/component/limiter.c
User/component/lqr.c User/component/lqr.c
User/component/kalman_filter.c
User/component/pid.c User/component/pid.c
User/component/user_math.c User/component/user_math.c
User/component/vmc.c User/component/vmc.c
User/component/QuaternionEKF.c
# User/device sources # User/device sources
User/device/bmi088.c User/device/bmi088.c

12
Core/Inc/FreeRTOSConfig.h
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@ -51,6 +51,10 @@
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) #if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
#include <stdint.h> #include <stdint.h>
extern uint32_t SystemCoreClock; extern uint32_t SystemCoreClock;
/* USER CODE BEGIN 0 */
extern void configureTimerForRunTimeStats(void);
extern unsigned long getRunTimeCounterValue(void);
/* USER CODE END 0 */
#endif #endif
#ifndef CMSIS_device_header #ifndef CMSIS_device_header
#define CMSIS_device_header "stm32h7xx.h" #define CMSIS_device_header "stm32h7xx.h"
@ -70,7 +74,9 @@
#define configMINIMAL_STACK_SIZE ((uint16_t)128) #define configMINIMAL_STACK_SIZE ((uint16_t)128)
#define configTOTAL_HEAP_SIZE ((size_t)0x10000) #define configTOTAL_HEAP_SIZE ((size_t)0x10000)
#define configMAX_TASK_NAME_LEN ( 16 ) #define configMAX_TASK_NAME_LEN ( 16 )
#define configGENERATE_RUN_TIME_STATS 1
#define configUSE_TRACE_FACILITY 1 #define configUSE_TRACE_FACILITY 1
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
#define configUSE_16_BIT_TICKS 0 #define configUSE_16_BIT_TICKS 0
#define configUSE_MUTEXES 1 #define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8 #define configQUEUE_REGISTRY_SIZE 8
@ -163,6 +169,12 @@ standard names. */
#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0 #define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0
/* USER CODE BEGIN 2 */
/* Definitions needed when configGENERATE_RUN_TIME_STATS is on */
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS configureTimerForRunTimeStats
#define portGET_RUN_TIME_COUNTER_VALUE getRunTimeCounterValue
/* USER CODE END 2 */
/* USER CODE BEGIN Defines */ /* USER CODE BEGIN Defines */
/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ /* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
/* USER CODE END Defines */ /* USER CODE END Defines */

3
Core/Inc/adc.h
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@ -34,11 +34,14 @@ extern "C" {
extern ADC_HandleTypeDef hadc1; extern ADC_HandleTypeDef hadc1;
extern ADC_HandleTypeDef hadc3;
/* USER CODE BEGIN Private defines */ /* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */ /* USER CODE END Private defines */
void MX_ADC1_Init(void); void MX_ADC1_Init(void);
void MX_ADC3_Init(void);
/* USER CODE BEGIN Prototypes */ /* USER CODE BEGIN Prototypes */

52
Core/Inc/bdma.h Normal file
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@ -0,0 +1,52 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file bdma.h
* @brief This file contains all the function prototypes for
* the bdma.c file
******************************************************************************
* @attention
*
* Copyright (c) 2026 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __BDMA_H__
#define __BDMA_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* DMA memory to memory transfer handles -------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_BDMA_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /* __BDMA_H__ */

2
Core/Inc/stm32h7xx_it.h
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@ -69,6 +69,8 @@ void USART3_IRQHandler(void);
void EXTI15_10_IRQHandler(void); void EXTI15_10_IRQHandler(void);
void UART5_IRQHandler(void); void UART5_IRQHandler(void);
void UART7_IRQHandler(void); void UART7_IRQHandler(void);
void ADC3_IRQHandler(void);
void BDMA_Channel0_IRQHandler(void);
void USART10_IRQHandler(void); void USART10_IRQHandler(void);
void FDCAN3_IT0_IRQHandler(void); void FDCAN3_IT0_IRQHandler(void);
void FDCAN3_IT1_IRQHandler(void); void FDCAN3_IT1_IRQHandler(void);

129
Core/Src/adc.c
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@ -25,7 +25,9 @@
/* USER CODE END 0 */ /* USER CODE END 0 */
ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc1;
ADC_HandleTypeDef hadc3;
DMA_HandleTypeDef hdma_adc1; DMA_HandleTypeDef hdma_adc1;
DMA_HandleTypeDef hdma_adc3;
/* ADC1 init function */ /* ADC1 init function */
void MX_ADC1_Init(void) void MX_ADC1_Init(void)
@ -99,36 +101,75 @@ void MX_ADC1_Init(void)
/* USER CODE END ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */
}
/* ADC3 init function */
void MX_ADC3_Init(void)
{
/* USER CODE BEGIN ADC3_Init 0 */
/* USER CODE END ADC3_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
/* USER CODE BEGIN ADC3_Init 1 */
/* USER CODE END ADC3_Init 1 */
/** Common config
*/
hadc3.Instance = ADC3;
hadc3.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
hadc3.Init.Resolution = ADC_RESOLUTION_12B;
hadc3.Init.DataAlign = ADC3_DATAALIGN_RIGHT;
hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc3.Init.LowPowerAutoWait = DISABLE;
hadc3.Init.ContinuousConvMode = DISABLE;
hadc3.Init.NbrOfConversion = 1;
hadc3.Init.DiscontinuousConvMode = DISABLE;
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc3.Init.DMAContinuousRequests = DISABLE;
hadc3.Init.SamplingMode = ADC_SAMPLING_MODE_NORMAL;
hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED;
hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
hadc3.Init.OversamplingMode = DISABLE;
hadc3.Init.Oversampling.Ratio = ADC3_OVERSAMPLING_RATIO_2;
if (HAL_ADC_Init(&hadc3) != HAL_OK)
{
Error_Handler();
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_VBAT;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC3_SAMPLETIME_2CYCLES_5;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
sConfig.OffsetSign = ADC3_OFFSET_SIGN_NEGATIVE;
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ADC3_Init 2 */
/* USER CODE END ADC3_Init 2 */
} }
void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{ {
GPIO_InitTypeDef GPIO_InitStruct = {0}; GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(adcHandle->Instance==ADC1) if(adcHandle->Instance==ADC1)
{ {
/* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
PeriphClkInitStruct.PLL2.PLL2M = 2;
PeriphClkInitStruct.PLL2.PLL2N = 16;
PeriphClkInitStruct.PLL2.PLL2P = 2;
PeriphClkInitStruct.PLL2.PLL2Q = 2;
PeriphClkInitStruct.PLL2.PLL2R = 2;
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* ADC1 clock enable */ /* ADC1 clock enable */
__HAL_RCC_ADC12_CLK_ENABLE(); __HAL_RCC_ADC12_CLK_ENABLE();
@ -171,6 +212,39 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
/* USER CODE END ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */
} }
else if(adcHandle->Instance==ADC3)
{
/* USER CODE BEGIN ADC3_MspInit 0 */
/* USER CODE END ADC3_MspInit 0 */
/* ADC3 clock enable */
__HAL_RCC_ADC3_CLK_ENABLE();
/* ADC3 DMA Init */
/* ADC3 Init */
hdma_adc3.Instance = BDMA_Channel0;
hdma_adc3.Init.Request = BDMA_REQUEST_ADC3;
hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_adc3.Init.MemInc = DMA_MINC_ENABLE;
hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
hdma_adc3.Init.Mode = DMA_NORMAL;
hdma_adc3.Init.Priority = DMA_PRIORITY_LOW;
if (HAL_DMA_Init(&hdma_adc3) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc3);
/* ADC3 interrupt Init */
HAL_NVIC_SetPriority(ADC3_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(ADC3_IRQn);
/* USER CODE BEGIN ADC3_MspInit 1 */
/* USER CODE END ADC3_MspInit 1 */
}
} }
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
@ -198,6 +272,23 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
/* USER CODE END ADC1_MspDeInit 1 */ /* USER CODE END ADC1_MspDeInit 1 */
} }
else if(adcHandle->Instance==ADC3)
{
/* USER CODE BEGIN ADC3_MspDeInit 0 */
/* USER CODE END ADC3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ADC3_CLK_DISABLE();
/* ADC3 DMA DeInit */
HAL_DMA_DeInit(adcHandle->DMA_Handle);
/* ADC3 interrupt Deinit */
HAL_NVIC_DisableIRQ(ADC3_IRQn);
/* USER CODE BEGIN ADC3_MspDeInit 1 */
/* USER CODE END ADC3_MspDeInit 1 */
}
} }
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */

55
Core/Src/bdma.c Normal file
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@ -0,0 +1,55 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file bdma.c
* @brief This file provides code for the configuration
* of all the requested memory to memory DMA transfers.
******************************************************************************
* @attention
*
* Copyright (c) 2026 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "bdma.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/*----------------------------------------------------------------------------*/
/* Configure DMA */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/**
* Enable DMA controller clock
*/
void MX_BDMA_Init(void)
{
/* DMA controller clock enable */
__HAL_RCC_BDMA_CLK_ENABLE();
/* DMA interrupt init */
/* BDMA_Channel0_IRQn interrupt configuration */
HAL_NVIC_SetPriority(BDMA_Channel0_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(BDMA_Channel0_IRQn);
}
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */

17
Core/Src/freertos.c
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@ -65,6 +65,23 @@ void StartDefaultTask(void *argument);
void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */
/* Hook prototypes */
void configureTimerForRunTimeStats(void);
unsigned long getRunTimeCounterValue(void);
/* USER CODE BEGIN 1 */
/* Functions needed when configGENERATE_RUN_TIME_STATS is on */
__weak void configureTimerForRunTimeStats(void)
{
}
__weak unsigned long getRunTimeCounterValue(void)
{
return 0;
}
/* USER CODE END 1 */
/** /**
* @brief FreeRTOS initialization * @brief FreeRTOS initialization
* @param None * @param None

35
Core/Src/main.c
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@ -20,6 +20,7 @@
#include "main.h" #include "main.h"
#include "cmsis_os.h" #include "cmsis_os.h"
#include "adc.h" #include "adc.h"
#include "bdma.h"
#include "dma.h" #include "dma.h"
#include "fdcan.h" #include "fdcan.h"
#include "octospi.h" #include "octospi.h"
@ -57,6 +58,7 @@
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void); void SystemClock_Config(void);
void PeriphCommonClock_Config(void);
void MX_FREERTOS_Init(void); void MX_FREERTOS_Init(void);
/* USER CODE BEGIN PFP */ /* USER CODE BEGIN PFP */
@ -90,6 +92,9 @@ int main(void)
/* Configure the system clock */ /* Configure the system clock */
SystemClock_Config(); SystemClock_Config();
/* Configure the peripherals common clocks */
PeriphCommonClock_Config();
/* USER CODE BEGIN SysInit */ /* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */ /* USER CODE END SysInit */
@ -97,6 +102,7 @@ int main(void)
/* Initialize all configured peripherals */ /* Initialize all configured peripherals */
MX_GPIO_Init(); MX_GPIO_Init();
MX_DMA_Init(); MX_DMA_Init();
MX_BDMA_Init();
MX_ADC1_Init(); MX_ADC1_Init();
MX_TIM12_Init(); MX_TIM12_Init();
MX_SPI1_Init(); MX_SPI1_Init();
@ -113,8 +119,9 @@ int main(void)
MX_TIM1_Init(); MX_TIM1_Init();
MX_TIM2_Init(); MX_TIM2_Init();
MX_OCTOSPI1_Init(); MX_OCTOSPI1_Init();
MX_USB_OTG_HS_PCD_Init();
MX_UART5_Init(); MX_UART5_Init();
MX_ADC3_Init();
MX_USB_OTG_HS_PCD_Init();
/* USER CODE BEGIN 2 */ /* USER CODE BEGIN 2 */
/* USER CODE END 2 */ /* USER CODE END 2 */
@ -202,6 +209,32 @@ void SystemClock_Config(void)
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1);
} }
/**
* @brief Peripherals Common Clock Configuration
* @retval None
*/
void PeriphCommonClock_Config(void)
{
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
PeriphClkInitStruct.PLL2.PLL2M = 2;
PeriphClkInitStruct.PLL2.PLL2N = 16;
PeriphClkInitStruct.PLL2.PLL2P = 2;
PeriphClkInitStruct.PLL2.PLL2Q = 2;
PeriphClkInitStruct.PLL2.PLL2R = 2;
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
}
/* USER CODE BEGIN 4 */ /* USER CODE BEGIN 4 */
/* USER CODE END 4 */ /* USER CODE END 4 */

983
Core/Src/stm32h7xx_it.c
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@ -1,475 +1,508 @@
/* USER CODE BEGIN Header */ /* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* @file stm32h7xx_it.c * @file stm32h7xx_it.c
* @brief Interrupt Service Routines. * @brief Interrupt Service Routines.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2026 STMicroelectronics. * Copyright (c) 2026 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */ /* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "main.h" #include "main.h"
#include "stm32h7xx_it.h" #include "stm32h7xx_it.h"
/* Private includes ----------------------------------------------------------*/ /* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
/* USER CODE END Includes */ #include "bsp/uart.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */ /* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */ /* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */ /* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */ /* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */ /* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern DMA_HandleTypeDef hdma_adc1; /* External variables --------------------------------------------------------*/
extern FDCAN_HandleTypeDef hfdcan1; extern DMA_HandleTypeDef hdma_adc1;
extern FDCAN_HandleTypeDef hfdcan2; extern DMA_HandleTypeDef hdma_adc3;
extern FDCAN_HandleTypeDef hfdcan3; extern ADC_HandleTypeDef hadc3;
extern DMA_HandleTypeDef hdma_spi2_rx; extern FDCAN_HandleTypeDef hfdcan1;
extern DMA_HandleTypeDef hdma_spi2_tx; extern FDCAN_HandleTypeDef hfdcan2;
extern SPI_HandleTypeDef hspi2; extern FDCAN_HandleTypeDef hfdcan3;
extern DMA_HandleTypeDef hdma_uart5_rx; extern DMA_HandleTypeDef hdma_spi2_rx;
extern DMA_HandleTypeDef hdma_usart1_tx; extern DMA_HandleTypeDef hdma_spi2_tx;
extern DMA_HandleTypeDef hdma_usart1_rx; extern SPI_HandleTypeDef hspi2;
extern UART_HandleTypeDef huart5; extern DMA_HandleTypeDef hdma_uart5_rx;
extern UART_HandleTypeDef huart7; extern DMA_HandleTypeDef hdma_usart1_tx;
extern UART_HandleTypeDef huart1; extern DMA_HandleTypeDef hdma_usart1_rx;
extern UART_HandleTypeDef huart2; extern UART_HandleTypeDef huart5;
extern UART_HandleTypeDef huart3; extern UART_HandleTypeDef huart7;
extern UART_HandleTypeDef huart10; extern UART_HandleTypeDef huart1;
extern TIM_HandleTypeDef htim23; extern UART_HandleTypeDef huart2;
extern UART_HandleTypeDef huart3;
/* USER CODE BEGIN EV */ extern UART_HandleTypeDef huart10;
extern TIM_HandleTypeDef htim23;
/* USER CODE END EV */
/* USER CODE BEGIN EV */
/******************************************************************************/
/* Cortex Processor Interruption and Exception Handlers */ /* USER CODE END EV */
/******************************************************************************/
/** /******************************************************************************/
* @brief This function handles Non maskable interrupt. /* Cortex Processor Interruption and Exception Handlers */
*/ /******************************************************************************/
void NMI_Handler(void) /**
{ * @brief This function handles Non maskable interrupt.
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */ */
void NMI_Handler(void)
/* USER CODE END NonMaskableInt_IRQn 0 */ {
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
while (1)
{ /* USER CODE END NonMaskableInt_IRQn 0 */
} /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */ while (1)
} {
}
/** /* USER CODE END NonMaskableInt_IRQn 1 */
* @brief This function handles Hard fault interrupt. }
*/
void HardFault_Handler(void) /**
{ * @brief This function handles Hard fault interrupt.
/* USER CODE BEGIN HardFault_IRQn 0 */ */
void HardFault_Handler(void)
/* USER CODE END HardFault_IRQn 0 */ {
while (1) /* USER CODE BEGIN HardFault_IRQn 0 */
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */ while (1)
} {
} /* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
/** }
* @brief This function handles Memory management fault. }
*/
void MemManage_Handler(void) /**
{ * @brief This function handles Memory management fault.
/* USER CODE BEGIN MemoryManagement_IRQn 0 */ */
void MemManage_Handler(void)
/* USER CODE END MemoryManagement_IRQn 0 */ {
while (1) /* USER CODE BEGIN MemoryManagement_IRQn 0 */
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */ while (1)
} {
} /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
/** }
* @brief This function handles Pre-fetch fault, memory access fault. }
*/
void BusFault_Handler(void) /**
{ * @brief This function handles Pre-fetch fault, memory access fault.
/* USER CODE BEGIN BusFault_IRQn 0 */ */
void BusFault_Handler(void)
/* USER CODE END BusFault_IRQn 0 */ {
while (1) /* USER CODE BEGIN BusFault_IRQn 0 */
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */ while (1)
} {
} /* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
/** }
* @brief This function handles Undefined instruction or illegal state. }
*/
void UsageFault_Handler(void) /**
{ * @brief This function handles Undefined instruction or illegal state.
/* USER CODE BEGIN UsageFault_IRQn 0 */ */
void UsageFault_Handler(void)
/* USER CODE END UsageFault_IRQn 0 */ {
while (1) /* USER CODE BEGIN UsageFault_IRQn 0 */
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */ while (1)
} {
} /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
/** }
* @brief This function handles Debug monitor. }
*/
void DebugMon_Handler(void) /**
{ * @brief This function handles Debug monitor.
/* USER CODE BEGIN DebugMonitor_IRQn 0 */ */
void DebugMon_Handler(void)
/* USER CODE END DebugMonitor_IRQn 0 */ {
/* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 0 */
} /* USER CODE BEGIN DebugMonitor_IRQn 1 */
/******************************************************************************/ /* USER CODE END DebugMonitor_IRQn 1 */
/* STM32H7xx Peripheral Interrupt Handlers */ }
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */ /******************************************************************************/
/* please refer to the startup file (startup_stm32h7xx.s). */ /* STM32H7xx Peripheral Interrupt Handlers */
/******************************************************************************/ /* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/** /* please refer to the startup file (startup_stm32h7xx.s). */
* @brief This function handles DMA1 stream0 global interrupt. /******************************************************************************/
*/
void DMA1_Stream0_IRQHandler(void) /**
{ * @brief This function handles DMA1 stream0 global interrupt.
/* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ */
void DMA1_Stream0_IRQHandler(void)
/* USER CODE END DMA1_Stream0_IRQn 0 */ {
HAL_DMA_IRQHandler(&hdma_adc1); /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
/* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
/* USER CODE END DMA1_Stream0_IRQn 0 */
/* USER CODE END DMA1_Stream0_IRQn 1 */ HAL_DMA_IRQHandler(&hdma_adc1);
} /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
/** /* USER CODE END DMA1_Stream0_IRQn 1 */
* @brief This function handles DMA1 stream1 global interrupt. }
*/
void DMA1_Stream1_IRQHandler(void) /**
{ * @brief This function handles DMA1 stream1 global interrupt.
/* USER CODE BEGIN DMA1_Stream1_IRQn 0 */ */
void DMA1_Stream1_IRQHandler(void)
/* USER CODE END DMA1_Stream1_IRQn 0 */ {
HAL_DMA_IRQHandler(&hdma_spi2_rx); /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
/* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
/* USER CODE END DMA1_Stream1_IRQn 0 */
/* USER CODE END DMA1_Stream1_IRQn 1 */ HAL_DMA_IRQHandler(&hdma_spi2_rx);
} /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
/** /* USER CODE END DMA1_Stream1_IRQn 1 */
* @brief This function handles DMA1 stream2 global interrupt. }
*/
void DMA1_Stream2_IRQHandler(void) /**
{ * @brief This function handles DMA1 stream2 global interrupt.
/* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ */
void DMA1_Stream2_IRQHandler(void)
/* USER CODE END DMA1_Stream2_IRQn 0 */ {
HAL_DMA_IRQHandler(&hdma_spi2_tx); /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */
/* USER CODE BEGIN DMA1_Stream2_IRQn 1 */
/* USER CODE END DMA1_Stream2_IRQn 0 */
/* USER CODE END DMA1_Stream2_IRQn 1 */ HAL_DMA_IRQHandler(&hdma_spi2_tx);
} /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */
/** /* USER CODE END DMA1_Stream2_IRQn 1 */
* @brief This function handles DMA1 stream3 global interrupt. }
*/
void DMA1_Stream3_IRQHandler(void) /**
{ * @brief This function handles DMA1 stream3 global interrupt.
/* USER CODE BEGIN DMA1_Stream3_IRQn 0 */ */
void DMA1_Stream3_IRQHandler(void)
/* USER CODE END DMA1_Stream3_IRQn 0 */ {
HAL_DMA_IRQHandler(&hdma_uart5_rx); /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */
/* USER CODE BEGIN DMA1_Stream3_IRQn 1 */
/* USER CODE END DMA1_Stream3_IRQn 0 */
/* USER CODE END DMA1_Stream3_IRQn 1 */ HAL_DMA_IRQHandler(&hdma_uart5_rx);
} /* USER CODE BEGIN DMA1_Stream3_IRQn 1 */
/** /* USER CODE END DMA1_Stream3_IRQn 1 */
* @brief This function handles DMA1 stream4 global interrupt. }
*/
void DMA1_Stream4_IRQHandler(void) /**
{ * @brief This function handles DMA1 stream4 global interrupt.
/* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ */
void DMA1_Stream4_IRQHandler(void)
/* USER CODE END DMA1_Stream4_IRQn 0 */ {
HAL_DMA_IRQHandler(&hdma_usart1_tx); /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */
/* USER CODE BEGIN DMA1_Stream4_IRQn 1 */
/* USER CODE END DMA1_Stream4_IRQn 0 */
/* USER CODE END DMA1_Stream4_IRQn 1 */ HAL_DMA_IRQHandler(&hdma_usart1_tx);
} /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */
/** /* USER CODE END DMA1_Stream4_IRQn 1 */
* @brief This function handles DMA1 stream5 global interrupt. }
*/
void DMA1_Stream5_IRQHandler(void) /**
{ * @brief This function handles DMA1 stream5 global interrupt.
/* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ */
void DMA1_Stream5_IRQHandler(void)
/* USER CODE END DMA1_Stream5_IRQn 0 */ {
HAL_DMA_IRQHandler(&hdma_usart1_rx); /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
/* USER CODE BEGIN DMA1_Stream5_IRQn 1 */
/* USER CODE END DMA1_Stream5_IRQn 0 */
/* USER CODE END DMA1_Stream5_IRQn 1 */ HAL_DMA_IRQHandler(&hdma_usart1_rx);
} /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */
/** /* USER CODE END DMA1_Stream5_IRQn 1 */
* @brief This function handles FDCAN1 interrupt 0. }
*/
void FDCAN1_IT0_IRQHandler(void) /**
{ * @brief This function handles FDCAN1 interrupt 0.
/* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */ */
void FDCAN1_IT0_IRQHandler(void)
/* USER CODE END FDCAN1_IT0_IRQn 0 */ {
HAL_FDCAN_IRQHandler(&hfdcan1); /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */
/* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */
/* USER CODE END FDCAN1_IT0_IRQn 0 */
/* USER CODE END FDCAN1_IT0_IRQn 1 */ HAL_FDCAN_IRQHandler(&hfdcan1);
} /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */
/** /* USER CODE END FDCAN1_IT0_IRQn 1 */
* @brief This function handles FDCAN2 interrupt 0. }
*/
void FDCAN2_IT0_IRQHandler(void) /**
{ * @brief This function handles FDCAN2 interrupt 0.
/* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */ */
void FDCAN2_IT0_IRQHandler(void)
/* USER CODE END FDCAN2_IT0_IRQn 0 */ {
HAL_FDCAN_IRQHandler(&hfdcan2); /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */
/* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */
/* USER CODE END FDCAN2_IT0_IRQn 0 */
/* USER CODE END FDCAN2_IT0_IRQn 1 */ HAL_FDCAN_IRQHandler(&hfdcan2);
} /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */
/** /* USER CODE END FDCAN2_IT0_IRQn 1 */
* @brief This function handles FDCAN1 interrupt 1. }
*/
void FDCAN1_IT1_IRQHandler(void) /**
{ * @brief This function handles FDCAN1 interrupt 1.
/* USER CODE BEGIN FDCAN1_IT1_IRQn 0 */ */
void FDCAN1_IT1_IRQHandler(void)
/* USER CODE END FDCAN1_IT1_IRQn 0 */ {
HAL_FDCAN_IRQHandler(&hfdcan1); /* USER CODE BEGIN FDCAN1_IT1_IRQn 0 */
/* USER CODE BEGIN FDCAN1_IT1_IRQn 1 */
/* USER CODE END FDCAN1_IT1_IRQn 0 */
/* USER CODE END FDCAN1_IT1_IRQn 1 */ HAL_FDCAN_IRQHandler(&hfdcan1);
} /* USER CODE BEGIN FDCAN1_IT1_IRQn 1 */
/** /* USER CODE END FDCAN1_IT1_IRQn 1 */
* @brief This function handles FDCAN2 interrupt 1. }
*/
void FDCAN2_IT1_IRQHandler(void) /**
{ * @brief This function handles FDCAN2 interrupt 1.
/* USER CODE BEGIN FDCAN2_IT1_IRQn 0 */ */
void FDCAN2_IT1_IRQHandler(void)
/* USER CODE END FDCAN2_IT1_IRQn 0 */ {
HAL_FDCAN_IRQHandler(&hfdcan2); /* USER CODE BEGIN FDCAN2_IT1_IRQn 0 */
/* USER CODE BEGIN FDCAN2_IT1_IRQn 1 */
/* USER CODE END FDCAN2_IT1_IRQn 0 */
/* USER CODE END FDCAN2_IT1_IRQn 1 */ HAL_FDCAN_IRQHandler(&hfdcan2);
} /* USER CODE BEGIN FDCAN2_IT1_IRQn 1 */
/** /* USER CODE END FDCAN2_IT1_IRQn 1 */
* @brief This function handles SPI2 global interrupt. }
*/
void SPI2_IRQHandler(void) /**
{ * @brief This function handles SPI2 global interrupt.
/* USER CODE BEGIN SPI2_IRQn 0 */ */
void SPI2_IRQHandler(void)
/* USER CODE END SPI2_IRQn 0 */ {
HAL_SPI_IRQHandler(&hspi2); /* USER CODE BEGIN SPI2_IRQn 0 */
/* USER CODE BEGIN SPI2_IRQn 1 */
/* USER CODE END SPI2_IRQn 0 */
/* USER CODE END SPI2_IRQn 1 */ HAL_SPI_IRQHandler(&hspi2);
} /* USER CODE BEGIN SPI2_IRQn 1 */
/** /* USER CODE END SPI2_IRQn 1 */
* @brief This function handles USART1 global interrupt. }
*/
void USART1_IRQHandler(void) /**
{ * @brief This function handles USART1 global interrupt.
/* USER CODE BEGIN USART1_IRQn 0 */ */
void USART1_IRQHandler(void)
/* USER CODE END USART1_IRQn 0 */ {
HAL_UART_IRQHandler(&huart1); /* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 1 */ HAL_UART_IRQHandler(&huart1);
} /* USER CODE BEGIN USART1_IRQn 1 */
BSP_UART_IRQHandler(&huart1);
/**
* @brief This function handles USART2 global interrupt. /* USER CODE END USART1_IRQn 1 */
*/ }
void USART2_IRQHandler(void)
{ /**
/* USER CODE BEGIN USART2_IRQn 0 */ * @brief This function handles USART2 global interrupt.
*/
/* USER CODE END USART2_IRQn 0 */ void USART2_IRQHandler(void)
HAL_UART_IRQHandler(&huart2); {
/* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE BEGIN USART2_IRQn 0 */
/* USER CODE END USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 0 */
} HAL_UART_IRQHandler(&huart2);
/* USER CODE BEGIN USART2_IRQn 1 */
/**
* @brief This function handles USART3 global interrupt. /* USER CODE END USART2_IRQn 1 */
*/ }
void USART3_IRQHandler(void)
{ /**
/* USER CODE BEGIN USART3_IRQn 0 */ * @brief This function handles USART3 global interrupt.
*/
/* USER CODE END USART3_IRQn 0 */ void USART3_IRQHandler(void)
HAL_UART_IRQHandler(&huart3); {
/* USER CODE BEGIN USART3_IRQn 1 */ /* USER CODE BEGIN USART3_IRQn 0 */
/* USER CODE END USART3_IRQn 1 */ /* USER CODE END USART3_IRQn 0 */
} HAL_UART_IRQHandler(&huart3);
/* USER CODE BEGIN USART3_IRQn 1 */
/**
* @brief This function handles EXTI line[15:10] interrupts. /* USER CODE END USART3_IRQn 1 */
*/ }
void EXTI15_10_IRQHandler(void)
{ /**
/* USER CODE BEGIN EXTI15_10_IRQn 0 */ * @brief This function handles EXTI line[15:10] interrupts.
*/
/* USER CODE END EXTI15_10_IRQn 0 */ void EXTI15_10_IRQHandler(void)
HAL_GPIO_EXTI_IRQHandler(ACCL_INT_Pin); {
HAL_GPIO_EXTI_IRQHandler(GYRO_INT_Pin); /* USER CODE BEGIN EXTI15_10_IRQn 0 */
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
/* USER CODE END EXTI15_10_IRQn 0 */
/* USER CODE END EXTI15_10_IRQn 1 */ HAL_GPIO_EXTI_IRQHandler(ACCL_INT_Pin);
} HAL_GPIO_EXTI_IRQHandler(GYRO_INT_Pin);
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
/**
* @brief This function handles UART5 global interrupt. /* USER CODE END EXTI15_10_IRQn 1 */
*/ }
void UART5_IRQHandler(void)
{ /**
/* USER CODE BEGIN UART5_IRQn 0 */ * @brief This function handles UART5 global interrupt.
*/
/* USER CODE END UART5_IRQn 0 */ void UART5_IRQHandler(void)
HAL_UART_IRQHandler(&huart5); {
/* USER CODE BEGIN UART5_IRQn 1 */ /* USER CODE BEGIN UART5_IRQn 0 */
/* USER CODE END UART5_IRQn 1 */ /* USER CODE END UART5_IRQn 0 */
} HAL_UART_IRQHandler(&huart5);
/* USER CODE BEGIN UART5_IRQn 1 */
/** BSP_UART_IRQHandler(&huart5);
* @brief This function handles UART7 global interrupt.
*/ /* USER CODE END UART5_IRQn 1 */
void UART7_IRQHandler(void) }
{
/* USER CODE BEGIN UART7_IRQn 0 */ /**
* @brief This function handles UART7 global interrupt.
/* USER CODE END UART7_IRQn 0 */ */
HAL_UART_IRQHandler(&huart7); void UART7_IRQHandler(void)
/* USER CODE BEGIN UART7_IRQn 1 */ {
/* USER CODE BEGIN UART7_IRQn 0 */
/* USER CODE END UART7_IRQn 1 */
} /* USER CODE END UART7_IRQn 0 */
HAL_UART_IRQHandler(&huart7);
/** /* USER CODE BEGIN UART7_IRQn 1 */
* @brief This function handles USART10 global interrupt.
*/ /* USER CODE END UART7_IRQn 1 */
void USART10_IRQHandler(void) }
{
/* USER CODE BEGIN USART10_IRQn 0 */ /**
* @brief This function handles ADC3 global interrupt.
/* USER CODE END USART10_IRQn 0 */ */
HAL_UART_IRQHandler(&huart10); void ADC3_IRQHandler(void)
/* USER CODE BEGIN USART10_IRQn 1 */ {
/* USER CODE BEGIN ADC3_IRQn 0 */
/* USER CODE END USART10_IRQn 1 */
} /* USER CODE END ADC3_IRQn 0 */
HAL_ADC_IRQHandler(&hadc3);
/** /* USER CODE BEGIN ADC3_IRQn 1 */
* @brief This function handles FDCAN3 interrupt 0.
*/ /* USER CODE END ADC3_IRQn 1 */
void FDCAN3_IT0_IRQHandler(void) }
{
/* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */ /**
* @brief This function handles BDMA channel0 global interrupt.
/* USER CODE END FDCAN3_IT0_IRQn 0 */ */
HAL_FDCAN_IRQHandler(&hfdcan3); void BDMA_Channel0_IRQHandler(void)
/* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */ {
/* USER CODE BEGIN BDMA_Channel0_IRQn 0 */
/* USER CODE END FDCAN3_IT0_IRQn 1 */
} /* USER CODE END BDMA_Channel0_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_adc3);
/** /* USER CODE BEGIN BDMA_Channel0_IRQn 1 */
* @brief This function handles FDCAN3 interrupt 1.
*/ /* USER CODE END BDMA_Channel0_IRQn 1 */
void FDCAN3_IT1_IRQHandler(void) }
{
/* USER CODE BEGIN FDCAN3_IT1_IRQn 0 */ /**
* @brief This function handles USART10 global interrupt.
/* USER CODE END FDCAN3_IT1_IRQn 0 */ */
HAL_FDCAN_IRQHandler(&hfdcan3); void USART10_IRQHandler(void)
/* USER CODE BEGIN FDCAN3_IT1_IRQn 1 */ {
/* USER CODE BEGIN USART10_IRQn 0 */
/* USER CODE END FDCAN3_IT1_IRQn 1 */
} /* USER CODE END USART10_IRQn 0 */
HAL_UART_IRQHandler(&huart10);
/** /* USER CODE BEGIN USART10_IRQn 1 */
* @brief This function handles TIM23 global interrupt.
*/ /* USER CODE END USART10_IRQn 1 */
void TIM23_IRQHandler(void) }
{
/* USER CODE BEGIN TIM23_IRQn 0 */ /**
* @brief This function handles FDCAN3 interrupt 0.
/* USER CODE END TIM23_IRQn 0 */ */
HAL_TIM_IRQHandler(&htim23); void FDCAN3_IT0_IRQHandler(void)
/* USER CODE BEGIN TIM23_IRQn 1 */ {
/* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */
/* USER CODE END TIM23_IRQn 1 */
} /* USER CODE END FDCAN3_IT0_IRQn 0 */
HAL_FDCAN_IRQHandler(&hfdcan3);
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */
/* USER CODE END 1 */ /* USER CODE END FDCAN3_IT0_IRQn 1 */
}
/**
* @brief This function handles FDCAN3 interrupt 1.
*/
void FDCAN3_IT1_IRQHandler(void)
{
/* USER CODE BEGIN FDCAN3_IT1_IRQn 0 */
/* USER CODE END FDCAN3_IT1_IRQn 0 */
HAL_FDCAN_IRQHandler(&hfdcan3);
/* USER CODE BEGIN FDCAN3_IT1_IRQn 1 */
/* USER CODE END FDCAN3_IT1_IRQn 1 */
}
/**
* @brief This function handles TIM23 global interrupt.
*/
void TIM23_IRQHandler(void)
{
/* USER CODE BEGIN TIM23_IRQn 0 */
/* USER CODE END TIM23_IRQn 0 */
HAL_TIM_IRQHandler(&htim23);
/* USER CODE BEGIN TIM23_IRQn 1 */
/* USER CODE END TIM23_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

110
CtrBoard-H7_ALL.ioc
View File

@ -16,6 +16,33 @@ ADC1.Rank-1\#ChannelRegularConversion=2
ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_32CYCLES_5 ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_32CYCLES_5
ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_32CYCLES_5 ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_32CYCLES_5
ADC1.master=1 ADC1.master=1
ADC3.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_VBAT
ADC3.ClockPrescaler=ADC_CLOCK_ASYNC_DIV64
ADC3.IPParameters=Rank-0\#ChannelRegularConversion,ClockPrescaler,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,OffsetSign-0\#ChannelRegularConversion,NbrOfConversionFlag
ADC3.NbrOfConversionFlag=1
ADC3.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
ADC3.OffsetSign-0\#ChannelRegularConversion=ADC3_OFFSET_SIGN_NEGATIVE
ADC3.Rank-0\#ChannelRegularConversion=1
ADC3.SamplingTime-0\#ChannelRegularConversion=ADC3_SAMPLETIME_2CYCLES_5
Bdma.ADC3.0.Direction=DMA_PERIPH_TO_MEMORY
Bdma.ADC3.0.EventEnable=DISABLE
Bdma.ADC3.0.Instance=BDMA_Channel0
Bdma.ADC3.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
Bdma.ADC3.0.MemInc=DMA_MINC_ENABLE
Bdma.ADC3.0.Mode=DMA_NORMAL
Bdma.ADC3.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
Bdma.ADC3.0.PeriphInc=DMA_PINC_DISABLE
Bdma.ADC3.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Bdma.ADC3.0.Priority=DMA_PRIORITY_LOW
Bdma.ADC3.0.RequestNumber=1
Bdma.ADC3.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Bdma.ADC3.0.SignalID=NONE
Bdma.ADC3.0.SyncEnable=DISABLE
Bdma.ADC3.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Bdma.ADC3.0.SyncRequestNumber=1
Bdma.ADC3.0.SyncSignalID=NONE
Bdma.Request0=ADC3
Bdma.RequestsNb=1
CAD.formats= CAD.formats=
CAD.pinconfig= CAD.pinconfig=
CAD.provider= CAD.provider=
@ -179,9 +206,11 @@ FDCAN3.RxFifo0ElmtsNbr=32
FDCAN3.RxFifo1ElmtsNbr=32 FDCAN3.RxFifo1ElmtsNbr=32
FDCAN3.StdFiltersNbr=1 FDCAN3.StdFiltersNbr=1
FDCAN3.TxFifoQueueElmtsNbr=32 FDCAN3.TxFifoQueueElmtsNbr=32
FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,configUSE_STATS_FORMATTING_FUNCTIONS,configGENERATE_RUN_TIME_STATS
FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL
FREERTOS.configGENERATE_RUN_TIME_STATS=1
FREERTOS.configTOTAL_HEAP_SIZE=0x10000 FREERTOS.configTOTAL_HEAP_SIZE=0x10000
FREERTOS.configUSE_STATS_FORMATTING_FUNCTIONS=1
File.Version=6 File.Version=6
GPIO.groupedBy=Group By Peripherals GPIO.groupedBy=Group By Peripherals
KeepUserPlacement=false KeepUserPlacement=false
@ -190,32 +219,34 @@ MMTConfigApplied=false
Mcu.CPN=STM32H723VGT6 Mcu.CPN=STM32H723VGT6
Mcu.Family=STM32H7 Mcu.Family=STM32H7
Mcu.IP0=ADC1 Mcu.IP0=ADC1
Mcu.IP1=CORTEX_M7 Mcu.IP1=ADC3
Mcu.IP10=OCTOSPI1 Mcu.IP10=MEMORYMAP
Mcu.IP11=RCC Mcu.IP11=NVIC
Mcu.IP12=SPI1 Mcu.IP12=OCTOSPI1
Mcu.IP13=SPI2 Mcu.IP13=RCC
Mcu.IP14=SYS Mcu.IP14=SPI1
Mcu.IP15=TIM1 Mcu.IP15=SPI2
Mcu.IP16=TIM2 Mcu.IP16=SYS
Mcu.IP17=TIM3 Mcu.IP17=TIM1
Mcu.IP18=TIM12 Mcu.IP18=TIM2
Mcu.IP19=UART5 Mcu.IP19=TIM3
Mcu.IP2=DEBUG Mcu.IP2=BDMA
Mcu.IP20=UART7 Mcu.IP20=TIM12
Mcu.IP21=USART1 Mcu.IP21=UART5
Mcu.IP22=USART2 Mcu.IP22=UART7
Mcu.IP23=USART3 Mcu.IP23=USART1
Mcu.IP24=USART10 Mcu.IP24=USART2
Mcu.IP25=USB_OTG_HS Mcu.IP25=USART3
Mcu.IP3=DMA Mcu.IP26=USART10
Mcu.IP4=FDCAN1 Mcu.IP27=USB_OTG_HS
Mcu.IP5=FDCAN2 Mcu.IP3=CORTEX_M7
Mcu.IP6=FDCAN3 Mcu.IP4=DEBUG
Mcu.IP7=FREERTOS Mcu.IP5=DMA
Mcu.IP8=MEMORYMAP Mcu.IP6=FDCAN1
Mcu.IP9=NVIC Mcu.IP7=FDCAN2
Mcu.IPNb=26 Mcu.IP8=FDCAN3
Mcu.IP9=FREERTOS
Mcu.IPNb=28
Mcu.Name=STM32H723VGTx Mcu.Name=STM32H723VGTx
Mcu.Package=LQFP100 Mcu.Package=LQFP100
Mcu.Pin0=PE2 Mcu.Pin0=PE2
@ -276,21 +307,26 @@ Mcu.Pin58=PB3(JTDO/TRACESWO)
Mcu.Pin59=PB5 Mcu.Pin59=PB5
Mcu.Pin6=PH1-OSC_OUT Mcu.Pin6=PH1-OSC_OUT
Mcu.Pin60=PB6 Mcu.Pin60=PB6
Mcu.Pin61=VP_FREERTOS_VS_CMSIS_V2 Mcu.Pin61=VP_ADC3_TempSens_Input
Mcu.Pin62=VP_OCTOSPI1_VS_octo Mcu.Pin62=VP_ADC3_Vref_Input
Mcu.Pin63=VP_SYS_VS_tim23 Mcu.Pin63=VP_ADC3_Vbat_Input
Mcu.Pin64=VP_MEMORYMAP_VS_MEMORYMAP Mcu.Pin64=VP_FREERTOS_VS_CMSIS_V2
Mcu.Pin65=VP_STMicroelectronics.X-CUBE-ALGOBUILD_VS_DSPOoLibraryJjLibrary_1.4.0_1.4.0 Mcu.Pin65=VP_OCTOSPI1_VS_octo
Mcu.Pin66=VP_SYS_VS_tim23
Mcu.Pin67=VP_MEMORYMAP_VS_MEMORYMAP
Mcu.Pin68=VP_STMicroelectronics.X-CUBE-ALGOBUILD_VS_DSPOoLibraryJjLibrary_1.4.0_1.4.0
Mcu.Pin7=PC0 Mcu.Pin7=PC0
Mcu.Pin8=PC1 Mcu.Pin8=PC1
Mcu.Pin9=PC2_C Mcu.Pin9=PC2_C
Mcu.PinsNb=66 Mcu.PinsNb=69
Mcu.ThirdParty0=STMicroelectronics.X-CUBE-ALGOBUILD.1.4.0 Mcu.ThirdParty0=STMicroelectronics.X-CUBE-ALGOBUILD.1.4.0
Mcu.ThirdPartyNb=1 Mcu.ThirdPartyNb=1
Mcu.UserConstants= Mcu.UserConstants=
Mcu.UserName=STM32H723VGTx Mcu.UserName=STM32H723VGTx
MxCube.Version=6.15.0 MxCube.Version=6.15.0
MxDb.Version=DB.6.0.150 MxDb.Version=DB.6.0.150
NVIC.ADC3_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.BDMA_Channel0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
NVIC.DMA1_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DMA1_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA1_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DMA1_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
@ -556,7 +592,7 @@ ProjectManager.ToolChainLocation=
ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptAfterPath=
ProjectManager.UAScriptBeforePath= ProjectManager.UAScriptBeforePath=
ProjectManager.UnderRoot=false ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_TIM12_Init-TIM12-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_SPI2_Init-SPI2-false-HAL-true,8-MX_TIM3_Init-TIM3-false-HAL-true,9-MX_USART1_UART_Init-USART1-false-HAL-true,10-MX_USART2_UART_Init-USART2-false-HAL-true,11-MX_USART3_UART_Init-USART3-false-HAL-true,12-MX_UART7_Init-UART7-false-HAL-true,13-MX_USART10_UART_Init-USART10-false-HAL-true,14-MX_FDCAN1_Init-FDCAN1-false-HAL-true,15-MX_FDCAN2_Init-FDCAN2-false-HAL-true,16-MX_FDCAN3_Init-FDCAN3-false-HAL-true,17-MX_TIM1_Init-TIM1-false-HAL-true,18-MX_TIM2_Init-TIM2-false-HAL-true,19-MX_OCTOSPI1_Init-OCTOSPI1-false-HAL-true,20-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,21-MX_UART5_Init-UART5-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,5-MX_BDMA_Init-BDMA-false-HAL-true,6-MX_ADC1_Init-ADC1-false-HAL-true,7-MX_TIM12_Init-TIM12-false-HAL-true,8-MX_SPI1_Init-SPI1-false-HAL-true,9-MX_SPI2_Init-SPI2-false-HAL-true,10-MX_TIM3_Init-TIM3-false-HAL-true,11-MX_USART1_UART_Init-USART1-false-HAL-true,12-MX_USART2_UART_Init-USART2-false-HAL-true,13-MX_USART3_UART_Init-USART3-false-HAL-true,14-MX_UART7_Init-UART7-false-HAL-true,15-MX_USART10_UART_Init-USART10-false-HAL-true,16-MX_FDCAN1_Init-FDCAN1-false-HAL-true,17-MX_FDCAN2_Init-FDCAN2-false-HAL-true,18-MX_FDCAN3_Init-FDCAN3-false-HAL-true,19-MX_TIM1_Init-TIM1-false-HAL-true,20-MX_TIM2_Init-TIM2-false-HAL-true,21-MX_OCTOSPI1_Init-OCTOSPI1-false-HAL-true,23-MX_UART5_Init-UART5-false-HAL-true,24-MX_ADC3_Init-ADC3-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
RCC.ADCFreq_Value=96000000 RCC.ADCFreq_Value=96000000
RCC.AHB12Freq_Value=240000000 RCC.AHB12Freq_Value=240000000
RCC.AHB4Freq_Value=240000000 RCC.AHB4Freq_Value=240000000
@ -734,6 +770,12 @@ USART3.VirtualMode-Asynchronous=VM_ASYNC
USART3.VirtualMode-Hardware\ Flow\ Control\ (RS485)=VM_ASYNC USART3.VirtualMode-Hardware\ Flow\ Control\ (RS485)=VM_ASYNC
USB_OTG_HS.IPParameters=VirtualMode-Device_Only_FS USB_OTG_HS.IPParameters=VirtualMode-Device_Only_FS
USB_OTG_HS.VirtualMode-Device_Only_FS=Device_Only_FS USB_OTG_HS.VirtualMode-Device_Only_FS=Device_Only_FS
VP_ADC3_TempSens_Input.Mode=IN-TempSens
VP_ADC3_TempSens_Input.Signal=ADC3_TempSens_Input
VP_ADC3_Vbat_Input.Mode=IN-Vbat
VP_ADC3_Vbat_Input.Signal=ADC3_Vbat_Input
VP_ADC3_Vref_Input.Mode=IN-Vrefint
VP_ADC3_Vref_Input.Signal=ADC3_Vref_Input
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2 VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2 VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg

2
User/task/init.c
View File

@ -40,7 +40,7 @@ void Task_Init(void *argument) {
task_runtime.thread.blink = osThreadNew(Task_blink, NULL, &attr_blink); task_runtime.thread.blink = osThreadNew(Task_blink, NULL, &attr_blink);
task_runtime.thread.ctrl_shoot = osThreadNew(Task_ctrl_shoot, NULL, &attr_ctrl_shoot); task_runtime.thread.ctrl_shoot = osThreadNew(Task_ctrl_shoot, NULL, &attr_ctrl_shoot);
task_runtime.thread.ai = osThreadNew(Task_ai, NULL, &attr_ai); task_runtime.thread.ai = osThreadNew(Task_ai, NULL, &attr_ai);
task_runtime.thread.vofa = osThreadNew(Task_vofa, NULL, &attr_vofa); // task_runtime.thread.vofa = osThreadNew(Task_vofa, NULL, &attr_vofa);
// 创建消息队列 // 创建消息队列
/* USER MESSAGE BEGIN */ /* USER MESSAGE BEGIN */

1
cmake/stm32cubemx/CMakeLists.txt
View File

@ -28,6 +28,7 @@ set(MX_Application_Src
${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/gpio.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/gpio.c
${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/freertos.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/freertos.c
${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/adc.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/adc.c
${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/bdma.c
${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/dma.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/dma.c
${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/fdcan.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/fdcan.c
${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/octospi.c ${CMAKE_CURRENT_SOURCE_DIR}/../../Core/Src/octospi.c