RMUL2025/lib/cmsis_svd/data/NXP/QN908XC.svd

<?xml version="1.0" encoding="UTF-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
  <vendor>nxp.com</vendor>
  <name>QN908XC</name>
  <version>1.0</version>
  <description>QN9080C, QN9083C</description>
  <cpu>
    <name>CM4</name>
    <revision>r0p1</revision>
    <endian>little</endian>
    <mpuPresent>true</mpuPresent>
    <fpuPresent>true</fpuPresent>
    <vtorPresent>true</vtorPresent>
    <nvicPrioBits>3</nvicPrioBits>
    <vendorSystickConfig>false</vendorSystickConfig>
  </cpu>
  <addressUnitBits>8</addressUnitBits>
  <width>32</width>
  <peripherals>
    <peripheral>
      <name>SYSCON</name>
      <description>syscon</description>
      <groupName>SYSCON</groupName>
      <baseAddress>0x40000000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x894</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>RST_SW_SET</name>
          <description>block software reset set register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x7E5FFFFF</resetValue>
          <resetMask>0xFE5FFFFF</resetMask>
          <fields>
            <field>
              <name>SET_FC0_RST</name>
              <description>Write 1 to set FLEXCOMM0 reset</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_FC1_RST</name>
              <description>Write 1 to set FLEXCOMM1 reset</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_FC2_RST</name>
              <description>Write 1 to set FLEXCOMM2 reset</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_FC3_RST</name>
              <description>Write 1 to set FLEXCOMM3 reset</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_TIM0_RST</name>
              <description>Write 1 to set CTIMER0 reset</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_TIM1_RST</name>
              <description>Write 1 to set CTIMER1 reset</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_TIM2_RST</name>
              <description>Write 1 to set CTIMER2 reset</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_TIM3_RST</name>
              <description>Write 1 to set CTIMER3 reset</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_SCT_RST</name>
              <description>Write 1 to set SCT reset</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_WDT_RST</name>
              <description>Write 1 to set Watch Dog reset</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_USB_RST</name>
              <description>Write 1 to set USB reset</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_GPIO_RST</name>
              <description>Write 1 to set GPIO reset</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_RTC_RST</name>
              <description>Write 1 to set RTC reset</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_ADC_RST</name>
              <description>Write 1 to set ADC interface reset</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_DAC_RST</name>
              <description>Write 1 to set DAC interface reset</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_CS_RST</name>
              <description>Write 1 to set Cap sensor interface reset</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_FSP_RST</name>
              <description>Write 1 to set FSP reset</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_DMA_RST</name>
              <description>Write 1 to set DMA reset</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_QDEC0_RST</name>
              <description>Write 1 to set QDEC 0 reset</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_QDEC1_RST</name>
              <description>Write 1 to set QDEC 1 reset</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_SPIFI_RST</name>
              <description>Write 1 to set SPIFI reset</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_CPU_RST</name>
              <description>Write 1 to set CPU reset</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_BLE_RST</name>
              <description>Write 1 to set BLE reset</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_FLASH_RST</name>
              <description>Write 1 to set flash controller reset</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_DP_RST</name>
              <description>Write 1 to set DataPath reset</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_REG_RST</name>
              <description>Write 1 to reset retention register</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SET_REBOOT</name>
              <description>Write 1 to Reboot entire system</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RST_SW_CLR</name>
          <description>block software reset clear register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x7E5FFFFF</resetValue>
          <resetMask>0x7E5FFFFF</resetMask>
          <fields>
            <field>
              <name>CLR_FC0_RST</name>
              <description>Write 1 to clear FLEXCOMM0 reset</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_FC1_RST</name>
              <description>Write 1 to clear FLEXCOMM1 reset</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_FC2_RST</name>
              <description>Write 1 to clear FLEXCOMM2 reset</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_FC3_RST</name>
              <description>Write 1 to clear FLEXCOMM3 reset</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_TIM0_RST</name>
              <description>Write 1 to clear CTIMER0 reset</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_TIM1_RST</name>
              <description>Write 1 to clear CTIMER1 reset</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_TIM2_RST</name>
              <description>Write 1 to clear CTIMER2 reset</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_TIM3_RST</name>
              <description>Write 1 to clear CTIMER3 reset</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_SCT_RST</name>
              <description>Write 1 to clear SCT reset</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_WDT_RST</name>
              <description>Write 1 to clear Watch Dog reset</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_USB_RST</name>
              <description>Write 1 to clear USB reset</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_GPIO_RST</name>
              <description>Write 1 to clear GPIO reset</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_RTC_RST</name>
              <description>Write 1 to clear RTC reset</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_ADC_RST</name>
              <description>Write 1 to clear ADC interface reset</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_DAC_RST</name>
              <description>Write 1 to clear DAC interface reset</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_CS_RST</name>
              <description>Write 1 to clear cap sensor interface reset</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_FSP_RST</name>
              <description>Write 1 to clear FSP reset</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_DMA_RST</name>
              <description>Write 1 to clear DMA reset</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_QDEC0_RST</name>
              <description>Write 1 to clear QDEC 0 reset</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_QDEC1_RST</name>
              <description>Write 1 to clear QDEC 1 reset</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_SPIFI_RST</name>
              <description>Write 1 to clear SPIFI reset</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_CPU_RST</name>
              <description>Write 1 to clear CPU reset</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_BLE_RST</name>
              <description>Write 1 to clear BLE reset</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_FLASH_RST</name>
              <description>Write 1 to clear flash controller reset</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_DP_RST</name>
              <description>Write 1 to clear DataPath reset</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLR_REG_RST</name>
              <description>Write 1 to clear retention register reset</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CLK_DIS</name>
          <description>clock disable register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xC0001200</resetValue>
          <resetMask>0xEA7FFFFF</resetMask>
          <fields>
            <field>
              <name>CLK_FC0_DIS</name>
              <description>Write 1 to disable FLEXCOMM0 clock</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_FC1_DIS</name>
              <description>Write 1 to disable FLEXCOMM1 clock</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_FC2_DIS</name>
              <description>Write 1 to disable FLEXCOMM2 clock</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_FC3_DIS</name>
              <description>Write 1 to disable FLEXCOMM3 clock</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_TIM0_DIS</name>
              <description>Write 1 to disable CTIMER0 clock</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_TIM1_DIS</name>
              <description>Write 1 to disable CTIMER1 clock</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_TIM2_DIS</name>
              <description>Write 1 to disable CTIMER2 clock</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_TIM3_DIS</name>
              <description>Write 1 to disable CTIMER3 clock</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_SCT_DIS</name>
              <description>Write 1 to disable SCT clock</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_WDT_DIS</name>
              <description>Write 1 to disable Watch Dog clock</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_USB_DIS</name>
              <description>Write 1 to disable USB clock;</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_GPIO_DIS</name>
              <description>Write 1 to disable GPIO clock</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_BIV_DIS</name>
              <description>Write 1 to disable BIV APB clock include RTC BiV register.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_ADC_DIS</name>
              <description>Write 1 to disable ADC clock;</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_DAC_DIS</name>
              <description>Write 1 to disable DAC clock;</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_CS_DIS</name>
              <description>Write 1 to disable Cap sensor clock;</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_FSP_DIS</name>
              <description>Write 1 to disable FSP clock;</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_DMA_DIS</name>
              <description>Write 1 to disable DMA clock</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_QDEC0_DIS</name>
              <description>Write 1 to disable QDEC0 clock;</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_QDEC1_DIS</name>
              <description>Write 1 to disable QDEC1 clock;</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_DP_DIS</name>
              <description>Write 1 to disable Data Path 16/8MHz clock;</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_SPIFI_DIS</name>
              <description>Write 1 to disable SPIFI clock;</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_CAL_DIS</name>
              <description>Write 1 to disable Calibration clock;</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CLK_BLE_DIS</name>
              <description>Write 1 to disable BLE clock</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>PCLK_DIS</name>
              <description>Write 1 to disable PCLK of some logic;</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FCLK_DIS</name>
              <description>Write 1 to disable CPU FCLK;</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CLK_EN</name>
          <description>clock enable register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xC0001200</resetValue>
          <resetMask>0xEA7FFFFF</resetMask>
          <fields>
            <field>
              <name>CLK_FC0_EN</name>
              <description>Write 1 to enable FLEXCOMM0 clock</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_FC1_EN</name>
              <description>Write 1 to enable FLEXCOMM1 clock</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_FC2_EN</name>
              <description>Write 1 to enable FLEXCOMM2 clock</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_FC3_EN</name>
              <description>Write 1 to enable FLEXCOMM3 clock</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_TIM0_EN</name>
              <description>Write 1 to enable CTIMER0 clock</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_TIM1_EN</name>
              <description>Write 1 to enable CTIMER1 clock</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_TIM2_EN</name>
              <description>Write 1 to enable CTIMER2 clock</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_TIM3_EN</name>
              <description>Write 1 to enable CTIMER3 clock</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_SCT_EN</name>
              <description>Write 1 to enable SCT clock</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_WDT_EN</name>
              <description>Write 1 to enable Watch Dog clock</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_USB_EN</name>
              <description>Write 1 to enable USB clock;</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_GPIO_EN</name>
              <description>Write 1 to enable GPIO clock</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_BIV_EN</name>
              <description>Write 1 to enable BIV APB clock include RTC BiV register.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_ADC_EN</name>
              <description>Write 1 to enable ADC clock;</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_DAC_EN</name>
              <description>Write 1 to enable DAC clock;</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_CS_EN</name>
              <description>Write 1 to enable Cap sensor clock;</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_FSP_EN</name>
              <description>Write 1 to enable FSP clock;</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_DMA_EN</name>
              <description>Write 1 to enable DMA clock</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_QDEC0_EN</name>
              <description>Write 1 to enable QDEC0 clock;</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_QDEC1_EN</name>
              <description>Write 1 to enable QDEC1 clock;</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_DP_EN</name>
              <description>Write 1 to enable Data Path 16/8MHz clock;</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_SPIFI_EN</name>
              <description>Write 1 to enable SPIFI clock;</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_CAL_EN</name>
              <description>Write 1 to enable Calibration clock;</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLK_BLE_EN</name>
              <description>Write 1 to enable BLE clock</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLK_CTRL</name>
          <description>system clock source and divider register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x103C0000</resetValue>
          <resetMask>0xDFFFFFFF</resetMask>
          <fields>
            <field>
              <name>APB_DIV</name>
              <description>APB_CLK = AHB_CLK/(APB_DIV+1)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AHB_DIV</name>
              <description>AHB_CLK = SYS_CLK / (AHB_DIV+1);Note Before enable BLE clock (CLK_BLE_EN =1) It is mandatory to set AHB_CLK = 32 or 16 or 8 MHz.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>13</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_BLE_SEL</name>
              <description>BLE frequency indicator</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CLK_BLE_SEL_8M</name>
                  <description>BLE run at 8M</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLK_BLE_SEL_16M</name>
                  <description>BLE run at 16M</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_WDT_SEL</name>
              <description>Select Watch Dog clock</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CLK_WDT_SEL_32K</name>
                  <description>watch dog run at 32K</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>APB</name>
                  <description>watch dog run at APB clock</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_XTAL_SEL</name>
              <description>Crytal clock selection</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>XTAL16M</name>
                  <description>external crystal is 16M</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>XTAL32M</name>
                  <description>external crystal is 32M</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_OSC32M_DIV</name>
              <description>digital OSC clock input selection</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>BY1</name>
                  <description>use original 32M RCO clock</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BY2</name>
                  <description>divide 32M OSC clock into 16M</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_32K_SEL</name>
              <description>32K clock source selection</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>XTAL32K</name>
                  <description>digital 32K clock source is external 32K crystal</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RCO32K</name>
                  <description>digital 32K clock source is internal 32K RCO</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLK_XTAL_OE</name>
              <description>system clock output enable</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_32K_OE</name>
              <description>32K clock output enable</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_OUT_DIV</name>
              <description>high frequency xtal clock output divider</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CGBYPASS</name>
              <description>If it is 0, it can save CPU power in active mode</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SYS_CLK_SEL</name>
              <description>Select SYS_CLK source</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CLK_OSC</name>
                  <description>32M internal clock</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLK_XTAL</name>
                  <description>external crystal clock</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLK_32K</name>
                  <description>32K clock</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SYS_MODE_CTRL</name>
          <description>system mode and address remap register</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF000007</resetMask>
          <fields>
            <field>
              <name>REMAP</name>
              <description>software remap system address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ROM</name>
                  <description>address 0 is mapped to ROM</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>FLASH</name>
                  <description>address 0 is mapped to FLASH</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RAM</name>
                  <description>address 0 is mapped to RAM</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LOCKUP_EN</name>
              <description>lock up enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_RDY</name>
              <description>16/32 MHz xtal ready readout</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>XTAL32K_RDY</name>
              <description>32KHz xtal ready readout</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PLL48M_RDY</name>
              <description>48MHz PLL ready readout</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OSC32M_RDY</name>
              <description>32MHz oscillator ready readout</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BG_RDY</name>
              <description>BG ready readout</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BOOT_MODE</name>
              <description>boot mode pin status</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ISP</name>
                  <description>when BOOT_MODE pin is 0, bootloader enter ISP</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NORMAL</name>
                  <description>when BOOT_MODE pin is 1, bootloader jump to flash without ISP</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SYS_STAT</name>
          <description>system status register</description>
          <addressOffset>0x80</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x3000</resetValue>
          <resetMask>0xB0037FFF</resetMask>
          <fields>
            <field>
              <name>FREQ_WORD</name>
              <description>BLE Frequency word;</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BLE_FREQ_HOP</name>
              <description>BLE frequency word change flag;</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>EVENT_IN_PROCESS</name>
              <description>BLE event indicator</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>BLE_NONE_ENV</name>
                  <description>BLE is not in event process</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BLE_IN_ENV</name>
                  <description>BLE is in event process</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RX_EN</name>
              <description>when 1, system is in RX state</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_EN</name>
              <description>when 1, system is in TX state</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OSC_EN</name>
              <description>BLE osc_en output;</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RADIO_EN</name>
              <description>BLE radio_en output;</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CLK_STATUS</name>
              <description>BLE status</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>BLE_IP_ACT</name>
                  <description>BLE is active</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BLE_IP_SLP</name>
                  <description>BLE is in sleep mode</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SYS_TICK</name>
          <description>systick timer control register</description>
          <addressOffset>0x100</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x81000147</resetValue>
          <resetMask>0x83FFFFFF</resetMask>
          <fields>
            <field>
              <name>TENMS</name>
              <description>system tick timer calibration value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>24</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SKEW</name>
              <description>whether THE TENMS value will generate a precise 10 millisencod time or an approximation</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>PRECISE</name>
                  <description>TENMS is considered to be precise</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NOT_PRECISE</name>
                  <description>TENMS is not considered to be precise</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>NOREF</name>
              <description>whether an external reference clock is available</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>AVAILABLE</name>
                  <description>external reference clock is available</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NOT_AVAILABLE</name>
                  <description>external reference clock is not available</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EN_STCLKEN</name>
              <description>1 is enable STCLKEN;</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SRAM_CTRL</name>
          <description>Exchange memory base address register</description>
          <addressOffset>0x104</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x2400</resetValue>
          <resetMask>0x7FFF</resetMask>
          <fields>
            <field>
              <name>EM_BASE_ADDR</name>
              <description>Exchange memory base address in system memory. Default value is 9K word.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>15</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CHIP_ID</name>
          <description>chip id register</description>
          <addressOffset>0x108</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFC001010</resetValue>
          <resetMask>0xFC00FFFF</resetMask>
          <fields>
            <field>
              <name>CID0</name>
              <description>CHIP ID for manufacture fab</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CID1</name>
              <description>CHIP ID for product family</description>
              <bitOffset>3</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CID2</name>
              <description>CHIP ID for minor revision</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CID3</name>
              <description>CHIP ID for product ID</description>
              <bitOffset>8</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>QN9020</name>
                  <description>QN9020</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>QN9030</name>
                  <description>QN9030</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>QN9080</name>
                  <description>QN9080</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CID4</name>
              <description>CHIP ID for major revision</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>A</name>
                  <description>revision A</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>B</name>
                  <description>revision B</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>C</name>
                  <description>revision C</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>D</name>
                  <description>revision D</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MEM_OPTION</name>
              <description>memory bond indicator</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>MEM_OPTION_64K</name>
                  <description>chip memory size is 64K</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>MEM_OPTION_128K</name>
                  <description>chip memory size is 128K</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_OPTION</name>
              <description>adc bond indicator</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>LOW</name>
                  <description>adc low resolution</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH</name>
                  <description>adc high resolution</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FLASH_OPTION</name>
              <description>flash bond indicator</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>FLASH_OPTION_256K</name>
                  <description>chip flash size is 256K</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>FLASH_OPTION_512K</name>
                  <description>chip flash size is 512K</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FPU_OPTION</name>
              <description>fpu bond indicator</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NONE</name>
                  <description>fpu is not exist</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EXIST</name>
                  <description>fpu is exist</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>USB_OPTION</name>
              <description>usb bond indicator</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NONE</name>
                  <description>chip doesnot have USB</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EXIST</name>
                  <description>chip has USB</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FSP_OPTION</name>
              <description>fsp bond indicator</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NONE</name>
                  <description>chip doesnot have FSP</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EXIST</name>
                  <description>chip has FSP</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>ANA_CTRL0</name>
          <description>crystal and PA register</description>
          <addressOffset>0x110</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x820007F</resetValue>
          <resetMask>0xDFF000FF</resetMask>
          <fields>
            <field>
              <name>PA_POWER</name>
              <description>PA power control (all of below is minus data)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>PA_POWER_20DBM</name>
                  <description>20dBm</description>
                  <value>0x10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PA_POWER_18DBM</name>
                  <description>18dBm</description>
                  <value>0x12</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PA_POWER_16DBM</name>
                  <description>16dBm</description>
                  <value>0x14</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PA_POWER_14DBM</name>
                  <description>14dBm</description>
                  <value>0x19</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PA_POWER_12DBM</name>
                  <description>12dBm</description>
                  <value>0x20</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PA_POWER_10DBM</name>
                  <description>10dBm</description>
                  <value>0x28</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PA_POWER_8DBM</name>
                  <description>8dBm</description>
                  <value>0x32</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PA_POWER_6DBM</name>
                  <description>6dBm</description>
                  <value>0x40</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PA_POWER_4DBM</name>
                  <description>4dBm</description>
                  <value>0x50</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PA_POWER_2DBM</name>
                  <description>2dBm</description>
                  <value>0x65</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PA_POWER_0DBM</name>
                  <description>0dBm</description>
                  <value>0x7F</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>XTAL_AMP</name>
              <description>crystal amplitude set register</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_LOAD_CAP</name>
              <description>Register controlled load cap of the XTAL in normal modeLOAD_CAP=5pF+0.35pF*CSEL+5pF*XADD_C</description>
              <bitOffset>22</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_EXTRA_CAP</name>
              <description>Add extra 16/32 MHz xtal load cap</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_MODE</name>
              <description>Injection mode of the XTAL</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>XTAL</name>
                  <description>High frequency crystal oscillator</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DIG</name>
                  <description>Inject digital clock</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SINGLE</name>
                  <description>Inject single-end sine-wave signal</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DIFF</name>
                  <description>inject differential sine-wave signal</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>XTAL_CTRL</name>
          <description>crystal control register</description>
          <addressOffset>0x180</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x20200800</resetValue>
          <resetMask>0xFF3F0FE0</resetMask>
          <fields>
            <field>
              <name>XTAL_XCUR_BOOST_REG</name>
              <description>1 to increase 16/32 MHz xtal current</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_BPXDLY</name>
              <description>Bypass the power up delay in the XTAL core.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_BP_HYSRES_REG</name>
              <description>1 to bypass the degeneration resistor in order to reduce the hysteresis voltage</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_XSMT_EN_REG</name>
              <description>1 to use hysteresis buffer</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_XRDY_REG</name>
              <description>1 to set xtal ready signal by register</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_XOUT_DIS_REG</name>
              <description>1 not to send 16/32 MHz xtal clk out</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DIV_DIFF_CLK_DIG_DIS</name>
              <description>disable differential clock of digital</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_SU_CB_REG</name>
              <description>Register controlled load cap of the XTAL_B in speed up modeCB=2pF+0.35pF*SU_CB+5pF*XADD_C</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_SU_CA_REG</name>
              <description>Register controlled load cap of the XTAL_A in speed up modeCA=2pF+0.35pF*SU_CA+5pF*XADD_C</description>
              <bitOffset>24</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_INV</name>
              <description>Inverse crystal clock</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_DIV</name>
              <description>Divide crystal clock when external crystal is 32M this bit should be configured into 1 otherwise 0.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BUCK</name>
          <description>buck control register</description>
          <addressOffset>0x184</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x302B03</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>BUCK_DRIVER_PART_EN</name>
              <description>1 to short external inductor</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUCK_IND_USE_EN</name>
              <description>1 to turn on buck output stage gradually</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUCK_ISEL</name>
              <description>buck current bias control</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUCK_VREF_SEL</name>
              <description>buck current setting</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUCK_VBG_SEL</name>
              <description>buck reference setting</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUCK_TMOS</name>
              <description>buck constant on time control</description>
              <bitOffset>16</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUCK_IC</name>
              <description>frequency compensation versus BVDD variation</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FC_FRG</name>
          <description>flexcomm 0 and 1 clock divider register</description>
          <addressOffset>0x200</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFF00FF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FRG_DIV0</name>
              <description>flexcomm0 clock generator, Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FRG_MULT0</name>
              <description>flexcomm0 clock generator, Numerator of the fractional divider. MULT is equal to the programmed value</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FRG_DIV1</name>
              <description>flexcomm1 clock generator, Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FRG_MULT1</name>
              <description>flexcomm1 clock generator, Numerator of the fractional divider. MULT is equal to the programmed value</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_PULL_CFG0</name>
          <description>pad pull control register 0</description>
          <addressOffset>0x800</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xAAAAAAAA</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA00_PULL</name>
              <description>PA00 pull control register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA01_PULL</name>
              <description>PA01 pull control register</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA02_PULL</name>
              <description>PA02 pull control register</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA03_PULL</name>
              <description>PA03 pull control register</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA04_PULL</name>
              <description>PA04 pull control register</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA05_PULL</name>
              <description>PA05 pull control register</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA06_PULL</name>
              <description>PA06 pull control register</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA07_PULL</name>
              <description>PA07 pull control register</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA08_PULL</name>
              <description>PA08 pull control register</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA09_PULL</name>
              <description>PA09 pull control register</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA10_PULL</name>
              <description>PA10 pull control register</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA11_PULL</name>
              <description>PA11 pull control register</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA12_PULL</name>
              <description>PA12 pull control register</description>
              <bitOffset>24</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA13_PULL</name>
              <description>PA13 pull control register</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA14_PULL</name>
              <description>PA14 pull control register</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA15_PULL</name>
              <description>PA15 pull control register</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_PULL_CFG1</name>
          <description>pad pull control register 1</description>
          <addressOffset>0x804</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xAAAAAAAA</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA16_PULL</name>
              <description>PA16 pull control register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA17_PULL</name>
              <description>PA17 pull control register</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA18_PULL</name>
              <description>PA18 pull control register</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA19_PULL</name>
              <description>PA19 pull control register</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA20_PULL</name>
              <description>PA20 pull control register</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA21_PULL</name>
              <description>PA21 pull control register</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA22_PULL</name>
              <description>PA22 pull control register</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA23_PULL</name>
              <description>PA23 pull control register</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA24_PULL</name>
              <description>PA24 pull control register</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA25_PULL</name>
              <description>PA25 pull control register</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA26_PULL</name>
              <description>PA26 pull control register</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA27_PULL</name>
              <description>PA27 pull control register</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA28_PULL</name>
              <description>PA28 pull control register</description>
              <bitOffset>24</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA29_PULL</name>
              <description>PA29 pull control register</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA30_PULL</name>
              <description>PA30 pull control register</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA31_PULL</name>
              <description>PA31 pull control register</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_PULL_CFG2</name>
          <description>pad pull control register 2</description>
          <addressOffset>0x808</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x2A</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PB00_PULL</name>
              <description>PB00 pull control register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PB01_PULL</name>
              <description>PB01 pull control register</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PB02_PULL</name>
              <description>PB02 pull control register</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IO_CAP</name>
          <description>io status capture register</description>
          <addressOffset>0x80C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>PIN_RETENTION</name>
              <description>Write 1 to capture pad output and output enable and the status will be saved in PIN_SLP_OEN0 PIN_SLP_OEN1 PIN_SLP_OUT0 and PIN_SLP_OUT1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_DRV_CFG0</name>
          <description>pad drive strength register 0</description>
          <addressOffset>0x810</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA00_DRV</name>
              <description>PA00 drive strength register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA01_DRV</name>
              <description>PA01 drive strength register</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA02_DRV</name>
              <description>PA02 drive strength register</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA03_DRV</name>
              <description>PA03 drive strength register</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA04_DRV</name>
              <description>PA04 drive strength register</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA05_DRV</name>
              <description>PA05 drive strength register</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA06_DRV</name>
              <description>PA06 drive strength register</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA07_DRV</name>
              <description>PA07 drive strength register</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA08_DRV</name>
              <description>PA08 drive strength register</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA09_DRV</name>
              <description>PA09 drive strength register</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA10_DRV</name>
              <description>PA10 drive strength register</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA11_DRV</name>
              <description>PA11 drive strength register</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA12_DRV</name>
              <description>PA12 drive strength register</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA13_DRV</name>
              <description>PA13 drive strength register</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA14_DRV</name>
              <description>PA14 drive strength register</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA15_DRV</name>
              <description>PA15 drive strength register</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA16_DRV</name>
              <description>PA16 drive strength register</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA17_DRV</name>
              <description>PA17 drive strength register</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA18_DRV</name>
              <description>PA18 drive strength register</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA19_DRV</name>
              <description>PA19 drive strength register</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA20_DRV</name>
              <description>PA20 drive strength register</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA21_DRV</name>
              <description>PA21 drive strength register</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA22_DRV</name>
              <description>PA22 drive strength register</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA23_DRV</name>
              <description>PA23 drive strength register</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA24_DRV</name>
              <description>PA24 drive strength register</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA25_DRV</name>
              <description>PA25 drive strength register</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA26_DRV</name>
              <description>PA26 drive strength register</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA27_DRV</name>
              <description>PA27 drive strength register</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA28_DRV</name>
              <description>PA28 drive strength register</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA29_DRV</name>
              <description>PA29 drive strength register</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA30_DRV</name>
              <description>PA30 drive strength register</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA31_DRV</name>
              <description>PA31 drive strength register</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_DRV_CFG1</name>
          <description>pad drive strength register 1</description>
          <addressOffset>0x814</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PB00_DRV</name>
              <description>PB00 drive strengh register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PB01_DRV</name>
              <description>PB01 drive strengh register</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PB02_DRV</name>
              <description>PB02 drive strengh register</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_DRV_CFG2</name>
          <description>pad drive extra register</description>
          <addressOffset>0x818</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA06_DRV_EXTRA</name>
              <description>Write 1 to enable extra driven on PA06</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA11_DRV_EXTRA</name>
              <description>Write 1 to enable extra driven on PA11</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA19_DRV_EXTRA</name>
              <description>Write 1 to enable extra driven on PA19</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA26_DRV_EXTRA</name>
              <description>Write 1 to enable extra driven on PA26</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA27_DRV_EXTRA</name>
              <description>Write 1 to enable extra driven on PA27</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_CFG_MISC</name>
          <description>pin misc control register</description>
          <addressOffset>0x81C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x3</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PB00_AE</name>
              <description>Enable PB00 analog function</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PB01_AE</name>
              <description>Enable PB01 analog function</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PSYNC</name>
              <description>when 1, bypass first stage of synchronization of DMA pin trigger</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PB02_MODE</name>
              <description>chip mode pin function select</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>BOOT_MODE</name>
                  <description>PB02 is used as chip mode input</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ANTENNA</name>
                  <description>PB02 is used as antena output</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TRX_EN_INV</name>
              <description>inverse TX_EN &amp;amp; RX_EN pin mux output polarity</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>TRX_EN_POL</name>
                  <description>inverse TX_EN &amp;amp; RX_EN pin mux output polarity</description>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RFE_INV</name>
              <description>Inverse RFE polarity</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RFE_POL</name>
                  <description>Inverse RFE polarity</description>
                  <value>0</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_WAKEUP_LVL0</name>
          <description>pin wakeup polarity register 0</description>
          <addressOffset>0x820</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA00_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA00 in sleep mode. 0: high level wakeup, 1: low level wakeup</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA01_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA01 in sleep mode.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA02_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA02 in sleep mode.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA03_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA03 in sleep mode.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA04_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA04 in sleep mode.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA05_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA05 in sleep mode.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA06_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA06 in sleep mode.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA07_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA07 in sleep mode.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA08_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA08 in sleep mode.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA09_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA09 in sleep mode.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA10_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA10 in sleep mode.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA11_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA11 in sleep mode.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA12_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA12 in sleep mode.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA13_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA13 in sleep mode.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA14_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA14 in sleep mode.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA15_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA15 in sleep mode.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA16_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA16 in sleep mode.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA17_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA17 in sleep mode.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA18_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA18 in sleep mode.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA19_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA19 in sleep mode.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA20_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA20 in sleep mode.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA21_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA21 in sleep mode.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA22_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA22 in sleep mode.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA23_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA23 in sleep mode.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA24_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA24 in sleep mode.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA25_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA25 in sleep mode.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA26_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA26 in sleep mode.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA27_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA27 in sleep mode.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA28_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA28 in sleep mode.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA29_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA29 in sleep mode.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA30_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA30 in sleep mode.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA31_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PA31 in sleep mode.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_WAKEUP_LVL1</name>
          <description>pin wakeup polarity register 1</description>
          <addressOffset>0x824</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x7</resetMask>
          <fields>
            <field>
              <name>PB00_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PB01 in sleep mode.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PB01_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PB02 in sleep mode.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PB02_WAKEUP_LVL</name>
              <description>Control the wake up polarity of PB03 in sleep mode.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_IE_CFG0</name>
          <description>pad input enable register 0</description>
          <addressOffset>0x828</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA00_IE</name>
              <description>PA00 digital input enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA01_IE</name>
              <description>PA01 digital input enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA02_IE</name>
              <description>PA02 digital input enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA03_IE</name>
              <description>PA03 digital input enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA04_IE</name>
              <description>PA04 digital input enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA05_IE</name>
              <description>PA05 digital input enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA06_IE</name>
              <description>PA06 digital input enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA07_IE</name>
              <description>PA07 digital input enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA08_IE</name>
              <description>PA08 digital input enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA09_IE</name>
              <description>PA09 digital input enable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA10_IE</name>
              <description>PA10 digital input enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA11_IE</name>
              <description>PA11 digital input enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA12_IE</name>
              <description>PA12 digital input enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA13_IE</name>
              <description>PA13 digital input enable</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA14_IE</name>
              <description>PA14 digital input enable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA15_IE</name>
              <description>PA15 digital input enable</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA16_IE</name>
              <description>PA16 digital input enable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA17_IE</name>
              <description>PA17 digital input enable</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA18_IE</name>
              <description>PA18 digital input enable</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA19_IE</name>
              <description>PA19 digital input enable</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA20_IE</name>
              <description>PA20 digital input enable</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA21_IE</name>
              <description>PA21 digital input enable</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA22_IE</name>
              <description>PA22 digital input enable</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA23_IE</name>
              <description>PA23 digital input enable</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA24_IE</name>
              <description>PA24 digital input enable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA25_IE</name>
              <description>PA25 digital input enable</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA26_IE</name>
              <description>PA26 digital input enable</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA27_IE</name>
              <description>PA27 digital input enable</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA28_IE</name>
              <description>PA28 digital input enable</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA29_IE</name>
              <description>PA29 digital input enable</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA30_IE</name>
              <description>PA30 digital input enable</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA31_IE</name>
              <description>PA31 digital input enable</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_IE_CFG1</name>
          <description>pad input enable register 1</description>
          <addressOffset>0x82C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x7</resetValue>
          <resetMask>0x7</resetMask>
          <fields>
            <field>
              <name>PB00_IE</name>
              <description>PB00 digital input enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PB01_IE</name>
              <description>PB01 digital input enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BOOT_MODE_IE</name>
              <description>PB02 input enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_FUNC_CFG0</name>
          <description>pin mux control register 0</description>
          <addressOffset>0x830</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA00_FUNC</name>
              <description>PA00 function control register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA01_FUNC</name>
              <description>PA01 function control register</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA02_FUNC</name>
              <description>PA02 function control register</description>
              <bitOffset>8</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA03_FUNC</name>
              <description>PA03 function control register</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA04_FUNC</name>
              <description>PA04 function control register</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA05_FUNC</name>
              <description>PA05 function control register</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA06_FUNC</name>
              <description>PA06 function control register</description>
              <bitOffset>24</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA07_FUNC</name>
              <description>PA07 function control register</description>
              <bitOffset>28</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_FUNC_CFG1</name>
          <description>pin mux control register 1</description>
          <addressOffset>0x834</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA08_FUNC</name>
              <description>PA08 function control register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA09_FUNC</name>
              <description>PA09 function control register</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA10_FUNC</name>
              <description>PA10 function control register</description>
              <bitOffset>8</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA11_FUNC</name>
              <description>PA11 function control register</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA12_FUNC</name>
              <description>PA12 function control register</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA13_FUNC</name>
              <description>PA13 function control register</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA14_FUNC</name>
              <description>PA14 function control register</description>
              <bitOffset>24</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA15_FUNC</name>
              <description>PA15 function control register</description>
              <bitOffset>28</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_FUNC_CFG2</name>
          <description>pin mux control register 2</description>
          <addressOffset>0x838</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA16_FUNC</name>
              <description>PA16 function control register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA17_FUNC</name>
              <description>PA17 function control register</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA18_FUNC</name>
              <description>PA18 function control register</description>
              <bitOffset>8</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA19_FUNC</name>
              <description>PA19 function control register</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA20_FUNC</name>
              <description>PA20 function control register</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA21_FUNC</name>
              <description>PA21 function control register</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA22_FUNC</name>
              <description>PA22 function control register</description>
              <bitOffset>24</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA23_FUNC</name>
              <description>PA23 function control register</description>
              <bitOffset>28</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_FUNC_CFG3</name>
          <description>pin mux control register 3</description>
          <addressOffset>0x83C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA24_FUNC</name>
              <description>PA24 function control register</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA25_FUNC</name>
              <description>PA25 function control register</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA26_FUNC</name>
              <description>PA26 function control register</description>
              <bitOffset>8</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA27_FUNC</name>
              <description>PA27 function control register</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA28_FUNC</name>
              <description>PA28 function control register</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA29_FUNC</name>
              <description>PA29 function control register</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA30_FUNC</name>
              <description>PA30 function control register</description>
              <bitOffset>24</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA31_FUNC</name>
              <description>PA31 function control register</description>
              <bitOffset>28</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_WAKEUP_EN0</name>
          <description>pin function selection in power down mode register 0</description>
          <addressOffset>0x840</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA00_WAKEUP_EN</name>
              <description>Control GPIOA[31-0] as Wakeup source.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA01_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA02_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA03_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA04_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA05_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA06_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA07_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA08_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA09_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA10_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA11_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA12_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA13_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA14_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA15_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA16_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA17_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA18_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA19_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA20_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA21_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA22_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA23_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA24_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA25_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA26_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA27_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA28_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA29_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA30_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA31_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_WAKEUP_EN1</name>
          <description>pin function selection in power down mode register 1</description>
          <addressOffset>0x844</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x830C0C37</resetMask>
          <fields>
            <field>
              <name>PB00_WAKEUP_EN</name>
              <description>Control GPIOB as Wakeup source.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PB01_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PB02_WAKEUP_EN</name>
              <description>no description available</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA04_32K_OE</name>
              <description>32K clock output enable. When this bit is set to 1 PA04 will output 32k clock. At this time PIN_CTRL register is not effective to control this IO's function.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA05_XTAL_OE</name>
              <description>XTAL clock output enable. When this bit is set to 1 PA05 will output XTAL clock. At this time PIN_CTRL register is not effective to control this IO's function.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA10_32K_OE</name>
              <description>32K clock output enable. When this bit is set to 1 PA10 (GPIO10) will output 32k clock. At this time PIN_CTRL register is not effective to control this IO's function.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA11_XTAL_OE</name>
              <description>XTAL clock output enable. When this bit is set to 1 PA11 will output XTAL clock. At this time PIN_CTRL register is not effective to control this IO's function.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA18_32K_OE</name>
              <description>32K clock output enable. When this bit is set to 1 PA18 will output 32k clock. At this time PIN_CTRL register is not effective to control this IO's function.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA19_XTAL_OE</name>
              <description>XTAL clock output enable. When this bit is set to 1 PA19 will output XTAL clock. At this time PIN_CTRL register is not effective to control this IO's function.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA24_32K_OE</name>
              <description>32K clock output enable. When this bit is set to 1 PA24 will output 32k clock. At this time PIN_CTRL register is not effective to control this IO's function.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA25_XTAL_OE</name>
              <description>XTAL clock output enable. When this bit is set to 1 PA25 will output XTAL clock. At this time PIN_CTRL register is not effective to control this IO's function.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PDM_IO_SEL</name>
              <description>pin status selection in power down mode</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_CAP_OE0</name>
          <description>pin output enable status register 0 while captured by writing 1 to IO_CAP</description>
          <addressOffset>0x848</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA00_CAP_OE</name>
              <description>PA00 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA01_CAP_OE</name>
              <description>PA01 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA02_CAP_OE</name>
              <description>PA02 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA03_CAP_OE</name>
              <description>PA03 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA04_CAP_OE</name>
              <description>PA04 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA05_CAP_OE</name>
              <description>PA05 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA06_CAP_OE</name>
              <description>PA06 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA07_CAP_OE</name>
              <description>PA07 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA08_CAP_OE</name>
              <description>PA08 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA09_CAP_OE</name>
              <description>PA09 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA10_CAP_OE</name>
              <description>PA10 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA11_CAP_OE</name>
              <description>PA11 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA12_CAP_OE</name>
              <description>PA12 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA13_CAP_OE</name>
              <description>PA13 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA14_CAP_OE</name>
              <description>PA14 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA15_CAP_OE</name>
              <description>PA15 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA16_CAP_OE</name>
              <description>PA16 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA17_CAP_OE</name>
              <description>PA17 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA18_CAP_OE</name>
              <description>PA18 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA19_CAP_OE</name>
              <description>PA19 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA20_CAP_OE</name>
              <description>PA20 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA21_CAP_OE</name>
              <description>PA21 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA22_CAP_OE</name>
              <description>PA22 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA23_CAP_OE</name>
              <description>PA23 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA24_CAP_OE</name>
              <description>PA24 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA25_CAP_OE</name>
              <description>PA25 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA26_CAP_OE</name>
              <description>PA26 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA27_CAP_OE</name>
              <description>PA27 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA28_CAP_OE</name>
              <description>PA28 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA29_CAP_OE</name>
              <description>PA29 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA30_CAP_OE</name>
              <description>PA30 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA31_CAP_OE</name>
              <description>PA31 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_CAP_OE1</name>
          <description>pin output enable status register 1 while captured by writing 1 to IO_CAP</description>
          <addressOffset>0x84C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x7</resetMask>
          <fields>
            <field>
              <name>PB00_CAP_OE</name>
              <description>PB00 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PB01_CAP_OE</name>
              <description>PB01 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PB02_CAP_OE</name>
              <description>PB02 output enable status captured by writing 1 to IO_CAP</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_CAP_OUT0</name>
          <description>pin output status register 0 while captured by writing 1 to IO_CAP</description>
          <addressOffset>0x850</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PA00_CAP_OUT</name>
              <description>PA00 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA01_CAP_OUT</name>
              <description>PA01 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA02_CAP_OUT</name>
              <description>PA02 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA03_CAP_OUT</name>
              <description>PA03 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA04_CAP_OUT</name>
              <description>PA04 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA05_CAP_OUT</name>
              <description>PA05 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA06_CAP_OUT</name>
              <description>PA06 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA07_CAP_OUT</name>
              <description>PA07 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA08_CAP_OUT</name>
              <description>PA08 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA09_CAP_OUT</name>
              <description>PA09 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA10_CAP_OUT</name>
              <description>PA10 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA11_CAP_OUT</name>
              <description>PA11 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA12_CAP_OUT</name>
              <description>PA12 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA13_CAP_OUT</name>
              <description>PA13 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA14_CAP_OUT</name>
              <description>PA14 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA15_CAP_OUT</name>
              <description>PA15 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA16_CAP_OUT</name>
              <description>PA16 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA17_CAP_OUT</name>
              <description>PA17 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA18_CAP_OUT</name>
              <description>PA18 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA19_CAP_OUT</name>
              <description>PA19 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA20_CAP_OUT</name>
              <description>PA20 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA21_CAP_OUT</name>
              <description>PA21 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA22_CAP_OUT</name>
              <description>PA22 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA23_CAP_OUT</name>
              <description>PA23 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA24_CAP_OUT</name>
              <description>PA24 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA25_CAP_OUT</name>
              <description>PA25 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA26_CAP_OUT</name>
              <description>PA26 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA27_CAP_OUT</name>
              <description>PA27 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA28_CAP_OUT</name>
              <description>PA28 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA29_CAP_OUT</name>
              <description>PA29 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA30_CAP_OUT</name>
              <description>PA30 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PA31_CAP_OUT</name>
              <description>PA31 output status captured by writing 1 to IO_CAP</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PIO_CAP_OUT1</name>
          <description>pin output status register 0 while captured by writing 1 to IO_CAP</description>
          <addressOffset>0x854</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x7</resetMask>
          <fields>
            <field>
              <name>PB00_CAP_OUT</name>
              <description>PB00 output status while captured by writing 1 to IO_CAP</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PB01_CAP_OUT</name>
              <description>PB01 output status while captured by writing 1 to IO_CAP</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PB02_CAP_OUT</name>
              <description>PB02 output status while captured by writing 1 to IO_CAP</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RST_CAUSE_SRC</name>
          <description>reset source status register</description>
          <addressOffset>0x858</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FF</resetMask>
          <fields>
            <field>
              <name>RESET_CAUSE</name>
              <description>reset source indicator. xxxxxxxx1b = Power-on Reset; xxxxxxx1xb = Brown-Down Reset; xxxxxx1xxb = External pin Reset; xxxxx1xxxb = Watch Dog Reset; xxxx1xxxxb = Lock Up Reset; xxx1xxxxxb = Reboot Reset; xx1000000b = CPU system Reset requirement; x10000000b = Wake Up reset 10000000b = CPU software Reset;</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RST_CAUSE_CLR</name>
              <description>Write '1' clear RESET_CAUSE bits;</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PMU_CTRL0</name>
          <description>power management uinit control register 0</description>
          <addressOffset>0x85C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x80000000</resetValue>
          <resetMask>0xFC1703FF</resetMask>
          <fields>
            <field>
              <name>MEM0_DIS</name>
              <description>power down sram memory block 0</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM1_DIS</name>
              <description>power down sram memory block 1</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM2_DIS</name>
              <description>power down sram memory block 2</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM3_DIS</name>
              <description>power down sram memory block 3</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM4_DIS</name>
              <description>power down sram memory block 4</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM5_DIS</name>
              <description>power down sram memory block 5</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM6_DIS</name>
              <description>power down sram memory block 6</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM7_DIS</name>
              <description>power down sram memory block 7</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM8_DIS</name>
              <description>power down sram memory block 8</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM9_DIS</name>
              <description>power down sram memory block 9</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BLE_DIS</name>
              <description>power down BLE</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_DIS</name>
              <description>power down FIR buffer</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FSP_DIS</name>
              <description>power down FSP</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MCU_MODE</name>
              <description>power control of BG, V2I, VREG_A, VREG_D</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ANA_PWRON</name>
                  <description>power on BG, V2I, VREG_A, VREG_D</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ANA_PWROFF</name>
                  <description>power off BG, V2I, VREG_A, VREG_D</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OSC_INT_EN</name>
              <description>1 to enable OSC_EN as interrupt and wakeup source</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RTC_SEC_WAKEUP_EN</name>
              <description>1 to enable RTC interrupt as wakeup source</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WAKEUP_EN</name>
              <description>1 to enable sleep wake up source</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PMU_EN</name>
              <description>1 to enable chip power down mode</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RETENTION_EN</name>
              <description>1 to enable all CPU registers to be retentioned in sleep mode</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BOND_EN</name>
              <description>1 to enable FSP_BOND_EN bond option</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PMU_CTRL1</name>
          <description>power management uinit control register 1</description>
          <addressOffset>0x860</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFF0</resetValue>
          <resetMask>0xC30F0FFF</resetMask>
          <fields>
            <field>
              <name>RCO32K_DIS</name>
              <description>1 to switch off 32K RCO power</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL32K_DIS</name>
              <description>1 to switch off 32K XTAL power</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_DIS</name>
              <description>1 to switch off XTAL of digital power</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OSC32M_DIS</name>
              <description>1 to switch off 32M OSC power</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USBPLL_DIS</name>
              <description>1 to switch off USB 48M PLL power</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_BUF_DIS</name>
              <description>1 to switch off buffer in SD ADC</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_BG_DIS</name>
              <description>1 to switch off bandgap in SD ADC</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_DIS</name>
              <description>1 to switch off SD ADC</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_VCM_DIS</name>
              <description>1 to switch off VCM DRV in SD ADC</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_VREF_DIS</name>
              <description>1 to switch off VREF DRV in SD ADC</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DAC_DIS</name>
              <description>1 to switch off DAC</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP_SEN_DIS</name>
              <description>1 to switch off CAP_SEN</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUCK_CTRL</name>
              <description>BUCK power control, 0x00 to power on, and 0x0F to power down</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RCO32K_PDM_DIS</name>
              <description>In sleep mode this bit ORs with DIS_RCO_32K to control the RCO 32K power</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL32K_PDM_DIS</name>
              <description>In sleep mode this bit ORs with DIS_XTAL32K to control the XTAL32 power</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANA_EN</name>
          <description>analog setting register</description>
          <addressOffset>0x864</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF7FFF7F</resetMask>
          <fields>
            <field>
              <name>BOD_AMP_EN</name>
              <description>Enable the AMP of browned out detector</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BOD_EN</name>
              <description>Enable browned out detector</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BAT_MON_EN</name>
              <description>Enable battery monitor</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ACMP0_EN</name>
              <description>Enable comparator 0</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ACMP1_EN</name>
              <description>Enable comparator 1</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BOR_AMP_EN</name>
              <description>Enable the AMP of browned reset detector</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BOR_EN</name>
              <description>Enable browned reset detector</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ACMP0_REF</name>
              <description>acmp0 reference voltage selection, vref0=Acmp_vref*ACMP0_REF/16</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ACMP1_REF</name>
              <description>acmp1 reference voltage selection, vref1=Acmp_vref*ACMP1_REF/16</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ACMP0_HYST_EN</name>
              <description>Hysteresis enable of ACMP0 when 1</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ACMP1_HYST_EN</name>
              <description>Hysteresis enable of ACMP1 when 1</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ACMP_VREF_SEL</name>
              <description>Acmp_vref selection</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BOD_THR</name>
              <description>Browned-out detector threshold voltages, when VDD is lower than this voltage, BOD_OUT interrupt happens. And the detector has a hysteresis.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>BOD_THR0</name>
                  <description>trigger at 2.06V, with 295mV hysteresis</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BOD_THR1</name>
                  <description>trigger at 2.45V, with 350mV hysteresis</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BOD_THR2</name>
                  <description>trigger at 2.72V, with 388mV hysteresis</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BOD_THR3</name>
                  <description>trigger at 3.04V, with 435mV hysteresis</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BOR_THR</name>
              <description>Browned-out reset threshold voltages</description>
              <bitOffset>21</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>BOR_THR0</name>
                  <description>trigger at 1.5V</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BOR_THR1</name>
                  <description>trigger at 1.85V</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BOR_THR2</name>
                  <description>trigger at 2V</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BOR_THR3</name>
                  <description>trigger at 2.3V</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ACMP0_OUT</name>
              <description>Comparator 0 output.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ACMP1_OUT</name>
              <description>Comparator 1 output.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ACMP0_EDGE_SEL</name>
              <description>ACMP0 interrupt edge selection</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>POSEDGE</name>
                  <description>posedge</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NEGEDGE</name>
                  <description>negedge</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BOTHEDGE</name>
                  <description>both edge</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ACMP1_EDGE_SEL</name>
              <description>ACMP1 interrupt edge selection</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ACMP0_INTEN</name>
              <description>1 to enable ACMP0 interrupt</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ACMP1_INTEN</name>
              <description>1 to enable ACMP1 interrupt</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>XTAL32K_CTRL</name>
          <description>crystal 32K control register</description>
          <addressOffset>0x868</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x3023</resetValue>
          <resetMask>0x7FFF</resetMask>
          <fields>
            <field>
              <name>XTAL32K_ICTRL</name>
              <description>Xtal 32 gm cell current bias Y</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL32K_INJ</name>
              <description>Xtal 32KHz clk injection mode1xb = external sine wave clock</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ONCHIP_OSC</name>
                  <description>on-chip oscillator</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EXT_DIG_CLK</name>
                  <description>external digital clock</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>XTAL32K_LOAD_CAP</name>
              <description>load cap selection of xtal32</description>
              <bitOffset>8</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL32K_EXTRA_CAP</name>
              <description>add extra xtal32 load cap</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USB_CFG</name>
          <description>USB configuration register</description>
          <addressOffset>0x86C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x32</resetValue>
          <resetMask>0x3B</resetMask>
          <fields>
            <field>
              <name>DPPUEN_B_PHY_POL</name>
              <description>drive high to inverse the polarity of the connection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DPPUEN_B_PHY_SEL</name>
              <description>The control source selection for pull-up resistor</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>BY_REG</name>
                  <description>connection controlled by register</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BY_USBCTRL</name>
                  <description>connection controlled by USB controller</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>USB_VBUS</name>
              <description>USB connection voltage selection</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>USB_PHYSTDBY</name>
              <description>1 to enable USB_PHY in standby mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ON</name>
                  <description>USB PHY power is on</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>OFF</name>
                  <description>USB PHY power is off</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>USB_PHYSTDBY_WEN</name>
              <description>1 to enable USB_PHYSTDBY control by register</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PMU_CTRL2</name>
          <description>power management uinit control register 2</description>
          <addressOffset>0x880</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x403FF0FF</resetValue>
          <resetMask>0xF03FFFFF</resetMask>
          <fields>
            <field>
              <name>BG_PDM_DIS</name>
              <description>1 to power down bandcap in power down mode</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>V2I_PDM_DIS</name>
              <description>1 to power down V2I in power down mode</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VREG_A_PDM_DIS</name>
              <description>1 to power down VREG_A in power down mode</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VREG_D_PDM_DIS</name>
              <description>1 to power down VREG_D in power down mode</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL_PDM_DIS</name>
              <description>1 to power down XTAL in power down mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OSC32M_PDM_DIS</name>
              <description>1 to power down OSC32M in power down mode</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RFAGC_ON</name>
              <description>1 to enable RFAGC</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_EN_SEL</name>
              <description>RX_EN width selection</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>EX_NOISE</name>
                  <description>exclude noise phase</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>IN_NOISE</name>
                  <description>include noise phase</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BG_DIS</name>
              <description>1 to switch off bandcap power</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>V2I_DIS</name>
              <description>1 to switch off V2I power</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VREG_A_DIS</name>
              <description>1 to switch off VREG_A power</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VREG_D_DIS</name>
              <description>1 to switch off VREG_D power</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LO_DIS</name>
              <description>1 to switch off LO power</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_DIS</name>
              <description>1 to switch off VCO power</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA_PK_DIS</name>
              <description>1 to switch off PA peek detector power</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA_DIS</name>
              <description>1 to switch off PA power</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LNA_DIS</name>
              <description>1 to switch off LNA power</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MIXER_DIS</name>
              <description>1 to switch off MIXER power</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PKDET_DIS</name>
              <description>1 to switch off RRF and PPF peek detector power</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PPF_DIS</name>
              <description>1 to switch off PPF power</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SAR_DIS</name>
              <description>1 to switch off SAR ADC power</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RC_CAL_DIS</name>
              <description>1 to switch off RCCAL power</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLSH_DIS</name>
              <description>1 to switch off flash power</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLSH_PDM_DIS</name>
              <description>1 to power down flash VDD25 in power down mode</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SEL_PD</name>
              <description>power control selection</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>HW_PWR</name>
                  <description>hardware control power</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SW_PWR</name>
                  <description>software control power</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>ANA_CTRL1</name>
          <description>IVREF and DVREG setting register</description>
          <addressOffset>0x884</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xE4D98000</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>VDD_PMU_SET_PDM</name>
              <description>Vdd_pmu while in power down</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VDD_PMU_SET</name>
              <description>Vdd_pmu while wakeup</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VDD_MEM_SET_PDM</name>
              <description>Vdd_mem while in power down mode</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VDD_MEM_SET</name>
              <description>Vdd_mem while wakeup</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VDD_PMU_SET_EXTRA</name>
              <description>extra high setting for vdd_pmu</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VDD_MEM_SET_EXTRA</name>
              <description>extra high setting for vdd_mem</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VDD_PMU_SET_ULTRA_LOW</name>
              <description>ultra low setting for vdd_pmu</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VDD_PMU_MEM_SW</name>
              <description>1 to close the switch betwwen vdd_omu and vdd_mem</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IV_BG_SEL</name>
              <description>VBG voltage select-</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PDM_DIS_BUCK</name>
              <description>1 to power off buck in power down mode</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUCK_PD_CCM</name>
              <description>0 buck in CCM mode</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUCK_PD_DCM</name>
              <description>0 buck in DCM mode</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IV_IREF_SEL</name>
              <description>Reference current select</description>
              <bitOffset>19</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IV_VREG11_SET</name>
              <description>VREG11 setting</description>
              <bitOffset>21</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTAL32K_FORCE_RDY</name>
              <description>Xtal32k ready from register</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>X32_SMT_EN</name>
              <description>1 to enable schmidt trigger in xtal32</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BM_X32BUF</name>
              <description>Xtal 32 buffer current bias</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DVREG11_SET_DIG</name>
              <description>Vregd set</description>
              <bitOffset>28</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUCK_DPD</name>
              <description>ZC control select</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MISC</name>
          <description>MISC register</description>
          <addressOffset>0x890</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x3000000</resetValue>
          <resetMask>0x3000000</resetMask>
          <fields>
            <field>
              <name>RCO_PWR_MODE</name>
              <description>RCO VDD selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RCO_PWR_HIGH</name>
                  <description>The highest RCO VDD setting, RCO current 630nA</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RCO_PWR_MIDDLE</name>
                  <description>The middle RCO VDD setting, RCO current 350nA</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RCO_PWR_LOW</name>
                  <description>The lowest RCO VDD setting, RCO current 200nA</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EN_SWD</name>
              <description>enable swd register when SWD is selected in PIO_FUNC_CTRL</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLE</name>
                  <description>disable SWD</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLE</name>
                  <description>enable SWD</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DIS_FLSH_POWER</name>
              <description>flash power disable</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ENABLE</name>
                  <description>flash power is depend on the value DIS_FLSH of PMU_CTRL2</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DISABLE</name>
                  <description>flash power is off</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DIS_USB_PULLUP</name>
              <description>USB pull resister connection</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CONNECT</name>
                  <description>USB pull up resistor state depend on other 3 USB control register</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DISCONNECT</name>
                  <description>USB pull up resister is disconnected</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DPPU_OPT_SEL</name>
              <description>pull up strength source. 0: from DPPU_OPT_POL, 1: from usb device</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RES1P2K</name>
                  <description>1.2kohm</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RES2P3K</name>
                  <description>2.3kohm</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DPPU_OPT_POL</name>
              <description>swap pull up strength value</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>WDT</name>
      <description>wdog</description>
      <groupName>WDT</groupName>
      <baseAddress>0x40001000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x24</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>LOAD</name>
          <description>watch dog counter start value register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>LOAD</name>
              <description>Contain the value from which the counter is to decrement. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>VALUE</name>
          <description>watch dog counter value register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1FFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>VALUE</name>
              <description>The current value of the decrementing counter.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL</name>
          <description>watch dog control register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3</resetMask>
          <fields>
            <field>
              <name>INTEN</name>
              <description>Enable the interrupt event WDOGINT. Set HIGH to enable the counter and the interrupt and set LOW to disable the counter and interrupt. Reloads the counter from the value in WDOGLOAD when the interrupt is enabled, and was previously disabled.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RESEN</name>
              <description>Enable watchdog reset output WDOGRES. Acts as a mask for the reset output. Set HIGH to enablethe reset and LOW to disable the reset.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_CLR</name>
          <description>interrupt clear register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1</resetMask>
          <fields>
            <field>
              <name>INTCLR</name>
              <description>A write of any value to the Register clears the watchdog interrupt and reloads the counter from the value in WDOGLOAD.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_RAW</name>
          <description>raw interrupt status register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1</resetMask>
          <fields>
            <field>
              <name>RAWINTSTAT</name>
              <description>Raw interrupt status from the counter</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MIS</name>
          <description>interrupt mask register</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1</resetMask>
          <fields>
            <field>
              <name>MASKINTSTAT</name>
              <description>Enabled interrupt status from the counter</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LOCK</name>
          <description>watch dog lock register</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>LOCK_31_0</name>
              <description>Writing 0x1ACCE551to this register enables write access to all other registers.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>CTIMER0</name>
      <description>timer</description>
      <groupName>CTIMER</groupName>
      <headerStructName>CTIMER</headerStructName>
      <baseAddress>0x40002000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x78</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>IR</name>
          <description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>MR0INT</name>
              <description>Interrupt flag for match channel 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR1INT</name>
              <description>Interrupt flag for match channel 1.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR2INT</name>
              <description>Interrupt flag for match channel 2.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR3INT</name>
              <description>Interrupt flag for match channel 3.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CR0INT</name>
              <description>Interrupt flag for capture channel 0 event.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CR1INT</name>
              <description>Interrupt flag for capture channel 1 event.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CR2INT</name>
              <description>Interrupt flag for capture channel 2 event.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TCR</name>
          <description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3</resetMask>
          <fields>
            <field>
              <name>CEN</name>
              <description>Counter enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled.The counters are disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The Timer Counter and Prescale Counter are enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CRST</name>
              <description>Counter reset.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. Do nothing.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>TC</name>
          <description>Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>TCVAL</name>
              <description>Timer counter value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PR</name>
          <description>Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PRVAL</name>
              <description>Prescale counter value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PC</name>
          <description>Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PCVAL</name>
              <description>Prescale counter value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MCR</name>
          <description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFF</resetMask>
          <fields>
            <field>
              <name>MR0I</name>
              <description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR0R</name>
              <description>Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR0S</name>
              <description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR1I</name>
              <description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR1R</name>
              <description>Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR1S</name>
              <description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR2I</name>
              <description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR2R</name>
              <description>Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR2S</name>
              <description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR3I</name>
              <description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR3R</name>
              <description>Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MR3S</name>
              <description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>4</dim>
          <dimIncrement>0x4</dimIncrement>
          <name>MR[%s]</name>
          <description>Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MATCH</name>
              <description>Timer counter match value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CCR</name>
          <description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFF</resetMask>
          <fields>
            <field>
              <name>CAP0RE</name>
              <description>Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP0FE</name>
              <description>Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP0I</name>
              <description>Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP1RE</name>
              <description>Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP1FE</name>
              <description>Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP1I</name>
              <description>Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP2RE</name>
              <description>Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP2FE</name>
              <description>Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAP2I</name>
              <description>Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>3</dim>
          <dimIncrement>0x4</dimIncrement>
          <name>CR[%s]</name>
          <description>Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CAP</name>
              <description>Timer counter capture value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EMR</name>
          <description>External Match Register. The EMR controls the match function and the external match pins.</description>
          <addressOffset>0x3C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFF</resetMask>
          <fields>
            <field>
              <name>EM0</name>
              <description>External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EM1</name>
              <description>External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EM2</name>
              <description>External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EM3</name>
              <description>External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EMC0</name>
              <description>External Match Control 0. Determines the functionality of External Match 0.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DO_NOTHING</name>
                  <description>Do Nothing.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE</name>
                  <description>Toggle. Toggle the corresponding External Match bit/output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EMC1</name>
              <description>External Match Control 1. Determines the functionality of External Match 1.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DO_NOTHING</name>
                  <description>Do Nothing.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE</name>
                  <description>Toggle. Toggle the corresponding External Match bit/output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EMC2</name>
              <description>External Match Control 2. Determines the functionality of External Match 2.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DO_NOTHING</name>
                  <description>Do Nothing.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE</name>
                  <description>Toggle. Toggle the corresponding External Match bit/output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EMC3</name>
              <description>External Match Control 3. Determines the functionality of External Match 3.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DO_NOTHING</name>
                  <description>Do Nothing.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE</name>
                  <description>Toggle. Toggle the corresponding External Match bit/output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CTCR</name>
          <description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
          <addressOffset>0x70</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>CTMODE</name>
              <description>Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer'-s Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>TIMER</name>
                  <description>Timer Mode. Incremented every rising APB bus clock edge.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>COUNTER_RISING_EDGE</name>
                  <description>Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>COUNTER_FALLING_EDGE</name>
                  <description>Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>COUNTER_DUAL_EDGE</name>
                  <description>Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CINSEL</name>
              <description>Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CHANNEL_0</name>
                  <description>Channel 0. CAPn.0 for CT32Bn</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CHANNEL_1</name>
                  <description>Channel 1. CAPn.1 for CT32Bn</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CHANNEL_2</name>
                  <description>Channel 2. CAPn.2 for CT32Bn</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ENCC</name>
              <description>Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SELCC</name>
              <description>Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CHANNEL_0_RISING</name>
                  <description>Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CHANNEL_0_FALLING</name>
                  <description>Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CHANNEL_1_RISING</name>
                  <description>Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CHANNEL_1_FALLING</name>
                  <description>Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CHANNEL_2_RISING</name>
                  <description>Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CHANNEL_2_FALLING</name>
                  <description>Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).</description>
                  <value>0x5</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PWMC</name>
          <description>PWM Control Register. The PWMCON enables PWM mode for the external match pins.</description>
          <addressOffset>0x74</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>PWMEN0</name>
              <description>PWM mode enable for channel0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>MATCH</name>
                  <description>Match. CT32Bn_MAT0 is controlled by EM0.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PWM</name>
                  <description>PWM. PWM mode is enabled for CT32Bn_MAT0.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PWMEN1</name>
              <description>PWM mode enable for channel1.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>MATCH</name>
                  <description>Match. CT32Bn_MAT01 is controlled by EM1.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PWM</name>
                  <description>PWM. PWM mode is enabled for CT32Bn_MAT1.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PWMEN2</name>
              <description>PWM mode enable for channel2.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>MATCH</name>
                  <description>Match. CT32Bn_MAT2 is controlled by EM2.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PWM</name>
                  <description>PWM. PWM mode is enabled for CT32Bn_MAT2.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PWMEN3</name>
              <description>PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>MATCH</name>
                  <description>Match. CT32Bn_MAT3 is controlled by EM3.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PWM</name>
                  <description>PWM. PWM mode is enabled for CT132Bn_MAT3.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="CTIMER0">
      <name>CTIMER1</name>
      <description>timer</description>
      <groupName>CTIMER</groupName>
      <baseAddress>0x40003000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x78</size>
        <usage>registers</usage>
      </addressBlock>
    </peripheral>
    <peripheral derivedFrom="CTIMER0">
      <name>CTIMER2</name>
      <description>timer</description>
      <groupName>CTIMER</groupName>
      <baseAddress>0x40004000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x78</size>
        <usage>registers</usage>
      </addressBlock>
    </peripheral>
    <peripheral derivedFrom="CTIMER0">
      <name>CTIMER3</name>
      <description>timer</description>
      <groupName>CTIMER</groupName>
      <baseAddress>0x40005000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x78</size>
        <usage>registers</usage>
      </addressBlock>
    </peripheral>
    <peripheral>
      <name>PINT</name>
      <description>QN908X Pin interrupt and pattern match (PINT)</description>
      <groupName>PINT</groupName>
      <baseAddress>0x40006000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x34</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>ISEL</name>
          <description>Pin Interrupt Mode register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>PMODE</name>
              <description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IENR</name>
          <description>Pin interrupt level or rising edge interrupt enable register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>ENRL</name>
              <description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIENR</name>
          <description>Pin interrupt level or rising edge interrupt set register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>SETENRL</name>
              <description>Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CIENR</name>
          <description>Pin interrupt level (rising edge interrupt) clear register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>CENRL</name>
              <description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IENF</name>
          <description>Pin interrupt active level or falling edge interrupt enable register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>ENAF</name>
              <description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIENF</name>
          <description>Pin interrupt active level or falling edge interrupt set register</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>SETENAF</name>
              <description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CIENF</name>
          <description>Pin interrupt active level or falling edge interrupt clear register</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>CENAF</name>
              <description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RISE</name>
          <description>Pin interrupt rising edge register</description>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>RDET</name>
              <description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FALL</name>
          <description>Pin interrupt falling edge register</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>FDET</name>
              <description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IST</name>
          <description>Pin interrupt status register</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>PSTAT</name>
              <description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PMCTRL</name>
          <description>Pattern match interrupt control register</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF000003</resetMask>
          <fields>
            <field>
              <name>SEL_PMATCH</name>
              <description>Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>PIN_INTERRUPT</name>
                  <description>Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PATTERN_MATCH</name>
                  <description>Pattern match. Interrupts are driven in response to pattern matches.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ENA_RXEV</name>
              <description>Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. RXEV output to the CPU is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. RXEV output to the CPU is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PMAT</name>
              <description>This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PMSRC</name>
          <description>Pattern match interrupt bit-slice source register</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFF00</resetMask>
          <fields>
            <field>
              <name>SRC0</name>
              <description>Selects the input source for bit slice 0</description>
              <bitOffset>8</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INPUT0</name>
                  <description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT1</name>
                  <description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT2</name>
                  <description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT3</name>
                  <description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT4</name>
                  <description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT5</name>
                  <description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT6</name>
                  <description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT7</name>
                  <description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SRC1</name>
              <description>Selects the input source for bit slice 1</description>
              <bitOffset>11</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INPUT0</name>
                  <description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT1</name>
                  <description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT2</name>
                  <description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT3</name>
                  <description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT4</name>
                  <description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT5</name>
                  <description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT6</name>
                  <description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT7</name>
                  <description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SRC2</name>
              <description>Selects the input source for bit slice 2</description>
              <bitOffset>14</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INPUT0</name>
                  <description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT1</name>
                  <description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT2</name>
                  <description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT3</name>
                  <description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT4</name>
                  <description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT5</name>
                  <description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT6</name>
                  <description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT7</name>
                  <description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SRC3</name>
              <description>Selects the input source for bit slice 3</description>
              <bitOffset>17</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INPUT0</name>
                  <description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT1</name>
                  <description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT2</name>
                  <description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT3</name>
                  <description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT4</name>
                  <description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT5</name>
                  <description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT6</name>
                  <description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT7</name>
                  <description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SRC4</name>
              <description>Selects the input source for bit slice 4</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INPUT0</name>
                  <description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT1</name>
                  <description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT2</name>
                  <description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT3</name>
                  <description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT4</name>
                  <description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT5</name>
                  <description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT6</name>
                  <description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT7</name>
                  <description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SRC5</name>
              <description>Selects the input source for bit slice 5</description>
              <bitOffset>23</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INPUT0</name>
                  <description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT1</name>
                  <description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT2</name>
                  <description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT3</name>
                  <description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT4</name>
                  <description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT5</name>
                  <description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT6</name>
                  <description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT7</name>
                  <description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SRC6</name>
              <description>Selects the input source for bit slice 6</description>
              <bitOffset>26</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INPUT0</name>
                  <description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT1</name>
                  <description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT2</name>
                  <description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT3</name>
                  <description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT4</name>
                  <description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT5</name>
                  <description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT6</name>
                  <description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT7</name>
                  <description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SRC7</name>
              <description>Selects the input source for bit slice 7</description>
              <bitOffset>29</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INPUT0</name>
                  <description>Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT1</name>
                  <description>Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT2</name>
                  <description>Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT3</name>
                  <description>Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT4</name>
                  <description>Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT5</name>
                  <description>Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT6</name>
                  <description>Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT7</name>
                  <description>Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PMCFG</name>
          <description>Pattern match interrupt bit slice configuration register</description>
          <addressOffset>0x30</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFF7F</resetMask>
          <fields>
            <field>
              <name>PROD_ENDPTS0</name>
              <description>Determines whether slice 0 is an endpoint.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect. Slice 0 is not an endpoint.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENDPOINT</name>
                  <description>endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PROD_ENDPTS1</name>
              <description>Determines whether slice 1 is an endpoint.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect. Slice 1 is not an endpoint.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENDPOINT</name>
                  <description>endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PROD_ENDPTS2</name>
              <description>Determines whether slice 2 is an endpoint.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect. Slice 2 is not an endpoint.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENDPOINT</name>
                  <description>endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PROD_ENDPTS3</name>
              <description>Determines whether slice 3 is an endpoint.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect. Slice 3 is not an endpoint.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENDPOINT</name>
                  <description>endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PROD_ENDPTS4</name>
              <description>Determines whether slice 4 is an endpoint.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect. Slice 4 is not an endpoint.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENDPOINT</name>
                  <description>endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PROD_ENDPTS5</name>
              <description>Determines whether slice 5 is an endpoint.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect. Slice 5 is not an endpoint.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENDPOINT</name>
                  <description>endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PROD_ENDPTS6</name>
              <description>Determines whether slice 6 is an endpoint.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect. Slice 6 is not an endpoint.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENDPOINT</name>
                  <description>endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CFG0</name>
              <description>Specifies the match contribution condition for bit slice 0.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CONSTANT_HIGH</name>
                  <description>Constant HIGH. This bit slice always contributes to a product term match.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_EDGE</name>
                  <description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_FALLING_EDGE</name>
                  <description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_FALLING_EDGE</name>
                  <description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH_LEVEL</name>
                  <description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>LOW_LEVEL</name>
                  <description>Low level. Match occurs when there is a low level on the specified input.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CONSTANT_ZERO</name>
                  <description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EVENT</name>
                  <description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CFG1</name>
              <description>Specifies the match contribution condition for bit slice 1.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CONSTANT_HIGH</name>
                  <description>Constant HIGH. This bit slice always contributes to a product term match.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_EDGE</name>
                  <description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_FALLING_EDGE</name>
                  <description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_FALLING_EDGE</name>
                  <description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH_LEVEL</name>
                  <description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>LOW_LEVEL</name>
                  <description>Low level. Match occurs when there is a low level on the specified input.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CONSTANT_ZERO</name>
                  <description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EVENT</name>
                  <description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CFG2</name>
              <description>Specifies the match contribution condition for bit slice 2.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CONSTANT_HIGH</name>
                  <description>Constant HIGH. This bit slice always contributes to a product term match.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_EDGE</name>
                  <description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_FALLING_EDGE</name>
                  <description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_FALLING_EDGE</name>
                  <description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH_LEVEL</name>
                  <description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>LOW_LEVEL</name>
                  <description>Low level. Match occurs when there is a low level on the specified input.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CONSTANT_ZERO</name>
                  <description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EVENT</name>
                  <description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CFG3</name>
              <description>Specifies the match contribution condition for bit slice 3.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CONSTANT_HIGH</name>
                  <description>Constant HIGH. This bit slice always contributes to a product term match.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_EDGE</name>
                  <description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_FALLING_EDGE</name>
                  <description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_FALLING_EDGE</name>
                  <description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH_LEVEL</name>
                  <description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>LOW_LEVEL</name>
                  <description>Low level. Match occurs when there is a low level on the specified input.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CONSTANT_ZERO</name>
                  <description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EVENT</name>
                  <description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CFG4</name>
              <description>Specifies the match contribution condition for bit slice 4.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CONSTANT_HIGH</name>
                  <description>Constant HIGH. This bit slice always contributes to a product term match.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_EDGE</name>
                  <description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_FALLING_EDGE</name>
                  <description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_FALLING_EDGE</name>
                  <description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH_LEVEL</name>
                  <description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>LOW_LEVEL</name>
                  <description>Low level. Match occurs when there is a low level on the specified input.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CONSTANT_ZERO</name>
                  <description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EVENT</name>
                  <description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CFG5</name>
              <description>Specifies the match contribution condition for bit slice 5.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CONSTANT_HIGH</name>
                  <description>Constant HIGH. This bit slice always contributes to a product term match.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_EDGE</name>
                  <description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_FALLING_EDGE</name>
                  <description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_FALLING_EDGE</name>
                  <description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH_LEVEL</name>
                  <description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>LOW_LEVEL</name>
                  <description>Low level. Match occurs when there is a low level on the specified input.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CONSTANT_ZERO</name>
                  <description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EVENT</name>
                  <description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CFG6</name>
              <description>Specifies the match contribution condition for bit slice 6.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CONSTANT_HIGH</name>
                  <description>Constant HIGH. This bit slice always contributes to a product term match.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_EDGE</name>
                  <description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_FALLING_EDGE</name>
                  <description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_FALLING_EDGE</name>
                  <description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH_LEVEL</name>
                  <description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>LOW_LEVEL</name>
                  <description>Low level. Match occurs when there is a low level on the specified input.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CONSTANT_ZERO</name>
                  <description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EVENT</name>
                  <description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CFG7</name>
              <description>Specifies the match contribution condition for bit slice 7.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CONSTANT_HIGH</name>
                  <description>Constant HIGH. This bit slice always contributes to a product term match.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_EDGE</name>
                  <description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_FALLING_EDGE</name>
                  <description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STICKY_RISING_FALLING_EDGE</name>
                  <description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH_LEVEL</name>
                  <description>High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>LOW_LEVEL</name>
                  <description>Low level. Match occurs when there is a low level on the specified input.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CONSTANT_ZERO</name>
                  <description>Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EVENT</name>
                  <description>Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>INPUTMUX</name>
      <description>dmamux</description>
      <groupName>INPUTMUX</groupName>
      <baseAddress>0x40006200</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x810</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <dim>4</dim>
          <dimIncrement>0x4</dimIncrement>
          <name>PINTSEL[%s]</name>
          <description>Pin interrupt select register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>INTPIN</name>
              <description>Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>20</dim>
          <dimIncrement>0x4</dimIncrement>
          <name>DMA_ITRIG_INMUX[%s]</name>
          <description>Trigger select register for DMA channel</description>
          <addressOffset>0x200</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1F</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CT32B0 Match 0 5 = Timer CT32B0 Match 1 6 = Timer CT32B1 Match 0 7 = Timer CT32B2 Match 0 8 = Timer CT32B2 Match 1 9 = Timer CT32B3 Match 0 10 = Timer CT32B4 Match 0 11 = Timer CT32B4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>4</dim>
          <dimIncrement>0x4</dimIncrement>
          <name>DMA_OTRIG_INMUX[%s]</name>
          <description>DMA output trigger selection to become DMA trigger</description>
          <addressOffset>0x800</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1F</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>INP</name>
              <description>DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>ADC</name>
      <description>adc</description>
      <groupName>ADC</groupName>
      <baseAddress>0x40007000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x100</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CTRL</name>
          <description>ADC control register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1000</resetValue>
          <resetMask>0x1FBCFF0F</resetMask>
          <fields>
            <field>
              <name>ENABLE</name>
              <description>ADC enable. Write 1 to Writing 1 before starting conversion and 0 to end conversion.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CONV_MODE</name>
              <description>ADC conversion mode</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>BURST</name>
                  <description>burst conversion</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SINGLE</name>
                  <description>single conversion</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SCAN_EN</name>
              <description>1 to enable scan mode</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WCMP_EN</name>
              <description>1 to enable window compare</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SW_START</name>
              <description>Software start ADC conversion write1 to trigger one time ADC conversion, no need clear.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CLKSEL</name>
              <description>Sigma-Delta ADC clock select</description>
              <bitOffset>8</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CLKSEL_31P25K</name>
                  <description>31P25K</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLKSEL_62P5K</name>
                  <description>62P5K</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLKSEL_125K</name>
                  <description>125K</description>
                  <value>0x8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLKSEL_250K</name>
                  <description>250K</description>
                  <value>0xC</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLKSEL_500K</name>
                  <description>500K</description>
                  <value>0x10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLKSEL_1M</name>
                  <description>1M</description>
                  <value>0x14</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLKSEL_2M</name>
                  <description>2M</description>
                  <value>0x18</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLKSEL_32K</name>
                  <description>32K</description>
                  <value>0x1D</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SIG_INV_EN</name>
              <description>1 to invert Signma-Delta input signal</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VREF_SEL</name>
              <description>Sigma-Delta ADC Reference source selection.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INT_1P2V</name>
                  <description>Internal vref 1.2V</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EXT_DRV</name>
                  <description>External VREF</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EXT_NO_DRV</name>
                  <description>Vext without driver</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VCC</name>
                  <description>VCC</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CH_IDX_EN</name>
              <description>1 to append channel index in data result to be used in scan mode</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA_FORMAT</name>
              <description>Data output format. When DATA_FORMAT ==0, When CH_IDX_EN ==0, the ADC_DATA[31:0] is adc data, signed data, 31 bit frac. When CH_IDX_EN ==1, the ADC_DATA[4:0] is channel output, {ADC_DATA[31:5],5'h0} is adc data, signed data, 31 bit frac. When DATA_FORMAT ==1, When CH_IDX_EN ==0, the ADC_DATA[22:0] is adc data, signed data, 22 bit frac. When CH_IDX_EN ==1, the ADC_DATA[31:27] is channel output, ADC_DATA[22:0] is adc data, signed data, 22 bit frac.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VREFO_EN</name>
              <description>1 to enable bandgap out-chip capacitor</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SRST_DIS</name>
              <description>1 to disable adc reset.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRIGGER</name>
              <description>Adc start trigger. 0 to 31 PA00 to PA31; 32 to 34 GPIOB0 to GPIOB2; 35, software trigger; 36, rng trigger; 56 to 59, timer 0 to timer 3; 60 to 63 pwm 0 to pwm 3</description>
              <bitOffset>23</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CH_SEL</name>
          <description>ADC channel selection register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CH_SEL</name>
              <description>In scan conversion mode, the channels with 1 set will be scanned, from LSB to MSB. In none scan conversion mode, only the first channel from LSB with 1 set will be converted. If all bits are set to 0, no ADC conversion will be started.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CH_CFG</name>
          <description>ADC channel configuration register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CH_CFG</name>
              <description>whenCH_CONFIG[N] is 0, the N channelwill select the configure 0 option(seeregister SD_CONFIG0). whenCH_CONFIG[N] is 1, the N channelwill select the configure 1 option(seeregister SD_CONFIG1).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WCMP_THR</name>
          <description>Window compare threshold register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x7FFF8000</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>WCMP_THR_LOW</name>
              <description>&amp;lt;s 0 15&amp;gt; Windows compare low threshold.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WCMP_THR_HIGH</name>
              <description>&amp;lt;s 0 15&amp;gt; Windows compare high threshold If ADC decimation result is out of the window one compare interrupt will be triggered.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTEN</name>
          <description>ADC interrupt enable register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x80000007</resetMask>
          <fields>
            <field>
              <name>DAT_RDY_INTEN</name>
              <description>1 to enable Data ready interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WCMP_INTEN</name>
              <description>1 to enable Window compare interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIFO_OF_INTEN</name>
              <description>1 to enalble FIFO overflow interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_INTEN</name>
              <description>1 to enable ADC interrupt</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT</name>
          <description>ADC interrupt status register</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x80000007</resetMask>
          <fields>
            <field>
              <name>DAT_RDY_INT</name>
              <description>Data ready interrupt will be cleared after fifo data is read can not be cleared by write 1.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>WCMP_INT</name>
              <description>Window compare interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FIFO_OF_INT</name>
              <description>FIFO overflow interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>ADC_INT</name>
              <description>ADC interrupt.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATA</name>
          <description>ADC converted data output</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>ADC data read from FIFO.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>2</dim>
          <dimIncrement>0x4</dimIncrement>
          <name>CFG[%s]</name>
          <description>ADC configuration register</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x83802950</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PGA_GAIN</name>
              <description>SD ADC input PGA gain=2^value the range is 1-16.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PGA_BP</name>
              <description>1 to bypass SD ADC input PGA</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PGA_VINN</name>
              <description>SD ADC PGA VIN input offset selection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>VREF</name>
                  <description>VREF</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VREF_0P75</name>
                  <description>3/4 VREF</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VREF_0P5</name>
                  <description>1/2 VREF</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>AVSS</name>
                  <description>AVSS</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_GAIN</name>
              <description>SD ADC gain selection.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ADC_GAIN_0P5X</name>
                  <description>0.5x</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_GAIN_1X</name>
                  <description>1x</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_GAIN_1P5X</name>
                  <description>1.5x</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_GAIN_2X</name>
                  <description>2x</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>VREF_GAIN</name>
              <description>SD ADC Reference Gain seletion</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>VREF_GAIN_1X</name>
                  <description>1x</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VREF_GAIN_1P5X</name>
                  <description>1.5x</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_VCM</name>
              <description>SD ADC input common voltage selection.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ADC_VCM_1D16</name>
                  <description>1/16 VCC</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_VCM_1D8</name>
                  <description>1/8 VCC</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_VCM_2D8</name>
                  <description>2/8 VCC</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_VCM_3D8</name>
                  <description>3/8 VCC</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_VCM_4D8</name>
                  <description>4/8 VCC</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_VCM_5D8</name>
                  <description>5/8 VCC</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_VCM_6D8</name>
                  <description>6/8 VCC</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_VCM_7D8</name>
                  <description>7/8 VCC</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PGA_VCM_EN</name>
              <description>SD ADC PGA output common voltage control enable signal.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PGA_VCM_DIR</name>
              <description>SD ADC PGA output common voltage control direction signal.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DOWN</name>
                  <description>down</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>UP</name>
                  <description>up</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PGA_VCM</name>
              <description>SD ADC PGA output common voltage, adjustment = (PGA_VCM0[5]+1)*(PGA_VCM0[3:0]+1)*40mv</description>
              <bitOffset>14</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DOWN_SAMPLE_RATE</name>
              <description>Down sample rate</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DOWN_SAMPLE_32</name>
                  <description>down sample 32</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DOWN_SAMPLE_64</name>
                  <description>down sample 64</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DOWN_SAMPLE_256</name>
                  <description>down sample 256</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DOWN_SAMPLE_128</name>
                  <description>down sample 128</description>
                  <value>0x5</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DS_DATA_STABLE</name>
              <description>Down sample date stable number. you can keep the bit 1:0 to 2'b11. DS_DATA_STABLE0[5:2]+1</description>
              <bitOffset>23</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCAN_INTV</name>
              <description>Interval when switching ADC source; 2/4/8/16/32/64/128/256 clock cycle.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SCAN_INTV_2CLK</name>
                  <description>2 clock cycle</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SCAN_INTV_4CLK</name>
                  <description>4 clock cycle</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SCAN_INTV_8CLK</name>
                  <description>8 clock cycle</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SCAN_INTV_16CLK</name>
                  <description>16 clock cycle</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SCAN_INTV_32CLK</name>
                  <description>32 clock cycle</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SCAN_INTV_64CLK</name>
                  <description>64 clock cycle</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SCAN_INTV_128CLK</name>
                  <description>128 clock cycle</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SCAN_INTV_256CLK</name>
                  <description>256 clock cycle</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>BG_BF</name>
          <description>ADC bandcap and buffer setting register</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x82</resetValue>
          <resetMask>0x30F7</resetMask>
          <fields>
            <field>
              <name>PGA_BM</name>
              <description>SD ADC buffer bias current selection.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>PGA_BM_50PCNT</name>
                  <description>50%</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PGA_BM_75PCNT</name>
                  <description>75%</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PGA_BM_100PCNT</name>
                  <description>100%</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PGA_BM_150PCNT</name>
                  <description>150%</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PGA_BM_200PCNT</name>
                  <description>200%</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PGA_BM_300PCNT</name>
                  <description>300%</description>
                  <value>0x5</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>BG_SEL</name>
              <description>Bandgap voltage selection to compensate PVT variations8 steps with 5mV each upward. VBG=1205+5*BGSEL(mV)</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TEMP_EN</name>
              <description>1 to enable temperature sensor</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PGA_CHOP_EN</name>
              <description>1 to enable chopper in PGA</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PGA_BM_DIV2</name>
              <description>1 to half PGA bias current</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANA_CTRL</name>
          <description>ADC core and reference setting regsiter</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x55564</resetValue>
          <resetMask>0xF77F7</resetMask>
          <fields>
            <field>
              <name>ADC_BM</name>
              <description>ADC bias current selection.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ADC_BM_50PCNT</name>
                  <description>50%</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_BM_75PCNT</name>
                  <description>75%</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_BM_100PCNT</name>
                  <description>100%</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_BM_150PCNT</name>
                  <description>150%</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_BM_200PCNT</name>
                  <description>200%</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_BM_300PCNT</name>
                  <description>300%</description>
                  <value>0x5</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADC_ORDER</name>
              <description>1 to enable SD ADC 2 order mode selection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ADC_ORDER_3ORDER</name>
                  <description>3 order</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADC_ORDER_2ORDER</name>
                  <description>2 order</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DITHER_EN</name>
              <description>1 to enable SD ADC PN Sequence in chopper mode</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CHOP_EN</name>
              <description>1 to enable SD ADC chopper</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INV_CLK</name>
              <description>1 to invert SD ADC Output Clock</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VREF_BM</name>
              <description>SD ADC Reference Driver bias current selection.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>VREF_BM_50PCNT</name>
                  <description>50%</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VREF_BM_75PCNT</name>
                  <description>75%</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VREF_BM_100PCNT</name>
                  <description>100%</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VREF_BM_150PCNT</name>
                  <description>150%</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VREF_BM_200PCNT</name>
                  <description>200%</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VREF_BM_300PCNT</name>
                  <description>300%</description>
                  <value>0x5</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>VREF_BM_X3</name>
              <description>SD ADC Reference Driver bias current triple.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VINN_IN_BM</name>
              <description>PGA VlNN Input Driver bias current selection.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>VINN_IN_BM_50PCNT</name>
                  <description>50%</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VINN_IN_BM_75PCNT</name>
                  <description>75%</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VINN_IN_BM_100PCNT</name>
                  <description>100%</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VINN_IN_BM_150PCNT</name>
                  <description>150%</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VINN_IN_BM_200PCNT</name>
                  <description>200%</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VINN_IN_BM_300PCNT</name>
                  <description>300%</description>
                  <value>0x5</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>VINN_OUT_BM</name>
              <description>PGA VlNN Output Driver bias current selection.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>VINN_OUT_BM_50PCNT</name>
                  <description>50%</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VINN_OUT_BM_75PCNT</name>
                  <description>75%</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VINN_OUT_BM_100PCNT</name>
                  <description>100%</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VINN_OUT_BM_150PCNT</name>
                  <description>150%</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VINN_OUT_BM_200PCNT</name>
                  <description>200%</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>VINN_OUT_BM_300PCNT</name>
                  <description>300%</description>
                  <value>0x5</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>VINN_OUT_BM_X3</name>
              <description>PGA VlNN Output Driver bias current triple.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_BM_DIV2</name>
              <description>SD ADC bias current half.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>DAC</name>
      <description>dac</description>
      <groupName>DAC</groupName>
      <baseAddress>0x40007400</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x2C</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>ANA_CFG</name>
          <description>reserved</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x71022</resetValue>
          <resetMask>0xF1377</resetMask>
          <fields>
            <field>
              <name>FILTER_BM</name>
              <description>Set the filter bias current</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DAC_AMP</name>
              <description>Set the current bias of the DAC</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FILTER_BW</name>
              <description>Set the Miller compensation capacitance of the OPAMP. This compensation capacitance is determined by the off-chip load resistance</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FILTER_150K_EN</name>
              <description>Set the filter type and bandwidth</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCM</name>
              <description>Set the common mode I of the driver.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL</name>
          <description>DAC clock invert</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF3F1FFF</resetMask>
          <fields>
            <field>
              <name>ENABLE</name>
              <description>DAC module enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SIN_EN</name>
              <description>Sin wave enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MOD_EN</name>
              <description>Modulator enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MOD_WD</name>
              <description>Modulator output width</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SMPL_RATE</name>
              <description>sigma delta modulator down sample rate</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SGN_INV</name>
              <description>Sign bit inverse</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_IN_ALGN</name>
              <description>FIFO input data align</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_OUT_ALGN</name>
              <description>FIFO output data and Sine wave generator output align mode when no modulation mode</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRG_MODE</name>
              <description>Trigger mode</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRG_EDGE</name>
              <description>Trigger edge select</description>
              <bitOffset>11</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRG_SEL</name>
              <description>Trigger select</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>DAC clock divider</description>
              <bitOffset>24</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_INV</name>
              <description>DAC clock invert</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIN_CFG0</name>
          <description>sin amplitude</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SIN_FREQ</name>
              <description>sin frequency</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SIN_AMP</name>
              <description>sin amplitude</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIN_CFG1</name>
          <description>reserved</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFF</resetMask>
          <fields>
            <field>
              <name>SIN_DC</name>
              <description>DC value of sin wave</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>GAIN_CTRL</name>
          <description>reserved</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x10</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>GAIN_CTRL</name>
              <description>digital FIFO output multiply with GAIN_CTRL to scale to certain range. Where GAIN_CTRL is a &amp;amp;lt;u 4 4&amp;amp;gt; value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLR_TRG</name>
          <description>Reserved</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>BUF_CLR</name>
              <description>clear buffer signal write 1 to clear.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SW_TRG</name>
              <description>Software trigger</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DIN</name>
          <description>DAC data input</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>DIN</name>
              <description>DAC data input</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT</name>
          <description>Reserved</description>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x7F</resetMask>
          <fields>
            <field>
              <name>BUF_NFUL_INT</name>
              <description>Buffer not full interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUF_FUL_INT</name>
              <description>Buffer full interrupt</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUF_EMT_INT</name>
              <description>Buffer empty interrupt</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUF_HEMT_INT</name>
              <description>buffer half empty interrupt</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUF_OV_INT</name>
              <description>Buffer overflow interrupt write 1 to clear</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>BUF_UD_INT</name>
              <description>Buffer underflow interrupt write 1 to clear</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>BUF_HFUL_INT</name>
              <description>Buffer half full interrupt</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTEN</name>
          <description>Reserved</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x7F</resetMask>
          <fields>
            <field>
              <name>BUF_NFUL_INTEN</name>
              <description>buffer not full interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_FUL_INTEN</name>
              <description>buffer full interrupt enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_EMT_INTEN</name>
              <description>buffer empty interrupt enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_HEMT_INTEN</name>
              <description>buffer half empty interrupt enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_OV_INTEN</name>
              <description>buffer over flow interrupt enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_UD_INTEN</name>
              <description>Buffer under flow interrupt enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_HFUL_INTEN</name>
              <description>buffer half full interrupt enable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_STAT</name>
          <description>Reserved</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1007F</resetMask>
          <fields>
            <field>
              <name>BUF_NFUL_INT_STAT</name>
              <description>buffer not full interrupt status</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUF_FUL_INT_STAT</name>
              <description>buffer full interrupt status</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUF_EMT_INT_STAT</name>
              <description>buffer empty interrupt status</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUF_HEMT_INT_STAT</name>
              <description>buffer half empty interrupt status</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUF_OV_INT_STAT</name>
              <description>buffer over flow interrupt status</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUF_UD_INT_STAT</name>
              <description>Buffer under flow interrupt status</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUF_HFUL_INT_STAT</name>
              <description>buffer half full interrupt status</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DAC_INT_STAT</name>
              <description>DAC all interrupt status</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATUS</name>
          <description>Reserved</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x770001</resetMask>
          <fields>
            <field>
              <name>BUSY</name>
              <description>busy</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUF_WR_PTR</name>
              <description>Buffer write pointer</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BUF_RD_PTR</name>
              <description>Buffer read pointer</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>CS</name>
      <description>tsc</description>
      <groupName>CS</groupName>
      <baseAddress>0x40007800</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x24</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CTRL0</name>
          <description>CapSense control register 0</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FF00FF</resetMask>
          <fields>
            <field>
              <name>ENABLE</name>
              <description>CapSense enable. Write 1 to start work, 0 to stop.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLE</name>
                  <description>OSC work disable.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLE</name>
                  <description>OSC work enable.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SRST</name>
              <description>Soft reset. Set 1 to reset, and 0 to de-assert.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OSC_FREQ</name>
              <description>Oscillation frequency control. The driving current will change accordingly.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_DIV</name>
              <description>Clock divider from CLK_APB : CLK_CS_DIV = CLK_APB/(CLK_DIV + 1)</description>
              <bitOffset>16</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL1</name>
          <description>CapSense control register 1</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFF</resetMask>
          <fields>
            <field>
              <name>PERIOD</name>
              <description>The scan period for one channel, which is PERIOD/(CLK_DIV+1) clock cycles of CLK_APB.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CH</name>
              <description>Channel enable, each bit represent one channel, with CH[0] for CS0, CH[1] for CS1</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT</name>
          <description>Interrupt status register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>FIFO_NOTEMPTY_INT</name>
              <description>FIFO not empty status indicator. Will clear automatically if no data available.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FIFO_HFULL_INT</name>
              <description>FIFO half full status indicator. Will clear automatically once less than half.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FIFO_FULL_INT</name>
              <description>FIFO full status indicator. Will clear automatically once not full.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SCAN_INT</name>
              <description>Scan done status flag for all enabled channels. Write 1 to clear.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTEN</name>
          <description>Interrupt mask register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>FIFO_NOTEMPTY_INTEN</name>
              <description>Interrupt mask of FIFO_NOTEMPTY_INT. Set 1 to enable the interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIFO_HFULL_INTEN</name>
              <description>Interrupt mask of FIFO_HFULL_INT. Set 1 to enable the interrupt.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIFO_FULL_INTEN</name>
              <description>Interrupt mask of FIFO_FULL_INT. Set 1 to enable the interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SCAN_INTEN</name>
              <description>Interrupt mask of SCAN_INT. Set 1 to enable the interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATA</name>
          <description>Output data register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>Output data to MCU: DATA[18:16]: channel index, DATA[15:0]: counter output for that channel.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>19</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LP_CTRL</name>
          <description>Control register for low power mode</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF00FF</resetMask>
          <fields>
            <field>
              <name>DEBONCE_NUM</name>
              <description>(DEBONCE_NUM+1) consecutive samples to judge one touch action.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LP_EN</name>
              <description>Enable for low power mode.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLE</name>
                  <description>Low power mode disable.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLE</name>
                  <description>Low power mode enable.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LP_CH</name>
              <description>The index of the channel to monitor in low power mode, representing 0~7.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>THR</name>
              <description>Threshold to decide the touch action.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LP_INT</name>
          <description>Low power interrupt register</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1</resetMask>
          <fields>
            <field>
              <name>LP_INT</name>
              <description>Interrupt in low power mode when counter output is less than THR.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LP_INTEN</name>
          <description>low power interrupt enable register</description>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1</resetMask>
          <fields>
            <field>
              <name>LP_INTEN</name>
              <description>Interrupt enable of LP_INT. Set 1 to enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IDLE_PERIOD</name>
          <description>Idle preiod number register</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>IDLE_PERIOD</name>
              <description>Number of idle period. Zero represents no idle time between consecutive scan.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>RNG</name>
      <description>rng</description>
      <groupName>RNG</groupName>
      <baseAddress>0x40007C00</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x14</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CTRL</name>
          <description>control register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x31</resetMask>
          <fields>
            <field>
              <name>ENABLE</name>
              <description>write 1 to enable randome number generator</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>START</name>
              <description>write 1 to start random number generation, auto clear</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>NUM</name>
              <description>total bits</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT</name>
          <description>status register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1</resetMask>
          <fields>
            <field>
              <name>BUSY</name>
              <description>module in processing</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATA</name>
          <description>random data output register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>final random data read by SW</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT</name>
          <description>interrupt register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1</resetMask>
          <fields>
            <field>
              <name>DONE</name>
              <description>random data generate done</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTEN</name>
          <description>interrupt mask register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1</resetMask>
          <fields>
            <field>
              <name>DONE_INTEN</name>
              <description>random data generate done mask</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>QDEC0</name>
      <description>qdec</description>
      <groupName>QDEC</groupName>
      <headerStructName>QDEC</headerStructName>
      <baseAddress>0x40009000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x28</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CTRL</name>
          <description>control register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x71</resetMask>
          <fields>
            <field>
              <name>QDEC_EN</name>
              <description>no description available</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>START</name>
              <description>no description available</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>STOP</name>
              <description>no description available</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SOFT_CLR</name>
              <description>no description available</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>AUTO_CLR_EN</name>
              <description>no description available</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SINGLE_SAMPLE_SRST_EN</name>
              <description>no description available</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DB_FILTER_EN</name>
              <description>no description available</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SAMP_CTRL</name>
          <description>QDEC sample settting register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF0F1F</resetMask>
          <fields>
            <field>
              <name>DIVIDE</name>
              <description>divide number to APB clk 0~20 total 21modes</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PTS</name>
              <description>total sample points 0~11 total 12modes cf. 8.2</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>PTS0</name>
                  <description>5 points</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PTS1</name>
                  <description>10 points</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PTS2</name>
                  <description>40 points</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PTS3</name>
                  <description>80 points</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PTS4</name>
                  <description>120 points</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PTS5</name>
                  <description>160 points</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PTS6</name>
                  <description>200 points</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PTS7</name>
                  <description>240 points</description>
                  <value>0x7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PTS8</name>
                  <description>280 points</description>
                  <value>0x8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PTS9</name>
                  <description>320 points</description>
                  <value>0x9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PTS10</name>
                  <description>360 points</description>
                  <value>0xA</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PTS11</name>
                  <description>400 points</description>
                  <value>0xB</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DB_SAMP_DIV</name>
              <description>Debounce filter sample clk devide cf. 8.3</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SAMPLE</name>
          <description>QDEC sample result register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x3</resetMask>
          <fields>
            <field>
              <name>SAMPLE</name>
              <description>Sample value each time (2's complement)</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ACC</name>
          <description>QDEC accumulate register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x7FF</resetMask>
          <fields>
            <field>
              <name>ACC</name>
              <description>shift counter (-1 &amp;amp; +1 ) normal case</description>
              <bitOffset>0</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ACC_R</name>
          <description>QDEC accumulate snapshot register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x7FF</resetMask>
          <fields>
            <field>
              <name>ACC_R</name>
              <description>ACC RO snapshot when END event is valid</description>
              <bitOffset>0</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DB</name>
          <description>double sample register</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>DB</name>
              <description>2 trans counter ERROR case max value 15.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DB_R</name>
          <description>DB snapshot register</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>DB_R</name>
              <description>DB_R RO snapshot when END event is valid</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT</name>
          <description>interrupt register</description>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>SINGLE_SAMPLE</name>
              <description>Each time when normal sample is done</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>SAMPLE_END</name>
              <description>END event triggered</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>ACC_OF</name>
              <description>Normal sample (+1/-1) number is overflow</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>DB_OF</name>
              <description>Double sample (2 trans )number is overflow</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTEN</name>
          <description>interrupt mask register</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>SINGLE_SAMPLE_INTEN</name>
              <description>single sample done interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SAMPLE_END_INTEN</name>
              <description>sample end interrupt enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ACC_OF_INTEN</name>
              <description>normal sample overflow interrupt enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DB_OF_INTEN</name>
              <description>double sample overflow interrupt enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT</name>
          <description>QDEC is running</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1</resetMask>
          <fields>
            <field>
              <name>BUSY</name>
              <description>QDEC is running</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="QDEC0">
      <name>QDEC1</name>
      <description>qdec</description>
      <groupName>QDEC</groupName>
      <baseAddress>0x40009800</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x28</size>
        <usage>registers</usage>
      </addressBlock>
    </peripheral>
    <peripheral>
      <name>RTC</name>
      <description>rtc</description>
      <groupName>RTC</groupName>
      <baseAddress>0x4000B000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x30</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CTRL</name>
          <description>RTC control register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x100</resetValue>
          <resetMask>0x175</resetMask>
          <fields>
            <field>
              <name>SEC_INT_EN</name>
              <description>RTC second interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CFG</name>
              <description>RTC second configuration control. This bit is self-cleared after synchronization</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAL_EN</name>
              <description>Calibration enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATUS</name>
          <description>RTC status register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x80071711</resetMask>
          <fields>
            <field>
              <name>SEC_INT</name>
              <description>Second interrupt flag</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CTRL_SYNC</name>
              <description>Control Register synchronization busy indicator</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>STATUS_SYNC</name>
              <description>Status Register synchronization busy indicator</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SEC_SYNC</name>
              <description>Second configuration Register synchronization busy indicator</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CALIB_SYNC</name>
              <description>Calibration Register synchronization busy indicator</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FREE_SYNC</name>
              <description>Free running counter control Register synchronization busy indicator</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THR_INT_SYNC</name>
              <description>Free running counter interrupt Threshold Register synchronization busy indicator</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>THR_RST_SYNC</name>
              <description>Free running counter Reset Threshold Register synchronization busy indicator</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FREE_RUNNING_INT</name>
              <description>Free running interrupt status.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SEC</name>
          <description>RTC second register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SEC</name>
              <description>Second configuration register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CAL</name>
          <description>RTC calibration register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFF</resetMask>
          <fields>
            <field>
              <name>PPM</name>
              <description>RTC calibration ppm value the precision is 1 ppm.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DIR</name>
              <description>RTC calibration direction indicator</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>FORWARD</name>
                  <description>forward calibrate</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BACKWARD</name>
                  <description>backward calibrate</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CNT_VAL</name>
          <description>RTC count value register</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x7FFF</resetMask>
          <fields>
            <field>
              <name>CNT</name>
              <description>RTC counter current value read only.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>15</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CNT2_CTRL</name>
          <description>Free running control register</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>CNT2_EN</name>
              <description>1 to enable free running counter</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CNT2_INT_EN</name>
              <description>1 to enable free running interrupt</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CNT2_WAKEUP</name>
              <description>1 to enable free running wakeup</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CNT2_RST</name>
              <description>1 to enable free running reset</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>THR_INT</name>
          <description>interrupt threshold of free running counter register</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF000000</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>THR_INT</name>
              <description>The Threshold of free running counter is to generate free running interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>THR_RST</name>
          <description>reset threshold of free running counter register</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFF000000</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>THR_RST</name>
              <description>The Threshold of free running counter is to generate free running reset.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CNT2</name>
          <description>free running count value</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CNT2</name>
              <description>The current value of free running counter</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>AGC</name>
      <description>agc</description>
      <groupName>AGC</groupName>
      <baseAddress>0x4000C000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1C</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CTRL0</name>
          <description>AGC control register 0</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x3954001</resetValue>
          <resetMask>0xFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PPF_INTRPT_MOD</name>
              <description>Control whether fsm can interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREZ_MOD</name>
              <description>Control whether fsm can restore last value when correalation trigh happens</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_GAIN_SEL</name>
              <description>LNA gain controlGAIN=26-12*LNA_GAIN_SEL</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_WEN</name>
              <description>Lna gain write enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PPF_GAIN</name>
              <description>PPF gain controlGain=36-3*PPF_GAIN</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PPF_WEN</name>
              <description>Ppf gain write enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PKWT_TH_DIG_1</name>
              <description>PKWT_TH_DIG + PKWT_TH_DIG_ADD in ccode</description>
              <bitOffset>13</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PD_CLR_EN</name>
              <description>Force clear analog PD</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PD_RST_LEN</name>
              <description>Pd disable time when reset0h0us 1h8us 2h16us 7h56us</description>
              <bitOffset>19</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RFAGC_FSYNC_DET_DIS</name>
              <description>Use to control rfagc gain adjust0brfagc stops when sync 1brfagc always on</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RFAGC_DIRECTION_FREEZE</name>
              <description>Use to disable rfagc gain adjust when switching antenna at direction found mode0b rfagc enable 1brfagc disable</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DOWN_24_EN</name>
              <description>Lna decrease 24dbm0bdisable 1benable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWITCH_PD_RST_LEN</name>
              <description>Pd disable time when direction found rfagc reset00b2us 01b4us 10b8us 11b16us</description>
              <bitOffset>25</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GLNA_MAX_REDU</name>
              <description>Lna max gain reduce 12dbm0bdisable 1benable</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL1</name>
          <description>AGC control register 1</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x5A10831</resetValue>
          <resetMask>0xFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PD3_TH_REG</name>
              <description>Pd3 threshold</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PD3_TH_HYST_REG</name>
              <description>Desired upper boundary</description>
              <bitOffset>3</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PKWT_TH_ANA_1</name>
              <description>PKWT_TH_ANA + PKWT_TH_ANA_ADD</description>
              <bitOffset>7</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PKWT_TH_ANA_0</name>
              <description>PKWT_TH_ANA in ccode</description>
              <bitOffset>13</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PKWT_TH_DIG_0</name>
              <description>PKWT_TH_DIG in ccode</description>
              <bitOffset>18</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SETL_TH_PPF_2</name>
              <description>SETL_TH_PPF_2 + DLY_DIG 1 in ccode</description>
              <bitOffset>23</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL2</name>
          <description>AGC control register 2</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x4800</resetValue>
          <resetMask>0x7F00</resetMask>
          <fields>
            <field>
              <name>PPF_PDVTH_LOW</name>
              <description>PPF peak detect threshold select</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_MG_PK</name>
              <description>LNA medium gain peak detect threshold selectAMP=(400-25* LNA_MG_PK)mv</description>
              <bitOffset>9</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_HG_PK</name>
              <description>LNA high gain peak detect threshold selectAMP=(100-8* LNA_HG_PK)mv</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL3</name>
          <description>AGC control register 3</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x12CC6C</resetValue>
          <resetMask>0x1FFFFF</resetMask>
          <fields>
            <field>
              <name>GF2_PAR00</name>
              <description>no description available</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GF2_PAR01</name>
              <description>no description available</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GF2_PAR10</name>
              <description>no description available</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SETL_TH_OVSHT_DIG</name>
              <description>no description available</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SETL_TH_OVSHT_INTRPT</name>
              <description>no description available</description>
              <bitOffset>15</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SETL_TH_OVSHT</name>
              <description>no description available</description>
              <bitOffset>18</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL4</name>
          <description>AGC control register 4</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xC49974</resetValue>
          <resetMask>0xFFFFFF</resetMask>
          <fields>
            <field>
              <name>SETL_TH_PD1</name>
              <description>no description available</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SETL_TH_PD2</name>
              <description>no description available</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SETL_TH_PD3_1</name>
              <description>no description available</description>
              <bitOffset>8</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SETL_TH_PD3_2</name>
              <description>no description available</description>
              <bitOffset>14</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>GF2_STAT24_TH</name>
              <description>no description available</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL5</name>
          <description>AGC control register 5</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>TEST_CTRL</name>
              <description>no description available</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT</name>
          <description>AGC status register</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x5700</resetValue>
          <resetMask>0x7FFFFF</resetMask>
          <fields>
            <field>
              <name>GLNA_CODE_OUT</name>
              <description>no description available</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>GF2_CODE_OUT</name>
              <description>no description available</description>
              <bitOffset>3</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RFAGC_TRIGGER_O</name>
              <description>no description available</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RF_GAIN</name>
              <description>no description available</description>
              <bitOffset>8</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>NUM_GAIN_ADJ</name>
              <description>no description available</description>
              <bitOffset>15</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CUR_STAT</name>
              <description>no description available</description>
              <bitOffset>20</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>PROP</name>
      <description>prop</description>
      <groupName>PROP</groupName>
      <baseAddress>0x4000D000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0xC</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>TX_BUF</name>
          <description>transmit data buffer input port register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>TX_BUF</name>
              <description>TX BUF</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RX_BUF</name>
          <description>received data buffer output register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>RX_BUF</name>
              <description>RX BUF</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT</name>
          <description>status register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x6</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>BIT_ORDER</name>
              <description>no description available</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_INTEN</name>
              <description>TX interrupt enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_INTEN</name>
              <description>RX interrupt enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_INT</name>
              <description>RX interrupt</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_INT</name>
              <description>TX interrupt</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RX_BUSY</name>
              <description>RX is busy</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_BUSY</name>
              <description>TX is busy</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CLR</name>
              <description>Clear intf control register.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>BLEDP</name>
      <description>bledp</description>
      <groupName>BLEDP</groupName>
      <baseAddress>0x4000E000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0xA4</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>DP_TOP_SYSTEM_CTRL</name>
          <description>datapath system control register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x808000F0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>RX_PDU_LEN_IN</name>
              <description>pdu length user programmed header+payload unit is bit.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AA_SEL</name>
              <description>access address selection</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PDU_LEN_SEL</name>
              <description>pdu length selection</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>H_IDX</name>
              <description>h index from 0.25 to 0.75 default is 0.5.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_EN_SEL</name>
              <description>rx enable select signal</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_EN_SEL</name>
              <description>tx enable select signal</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_REQ</name>
              <description>rx request.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_REQ</name>
              <description>tx request.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_MODE</name>
              <description>rx mode</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ANT_DATA_START</name>
              <description>ant mode data start signal need write 0 first then to 1.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DET_MODE</name>
              <description>detection mode 0low ppwer mode 1high performance mode.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PROP_MODE_CTRL</name>
          <description>properity mode control register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x50002300</resetValue>
          <resetMask>0xFFF733FF</resetMask>
          <fields>
            <field>
              <name>PROP_AA_ADDR_IN</name>
              <description>prop mode when access address is 5 byte the access address is {prop_aa_addr_in aa_addr_in} otherwise is aa_addr_in</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PROP_CRC_NUM</name>
              <description>prop mode crc number</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PROP_AA_NUM</name>
              <description>prop mode network address number</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PROP_PRE_NUM</name>
              <description>prop mode preamble number</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PROP_DATA_RATE</name>
              <description>prop mode data rate</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PROP_DIRECTION_RATE</name>
              <description>prop direction find mode sample rate</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PROP_DIRECTION_MODE</name>
              <description>prop direction find mode just work at prop mode.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_ALWAYS_ON</name>
              <description>rx always on</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_ALWAYS_ON</name>
              <description>tx always on</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_POWER_DONE_TIME</name>
              <description>tx power down time in ant mode and prop mode unit is us.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ACCESS_ADDRESS</name>
          <description>access address register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x8E89BED6</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>AA_ADDR_IN</name>
              <description>access address user programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANT_PDU_DATA0</name>
          <description>pdu data 0 to 1 byte, and preamble register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x5502FF3B</resetValue>
          <resetMask>0xFF9FFFFF</resetMask>
          <fields>
            <field>
              <name>PDU_DATA0</name>
              <description>pdu data 0 to 1 byte</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PATTERN_SEL</name>
              <description>pattern selection</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TEST_PATTERN_EN</name>
              <description>enable test pattern.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PROP_PREAMBLE_WEN</name>
              <description>when high enable manual prop mode preamble.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PROP_PREAMBLE</name>
              <description>prop mode preamble.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANT_PDU_DATA1</name>
          <description>pdu data 2 to 5 byte</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x7BE2E64</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PDU_DATA1</name>
              <description>pdu data 2 to 5 byte</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANT_PDU_DATA2</name>
          <description>pdu data 6 to 9 byte</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x129DA3CF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PDU_DATA2</name>
              <description>pdu data 6 to 9 byte</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANT_PDU_DATA3</name>
          <description>pdu data 10 to 13 byte</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x9B15238D</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PDU_DATA3</name>
              <description>pdu data 10 to 13 byte</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANT_PDU_DATA4</name>
          <description>pdu data 14 to 17 byte</description>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xAB898880</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PDU_DATA4</name>
              <description>pdu data 14 to 17 byte</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANT_PDU_DATA5</name>
          <description>pdu data 18 to 21 byte</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x42309CAB</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PDU_DATA5</name>
              <description>pdu data 18 to 21 byte</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANT_PDU_DATA6</name>
          <description>pdu data 22 to 25 byte</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xDE9B914</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PDU_DATA6</name>
              <description>pdu data 22 to 25 byte</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANT_PDU_DATA7</name>
          <description>pdu data 26 to 29 byte</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x2B4FD925</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PDU_DATA7</name>
              <description>pdu data 26 to 29 byte</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CRCSEED</name>
          <description>crc seed</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFFFF</resetValue>
          <resetMask>0x1FFFFFF</resetMask>
          <fields>
            <field>
              <name>CRC_SEED_IN</name>
              <description>user programmed crc seed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>24</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CRC_SEED_WEN</name>
              <description>when high enable manual program crc seed.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DP_FUNCTION_CTRL</name>
          <description>datapath function control register</description>
          <addressOffset>0x30</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1C273A40</resetValue>
          <resetMask>0xFFFF7FFF</resetMask>
          <fields>
            <field>
              <name>DP_STATISTICS_SEL</name>
              <description>datapath statistics selection.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CHF_COEF_WEN</name>
              <description>manual select channel filter coefficent.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CHF_COEF_IDX</name>
              <description>no description available</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LP_SNR_LEN_AUTO</name>
              <description>when enable auto adjust lp mode snr acc length otherwise the legnth fixed.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DOUT_ADJ_DIS</name>
              <description>data delay adjust disable.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LP_ADJ_MODE</name>
              <description>lp mode delay adjust mode</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FR_OFFSET_EN</name>
              <description>pdu frequency offset track enable.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DC_AVE_EN</name>
              <description>when high enable cfo estimation average.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIX_DELAY_EN</name>
              <description>no description available</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRACK_LEN</name>
              <description>track length</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRACK_LEN_WEN</name>
              <description>when high manual track length.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_FILT_EN</name>
              <description>when high enable xcorr filter.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_FULLWIN_EN</name>
              <description>when xcorr_win_auto_en low full sync enable.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_AA_LEN</name>
              <description>select access address bit number</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_AA_LEN_WEN</name>
              <description>enable manual correlation aa length.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_WIN_AUTO_EN</name>
              <description>correlation window size auto selection enable.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RESAMPLER_TAP</name>
              <description>resampler tap number</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RESAMPLER_TAP_WEN</name>
              <description>when high enable manual resampler tap number otherwise auto selection.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RESAMPLER_BP</name>
              <description>resampler enable or bypass</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FAGC_WIN_LEN</name>
              <description>select estimation length</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FAGC_WEN</name>
              <description>when high enable manual fine agc gain.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HP_CFO_EN</name>
              <description>when hp mode cfo estimation enable</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CFO_TRACK_EN</name>
              <description>tracking cfo enable.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CFO_INI_EN</name>
              <description>initial cfo enable.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC_IN_FLIP</name>
              <description>when 1 exchange i and q signals.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_EN_MODE</name>
              <description>transmit mode</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_EN_MODE</name>
              <description>receiver mode</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DP_TEST_CTRL</name>
          <description>datapath test iinterface register</description>
          <addressOffset>0x34</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFBFFBFF</resetMask>
          <fields>
            <field>
              <name>TIF_SEL</name>
              <description>test interface selection.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIF_CLK_SEL</name>
              <description>test interface clock selection</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORDIC_DAC_OUT</name>
              <description>when high cordic to dac</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIF_EN</name>
              <description>test interface enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IMR_INV</name>
              <description>datapath mixer nco if selection</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_TX_GATE_DIS</name>
              <description>clock tx gate disable</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_FULL_OFFRF_DIS</name>
              <description>(new standard)______when high rf always on in rx_en other wise when buffer full rf will be off.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_BUST_GATE_DIS</name>
              <description>clock burst gate disable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_RX_GATE_DIS</name>
              <description>clock rx gate disable</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_LPDET_GATE_DIS</name>
              <description>clock lp mode detector gate disable</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_HPDET_GATE_DIS</name>
              <description>clock hp mode detector gate disable</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLK_RFE_GATE_DIS</name>
              <description>clock rfe gate disable</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IQSWAP_XOR</name>
              <description>iq swap xor.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DAC_TEST_EN</name>
              <description>dac test enable dac input comes from register</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DAC_TEST</name>
              <description>dac input data value</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BLE_DP_STATUS1</name>
          <description>datapath status register 1</description>
          <addressOffset>0x38</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFF3FFF</resetMask>
          <fields>
            <field>
              <name>SNR_EST</name>
              <description>snr estimation</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CNR_EST</name>
              <description>cnr estimation</description>
              <bitOffset>8</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AGC_RSSI</name>
              <description>signal rssi db value.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AGC_RSSI_READY</name>
              <description>signal rssi valid.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SNR_VLD</name>
              <description>snr estimation valid.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CNR_VLD</name>
              <description>cnr estimation valid.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_BUSY</name>
              <description>tx busy signal.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BLE_DP_STATUS2</name>
          <description>datapath status register 2</description>
          <addressOffset>0x3C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xE03FFFFF</resetMask>
          <fields>
            <field>
              <name>VALID_PCK_NUM</name>
              <description>received valid packet number.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AA_ERR_NUM</name>
              <description>access address error number.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CRC_ERROR</name>
              <description>indicator of packet crc error.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>BURST_DET</name>
              <description>indicator of burst detection</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DP_STATUS_VLD_0</name>
              <description>data path status valid after access address valid.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BLE_DP_STATUS3</name>
          <description>datapath status register 3</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x7FF07FF</resetMask>
          <fields>
            <field>
              <name>FD_CFO_TRACK</name>
              <description>normalized cfo tracking estimation.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CFO_EST_FD</name>
              <description>normalized lp cfo initial estimation.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BLE_DP_STATUS4</name>
          <description>datapath status register 4</description>
          <addressOffset>0x44</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x8FFF03FF</resetMask>
          <fields>
            <field>
              <name>RESAMPLER_PH</name>
              <description>resampler phase.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>HP_CFO</name>
              <description>normalized hp cfo estimation.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>HP_CFO_VLD</name>
              <description>hp mode cfo estimation result valid</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RX_FRONT_END_CTRL1</name>
          <description>rx front end control register 1</description>
          <addressOffset>0x48</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x10000</resetValue>
          <resetMask>0x37FFF</resetMask>
          <fields>
            <field>
              <name>CFO_COMP</name>
              <description>______cfo user programmed.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>15</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DCNOTCH_GIN</name>
              <description>dc notch coefficient</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RX_FRONT_END_CTRL2</name>
          <description>rx front end control register 2</description>
          <addressOffset>0x4C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x10403000</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FAGC_GAIN</name>
              <description>fine agc gain.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FAGC_INI_VAL</name>
              <description>fagc gain initial value</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CNR_IDX_DELTA</name>
              <description>cnr index delta.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FAGC_REF</name>
              <description>fine agc signal reference.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORDIC_MIN_VIN_TH</name>
              <description>cordic input signal min threshold</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FREQ_TRADE_EN</name>
              <description>enable frequency trade when cordic input signal small than cordic_min_vin_th</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CHN_SHIFT</name>
              <description>channel filter shift</description>
              <bitOffset>29</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FREQ_DOMAIN_CTRL1</name>
          <description>frequency domain control register 1</description>
          <addressOffset>0x50</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x7F068000</resetValue>
          <resetMask>0xFF0E81FF</resetMask>
          <fields>
            <field>
              <name>SYNC_WORD_IN0</name>
              <description>manul sync word [3932]</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SYNC_WORD_WEN</name>
              <description>when high enable manul sync word</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SYNC_P_SEL</name>
              <description>no description available</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RD_EXBIT_EN</name>
              <description>read extra 8 samples after sync</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RFAGC_TRACK_DLY</name>
              <description>buffer settle threshold from 1us to 127us step is 1us</description>
              <bitOffset>17</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PROP_DF_16US</name>
              <description>prop mode direct found waiting 16 us.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FREQ_DOMAIN_CTRL2</name>
          <description>frequency domain control register 2</description>
          <addressOffset>0x54</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SYNC_WORD_IN1</name>
              <description>manul sync word [310]</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FREQ_DOMAIN_CTRL3</name>
          <description>frequency domain control register 3</description>
          <addressOffset>0x58</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF101816</resetValue>
          <resetMask>0x3F3F3F3F</resetMask>
          <fields>
            <field>
              <name>XCORR_PAR_TH3</name>
              <description>xcorr trigger par threshold3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_PAR_TH2</name>
              <description>xcorr trigger par threshold2</description>
              <bitOffset>8</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_PAR_TH1</name>
              <description>xcorr trigger par threshold1</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_PAR_TH0</name>
              <description>xcorr trigger par threshold0</description>
              <bitOffset>24</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FREQ_DOMAIN_CTRL4</name>
          <description>frequency domain control register 4</description>
          <addressOffset>0x5C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x304090B</resetValue>
          <resetMask>0x3F3F3F3F</resetMask>
          <fields>
            <field>
              <name>XCORR_POW_TH3</name>
              <description>xcorr power threshold3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_POW_TH2</name>
              <description>xcorr power threshold2</description>
              <bitOffset>8</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_POW_TH1</name>
              <description>xcorr power threshold1</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_POW_TH0</name>
              <description>xcorr power threshold0</description>
              <bitOffset>24</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FREQ_DOMAIN_CTRL5</name>
          <description>frequency domain control register 5</description>
          <addressOffset>0x60</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x457A8001</resetValue>
          <resetMask>0xFFFFF7F3</resetMask>
          <fields>
            <field>
              <name>GAIN_TED</name>
              <description>ted gain</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SYNC_DIN_SAT_VALUE</name>
              <description>&amp;lt;u 1 2&amp;gt;sync din amplitude limit value 0 to 1.75 correspond to 2 to 3.75</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SYNC_DIN_SAT_EN</name>
              <description>sync din amplitude limit enable</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CNT_SETTLE_IDX</name>
              <description>buffer settle threshold from 32 to 256 step is 32</description>
              <bitOffset>8</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRIG_XCORR_CNT</name>
              <description>correlation search window size.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_RSSI_TH3</name>
              <description>xcorr triger rssi threshold0</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_RSSI_TH2</name>
              <description>xcorr triger rssi threshold0</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_RSSI_TH1</name>
              <description>xcorr triger rssi threshold0</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XCORR_RSSI_TH0</name>
              <description>xcorr triger rssi threshold0</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FREQ_DOMAIN_CTRL6</name>
          <description>frequency domain control register 5</description>
          <addressOffset>0x64</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x11207B09</resetValue>
          <resetMask>0x333FFF1F</resetMask>
          <fields>
            <field>
              <name>HP_TRAIN_SIZ</name>
              <description>hp mode training size.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HP_HIDX_GAIN</name>
              <description>h index reference gain when hp mode default is 1.0</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>H_REF_GAIN</name>
              <description>h index reference gain when frequency offset track default is 1.0</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DET_FR_IDX</name>
              <description>pdu cfo tracking loop gain</description>
              <bitOffset>24</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CFO_FR_IDX</name>
              <description>aa cfo tracking loop gain</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>HP_MODE_CTRL1</name>
          <description>when high hp mode training size same as cfo tracking.</description>
          <addressOffset>0x68</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x80120D0A</resetValue>
          <resetMask>0xFF3F3F3F</resetMask>
          <fields>
            <field>
              <name>HP_BMC_P_TRACK</name>
              <description>p paramter in search period of frequency offset iir of bmc</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HP_BMC_P_TRAIN</name>
              <description>p paramter in training period of frequency offset iir of bmc</description>
              <bitOffset>8</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HP_BMC_CZ1</name>
              <description>cz1 parameter.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_IDX_DELTA</name>
              <description>buffer index delta</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WMF2_DSAMP_IDX</name>
              <description>wmf2 down sampling position -4 to 3</description>
              <bitOffset>28</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HP_TRAIN_SIZ_FIX</name>
              <description>when high hp mode training size same as cfo tracking.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>HP_MODE_CTRL2</name>
          <description>q paramter in training period of phase offset iir of bmc</description>
          <addressOffset>0x6C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x717B1122</resetValue>
          <resetMask>0xFFFF13FF</resetMask>
          <fields>
            <field>
              <name>SNR_EST_REF</name>
              <description>signal amplitude used in snr estimation whose unit is db</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SNR_EST_LEN</name>
              <description>symbol number used in snr estimation when pdu length is less than 4 8 32 will be used otherwise the value configured from register will be used</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SNR_EST_EN</name>
              <description>snr estimation in time domain enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HP_BMC_Q_TRACK</name>
              <description>q paramter in search period of phase offset iir of bmc</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HP_BMC_Q_TRAIN</name>
              <description>q paramter in training period of phase offset iir of bmc</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FREQ_DOMAIN_STATUS1</name>
          <description>frequency domain status register 1</description>
          <addressOffset>0x70</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xF1FF03FF</resetMask>
          <fields>
            <field>
              <name>MAX_XCORR</name>
              <description>xcorr_org value at the max par position</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PKT_OFFSET_COM</name>
              <description>time from access addres last bit to trigger finish.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>NIDX</name>
              <description>noise db buffer index</description>
              <bitOffset>28</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FREQ_DOMAIN_STATUS2</name>
          <description>frequency domain status register 2</description>
          <addressOffset>0x74</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x3FF03FF</resetMask>
          <fields>
            <field>
              <name>MAX_PAR_SPWR</name>
              <description>spwr value at the max par position</description>
              <bitOffset>0</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MAX_PAR_XCORR</name>
              <description>xcorr*xcorr value at the max par position</description>
              <bitOffset>16</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DP_AA_ERROR_CTRL</name>
          <description>AA error control register</description>
          <addressOffset>0x84</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>IQSWAP_SEL</name>
              <description>when high adc data iq swap with analog iqswap. datapath mixer nco if selection changed with analog iqswap.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AA_ERROR_EN</name>
              <description>when high it will reset datapath when aa error.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AA_ERROR_CNR_EN</name>
              <description>when high the aa error reset condition is cnr &amp;gt; threshold and aa error. when low it don care cnr.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AA_ERROR_CNR_SEL</name>
              <description>when high the cnr threshold is 24. when low the cnr threshold is 32.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DP_INT</name>
          <description>data path interrupt register</description>
          <addressOffset>0x88</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xC0000000</resetValue>
          <resetMask>0xFFFF000F</resetMask>
          <fields>
            <field>
              <name>DP_INTERRUPT0</name>
              <description>datapath interrupt0</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DP_INTERRUPT1</name>
              <description>datapath interrupt1</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DP_INTERRUPT2</name>
              <description>datapath interrupt2</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DP_INTERRUPT</name>
              <description>datapath interrupt</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DP_INTERRUPT0_SEL</name>
              <description>datapath interrupt0 selection</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DP_INTERRUPT1_SEL</name>
              <description>datapath interrupt1 selection</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DP_INTERRUPT2_SEL</name>
              <description>datapath interrupt2 selection</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DP_INTERRUPT0_MSK</name>
              <description>datapath interrupt0 msk</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DP_INTERRUPT1_MSK</name>
              <description>datapath interrupt1 msk</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DP_INTERRUPT2_MSK</name>
              <description>datapath interrupt2 msk</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DP_INTERRUPT_MSK</name>
              <description>datapath interrupt msk</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DP_AA_ERROR_TH</name>
          <description>AA error threshold register</description>
          <addressOffset>0x8C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x35351820</resetValue>
          <resetMask>0xFFFF3F7F</resetMask>
          <fields>
            <field>
              <name>HP_TRAIN_POSITION</name>
              <description>when high use the bits just ahead of pdu for rsve training. when low the training bit starts at the track bits.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORDIC_IN_SCALE</name>
              <description>when high cordic input will be auto scaled(shift) according to the magnitude of real/imag data.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PAR_AUTO_HIGHER_SEL</name>
              <description>when high par auto higher 1/4 when low par auto higher 1/8 it will work together with par_auto_higher_en and rssi_good_dbm.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PAR_AUTO_HIGHER_EN</name>
              <description>when high when signal is good ( rssi large than rssi_good_dbm) it will auto higher the par threshold.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SNR_GOOD_TH</name>
              <description>threshold for snr(fd mode calculated use aa) to reset datapath cooperate with cnr snr and aa error.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CNR_GOOD_TH</name>
              <description>threshold for cnr to reset datapath cooperate with cnr snr and aa error.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RSSI_GOOD_TH</name>
              <description>threshold for rssi to reset datapath cooperate with cnr snr and aa error.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RSSI_GOOD_DBM</name>
              <description>when rssi dbm large than the -rssi_good_dbm the signal is good enough to higher the par threshold if the function enable.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DF_ANTENNA_CTRL</name>
          <description>antenna register</description>
          <addressOffset>0x90</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x6</resetValue>
          <resetMask>0xFFFF01FF</resetMask>
          <fields>
            <field>
              <name>SWITCH_MAP_SEL_8F</name>
              <description>switch antenna map selection 8 to f</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWITCH_MAP_SEL_07</name>
              <description>switch antenna map selection 0 to 7</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EXT_ANTENNA_NUM</name>
              <description>user programmed switch antenna number</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EXT_ANTENNA_NUM_WEN</name>
              <description>user programmed switch antenna enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUFFER_BP</name>
              <description>when high, bypass buffer, and not write/read buffer for datapath power test</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TEST_TD_POWER</name>
              <description>when high, test rfe,td detector power, other module don't work, the cordic work or not decided by resampler_bp</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TEST_FD_POWER</name>
              <description>when high, test rfe, cordic and fd detector power, other module don't work</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TEST_SYNC_POWER</name>
              <description>when high, test rfe. Cordic and sync power. Other module don't work</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TEST_RFE_CORDIC_POWER</name>
              <description>when high, test rfe and cordic power, other module don't work</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TEST_RFE_POWER</name>
              <description>when high, test rfe power, other module don't work</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ADC01_SAMPLE_TIME</name>
              <description>when high, will exchange the adc0/adc1 sample time, to avoid the error sample time for adc0/adc1</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PHY_RATE_MUX</name>
              <description>ble data rate used in datapath, 0: 1mbps 1: 2mbps</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PHY_RATE_REG</name>
              <description>user programmed phy data rate</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PHY_RATE_WEN</name>
              <description>0: phy rate comes from ble ip 1:phy rate comes from regsiter phy_rate_reg</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PDU_RSSI_WAIT_TIME</name>
              <description>0:wait 0us 1: wait 4us</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PDU_RSSI_WIN_LEN</name>
              <description>select estimation length for pdu rssi calculate</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAL_PDU_RSSI_EN</name>
              <description>calculate rssi use pdu data enbale.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PROP_CRC_AA_DIS</name>
              <description>prop mode crc check disable check access address.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PROP_AA_LSB_FIRST</name>
              <description>prop mode access address lsb first for cbt test.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PRE_NUM_WEN</name>
              <description>preamble number write enable</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANTENNA_MAP01</name>
          <description>antenna switch map register 0</description>
          <addressOffset>0x94</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x18801840</resetValue>
          <resetMask>0x3FFF3FFF</resetMask>
          <fields>
            <field>
              <name>SWITCH_MAP_1</name>
              <description>switch antenna map 1</description>
              <bitOffset>0</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWITCH_MAP_0</name>
              <description>switch antenna map 0</description>
              <bitOffset>16</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANTENNA_MAP23</name>
          <description>antenna switch map register 1</description>
          <addressOffset>0x98</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x14201410</resetValue>
          <resetMask>0x3FFF3FFF</resetMask>
          <fields>
            <field>
              <name>SWITCH_MAP_3</name>
              <description>switch antenna map 3</description>
              <bitOffset>0</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWITCH_MAP_2</name>
              <description>switch antenna map 2</description>
              <bitOffset>16</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANTENNA_MAP45</name>
          <description>antenna switch map register 2</description>
          <addressOffset>0x9C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x22082204</resetValue>
          <resetMask>0x3FFF3FFF</resetMask>
          <fields>
            <field>
              <name>SWITCH_MAP_5</name>
              <description>switch antenna map 5</description>
              <bitOffset>0</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWITCH_MAP_4</name>
              <description>switch antenna map 4</description>
              <bitOffset>16</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ANTENNA_MAP67</name>
          <description>antenna switch map register 3</description>
          <addressOffset>0xA0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x21022101</resetValue>
          <resetMask>0x3FFF3FFF</resetMask>
          <fields>
            <field>
              <name>SWITCH_MAP_7</name>
              <description>switch antenna map 7</description>
              <bitOffset>0</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SWITCH_MAP_6</name>
              <description>switch antenna map 6</description>
              <bitOffset>16</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>CALIB</name>
      <description>calib</description>
      <groupName>CALIB</groupName>
      <baseAddress>0x4000F000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x83C</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>START</name>
          <description>calibration start register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>PO_CLB_START</name>
              <description>Power on calibration start</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>HOP_CLB_START</name>
              <description>Frequency hop calibration start</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>OSC_CLB_START</name>
              <description>OSC calibration start</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>REF_CLB_START</name>
              <description>REF PLL calibration start</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>RCO_CLB_START</name>
              <description>RCO calibration start</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>XTL_CLB_START</name>
              <description>XTAL calibration start</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATUS</name>
          <description>calibration FSM status register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x3FFFFFFF</resetMask>
          <fields>
            <field>
              <name>TOP_FSM</name>
              <description>TOP FSM</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DC_FSM</name>
              <description>DC FSM</description>
              <bitOffset>5</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>VCOA_FSM</name>
              <description>VCOA FSM</description>
              <bitOffset>9</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>VCOF_FSM</name>
              <description>VCOF FSM</description>
              <bitOffset>12</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>KVCO_FSM</name>
              <description>KVCO FSM</description>
              <bitOffset>17</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RCO_FSM</name>
              <description>RCO FSM</description>
              <bitOffset>21</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OSC_FSM</name>
              <description>OSC FSM</description>
              <bitOffset>24</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>REF_FSM</name>
              <description>REF FSM</description>
              <bitOffset>27</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DC_CODE</name>
          <description>DC code status register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x20200088</resetValue>
          <resetMask>0x3F3F00FF</resetMask>
          <fields>
            <field>
              <name>PPF_DCCAL2_I</name>
              <description>Power on DC calibration i code</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PPF_DCCAL2_Q</name>
              <description>Power on DC calibration q code</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PPF_DCCAL_I</name>
              <description>DC re-calibration i code</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PPF_DCCAL_Q</name>
              <description>DC re-calibration q code</description>
              <bitOffset>24</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DC_CFG</name>
          <description>DC code configured code register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x400000</resetValue>
          <resetMask>0xFF7F03FF</resetMask>
          <fields>
            <field>
              <name>PPF_DCCAL2_CFG_I</name>
              <description>Power on DC calibration i code configured</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PPF_DCCAL2_CFG_Q</name>
              <description>Power on DC calibration q code configured</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DC_2NDCAL_DIS</name>
              <description>DC calibration disable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DC_2NDCAL_REQ</name>
              <description>DC calibration request</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PPF_DCCAL_CFG_I</name>
              <description>DC re-calibration i code configured</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DC_HOP_CAL_BP</name>
              <description>DC hop calibration bypass</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PPF_DCCAL_CFG_Q</name>
              <description>DC re-calibration q code configured</description>
              <bitOffset>24</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DC_1STCAL_DIS</name>
              <description>DC hop calibration disable</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DC_1STCAL_REQ</name>
              <description>DC hop calibration request</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RCO_RC_REF_OSC_CODE</name>
          <description>RCO RC PLL48M OSC code status register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x8001F00</resetValue>
          <resetMask>0xF0F1F0F</resetMask>
          <fields>
            <field>
              <name>CAU_RCO_CAP</name>
              <description>RCO calibration output code</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CAU_OSC_CUR</name>
              <description>OSC calibration output code</description>
              <bitOffset>8</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CAU_RC_CAL_OUT2REG</name>
              <description>RC calibration output code</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PLL48_ENREF</name>
              <description>REF calibration output code</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RCO_RC_REF_OSC_CFG</name>
          <description>RCO RC PLL48M OSC configured code register</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3F3F7F3F</resetMask>
          <fields>
            <field>
              <name>CAU_RCO_CAP_CFG</name>
              <description>RCO calibration code configured</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RCO_CAL_DIS</name>
              <description>RCO calibration disable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RCO_CAL_REQ</name>
              <description>RCO calibration request</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAU_OSC_CUR_CFG</name>
              <description>OSC calibration output code configured</description>
              <bitOffset>8</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OSC_CAL_DIS</name>
              <description>OSC calibration disable</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OSC_CAL_REQ</name>
              <description>OSC calibration request</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAU_RC_CAL_REG_IN</name>
              <description>RC calibration code to analog</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAU_RC_CAL_DIS</name>
              <description>RC calibration disable</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RC_CAL_REQ</name>
              <description>RC calibration request</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PLL48_ENREF_CFG</name>
              <description>REF calibration output code configured</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REF_CAL_DIS</name>
              <description>REF PLL calibration disable</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REF_CAL_REQ</name>
              <description>REF PLL calibration request</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>VCOA_KVCO2M_CODE</name>
          <description>reserved</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x400</resetValue>
          <resetMask>0x1F1F07FF</resetMask>
          <fields>
            <field>
              <name>KCALF2M_PO</name>
              <description>KVCO 2M mode calibration power on code</description>
              <bitOffset>0</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_VCO_AMP</name>
              <description>VCO TX amplitude calibration output code</description>
              <bitOffset>16</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RX_VCO_AMP</name>
              <description>VCO RX amplitude calibration output code</description>
              <bitOffset>24</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>VCOA_KVCO2M_CFG</name>
          <description>reserved</description>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1F7F7FFF</resetMask>
          <fields>
            <field>
              <name>KCALF2M_CFG</name>
              <description>KVCO 2M mode calibration code configure</description>
              <bitOffset>0</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>KCALF2M_BP</name>
              <description>bypass KVCO 2M mode power on calibration</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>KVCO_CAL_E</name>
              <description>no description available</description>
              <bitOffset>12</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_VCO_AMP_CFG</name>
              <description>TX VCO amplitude calibration output code configured</description>
              <bitOffset>16</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCOA_CAL_DIS</name>
              <description>VCO amplitude calibration disable</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCOA_CAL_REQ</name>
              <description>VCO amplitude calibration request</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_VCO_AMP_CFG</name>
              <description>RX VCO amplitude calibration output code configured</description>
              <bitOffset>24</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>VCOF_KVCO_PO_CODE</name>
          <description>reserved</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x20200400</resetValue>
          <resetMask>0x3F3F07FF</resetMask>
          <fields>
            <field>
              <name>KCALF_PO</name>
              <description>KVCO power up calibration result</description>
              <bitOffset>0</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_VCO_CBANK_PO</name>
              <description>TX VCO frequency power on calibration output code</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RX_VCO_CBANK_PO</name>
              <description>RX VCO frequency power on calibration output code</description>
              <bitOffset>24</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>VCOF_KVCO_CFG</name>
          <description>VCOF hop calibration bypass</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF3FFF</resetMask>
          <fields>
            <field>
              <name>KCALF_CFG</name>
              <description>KVCO calibration code configure</description>
              <bitOffset>0</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>KVCO_REQ</name>
              <description>KVCO calibration request</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>KVCO_DIS</name>
              <description>KVCO calibration disable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>KVCO_SKIP</name>
              <description>KVCO hop calibration calculation skip</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_VCO_CBANK_CFG</name>
              <description>TX VCO frequency calibration output code configured</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCOF_CAL_DIS</name>
              <description>VCO frequency calibration disable</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCOF_CAL_REQ</name>
              <description>VCO frequency calibration request</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_VCO_CBANK_CFG</name>
              <description>RX VCO frequency calibration output code configured</description>
              <bitOffset>24</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCOF_SKIP</name>
              <description>VCOF hop calibration calculation skip</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCOF_HOP_BP</name>
              <description>VCOF hop calibration bypass</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>VCOF_KVCO_CODE</name>
          <description>reserved</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x20200400</resetValue>
          <resetMask>0x3F3F07FF</resetMask>
          <fields>
            <field>
              <name>KCALF</name>
              <description>KVCO calibration output at carrier frequency</description>
              <bitOffset>0</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TX_VCO_CBANK</name>
              <description>TX VCO frequency calibration output code</description>
              <bitOffset>16</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RX_VCO_CBANK</name>
              <description>RX VCO frequency calibration output code</description>
              <bitOffset>24</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>KVCO_HOP_CODE</name>
          <description>reserved</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x4000400</resetValue>
          <resetMask>0x7FF07FF</resetMask>
          <fields>
            <field>
              <name>KCALF1M</name>
              <description>KVCO hop calibration output at carrier frequency in 1M mode</description>
              <bitOffset>0</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>KCALF2M</name>
              <description>KVCO hop calibration output at carrier frequency in 2M mode</description>
              <bitOffset>16</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>VCOF_CNT_SLOPE</name>
          <description>reserved</description>
          <addressOffset>0x30</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1F3F1F3F</resetMask>
          <fields>
            <field>
              <name>TX_VCOF_CNT</name>
              <description>TX VCO frequency power up calibration 8us count value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_SLOPE</name>
              <description>TX frequency curve slope</description>
              <bitOffset>8</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_VCOF_CNT</name>
              <description>RX VCO frequency power up calibration 8us count value</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_SLOPE</name>
              <description>RX frequency curve slope</description>
              <bitOffset>24</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>XTL_CODE</name>
          <description>Reserved</description>
          <addressOffset>0x34</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x3F</resetValue>
          <resetMask>0x13F</resetMask>
          <fields>
            <field>
              <name>XTL_XICTRL_CODE</name>
              <description>crystal calibration code</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>XTL_AMP_DET_OUT</name>
              <description>crystal comparator output result</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>XTL_CFG</name>
          <description>Reserved</description>
          <addressOffset>0x38</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x3F</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>XTL_XICTRL_CFG</name>
              <description>crystal calibration CFG</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTL_CAL_DIS</name>
              <description>crystal code disable</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTL_CAL_REQ</name>
              <description>crystal calibration request</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CAL_DLY</name>
          <description>hop calibration delay bypass</description>
          <addressOffset>0x3C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x36464113</resetValue>
          <resetMask>0xFFFFFFBF</resetMask>
          <fields>
            <field>
              <name>HOP_DLY</name>
              <description>hop calibration delay time</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HOP_DLY_BP</name>
              <description>hop calibration delay bypass</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_DLY_DIG1M</name>
              <description>no description available</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_DLY_DIG2M</name>
              <description>no description available</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_DLY_DAC_1M</name>
              <description>no description available</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_DLY_DAC_2M</name>
              <description>no description available</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_PWRUP_CNT_TH1M</name>
              <description>no description available</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_PWRUP_CNT_TH2M</name>
              <description>no description available</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DONE</name>
          <description>Reserved</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x1FDC</resetValue>
          <resetMask>0x1FFC</resetMask>
          <fields>
            <field>
              <name>OSC_CAL_DONE</name>
              <description>OSC calibration done</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>REF_CAL_DONE</name>
              <description>REF PLL calibration done</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RCO_CAL_DONE</name>
              <description>RCO calibration done</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RC_CAL_DONE</name>
              <description>RC calibration done</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>VCOF_CAL_DONE</name>
              <description>VCO frequency calibration done</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>VCOA_CAL_DONE</name>
              <description>VCO amplitude calibration done</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DC2ND_CAL_DONE</name>
              <description>DC 2nd stage calibration done</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DC1ST_CAL_DONE</name>
              <description>DC 1st stage calibration done</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>XTL_CAL_DONE</name>
              <description>XTL calibration done</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>KVCO_CAL_DONE</name>
              <description>KVCO calibration done</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>KVCO_HOP_DONE</name>
              <description>KVCO calibration done</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>RRF1</name>
          <description>Amplitude of LO buffer for active mixer</description>
          <addressOffset>0x400</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xA8AADC44</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>RRF_INCAP2</name>
              <description>LNA input LC cap bank</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_LOAD_CAP</name>
              <description>LNA load LC cap bank</description>
              <bitOffset>3</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_TX_INCAP1</name>
              <description>LNA&amp;amp;PA matching cap bank</description>
              <bitOffset>7</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_RX_INCAP1</name>
              <description>LNA&amp;amp;PA matching cap bank</description>
              <bitOffset>10</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_VGATE11_LNA</name>
              <description>LNA vrega voltage</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_BM_GM</name>
              <description>Constant gm current control</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_BM_LNA</name>
              <description>LNA bias current control-</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_BM_MIXER</name>
              <description>Mixer current bias</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PPF_DCCAL_RES</name>
              <description>Input res selection of ppf for dccal</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_CAL_MIX_EN</name>
              <description>no description available</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_CAL_MIX1_EN</name>
              <description>no description available</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_LO_SEL_P</name>
              <description>Dc voltage bias control for the pmos switch of active mixer</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_LO_SEL_N</name>
              <description>Dc voltage bias control for the nmos switch of active mixer</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RRF_LO_AMP</name>
              <description>Amplitude of LO buffer for active mixer</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PLL48_PPF</name>
          <description>reserved</description>
          <addressOffset>0x404</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x5A</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>PPF_BM</name>
              <description>Ppf current control-</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PPF_IQSW</name>
              <description>no description available</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PLL48_DIFF_CLK_48M_DIS</name>
              <description>no description available</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PLL48_TST_CPREF</name>
              <description>CP current selecting</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LO0</name>
          <description>reserved</description>
          <addressOffset>0x408</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x8A8F50</resetValue>
          <resetMask>0xFF8FFFFF</resetMask>
          <fields>
            <field>
              <name>VCO_DAC_IPTAT</name>
              <description>Set the temperature characteristic of TX DAC in order to compensate the modulation gain error of the VCO</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_TST_CP</name>
              <description>LO CP current control-</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_VTUN_SET</name>
              <description>Set VTUNE voltage change in order to properly compensate the VUNE error introduced by charge injection when the PLL loop is broken;VTUNE change introduced by this register is around 50uV*(VTUNE_SET-16)</description>
              <bitOffset>8</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_ACAL_SET</name>
              <description>Set the threshold (differential peak) in VCO amplitude calibration-VTH=0.2+0.05*ACAL_SET</description>
              <bitOffset>13</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_BM_TXFIL</name>
              <description>Set the bias current of the TX filter</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_BM_TXDAC</name>
              <description>Set the bias current of the TX DAC</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_SAMP_EN</name>
              <description>no description available</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_CAP_HALF_EN</name>
              <description>no description available</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_SET_VCO_VDD_LOW</name>
              <description>no description available</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_8OR16M_INV_EN</name>
              <description>no description available</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_DIV_PD_EN</name>
              <description>no description available</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_TXDLY1M</name>
              <description>no description available</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_TXDLY2M</name>
              <description>no description available</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_RX_CK_TST</name>
              <description>no description available</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_DSM_INT_EN</name>
              <description>no description available</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LO1</name>
          <description>Reserved</description>
          <addressOffset>0x40C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xBA010</resetValue>
          <resetMask>0xFFFFF</resetMask>
          <fields>
            <field>
              <name>SPEED_UP_TIME</name>
              <description>LO speed up time</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SW_LO_SPEED_UP</name>
              <description>software LO speed up</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_PLLPFD_EN</name>
              <description>PLL pfd enable in RX mode</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_PLLPFD_EN</name>
              <description>PLL pfd enable in TX mode</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LO_SET_TIME</name>
              <description>LO settle time</description>
              <bitOffset>8</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MOD_TEST</name>
              <description>LO open loop or close loop select</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DIV_DIFF_CLK_LO_DIS</name>
              <description>no description available</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TX_VCO_FTC_SET</name>
              <description>no description available</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RX_VCO_FTC_SET</name>
              <description>no description available</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PA_CTRL</name>
          <description>Reserved</description>
          <addressOffset>0x410</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xAC040A</resetValue>
          <resetMask>0x1FF0F3F</resetMask>
          <fields>
            <field>
              <name>PA_ON_DLY</name>
              <description>PA turn on delay time</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA_OFF_DLY</name>
              <description>PA turn off delay time</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA_INCREASE_SEL</name>
              <description>PA output power increasing control</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA_SEL_BIAS</name>
              <description>PA duty cycle voltage bias</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA_BM_CUR</name>
              <description>Pa bias current control</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA_VDUTY_CYCLE_SEL</name>
              <description>PA duty cycle control voltage select</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PA_VCDCG</name>
              <description>PA duty cycle control</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL</name>
          <description>Reserved</description>
          <addressOffset>0x800</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x50000</resetValue>
          <resetMask>0x7F0113</resetMask>
          <fields>
            <field>
              <name>RC_TIM</name>
              <description>RC calibration reset time</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_TEST_INT</name>
              <description>no description available</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HOP_CLB_SEL</name>
              <description>Frequency hop calibration start select</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTL_PO_TIM</name>
              <description>crystal calibration power on wait time</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTL_CAL_TIM</name>
              <description>crystal calibration code wait time</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTL_AMP_DET_PWR_SEL</name>
              <description>crystal amplitude detector power select</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>PO1MS</name>
                  <description>power on detector only 1ms each code</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>POCAL</name>
                  <description>power on detector during all calibration time</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>POALWAYS</name>
                  <description>always power on detector</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PDALWAYS</name>
                  <description>always power down detector</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>XTL_SWCAL_EN</name>
              <description>crystal software calibration enable</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_RAW</name>
          <description>Reserved</description>
          <addressOffset>0x804</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1013F</resetMask>
          <fields>
            <field>
              <name>PO_CAL_DONE_INT</name>
              <description>power on calibration done interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>HOP_CAL_DONE_INT</name>
              <description>hop calibration done interrupt</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>OSC_CAL_DONE_INT</name>
              <description>OSC calibration done interrupt</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>REF_CAL_DONE_INT</name>
              <description>REF PLL calibration done interrupt</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>RCO_CAL_DONE_INT</name>
              <description>RCO calibration done interrupt</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>XTL_CAL_DONE_INT</name>
              <description>XTL calibration done interrupt</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>PO_ALL_DONE_INT</name>
              <description>RCO &amp;amp; REF &amp;amp; OSC &amp;amp; Power on calibration all done interrupt. And signal of above interrupt</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CAL_INT</name>
              <description>or signal of all calibration interrupt</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTEN</name>
          <description>Reserved</description>
          <addressOffset>0x808</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x13F</resetMask>
          <fields>
            <field>
              <name>PO_CAL_DONE_INTEN</name>
              <description>power on calibration done interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HOP_CAL_DONE_INTEN</name>
              <description>hop calibration done interrupt enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>OSC_CAL_DONE_INTEN</name>
              <description>OSC calibration done interrupt enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REF_CAL_DONE_INTEN</name>
              <description>REF PLL calibration done interrupt enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RCO_CAL_DONE_INTEN</name>
              <description>RCO calibration done interrupt enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>XTL_CAL_DONE_INTEN</name>
              <description>XTL calibration done interrupt enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PO_ALL_DONE_INTEN</name>
              <description>PO_ALL_DONE_INT enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_STAT</name>
          <description>Reserved</description>
          <addressOffset>0x80C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1013F</resetMask>
          <fields>
            <field>
              <name>PO_CAL_DONE_INT_STAT</name>
              <description>power on calibration done interrupt status</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>HOP_CAL_DONE_INT_STAT</name>
              <description>hop calibration done interrupt status</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>OSC_CAL_DONE_INT_STAT</name>
              <description>OSC calibration done interrupt status</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>REF_CAL_DONE_INT_STAT</name>
              <description>REF PLL calibration done interrupt status</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RCO_CAL_DONE_INT_STAT</name>
              <description>RCO calibration done interrupt status</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>XTL_CAL_DONE_INT_STAT</name>
              <description>XTL calibration done interrupt status</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PO_ALL_DONE_INT_STAT</name>
              <description>PO_ALL_DONE_INT status</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CAL_INT_STAT</name>
              <description>calibration all interrupt status</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIF</name>
          <description>reserved</description>
          <addressOffset>0x810</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>TEST_CTRL</name>
              <description>Test interface selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>KVCO_MEAN</name>
          <description>reserved</description>
          <addressOffset>0x814</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFFF</resetMask>
          <fields>
            <field>
              <name>KVCO_CNT_MEAN</name>
              <description>KVCO counter 1 and counter 2 mean</description>
              <bitOffset>0</bitOffset>
              <bitWidth>21</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>KVCO_DLT</name>
          <description>reserved</description>
          <addressOffset>0x818</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FF</resetMask>
          <fields>
            <field>
              <name>KVCO_CNT_DLT</name>
              <description>KVCO counter 1 and counter 2 delta</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LO_CFG</name>
          <description>no description available</description>
          <addressOffset>0x81C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x3B6DB6E</resetValue>
          <resetMask>0xCFFFFFFF</resetMask>
          <fields>
            <field>
              <name>LO_INT_CFG</name>
              <description>no description available</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LO_FRAC_CFG</name>
              <description>no description available</description>
              <bitOffset>6</bitOffset>
              <bitWidth>22</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LO_SEL</name>
              <description>no description available</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LO_CHANGE</name>
              <description>no description available</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LO_TABLE</name>
          <description>no description available</description>
          <addressOffset>0x820</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x3B6DB6E</resetValue>
          <resetMask>0x3FFFFFF</resetMask>
          <fields>
            <field>
              <name>LO_INT_TABLE</name>
              <description>no description available</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>LO_FRAC_TABLE</name>
              <description>no description available</description>
              <bitOffset>6</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LO_RATIO</name>
          <description>no description available</description>
          <addressOffset>0x824</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x3B6DB6E</resetValue>
          <resetMask>0xFFFFFFF</resetMask>
          <fields>
            <field>
              <name>LO_INT</name>
              <description>no description available</description>
              <bitOffset>0</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>LO_FRAC</name>
              <description>no description available</description>
              <bitOffset>6</bitOffset>
              <bitWidth>22</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>VCO_MOD_CFG</name>
          <description>TRX 2M mode selection signal</description>
          <addressOffset>0x828</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1F</resetMask>
          <fields>
            <field>
              <name>VCO_MOD_TX_CFG</name>
              <description>VCO_MOD_TX register configured value. See section 6.10.5 for detail.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VCO_MOD_TX_SEL</name>
              <description>VCO_MOD_TX selection</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRX2M_MODE_CFG</name>
              <description>TRX 2M mode software configured value</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRX2M_MODE_SEL</name>
              <description>TRX 2M mode selection signal</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>IMR</name>
              <description>no description available</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>VCO_MOD_STAT</name>
          <description>no description available</description>
          <addressOffset>0x82C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x5</resetMask>
          <fields>
            <field>
              <name>VCO_MOD_TX</name>
              <description>no description available</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TRX2M_MODE</name>
              <description>no description available</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CH_IDX</name>
          <description>no description available</description>
          <addressOffset>0x830</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>CH_IDX</name>
              <description>no description available</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>VCOF_CNT_UP</name>
          <description>reserved</description>
          <addressOffset>0x834</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF00FF</resetMask>
          <fields>
            <field>
              <name>TX_VCOF_CNT_UP</name>
              <description>TX VCO frequency power up calibration 8us count value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RX_VCOF_CNT_UP</name>
              <description>RX VCO frequency power up calibration 8us count value</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>VCOF_CNT_DN</name>
          <description>reserved</description>
          <addressOffset>0x838</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF00FF</resetMask>
          <fields>
            <field>
              <name>TX_VCOF_CNT_DN</name>
              <description>TX VCO frequency power up calibration 8us count value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RX_VCOF_CNT_DN</name>
              <description>RX VCO frequency power up calibration 8us count value</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>SPIFI0</name>
      <description>spifi</description>
      <groupName>SPIFI</groupName>
      <baseAddress>0x40080000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x20</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CTRL</name>
          <description>SPIFI control register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x400FFFFF</resetValue>
          <resetMask>0xF8EFFFFF</resetMask>
          <fields>
            <field>
              <name>TIMEOUT</name>
              <description>This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CSHIGH</name>
              <description>This field controls the minimum CS high time, expressed as a number of serial clock periods minus one.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>D_PRFTCH_DIS</name>
              <description>This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INTEN</name>
              <description>If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MODE3</name>
              <description>SPI Mode 3 select.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SCK_LOW</name>
                  <description>SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SCK_HIGH</name>
                  <description>SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PRFTCH_DIS</name>
              <description>Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ENABLE</name>
                  <description>Enable. Cache prefetching enabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DISABLE</name>
                  <description>Disable. Disables prefetching of cache lines.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DUAL</name>
              <description>Select dual protocol.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>QUAD</name>
                  <description>Quad protocol. This protocol uses IO3:0.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DUAL</name>
                  <description>Dual protocol. This protocol uses IO1:0.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RFCLK</name>
              <description>Select active clock edge for input data.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>RISING_EDGE</name>
                  <description>Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>FALLING_EDGE</name>
                  <description>Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FBCLK</name>
              <description>Feedback clock select.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INTERNAL_CLOCK</name>
                  <description>Internal clock. The SPIFI samples read data using an internal clock.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>FEEDBACK_CLOCK</name>
                  <description>Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DMAEN</name>
              <description>A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used in Command mode.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CMD</name>
          <description>SPIFI command register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATALEN</name>
              <description>Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>14</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>POLL</name>
              <description>This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DOUT</name>
              <description>If the DATALEN field is not zero, this bit controls the direction of the data:</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INPUT</name>
                  <description>Input from serial flash.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>OUTPUT</name>
                  <description>Output to serial flash.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INTLEN</name>
              <description>This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIELDFORM</name>
              <description>This field controls how the fields of the command are sent.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ALL_SERIAL</name>
                  <description>All serial. All fields of the command are serial.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>QUAD_DUAL_DATA</name>
                  <description>Quad/dual data. Data field is quad/dual, other fields are serial.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SERIAL_OPCODE</name>
                  <description>Serial opcode. Opcode field is serial. Other fields are quad/dual.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ALL_QUAD_DUAL</name>
                  <description>All quad/dual. All fields of the command are in quad/dual format.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FRAMEFORM</name>
              <description>This field controls the opcode and address fields.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>OPCODE</name>
                  <description>Opcode. Opcode only, no address.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>OPCODE_1_BYTE</name>
                  <description>Opcode one byte. Opcode, least significant byte of address.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>OPCODE_2_BYTES</name>
                  <description>Opcode two bytes. Opcode, two least significant bytes of address.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>OPCODE_3_BYTES</name>
                  <description>Opcode three bytes. Opcode, three least significant bytes of address.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>OPCODE_4_BYTES</name>
                  <description>Opcode four bytes. Opcode, 4 bytes of address.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NO_OPCODE_3_BYTES</name>
                  <description>No opcode three bytes. No opcode, 3 least significant bytes of address.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NO_OPCODE_4_BYTES</name>
                  <description>No opcode four bytes. No opcode, 4 bytes of address.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OPCODE</name>
              <description>The opcode of the command (not used for some FRAMEFORM values).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ADDR</name>
          <description>SPIFI address register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>ADDRESS</name>
              <description>Address.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>IDATA</name>
          <description>SPIFI intermediate data register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>IDATA</name>
              <description>Value of intermediate bytes.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLIMIT</name>
          <description>SPIFI limit register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x8000000</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CLIMIT</name>
              <description>Zero-based upper limit of cacheable memory</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATA</name>
          <description>SPIFI data register</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>Input or output data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MCMD</name>
          <description>SPIFI memory command register</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFC000</resetMask>
          <fields>
            <field>
              <name>POLL</name>
              <description>This bit should be written as 0.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DOUT</name>
              <description>This bit should be written as 0.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INTLEN</name>
              <description>This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIELDFORM</name>
              <description>This field controls how the fields of the command are sent.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ALL_SERIAL</name>
                  <description>All serial. All fields of the command are serial.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>QUAD_DUAL_DATA</name>
                  <description>Quad/dual data. Data field is quad/dual, other fields are serial.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SERIAL_OPCODE</name>
                  <description>Serial opcode. Opcode field is serial. Other fields are quad/dual.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ALL_QUAD_DUAL</name>
                  <description>All quad/dual. All fields of the command are in quad/dual format.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>FRAMEFORM</name>
              <description>This field controls the opcode and address fields.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>OPCODE</name>
                  <description>Opcode. Opcode only, no address.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>OPCODE_1_BYTE</name>
                  <description>Opcode one byte. Opcode, least-significant byte of address.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>OPCODE_2_BYTES</name>
                  <description>Opcode two bytes. Opcode, 2 least-significant bytes of address.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>OPCODE_3_BYTES</name>
                  <description>Opcode three bytes. Opcode, 3 least-significant bytes of address.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>OPCODE_4_BYTES</name>
                  <description>Opcode four bytes. Opcode, 4 bytes of address.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NO_OPCODE_3_BYTES</name>
                  <description>No opcode three bytes. No opcode, 3 least-significant bytes of address.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NO_OPCODE_4_BYTES</name>
                  <description>No opcode, 4 bytes of address.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OPCODE</name>
              <description>The opcode of the command (not used for some FRAMEFORM values).</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT</name>
          <description>SPIFI status register</description>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x2000000</resetValue>
          <resetMask>0xFF000033</resetMask>
          <fields>
            <field>
              <name>MCINIT</name>
              <description>This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CMD</name>
              <description>This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RESET</name>
              <description>Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INTRQ</name>
              <description>This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VERSION</name>
              <description>-</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>FLASH</name>
      <description>flash</description>
      <groupName>FLASH</groupName>
      <baseAddress>0x40081000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0xB0</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>INI_RD_EN</name>
          <description>flash initial read register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FBCFF0F</resetMask>
          <fields>
            <field>
              <name>INI_RD_EN</name>
              <description>enable contoller to automatically read GDR repaired information and lock bit</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ERASE_CTRL</name>
          <description>flash erase control register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PAGE_IDXL</name>
              <description>Low 256KB page erase index</description>
              <bitOffset>0</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PAGE_IDXH</name>
              <description>High 256KB page erase index</description>
              <bitOffset>8</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HALF_ERASEL_EN</name>
              <description>Write '1' to Enable Mass Erase Low 256KB Flash; Write '0' is inactive. This bit is set by software and reset at the end of low 256KB flash mass erase operation by hardware.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HALF_ERASEH_EN</name>
              <description>Write '1' to Enable Mass Erase High 256KB Flash; Write '0' is inactive. This bit is set by software and reset at the end of high 256KB flash mass erase operation by hardware.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PAGE_ERASEL_EN</name>
              <description>Low 256KB block page erase enable. This bit initiates a page erase operation when set. This bit is set by software and reset at the end of page erase operation by hardware.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PAGE_ERASEH_EN</name>
              <description>High 256KB block page erase enable. This bit initiates a page erase operation when set. This bit is set by software and reset at the end of page erase operation by hardware.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ERASE_TIME</name>
          <description>flash erase time setting register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x9C400</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>ERASE_TIME_BASE</name>
              <description>Erase time, which is used to control Terase, Tme and Tsme. An 8MHz clock is to count the erase time. The maximum time of erase is 100ms. Default value is 640000 cycles in 8 MHz, that's 80 ms. User should set a pessimistic value to avoid possible error in erase operation.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIME_CTRL</name>
          <description>flash operation time setting register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x4001E</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PRGM_CYCLE</name>
              <description>Time base of some flash timing parameters, which represents 2 us. Default value is 64 cycles in 32 MHz (ahb clock). It is used in write and erase operations.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TIME_BASE</name>
              <description>Max write operation times in one program, which are used to control Terase and Tme. User should set a pessimistic value to avoid possible error in erase/page erase operation. When user do write operation: It is used to limit allowed write numbers. (Max 21 ms-Tnvs-Tpgs-Tpgh-Tnvh)/18us = 1167 This register is only used when common write.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SMART_CTRL</name>
          <description>smart erase control register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x553C</resetValue>
          <resetMask>0x3FF3F</resetMask>
          <fields>
            <field>
              <name>PRGML_EN</name>
              <description>It enable Low 256KB Flash write operation;</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PRGMH_EN</name>
              <description>It enable High 256KB Flash write operation;</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SMART_WRITEL_EN</name>
              <description>It enable Low 256KB Flash Smart program flow. When smart write is done, hardware automatically clear it</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SMART_WRITEH_EN</name>
              <description>It enable High 256KB Flash Smart program flow. When smart write is done, hardware automatically clear it</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SMART_ERASEL_EN</name>
              <description>It enable Low 256KB Flash Smart erase flow; When smart erase is done, hardware automatically clear it</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SMART_ERASEH_EN</name>
              <description>It enable High 256KB Flash Smart erase flow; When smart erase is done, hardware automatically clear it</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAX_WRITE</name>
              <description>When smart program is used, this is the maximum retry number for one write operation.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAX_ERASE</name>
              <description>When smart erase is used, this is the maximum retry number for one erase operation.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTEN</name>
          <description>interrupt enable register</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x80000007</resetMask>
          <fields>
            <field>
              <name>AHBL_INTEN</name>
              <description>low 256K flash AHB error interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LOCKL_INTEN</name>
              <description>low 256K flash lock error interrupt enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ERASEL_INTEN</name>
              <description>low 256K flash erase status interrupt enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WRITEL_INTEN</name>
              <description>low 256K flash write status interrupt enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WRBUFL_INTEN</name>
              <description>low 256K flash write buffer status interrupt enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AHBH_INTEN</name>
              <description>high 256K flash AHB error interrupt enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LOCKH_INTEN</name>
              <description>high 256K flash lock error interrupt enable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ERASEH_INTEN</name>
              <description>high 256K flash erase status interrupt enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WRITEH_INTEN</name>
              <description>high 256K flash write status interrupt enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WRBUFH_INTEN</name>
              <description>high 256K flash write buffer status interrupt enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FLASH_INTEN</name>
              <description>flash total interrupt enable</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT_STAT</name>
          <description>interrupt status register</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>AHBL_INT</name>
              <description>It is low 256KB Flash AHB error interrupt stat. 1 indicates AHB operation error AHB error include: Write/read unmapped space; AHB align rules violation; Byte/half-word Flash write operation;</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LOCKL_INT</name>
              <description>It is low 256KB Flash Lock page be accessed interrupt status</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ERASEL_INT</name>
              <description>It is low 256KB Erase operation done interrupt status If erase is used, it indicates one erase is done.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WRITEL_INT</name>
              <description>It is low 256KB write operation done interrupt status If write is used, it indicates one program is done.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WRBUFL_INT</name>
              <description>It is low 256KB Write Buffer empty interrupt status 0 = write buffer is not empty 1 = write buffer is empty It is auto cleared when write buffer is written. It is enabled only when PRGML_EN is enabled and write buffer is empty</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WRITE_FAIL_L_INT</name>
              <description>When smart write of low 256KB Flash is enable, 0 = Smart write is successful, 1 = Smart write is fail.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ERASE_FAIL_L_INT</name>
              <description>When smart erase of low 256KB Flash is enable, 0 = Smart erase is successful, 1 = Smart erase is fail.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AHBH_INT</name>
              <description>it is high 256KB Flash AHB error interrupt stat 1 indicates AHB operation error AHB error include: Write/read unmapped space; AHB align rules violation; Byte/half-word Flash write operation;</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LOCKH_INT</name>
              <description>it is high 256KB Flash Lock page be accessed interrupt status</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ERASEH_INT</name>
              <description>it is high 256KB Flash Erase operation done interrupt status If erase is used, it indicates one erase is done.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WRITEH_INT</name>
              <description>it is high 256KB Flash write operation done interrupt status If write is used, it indicates one program is done.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WRBUFH_INT</name>
              <description>it is high 256KB Flash Write Buffer empty interrupt status 0 = write buffer is not empty 1 = write buffer is empty It is auto cleared when write buffer is written. It is enabled only when PRGMH_EN is enabled and write buffer is empty</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>WRITE_FAIL_H_INT</name>
              <description>When smart write of high 256KB Flash is enable, 0 = Smart write is successful, 1 = Smart write is fail.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ERASE_FAIL_H_INT</name>
              <description>When smart erase of high 256KB Flash is enable, 0 = Smart erase is successful, 1 = Smart erase is fail.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTCLR</name>
          <description>interrupt clear register</description>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>AHBL_INTCLR</name>
              <description>low 256K flash AHB error interrupt clear</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>LOCKL_INTCLR</name>
              <description>low 256K flash lock error interrupt clear</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>ERASEL_INTCLR</name>
              <description>low 256K flash erase status interrupt clear</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>WRITEL_INTCLR</name>
              <description>low 256K flash write status interrupt clear</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>AHBH_INTCLR</name>
              <description>high 256K flash AHB error interrupt clear</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>LOCKH_INTCLR</name>
              <description>high 256K flash lock error interrupt clear</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>ERASEH_INTCLR</name>
              <description>high 256K flash erase status interrupt clear</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>WRITEH_INTCLR</name>
              <description>high 256K flash write status interrupt clear</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
          </fields>
        </register>
        <register>
          <name>LOCK_STAT0</name>
          <description>lock control register 0</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PAGE_LOCK0</name>
              <description>Low 256K flash main memory page 0-31 write and erase lock status</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LOCK_STAT1</name>
          <description>no description available</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PAGE_LOCK1</name>
              <description>Low 256K flash main memory page 32-63 write and erase lock status</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LOCK_STAT2</name>
          <description>no description available</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PAGE_LOCK2</name>
              <description>Low 256K flash main memory page 64-95 write and erase lock status</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LOCK_STAT3</name>
          <description>no description available</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PAGE_LOCK3</name>
              <description>Low 256K flash main memory page 96-127 write and erase lock status</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LOCK_STAT4</name>
          <description>no description available</description>
          <addressOffset>0x30</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PAGE_LOCK4</name>
              <description>high 256K flash main memory page 0-31 write and erase lock status</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LOCK_STAT5</name>
          <description>no description available</description>
          <addressOffset>0x34</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PAGE_LOCK5</name>
              <description>high 256K flash main memory page 32-63 write and erase lock status</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LOCK_STAT6</name>
          <description>no description available</description>
          <addressOffset>0x38</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PAGE_LOCK6</name>
              <description>high 256K flash main memory page 64-95 write and erase lock status</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LOCK_STAT7</name>
          <description>no description available</description>
          <addressOffset>0x3C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFFFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>PAGE_LOCK7</name>
              <description>high 256K flash main memory page 96-127 write and erase lock status</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LOCK_STAT8</name>
          <description>no description available</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MASS_ERASE_LOCK</name>
              <description>Mass erase operation lock status 0 : Mass erase operation is locked 1 : Mass erase operation is unlocked</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FSH_PROTECT</name>
              <description>SWD flash protection status 0 : flash is unprotected 1 : flash is protected</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MEM_PROTECT</name>
              <description>SWD memory protection status 0 : Memory is unprotected 1 : Memory is protected</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATUS1</name>
          <description>no description available</description>
          <addressOffset>0x48</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x4010001</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FSH_ERA_BUSY_L</name>
              <description>flash block 0 erase operation status 0 : no flash block 0 erase operation in progress. 1 : flash block 0 erase operation is in progress.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FSH_WR_BUSY_L</name>
              <description>flash block 0 write operation status: 0 : no flash block 0 write operation in progress. 1 : flash block 0 write operation is in progress.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DBG_ERA_DONE_L</name>
              <description>A flash block 0 debug initiated smart mass erase status. 0 : no debug port initiated flash block 0 smart mass erase operation in progress. 1 : debug port initiated flash block 0 smart mass erase operation in progress.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FSH_ERA_BUSY_H</name>
              <description>flash block 1 erase operation status 0 : no flash block 1 erase operation in progress. 1 : flash block 1 erase operation is in progress.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FSH_WR_BUSY_H</name>
              <description>flash block 1 write operation status: 0 : no flash block 1 write operation in progress. 1 : flash block 1 write operation is in progress.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DBG_ERA_DONE_H</name>
              <description>A flash block 1 debug initiated smart mass erase status. 0 : no debug port initiated flash block 1 smart mass erase operation in progress. 1 : debug port initiated flash block 1 smart mass erase operation in progress.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>INI_RD_DONE</name>
              <description>flash initial read done.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FSH_STA</name>
              <description>when 0 means data information is 0x55AA.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RESERVED</name>
              <description>reserved</description>
              <bitOffset>27</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ERR_INFOL1</name>
          <description>no description available</description>
          <addressOffset>0x5C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>WR_FAILEDL_ADDR</name>
              <description>When a flash block 0 smart write fails, the address is stored in this bit filed</description>
              <bitOffset>0</bitOffset>
              <bitWidth>18</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SMART_FAILL_CTR</name>
              <description>The amount of fails during a smart write or smart erase is stored in this bit field</description>
              <bitOffset>18</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ERR_INFOL2</name>
          <description>no description available</description>
          <addressOffset>0x60</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>WR_FAILEDL_DATA</name>
              <description>When a flash block 0 smart write fails, the data is stored in this bit field</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ERR_INFOL3</name>
          <description>no description available</description>
          <addressOffset>0x64</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>ERA_FAILEDL_INFO</name>
              <description>When a smart erase on flash block 0 fails, the address is stored in this bit field</description>
              <bitOffset>0</bitOffset>
              <bitWidth>18</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ERR_INFOH1</name>
          <description>no description available</description>
          <addressOffset>0x68</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>WR_FAILEDH_ADDR</name>
              <description>When a flash block 1 smart write fails, the address is stored in this bit field</description>
              <bitOffset>0</bitOffset>
              <bitWidth>18</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SMART_FAILH_CTR</name>
              <description>The amount of fails during a msart write or smart erase is stored int his bit field</description>
              <bitOffset>18</bitOffset>
              <bitWidth>6</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ERR_INFOH2</name>
          <description>no description available</description>
          <addressOffset>0x6C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>WR_FAILEDH_DATA</name>
              <description>When a flash block 1 smart write fails, the data is stored in this bit field</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ERR_INFOH3</name>
          <description>no description available</description>
          <addressOffset>0x70</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>ERA_FAILEDH_INFO</name>
              <description>when a smart erase on flash block 1 fails, the address is stored in this bit field</description>
              <bitOffset>0</bitOffset>
              <bitWidth>18</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DEBUG_PASSWORD</name>
          <description>no description available</description>
          <addressOffset>0xA8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DEBUG_PASSWORD</name>
              <description>An SWD initiated smart mass erase operation will only be issued if this register is programmed with the value 0xCA1E093F.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ERASE_PASSWORD</name>
          <description>no description available</description>
          <addressOffset>0xAC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>ERASE_PASSWORD</name>
              <description>When this register is programmed with the value 0xCA1E093F, a FW initiated mass erase or page erase operation will bypass the current lock and protection scheme.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>DMA0</name>
      <description>LPC5411x DMA controller</description>
      <groupName>DMA</groupName>
      <baseAddress>0x40082000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x53C</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CTRL</name>
          <description>DMA control.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1</resetMask>
          <fields>
            <field>
              <name>ENABLE</name>
              <description>DMA controller master enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The DMA controller is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTSTAT</name>
          <description>Interrupt status.</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x6</resetMask>
          <fields>
            <field>
              <name>ACTIVEINT</name>
              <description>Summarizes whether any enabled interrupts (other than error interrupts) are pending.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_PENDING</name>
                  <description>Not pending. No enabled interrupts are pending.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PENDING</name>
                  <description>Pending. At least one enabled interrupt is pending.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ACTIVEERRINT</name>
              <description>Summarizes whether any error interrupts are pending.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_PENDING</name>
                  <description>Not pending. No error interrupts are pending.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PENDING</name>
                  <description>Pending. At least one error interrupt is pending.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SRAMBASE</name>
          <description>SRAM address of the channel configuration table.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFE00</resetMask>
          <fields>
            <field>
              <name>OFFSET</name>
              <description>Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>23</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ENABLESET0</name>
          <description>Channel Enable read and Set for all DMA channels.</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>ENA</name>
              <description>Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ENABLECLR0</name>
          <description>Channel Enable Clear for all DMA channels.</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CLR</name>
              <description>Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ACTIVE0</name>
          <description>Channel Active status for all DMA channels.</description>
          <addressOffset>0x30</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>ACT</name>
              <description>Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BUSY0</name>
          <description>Channel Busy status for all DMA channels.</description>
          <addressOffset>0x38</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>BSY</name>
              <description>Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ERRINT0</name>
          <description>Error Interrupt status for all DMA channels.</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>ERR</name>
              <description>Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENSET0</name>
          <description>Interrupt Enable read and Set for all DMA channels.</description>
          <addressOffset>0x48</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>INTEN</name>
              <description>Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENCLR0</name>
          <description>Interrupt Enable Clear for all DMA channels.</description>
          <addressOffset>0x50</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CLR</name>
              <description>Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTA0</name>
          <description>Interrupt A status for all DMA channels.</description>
          <addressOffset>0x58</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>IA</name>
              <description>Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTB0</name>
          <description>Interrupt B status for all DMA channels.</description>
          <addressOffset>0x60</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>IB</name>
              <description>Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SETVALID0</name>
          <description>Set ValidPending control bits for all DMA channels.</description>
          <addressOffset>0x68</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>SV</name>
              <description>SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SETTRIG0</name>
          <description>Set Trigger control bits for all DMA channels.</description>
          <addressOffset>0x70</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>TRIG</name>
              <description>Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ABORT0</name>
          <description>Channel Abort control for all DMA channels.</description>
          <addressOffset>0x78</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>ABORTCTRL</name>
              <description>Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <cluster>
          <dim>20</dim>
          <dimIncrement>0x10</dimIncrement>
          <name>CHANNEL[%s]</name>
          <description>no description available</description>
          <addressOffset>0x400</addressOffset>
          <register>
            <name>CFG</name>
            <description>Configuration register for DMA channel .</description>
            <addressOffset>0</addressOffset>
            <size>32</size>
            <access>read-write</access>
            <resetValue>0</resetValue>
            <resetMask>0x7CF73</resetMask>
            <fields>
              <field>
                <name>PERIPHREQEN</name>
                <description>Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>DISABLED</name>
                    <description>Disabled. Peripheral DMA requests are disabled.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>ENABLED</name>
                    <description>Enabled. Peripheral DMA requests are enabled.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>HWTRIGEN</name>
                <description>Hardware Triggering Enable for this channel.</description>
                <bitOffset>1</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>DISABLED</name>
                    <description>Disabled. Hardware triggering is not used.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>ENABLED</name>
                    <description>Enabled. Use hardware triggering.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>TRIGPOL</name>
                <description>Trigger Polarity. Selects the polarity of a hardware trigger for this channel.</description>
                <bitOffset>4</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>ACTIVE_LOW_FALLING</name>
                    <description>Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>ACTIVE_HIGH_RISING</name>
                    <description>Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>TRIGTYPE</name>
                <description>Trigger Type. Selects hardware trigger as edge triggered or level triggered.</description>
                <bitOffset>5</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>EDGE</name>
                    <description>Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>LEVEL</name>
                    <description>Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>TRIGBURST</name>
                <description>Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.</description>
                <bitOffset>6</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>SINGLE</name>
                    <description>Single transfer. Hardware trigger causes a single transfer.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>BURST</name>
                    <description>Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>BURSTPOWER</name>
                <description>Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.</description>
                <bitOffset>8</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>SRCBURSTWRAP</name>
                <description>Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.</description>
                <bitOffset>14</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>DISABLED</name>
                    <description>Disabled. Source burst wrapping is not enabled for this DMA channel.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>ENABLED</name>
                    <description>Enabled. Source burst wrapping is enabled for this DMA channel.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>DSTBURSTWRAP</name>
                <description>Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.</description>
                <bitOffset>15</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>DISABLED</name>
                    <description>Disabled. Destination burst wrapping is not enabled for this DMA channel.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>ENABLED</name>
                    <description>Enabled. Destination burst wrapping is enabled for this DMA channel.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CHPRIORITY</name>
                <description>Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority.</description>
                <bitOffset>16</bitOffset>
                <bitWidth>3</bitWidth>
                <access>read-write</access>
              </field>
            </fields>
          </register>
          <register>
            <name>CTLSTAT</name>
            <description>Control and status register for DMA channel .</description>
            <addressOffset>0x4</addressOffset>
            <size>32</size>
            <access>read-only</access>
            <resetValue>0</resetValue>
            <resetMask>0x5</resetMask>
            <fields>
              <field>
                <name>VALIDPENDING</name>
                <description>Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-only</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>NO_EFFECT</name>
                    <description>No effect. No effect on DMA operation.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>VALID_PENDING</name>
                    <description>Valid pending.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>TRIG</name>
                <description>Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.</description>
                <bitOffset>2</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-only</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>NOT_TRIGGERED</name>
                    <description>Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>TRIGGERED</name>
                    <description>Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
          <register>
            <name>XFERCFG</name>
            <description>Transfer configuration register for DMA channel .</description>
            <addressOffset>0x8</addressOffset>
            <size>32</size>
            <access>read-write</access>
            <resetValue>0</resetValue>
            <resetMask>0x3FFF33F</resetMask>
            <fields>
              <field>
                <name>CFGVALID</name>
                <description>Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>NOT_VALID</name>
                    <description>Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>VALID</name>
                    <description>Valid. The current channel descriptor is considered valid.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>RELOAD</name>
                <description>Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.</description>
                <bitOffset>1</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>DISABLED</name>
                    <description>Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>ENABLED</name>
                    <description>Enabled. Reload the channels' control structure when the current descriptor is exhausted.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SWTRIG</name>
                <description>Software Trigger.</description>
                <bitOffset>2</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>NOT_SET</name>
                    <description>Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>SET</name>
                    <description>Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>CLRTRIG</name>
                <description>Clear Trigger.</description>
                <bitOffset>3</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>NOT_CLEARED</name>
                    <description>Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>CLEARED</name>
                    <description>Cleared. The trigger is cleared when this descriptor is exhausted</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SETINTA</name>
                <description>Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.</description>
                <bitOffset>4</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>NO_EFFECT</name>
                    <description>No effect.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>SET</name>
                    <description>Set. The INTA flag for this channel will be set when the current descriptor is exhausted.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SETINTB</name>
                <description>Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.</description>
                <bitOffset>5</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>NO_EFFECT</name>
                    <description>No effect.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>SET</name>
                    <description>Set. The INTB flag for this channel will be set when the current descriptor is exhausted.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>WIDTH</name>
                <description>Transfer width used for this DMA channel.</description>
                <bitOffset>8</bitOffset>
                <bitWidth>2</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>BIT_8</name>
                    <description>8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>BIT_16</name>
                    <description>16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>BIT_32</name>
                    <description>32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).</description>
                    <value>0x2</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>SRCINC</name>
                <description>Determines whether the source address is incremented for each DMA transfer.</description>
                <bitOffset>12</bitOffset>
                <bitWidth>2</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>NO_INCREMENT</name>
                    <description>No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>WIDTH_X_1</name>
                    <description>1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>WIDTH_X_2</name>
                    <description>2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.</description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>WIDTH_X_4</name>
                    <description>4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.</description>
                    <value>0x3</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>DSTINC</name>
                <description>Determines whether the destination address is incremented for each DMA transfer.</description>
                <bitOffset>14</bitOffset>
                <bitWidth>2</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>NO_INCREMENT</name>
                    <description>No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>WIDTH_X_1</name>
                    <description>1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>WIDTH_X_2</name>
                    <description>2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.</description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>WIDTH_X_4</name>
                    <description>4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.</description>
                    <value>0x3</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>XFERCOUNT</name>
                <description>Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed.</description>
                <bitOffset>16</bitOffset>
                <bitWidth>10</bitWidth>
                <access>read-write</access>
              </field>
            </fields>
          </register>
        </cluster>
      </registers>
    </peripheral>
    <peripheral>
      <name>FLEXCOMM0</name>
      <description>flexcomm</description>
      <groupName>FLEXCOMM</groupName>
      <headerStructName>FLEXCOMM</headerStructName>
      <baseAddress>0x40083000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>IOMODE</name>
          <description>io mode register</description>
          <addressOffset>0xF00</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3</resetMask>
          <fields>
            <field>
              <name>DIO_MODE</name>
              <description>IO mode register, SPI share MISO/MOSI at MOSI, USART share TXD/RXD at RXD</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOSHAREPIN</name>
                  <description>do not share pin</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SHAREPIN</name>
                  <description>share pin</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DIO_OEN</name>
              <description>shared pin direction register</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SP_NOEN</name>
                  <description>shared pin do not output</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SP_OEN</name>
                  <description>shared pin output enable</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>PSELID</name>
          <description>Peripheral Select and Flexcomm ID register.</description>
          <addressOffset>0xFF8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x101000</resetValue>
          <resetMask>0xFFFFF1FF</resetMask>
          <fields>
            <field>
              <name>PERSEL</name>
              <description>Peripheral Select. This field is writable by software.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_PERIPH_SELECTED</name>
                  <description>No peripheral selected.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>USART</name>
                  <description>USART function selected.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SPI</name>
                  <description>SPI function selected.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>I2C</name>
                  <description>I2C function selected.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>I2S_TRANSMIT</name>
                  <description>I2S transmit function selected.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>I2S_RECEIVE</name>
                  <description>I2S receive function selected.</description>
                  <value>0x5</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LOCK</name>
              <description>Lock the peripheral select. This field is writable by software.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>UNLOCKED</name>
                  <description>Peripheral select can be changed by software.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>LOCKED</name>
                  <description>Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>USARTPRESENT</name>
              <description>USART present indicator. This field is Read-only.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_PRESENT</name>
                  <description>This Flexcomm does not include the USART function.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PRESENT</name>
                  <description>This Flexcomm includes the USART function.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SPIPRESENT</name>
              <description>SPI present indicator. This field is Read-only.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_PRESENT</name>
                  <description>This Flexcomm does not include the SPI function.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PRESENT</name>
                  <description>This Flexcomm includes the SPI function.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>I2CPRESENT</name>
              <description>I2C present indicator. This field is Read-only.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_PRESENT</name>
                  <description>This Flexcomm does not include the I2C function.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PRESENT</name>
                  <description>This Flexcomm includes the I2C function.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>I2SPRESENT</name>
              <description>I 2S present indicator. This field is Read-only.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_PRESENT</name>
                  <description>This Flexcomm does not include the I2S function.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PRESENT</name>
                  <description>This Flexcomm includes the I2S function.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SC3W</name>
              <description>Smart card/SPI 3 wire mode feature indicator. This field is Read-only</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_PRESENT</name>
                  <description>This Flexcomm does not support smart card/SPI 3 wire mdoe feature</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PRESENT</name>
                  <description>This Flexcomm support smart card/SPI 3 wire mode feature</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ID</name>
              <description>Flexcomm ID.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>20</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>PID</name>
          <description>Peripheral identification register.</description>
          <addressOffset>0xFFC</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFF00</resetMask>
          <fields>
            <field>
              <name>Minor_Rev</name>
              <description>Minor revision of module implementation.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>Major_Rev</name>
              <description>Major revision of module implementation.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ID</name>
              <description>Module identifier for the selected function.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="FLEXCOMM0">
      <name>FLEXCOMM1</name>
      <description>flexcomm</description>
      <groupName>FLEXCOMM</groupName>
      <baseAddress>0x40086000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
    </peripheral>
    <peripheral derivedFrom="FLEXCOMM0">
      <name>FLEXCOMM2</name>
      <description>flexcomm</description>
      <groupName>FLEXCOMM</groupName>
      <baseAddress>0x40087000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
    </peripheral>
    <peripheral derivedFrom="FLEXCOMM0">
      <name>FLEXCOMM3</name>
      <description>flexcomm</description>
      <groupName>FLEXCOMM</groupName>
      <baseAddress>0x4008F000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
    </peripheral>
    <peripheral>
      <name>USART0</name>
      <alternatePeripheral>FLEXCOMM0</alternatePeripheral>
      <description>usart</description>
      <groupName>USART</groupName>
      <headerStructName>USART</headerStructName>
      <baseAddress>0x40083000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CFG</name>
          <description>USART Configuration register. Basic USART configuration settings that typically are not changed during operation.</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFDDBFD</resetMask>
          <fields>
            <field>
              <name>ENABLE</name>
              <description>USART Enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The USART is enabled for operation.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DATALEN</name>
              <description>Selects the data size for the USART.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>_7_BIT</name>
                  <description>7 bit Data length.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_8_BIT</name>
                  <description>8 bit Data length.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_9_BIT</name>
                  <description>9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PARITYSEL</name>
              <description>Selects what type of parity is used by the USART.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_PARITY</name>
                  <description>No parity.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EVEN_PARITY</name>
                  <description>Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ODD_PARITY</name>
                  <description>Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>STOPLEN</name>
              <description>Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>_1_BIT</name>
                  <description>1 stop bit.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_2_BITS</name>
                  <description>2 stop bits. This setting should only be used for asynchronous communication.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MODE32K</name>
              <description>Selects standard or 32 kHz clocking mode.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. USART uses standard clocking.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LINMODE</name>
              <description>LIN break mode enable.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. Break detect and generate is configured for normal operation.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. Break detect and generate is configured for LIN bus operation.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CTSEN</name>
              <description>CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART'-s own RTS if loopback mode is enabled.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>No flow control. The transmitter does not receive any automatic flow control signal.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SYNCEN</name>
              <description>Selects synchronous or asynchronous operation.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ASYNCHRONOUS_MODE</name>
                  <description>Asynchronous mode.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SYNCHRONOUS_MODE</name>
                  <description>Synchronous mode.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLKPOL</name>
              <description>Selects the clock polarity and sampling edge of received data in synchronous mode.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>FALLING_EDGE</name>
                  <description>Falling edge. Un_RXD is sampled on the falling edge of SCLK.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RISING_EDGE</name>
                  <description>Rising edge. Un_RXD is sampled on the rising edge of SCLK.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SYNCMST</name>
              <description>Synchronous mode Master select.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SLAVE</name>
                  <description>Slave. When synchronous mode is enabled, the USART is a slave.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>MASTER</name>
                  <description>Master. When synchronous mode is enabled, the USART is a master.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LOOP</name>
              <description>Selects data loopback mode.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NORMAL</name>
                  <description>Normal operation.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>LOOPBACK</name>
                  <description>Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OETA</name>
              <description>Output Enable Turnaround time enable for RS-485 operation.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>AUTOADDR</name>
              <description>Automatic Address matching enable.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OESEL</name>
              <description>Output Enable Select.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>STANDARD</name>
                  <description>Standard. The RTS signal is used as the standard flow control function.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RS_485</name>
                  <description>RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>OEPOL</name>
              <description>Output Enable Polarity.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>LOW</name>
                  <description>Low. If selected by OESEL, the output enable is active low.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH</name>
                  <description>High. If selected by OESEL, the output enable is active high.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RXPOL</name>
              <description>Receive data polarity.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>STANDARD</name>
                  <description>Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INVERTED</name>
                  <description>Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TXPOL</name>
              <description>Transmit data polarity.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>STANDARD</name>
                  <description>Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INVERTED</name>
                  <description>Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CTL</name>
          <description>USART Control register. USART control settings that are more likely to change during operation.</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x10346</resetMask>
          <fields>
            <field>
              <name>TXBRKEN</name>
              <description>Break Enable.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NORMAL</name>
                  <description>Normal operation.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CONTINOUS</name>
                  <description>Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ADDRDET</name>
              <description>Enable address detect mode.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The USART presents all incoming data.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TXDIS</name>
              <description>Transmit Disable.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Not disabled. USART transmitter is not disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CC</name>
              <description>Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CLOCK_ON_CHARACTER</name>
                  <description>Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CONTINOUS_CLOCK</name>
                  <description>Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLRCCONRX</name>
              <description>Clear Continuous Clock.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect. No effect on the CC bit.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>AUTO_CLEAR</name>
                  <description>Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>AUTOBAUD</name>
              <description>Autobaud enable.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. USART is in normal operating mode.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT</name>
          <description>USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xA</resetValue>
          <resetMask>0x45A</resetMask>
          <fields>
            <field>
              <name>RXIDLE</name>
              <description>Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXIDLE</name>
              <description>Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>CTS</name>
              <description>This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DELTACTS</name>
              <description>This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TXDISSTAT</name>
              <description>Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXBRK</name>
              <description>Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DELTARXBRK</name>
              <description>This bit is set when a change in the state of receiver break detection occurs. Cleared by software.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>START</name>
              <description>This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>FRAMERRINT</name>
              <description>Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>PARITYERRINT</name>
              <description>Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>RXNOISEINT</name>
              <description>Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>ABERR</name>
              <description>Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENSET</name>
          <description>Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1F868</resetMask>
          <fields>
            <field>
              <name>TXIDLEEN</name>
              <description>When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DELTACTSEN</name>
              <description>When 1, enables an interrupt when there is a change in the state of the CTS input.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXDISEN</name>
              <description>When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DELTARXBRKEN</name>
              <description>When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>STARTEN</name>
              <description>When 1, enables an interrupt when a received start bit has been detected.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FRAMERREN</name>
              <description>When 1, enables an interrupt when a framing error has been detected.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PARITYERREN</name>
              <description>When 1, enables an interrupt when a parity error has been detected.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXNOISEEN</name>
              <description>When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>ABERREN</name>
              <description>When 1, enables an interrupt when an auto baud error occurs.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENCLR</name>
          <description>Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>TXIDLECLR</name>
              <description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DELTACTSCLR</name>
              <description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TXDISCLR</name>
              <description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>DELTARXBRKCLR</name>
              <description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>STARTCLR</name>
              <description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>FRAMERRCLR</name>
              <description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>PARITYERRCLR</name>
              <description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>RXNOISECLR</name>
              <description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>ABERRCLR</name>
              <description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>BRG</name>
          <description>Baud Rate Generator register. 16-bit integer baud rate divisor value.</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>BRGVAL</name>
              <description>This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTSTAT</name>
          <description>Interrupt status register. Reflects interrupts that are currently enabled.</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1F968</resetMask>
          <fields>
            <field>
              <name>TXIDLE</name>
              <description>Transmitter Idle status.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DELTACTS</name>
              <description>This bit is set when a change in the state of the CTS input is detected.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXDISINT</name>
              <description>Transmitter Disabled Interrupt flag.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DELTARXBRK</name>
              <description>This bit is set when a change in the state of receiver break detection occurs.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>START</name>
              <description>This bit is set when a start is detected on the receiver input.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FRAMERRINT</name>
              <description>Framing Error interrupt flag.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PARITYERRINT</name>
              <description>Parity Error interrupt flag.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXNOISEINT</name>
              <description>Received Noise interrupt flag.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ABERRINT</name>
              <description>Auto baud Error Interrupt flag.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OSR</name>
          <description>Oversample selection register for asynchronous communication.</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xF</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>OSRVAL</name>
              <description>Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ADDR</name>
          <description>Address register for automatic address matching.</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>ADDRESS</name>
              <description>8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOCFG</name>
          <description>FIFO configuration and enable register.</description>
          <addressOffset>0xE00</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x7F033</resetMask>
          <fields>
            <field>
              <name>ENABLETX</name>
              <description>Enable the transmit FIFO.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>The transmit FIFO is not enabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>The transmit FIFO is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ENABLERX</name>
              <description>Enable the receive FIFO.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>The receive FIFO is not enabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>The receive FIFO is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SIZE</name>
              <description>FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DMATX</name>
              <description>DMA configuration for transmit.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>DMA is not used for the transmit function.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DMARX</name>
              <description>DMA configuration for receive.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>DMA is not used for the receive function.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EMPTYTX</name>
              <description>Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EMPTYRX</name>
              <description>Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOSTAT</name>
          <description>FIFO status register.</description>
          <addressOffset>0xE04</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x30</resetValue>
          <resetMask>0x1F1FFB</resetMask>
          <fields>
            <field>
              <name>TXERR</name>
              <description>TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXERR</name>
              <description>RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PERINT</name>
              <description>Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral'-s STAT register.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXEMPTY</name>
              <description>Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXNOTFULL</name>
              <description>Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXNOTEMPTY</name>
              <description>Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXFULL</name>
              <description>Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXLVL</name>
              <description>Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXLVL</name>
              <description>Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOTRIG</name>
          <description>FIFO trigger settings for interrupt and DMA request.</description>
          <addressOffset>0xE08</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF0F03</resetMask>
          <fields>
            <field>
              <name>TXLVLENA</name>
              <description>Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Transmit FIFO level does not generate a FIFO level trigger.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RXLVLENA</name>
              <description>Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Receive FIFO level does not generate a FIFO level trigger.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TXLVL</name>
              <description>Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXLVL</name>
              <description>Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOINTENSET</name>
          <description>FIFO interrupt enable set (enable) and read register.</description>
          <addressOffset>0xE10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>TXERR</name>
              <description>Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>No interrupt will be generated for a transmit error.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>An interrupt will be generated when a transmit error occurs.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RXERR</name>
              <description>Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>No interrupt will be generated for a receive error.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>An interrupt will be generated when a receive error occurs.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TXLVL</name>
              <description>Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>No interrupt will be generated based on the TX FIFO level.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RXLVL</name>
              <description>Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>No interrupt will be generated based on the RX FIFO level.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOINTENCLR</name>
          <description>FIFO interrupt enable clear (disable) and read register.</description>
          <addressOffset>0xE14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>TXERR</name>
              <description>Writing one clears the corresponding bits in the FIFOINTENSET register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXERR</name>
              <description>Writing one clears the corresponding bits in the FIFOINTENSET register.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXLVL</name>
              <description>Writing one clears the corresponding bits in the FIFOINTENSET register.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXLVL</name>
              <description>Writing one clears the corresponding bits in the FIFOINTENSET register.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOINTSTAT</name>
          <description>FIFO interrupt status register.</description>
          <addressOffset>0xE18</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1F</resetMask>
          <fields>
            <field>
              <name>TXERR</name>
              <description>TX FIFO error.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXERR</name>
              <description>RX FIFO error.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXLVL</name>
              <description>Transmit FIFO level interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXLVL</name>
              <description>Receive FIFO level interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PERINT</name>
              <description>Peripheral interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOWR</name>
          <description>FIFO write data.</description>
          <addressOffset>0xE20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>TXDATA</name>
              <description>Transmit data to the FIFO.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFORD</name>
          <description>FIFO read data.</description>
          <addressOffset>0xE30</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xE1FF</resetMask>
          <fields>
            <field>
              <name>RXDATA</name>
              <description>Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FRAMERR</name>
              <description>Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PARITYERR</name>
              <description>Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXNOISE</name>
              <description>Received Noise flag. See description of the RxNoiseInt bit in Table 354.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFORDNOPOP</name>
          <description>FIFO data read with no FIFO pop.</description>
          <addressOffset>0xE40</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xE1FF</resetMask>
          <fields>
            <field>
              <name>RXDATA</name>
              <description>Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>9</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FRAMERR</name>
              <description>Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PARITYERR</name>
              <description>Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXNOISE</name>
              <description>Received Noise flag. See description of the RxNoiseInt bit in Table 354.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ID</name>
          <description>USART module Identification. This value appears in the shared Flexcomm peripheral ID register when USART is selected.</description>
          <addressOffset>0xFFC</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xE0100000</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>APERTURE</name>
              <description>Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MINOR_REV</name>
              <description>Minor revision of module implementation, starting at 0. Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MAJOR_REV</name>
              <description>Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ID</name>
              <description>Unique module identifier for this IP block.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="USART0">
      <name>USART1</name>
      <alternatePeripheral>FLEXCOMM1</alternatePeripheral>
      <description>usart</description>
      <groupName>USART</groupName>
      <baseAddress>0x40086000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
    </peripheral>
    <peripheral>
      <name>USB0</name>
      <description>usb</description>
      <groupName>USB</groupName>
      <baseAddress>0x40084000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x38</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>DEVCMDSTAT</name>
          <description>USB Device Command/Status register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x800</resetValue>
          <resetMask>0x171BFBFF</resetMask>
          <fields>
            <field>
              <name>DEV_ADDR</name>
              <description>USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DEV_EN</name>
              <description>USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SETUP</name>
              <description>SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FORCE_NEEDCLK</name>
              <description>Forces the NEEDCLK output to always be on:</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NORMAL</name>
                  <description>USB_NEEDCLK has normal function.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ALWAYS_ON</name>
                  <description>USB_NEEDCLK always 1. Clock will not be stopped in case of suspend.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LPM_SUP</name>
              <description>LPM Supported:</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO</name>
                  <description>LPM not supported.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>YES</name>
                  <description>LPM supported.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INTONNAK_AO</name>
              <description>Interrupt on NAK for interrupt and bulk OUT EP</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Only acknowledged packets generate an interrupt</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Both acknowledged and NAKed packets generate interrupts.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INTONNAK_AI</name>
              <description>Interrupt on NAK for interrupt and bulk IN EP</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Only acknowledged packets generate an interrupt</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Both acknowledged and NAKed packets generate interrupts.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INTONNAK_CO</name>
              <description>Interrupt on NAK for control OUT EP</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Only acknowledged packets generate an interrupt</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Both acknowledged and NAKed packets generate interrupts.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>INTONNAK_CI</name>
              <description>Interrupt on NAK for control IN EP</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Only acknowledged packets generate an interrupt</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Both acknowledged and NAKed packets generate interrupts.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DCON</name>
              <description>Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DSUS</name>
              <description>Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn'-t seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LPM_SUS</name>
              <description>Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LPM_REWP</name>
              <description>LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DCON_C</name>
              <description>Device status - connect change. The Connect Change bit is set when the device'-s pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DSUS_C</name>
              <description>Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DRES_C</name>
              <description>Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>VBUSDEBOUNCED</name>
              <description>This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INFO</name>
          <description>USB Info register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x7FFF</resetMask>
          <fields>
            <field>
              <name>FRAME_NR</name>
              <description>Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>11</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ERR_CODE</name>
              <description>The error code which last occurred:</description>
              <bitOffset>11</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_ERROR</name>
                  <description>No error</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PID_ENCODING_ERROR</name>
                  <description>PID encoding error</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PID_UNKNOWN</name>
                  <description>PID unknown</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PACKET_UNEXPECTED</name>
                  <description>Packet unexpected</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOKEN_CRC_ERROR</name>
                  <description>Token CRC error</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DATA_CRC_ERROR</name>
                  <description>Data CRC error</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TIMEOUT</name>
                  <description>Time out</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BABBLE</name>
                  <description>Babble</description>
                  <value>0x7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TRUNCATED_EOP</name>
                  <description>Truncated EOP</description>
                  <value>0x8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SENT_RECEIVED_NAK</name>
                  <description>Sent/Received NAK</description>
                  <value>0x9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SENT_STALL</name>
                  <description>Sent Stall</description>
                  <value>0xA</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>OVERRUN</name>
                  <description>Overrun</description>
                  <value>0xB</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SENT_EMPTY_PACKET</name>
                  <description>Sent empty packet</description>
                  <value>0xC</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>BITSTUFF_ERROR</name>
                  <description>Bitstuff error</description>
                  <value>0xD</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SYNC_ERROR</name>
                  <description>Sync error</description>
                  <value>0xE</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>WRONG_DATA_TOGGLE</name>
                  <description>Wrong data toggle</description>
                  <value>0xF</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>EPLISTSTART</name>
          <description>USB EP Command/Status List start address</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFF00</resetMask>
          <fields>
            <field>
              <name>EP_LIST</name>
              <description>Start address of the USB EP Command/Status List.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>24</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATABUFSTART</name>
          <description>USB Data buffer start address</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFC00000</resetMask>
          <fields>
            <field>
              <name>DA_BUF</name>
              <description>Start address of the buffer pointer page where all endpoint data buffers are located.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>10</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LPM</name>
          <description>USB Link Power Management register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FF</resetMask>
          <fields>
            <field>
              <name>HIRD_HW</name>
              <description>Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>HIRD_SW</name>
              <description>Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA_PENDING</name>
              <description>As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EPSKIP</name>
          <description>USB Endpoint skip</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3FFFFFFF</resetMask>
          <fields>
            <field>
              <name>SKIP</name>
              <description>Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>30</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EPINUSE</name>
          <description>USB Endpoint Buffer in use</description>
          <addressOffset>0x18</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3FC</resetMask>
          <fields>
            <field>
              <name>BUF</name>
              <description>Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EPBUFCFG</name>
          <description>USB Endpoint Buffer Configuration register</description>
          <addressOffset>0x1C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3FC</resetMask>
          <fields>
            <field>
              <name>BUF_SB</name>
              <description>Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTSTAT</name>
          <description>USB interrupt status register</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xC000FFFF</resetMask>
          <fields>
            <field>
              <name>EP0OUT</name>
              <description>Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP0IN</name>
              <description>Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP1OUT</name>
              <description>Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP1IN</name>
              <description>Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP2OUT</name>
              <description>Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP2IN</name>
              <description>Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP3OUT</name>
              <description>Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP3IN</name>
              <description>Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP4OUT</name>
              <description>Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP4IN</name>
              <description>Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP5OUT</name>
              <description>Interrupt status register bit for the EP5 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP5 OUT direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP5IN</name>
              <description>Interrupt status register bit for the EP5 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP5 IN direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP6OUT</name>
              <description>Interrupt status register bit for the EP6 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP6 OUT direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP6IN</name>
              <description>Interrupt status register bit for the EP6 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP6 IN direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP7OUT</name>
              <description>Interrupt status register bit for the EP7 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP7 OUT direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>EP7IN</name>
              <description>Interrupt status register bit for the EP7 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP7 IN direction. Software can clear this bit by writing a one to it.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FRAME_INT</name>
              <description>Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DEV_INT</name>
              <description>Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTEN</name>
          <description>USB interrupt enable register</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xC000FFFF</resetMask>
          <fields>
            <field>
              <name>EP_INT_EN</name>
              <description>If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FRAME_INT_EN</name>
              <description>If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DEV_INT_EN</name>
              <description>If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTSETSTAT</name>
          <description>USB set interrupt status register</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xC000FFFF</resetMask>
          <fields>
            <field>
              <name>EP_SET_INT</name>
              <description>If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FRAME_SET_INT</name>
              <description>If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DEV_SET_INT</name>
              <description>If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EPTOGGLE</name>
          <description>USB Endpoint toggle register</description>
          <addressOffset>0x34</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>TOGGLE</name>
              <description>Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>SCT0</name>
      <description>LPC5411x SCTimer/PWM (SCT)</description>
      <groupName>SCT</groupName>
      <baseAddress>0x40085000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x800</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CONFIG</name>
          <description>SCT configuration register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1E00</resetValue>
          <resetMask>0x61FFF</resetMask>
          <fields>
            <field>
              <name>UNIFY</name>
              <description>SCT operation</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DUAL_COUNTER</name>
                  <description>The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>UNIFIED_COUNTER</name>
                  <description>The SCT operates as a unified 32-bit counter.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CLKMODE</name>
              <description>SCT clock mode</description>
              <bitOffset>1</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SYSTEM_CLOCK_MODE</name>
                  <description>System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SAMPLED_SYSTEM_CLOCK_MODE</name>
                  <description>Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SCT_INPUT_CLOCK_MODE</name>
                  <description>SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ASYNCHRONOUS_MODE</name>
                  <description>Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CKSEL</name>
              <description>SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INPUT_0_RISING_EDGES</name>
                  <description>Rising edges on input 0.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT_0_FALLING_EDGE</name>
                  <description>Falling edges on input 0.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT_1_RISING_EDGES</name>
                  <description>Rising edges on input 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT_1_FALLING_EDGE</name>
                  <description>Falling edges on input 1.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT_2_RISING_EDGES</name>
                  <description>Rising edges on input 2.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT_2_FALLING_EDGE</name>
                  <description>Falling edges on input 2.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT_3_RISING_EDGES</name>
                  <description>Rising edges on input 3.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>INPUT_3_FALLING_EDGE</name>
                  <description>Falling edges on input 3.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>NORELAOD_L</name>
              <description>A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>NORELOAD_H</name>
              <description>A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>INSYNC</name>
              <description>Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AUTOLIMIT_L</name>
              <description>A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AUTOLIMIT_H</name>
              <description>A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CTRL</name>
          <description>SCT control register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x40004</resetValue>
          <resetMask>0x1FFF1FFF</resetMask>
          <fields>
            <field>
              <name>DOWN_L</name>
              <description>This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>STOP_L</name>
              <description>When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HALT_L</name>
              <description>When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLRCTR_L</name>
              <description>Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIDIR_L</name>
              <description>L or unified counter direction select</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>UP</name>
                  <description>Up. The counter counts up to a limit condition, then is cleared to zero.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>UP_DOWN</name>
                  <description>Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PRE_L</name>
              <description>Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DOWN_H</name>
              <description>This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>STOP_H</name>
              <description>When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HALT_H</name>
              <description>When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CLRCTR_H</name>
              <description>Writing a 1 to this bit clears the H counter. This bit always reads as 0.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIDIR_H</name>
              <description>Direction select</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>UP</name>
                  <description>The H counter counts up to its limit condition, then is cleared to zero.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>UP_DOWN</name>
                  <description>The H counter counts up to its limit, then counts down to a limit condition or to 0.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>PRE_H</name>
              <description>Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LIMIT</name>
          <description>SCT limit event select register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>LIMMSK_L</name>
              <description>If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LIMMSK_H</name>
              <description>If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>HALT</name>
          <description>SCT halt event select register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>HALTMSK_L</name>
              <description>If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>HALTMSK_H</name>
              <description>If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STOP</name>
          <description>SCT stop event select register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>STOPMSK_L</name>
              <description>If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>STOPMSK_H</name>
              <description>If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>START</name>
          <description>SCT start event select register</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>STARTMSK_L</name>
              <description>If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>STARTMSK_H</name>
              <description>If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COUNT</name>
          <description>SCT counter register</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CTR_L</name>
              <description>When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CTR_H</name>
              <description>When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATE</name>
          <description>SCT state register</description>
          <addressOffset>0x44</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1F001F</resetMask>
          <fields>
            <field>
              <name>STATE_L</name>
              <description>State variable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>STATE_H</name>
              <description>State variable.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INPUT</name>
          <description>SCT input register</description>
          <addressOffset>0x48</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>AIN0</name>
              <description>Input 0 state. Input 0 state on the last SCT clock edge.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN1</name>
              <description>Input 1 state. Input 1 state on the last SCT clock edge.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN2</name>
              <description>Input 2 state. Input 2 state on the last SCT clock edge.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN3</name>
              <description>Input 3 state. Input 3 state on the last SCT clock edge.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN4</name>
              <description>Input 4 state. Input 4 state on the last SCT clock edge.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN5</name>
              <description>Input 5 state. Input 5 state on the last SCT clock edge.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN6</name>
              <description>Input 6 state. Input 6 state on the last SCT clock edge.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN7</name>
              <description>Input 7 state. Input 7 state on the last SCT clock edge.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN8</name>
              <description>Input 8 state. Input 8 state on the last SCT clock edge.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN9</name>
              <description>Input 9 state. Input 9 state on the last SCT clock edge.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN10</name>
              <description>Input 10 state. Input 10 state on the last SCT clock edge.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN11</name>
              <description>Input 11 state. Input 11 state on the last SCT clock edge.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN12</name>
              <description>Input 12 state. Input 12 state on the last SCT clock edge.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN13</name>
              <description>Input 13 state. Input 13 state on the last SCT clock edge.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN14</name>
              <description>Input 14 state. Input 14 state on the last SCT clock edge.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>AIN15</name>
              <description>Input 15 state. Input 15 state on the last SCT clock edge.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN0</name>
              <description>Input 0 state. Input 0 state following the synchronization specified by INSYNC.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN1</name>
              <description>Input 1 state. Input 1 state following the synchronization specified by INSYNC.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN2</name>
              <description>Input 2 state. Input 2 state following the synchronization specified by INSYNC.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN3</name>
              <description>Input 3 state. Input 3 state following the synchronization specified by INSYNC.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN4</name>
              <description>Input 4 state. Input 4 state following the synchronization specified by INSYNC.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN5</name>
              <description>Input 5 state. Input 5 state following the synchronization specified by INSYNC.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN6</name>
              <description>Input 6 state. Input 6 state following the synchronization specified by INSYNC.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN7</name>
              <description>Input 7 state. Input 7 state following the synchronization specified by INSYNC.</description>
              <bitOffset>23</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN8</name>
              <description>Input 8 state. Input 8 state following the synchronization specified by INSYNC.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN9</name>
              <description>Input 9 state. Input 9 state following the synchronization specified by INSYNC.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN10</name>
              <description>Input 10 state. Input 10 state following the synchronization specified by INSYNC.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN11</name>
              <description>Input 11 state. Input 11 state following the synchronization specified by INSYNC.</description>
              <bitOffset>27</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN12</name>
              <description>Input 12 state. Input 12 state following the synchronization specified by INSYNC.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN13</name>
              <description>Input 13 state. Input 13 state following the synchronization specified by INSYNC.</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN14</name>
              <description>Input 14 state. Input 14 state following the synchronization specified by INSYNC.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SIN15</name>
              <description>Input 15 state. Input 15 state following the synchronization specified by INSYNC.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>REGMODE</name>
          <description>SCT match/capture mode register</description>
          <addressOffset>0x4C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>REGMOD_L</name>
              <description>Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>REGMOD_H</name>
              <description>Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUTPUT</name>
          <description>SCT output register</description>
          <addressOffset>0x50</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>OUT</name>
              <description>Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUTPUTDIRCTRL</name>
          <description>SCT output counter direction control register</description>
          <addressOffset>0x54</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SETCLR0</name>
              <description>Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR1</name>
              <description>Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR2</name>
              <description>Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR3</name>
              <description>Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR4</name>
              <description>Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR5</name>
              <description>Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR6</name>
              <description>Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR7</name>
              <description>Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR8</name>
              <description>Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR9</name>
              <description>Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR10</name>
              <description>Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR11</name>
              <description>Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR12</name>
              <description>Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR13</name>
              <description>Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR14</name>
              <description>Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SETCLR15</name>
              <description>Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INDEPENDENT</name>
                  <description>Set and clear do not depend on the direction of any counter.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>L_REVERSED</name>
                  <description>Set and clear are reversed when counter L or the unified counter is counting down.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>H_REVERSED</name>
                  <description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>RES</name>
          <description>SCT conflict resolution register</description>
          <addressOffset>0x58</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>O0RES</name>
              <description>Effect of simultaneous set and clear on output 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR0 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O1RES</name>
              <description>Effect of simultaneous set and clear on output 1.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR1 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O2RES</name>
              <description>Effect of simultaneous set and clear on output 2.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output n (or set based on the SETCLR2 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O3RES</name>
              <description>Effect of simultaneous set and clear on output 3.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR3 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O4RES</name>
              <description>Effect of simultaneous set and clear on output 4.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR4 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O5RES</name>
              <description>Effect of simultaneous set and clear on output 5.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR5 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O6RES</name>
              <description>Effect of simultaneous set and clear on output 6.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR6 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O7RES</name>
              <description>Effect of simultaneous set and clear on output 7.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output n (or set based on the SETCLR7 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O8RES</name>
              <description>Effect of simultaneous set and clear on output 8.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR8 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O9RES</name>
              <description>Effect of simultaneous set and clear on output 9.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR9 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O10RES</name>
              <description>Effect of simultaneous set and clear on output 10.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR10 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O11RES</name>
              <description>Effect of simultaneous set and clear on output 11.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR11 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O12RES</name>
              <description>Effect of simultaneous set and clear on output 12.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR12 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O13RES</name>
              <description>Effect of simultaneous set and clear on output 13.</description>
              <bitOffset>26</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR13 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O14RES</name>
              <description>Effect of simultaneous set and clear on output 14.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR14 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>O15RES</name>
              <description>Effect of simultaneous set and clear on output 15.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_CHANGE</name>
                  <description>No change.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SET</name>
                  <description>Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CLEAR</name>
                  <description>Clear output (or set based on the SETCLR15 field).</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TOGGLE_OUTPUT</name>
                  <description>Toggle output.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA0REQUEST</name>
          <description>SCT DMA request 0 register</description>
          <addressOffset>0x5C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xC000FFFF</resetMask>
          <fields>
            <field>
              <name>DEV_0</name>
              <description>If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DRL0</name>
              <description>A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DRQ0</name>
              <description>This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DMA1REQUEST</name>
          <description>SCT DMA request 1 register</description>
          <addressOffset>0x60</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xC000FFFF</resetMask>
          <fields>
            <field>
              <name>DEV_1</name>
              <description>If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DRL1</name>
              <description>A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DRQ1</name>
              <description>This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EVEN</name>
          <description>SCT event interrupt enable register</description>
          <addressOffset>0xF0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>IEN</name>
              <description>The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EVFLAG</name>
          <description>SCT event flag register</description>
          <addressOffset>0xF4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>FLAG</name>
              <description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CONEN</name>
          <description>SCT conflict interrupt enable register</description>
          <addressOffset>0xF8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>NCEN</name>
              <description>The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CONFLAG</name>
          <description>SCT conflict flag register</description>
          <addressOffset>0xFC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xC000FFFF</resetMask>
          <fields>
            <field>
              <name>NCFLAG</name>
              <description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUSERRL</name>
              <description>The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful.</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BUSERRH</name>
              <description>The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted.</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>10</dim>
          <dimIncrement>0x4</dimIncrement>
          <name>SCTCAP[%s]</name>
          <description>SCT capture register of capture channel</description>
          <alternateGroup>CAP_MATCH</alternateGroup>
          <addressOffset>0x100</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CAPn_L</name>
              <description>When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAPn_H</name>
              <description>When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>10</dim>
          <dimIncrement>0x4</dimIncrement>
          <name>SCTMATCH[%s]</name>
          <description>SCT match value register of match channels</description>
          <alternateGroup>CAP_MATCH</alternateGroup>
          <addressOffset>0x100</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MATCHn_L</name>
              <description>When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MATCHn_H</name>
              <description>When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>10</dim>
          <dimIncrement>0x4</dimIncrement>
          <name>SCTCAPCTRL[%s]</name>
          <description>SCT capture control register</description>
          <alternateGroup>CAPCTRL_MATCHREL</alternateGroup>
          <addressOffset>0x200</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CAPCONn_L</name>
              <description>If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CAPCONn_H</name>
              <description>If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>10</dim>
          <dimIncrement>0x4</dimIncrement>
          <name>SCTMATCHREL[%s]</name>
          <description>SCT match reload value register</description>
          <alternateGroup>CAPCTRL_MATCHREL</alternateGroup>
          <addressOffset>0x200</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>RELOADn_L</name>
              <description>When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RELOADn_H</name>
              <description>When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <cluster>
          <dim>10</dim>
          <dimIncrement>0x8</dimIncrement>
          <name>EVENT[%s]</name>
          <description>no description available</description>
          <addressOffset>0x300</addressOffset>
          <register>
            <name>STATE</name>
            <description>SCT event state register 0</description>
            <addressOffset>0</addressOffset>
            <size>32</size>
            <access>read-write</access>
            <resetValue>0</resetValue>
            <resetMask>0xFFFF</resetMask>
            <fields>
              <field>
                <name>STATEMSKn</name>
                <description>If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>16</bitWidth>
                <access>read-write</access>
              </field>
            </fields>
          </register>
          <register>
            <name>CTRL</name>
            <description>SCT event control register 0</description>
            <addressOffset>0x4</addressOffset>
            <size>32</size>
            <access>read-write</access>
            <resetValue>0</resetValue>
            <resetMask>0x7FFFFF</resetMask>
            <fields>
              <field>
                <name>MATCHSEL</name>
                <description>Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>HEVENT</name>
                <description>Select L/H counter. Do not set this bit if UNIFY = 1.</description>
                <bitOffset>4</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>L_COUNTER</name>
                    <description>Selects the L state and the L match register selected by MATCHSEL.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>H_COUNTER</name>
                    <description>Selects the H state and the H match register selected by MATCHSEL.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>OUTSEL</name>
                <description>Input/output select</description>
                <bitOffset>5</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>INPUT</name>
                    <description>Selects the inputs selected by IOSEL.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>OUTPUT</name>
                    <description>Selects the outputs selected by IOSEL.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>IOSEL</name>
                <description>Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.</description>
                <bitOffset>6</bitOffset>
                <bitWidth>4</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>IOCOND</name>
                <description>Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .</description>
                <bitOffset>10</bitOffset>
                <bitWidth>2</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>LOW</name>
                    <description>LOW</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>RISE</name>
                    <description>Rise</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>FALL</name>
                    <description>Fall</description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>HIGH</name>
                    <description>HIGH</description>
                    <value>0x3</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>COMBMODE</name>
                <description>Selects how the specified match and I/O condition are used and combined.</description>
                <bitOffset>12</bitOffset>
                <bitWidth>2</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>OR</name>
                    <description>OR. The event occurs when either the specified match or I/O condition occurs.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>MATCH</name>
                    <description>MATCH. Uses the specified match only.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>IO</name>
                    <description>IO. Uses the specified I/O condition only.</description>
                    <value>0x2</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>AND</name>
                    <description>AND. The event occurs when the specified match and I/O condition occur simultaneously.</description>
                    <value>0x3</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>STATELD</name>
                <description>This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.</description>
                <bitOffset>14</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>ADD</name>
                    <description>STATEV value is added into STATE (the carry-out is ignored).</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>LOAD</name>
                    <description>STATEV value is loaded into STATE.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
              <field>
                <name>STATEV</name>
                <description>This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.</description>
                <bitOffset>15</bitOffset>
                <bitWidth>5</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>MATCHMEM</name>
                <description>If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.</description>
                <bitOffset>20</bitOffset>
                <bitWidth>1</bitWidth>
                <access>read-write</access>
              </field>
              <field>
                <name>DIRECTION</name>
                <description>Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.</description>
                <bitOffset>21</bitOffset>
                <bitWidth>2</bitWidth>
                <access>read-write</access>
                <enumeratedValues>
                  <enumeratedValue>
                    <name>DIRECTION_INDEPENDENT</name>
                    <description>Direction independent. This event is triggered regardless of the count direction.</description>
                    <value>0</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>COUNTING_UP</name>
                    <description>Counting up. This event is triggered only during up-counting when BIDIR = 1.</description>
                    <value>0x1</value>
                  </enumeratedValue>
                  <enumeratedValue>
                    <name>COUNTING_DOWN</name>
                    <description>Counting down. This event is triggered only during down-counting when BIDIR = 1.</description>
                    <value>0x2</value>
                  </enumeratedValue>
                </enumeratedValues>
              </field>
            </fields>
          </register>
        </cluster>
        <cluster>
          <dim>8</dim>
          <dimIncrement>0x8</dimIncrement>
          <name>OUT[%s]</name>
          <description>no description available</description>
          <addressOffset>0x500</addressOffset>
          <register>
            <name>SET</name>
            <description>SCT output 0 set register</description>
            <addressOffset>0</addressOffset>
            <size>32</size>
            <access>read-write</access>
            <resetValue>0</resetValue>
            <resetMask>0xFFFF</resetMask>
            <fields>
              <field>
                <name>SET</name>
                <description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>16</bitWidth>
                <access>read-write</access>
              </field>
            </fields>
          </register>
          <register>
            <name>CLR</name>
            <description>SCT output 0 clear register</description>
            <addressOffset>0x4</addressOffset>
            <size>32</size>
            <access>read-write</access>
            <resetValue>0</resetValue>
            <resetMask>0xFFFF</resetMask>
            <fields>
              <field>
                <name>CLR</name>
                <description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.</description>
                <bitOffset>0</bitOffset>
                <bitWidth>16</bitWidth>
                <access>read-write</access>
              </field>
            </fields>
          </register>
        </cluster>
        <register>
          <name>MODULECONTENT</name>
          <description>Reserved</description>
          <addressOffset>0x7FC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>I2C0</name>
      <alternatePeripheral>FLEXCOMM1</alternatePeripheral>
      <description>i2c</description>
      <groupName>I2C</groupName>
      <headerStructName>I2C</headerStructName>
      <baseAddress>0x40086000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CFG</name>
          <description>Configuration for shared functions.</description>
          <addressOffset>0x800</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3F</resetMask>
          <fields>
            <field>
              <name>MSTEN</name>
              <description>Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The I2C Master function is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The I2C Master function is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVEN</name>
              <description>Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The I2C slave function is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The I2C slave function is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONEN</name>
              <description>Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The I2C Monitor function is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The I2C Monitor function is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TIMEOUTEN</name>
              <description>I2C bus Time-out Enable. When disabled, the time-out function is internally reset.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. Time-out function is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONCLKSTR</name>
              <description>Monitor function Clock Stretching.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT</name>
          <description>Status register for Master, Slave, and Monitor functions.</description>
          <addressOffset>0x804</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x801</resetValue>
          <resetMask>0x30FFF5F</resetMask>
          <fields>
            <field>
              <name>MSTPENDING</name>
              <description>Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>IN_PROGRESS</name>
                  <description>In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PENDING</name>
                  <description>Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTATE</name>
              <description>Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>IDLE</name>
                  <description>Idle. The Master function is available to be used for a new transaction.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>RECEIVE_READY</name>
                  <description>Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TRANSMIT_READY</name>
                  <description>Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NACK_ADDRESS</name>
                  <description>NACK Address. Slave NACKed address.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NACK_DATA</name>
                  <description>NACK Data. Slave NACKed transmitted data.</description>
                  <value>0x4</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTARBLOSS</name>
              <description>Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_LOSS</name>
                  <description>No Arbitration Loss has occurred.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ARBITRATION_LOSS</name>
                  <description>Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTSTPERR</name>
              <description>Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_ERROR</name>
                  <description>No Start/Stop Error has occurred.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ERROR</name>
                  <description>The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVPENDING</name>
              <description>Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>IN_PROGRESS</name>
                  <description>In progress. The Slave function does not currently need service.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>PENDING</name>
                  <description>Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVSTATE</name>
              <description>Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SLAVE_ADDRESS</name>
                  <description>Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SLAVE_RECEIVE</name>
                  <description>Slave receive. Received data is available (Slave Receiver mode).</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SLAVE_TRANSMIT</name>
                  <description>Slave transmit. Data can be transmitted (Slave Transmitter mode).</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNOTSTR</name>
              <description>Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>STRETCHING</name>
                  <description>Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NOT_STRETCHING</name>
                  <description>Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVIDX</name>
              <description>Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ADDRESS0</name>
                  <description>Address 0. Slave address 0 was matched.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADDRESS1</name>
                  <description>Address 1. Slave address 1 was matched.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADDRESS2</name>
                  <description>Address 2. Slave address 2 was matched.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ADDRESS3</name>
                  <description>Address 3. Slave address 3 was matched.</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVSEL</name>
              <description>Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data.</description>
              <bitOffset>14</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_SELECTED</name>
                  <description>Not selected. The Slave function is not currently selected.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SELECTED</name>
                  <description>Selected. The Slave function is currently selected.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDESEL</name>
              <description>Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_DESELECTED</name>
                  <description>Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DESELECTED</name>
                  <description>Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRDY</name>
              <description>Monitor Ready. This flag is cleared when the MONRXDAT register is read.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_DATA</name>
                  <description>No data. The Monitor function does not currently have data available.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DATA_WAITING</name>
                  <description>Data waiting. The Monitor function has data waiting to be read.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONOV</name>
              <description>Monitor Overflow flag.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_OVERRUN</name>
                  <description>No overrun. Monitor data has not overrun.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>OVERRUN</name>
                  <description>Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONACTIVE</name>
              <description>Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INACTIVE</name>
                  <description>Inactive. The Monitor function considers the I2C bus to be inactive.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACTIVE</name>
                  <description>Active. The Monitor function considers the I2C bus to be active.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONIDLE</name>
              <description>Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_IDLE</name>
                  <description>Not idle. The I2C bus is not idle, or this flag has been cleared by software.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>IDLE</name>
                  <description>Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EVENTTIMEOUT</name>
              <description>Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_TIMEOUT</name>
                  <description>No time-out. I2C bus events have not caused a time-out.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EVEN_TIMEOUT</name>
                  <description>Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SCLTIMEOUT</name>
              <description>SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_TIMEOUT</name>
                  <description>No time-out. SCL low time has not caused a time-out.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TIMEOUT</name>
                  <description>Time-out. SCL low time has caused a time-out.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENSET</name>
          <description>Interrupt Enable Set and read register.</description>
          <addressOffset>0x808</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x30B8951</resetMask>
          <fields>
            <field>
              <name>MSTPENDINGEN</name>
              <description>Master Pending interrupt Enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The MstPending interrupt is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The MstPending interrupt is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTARBLOSSEN</name>
              <description>Master Arbitration Loss interrupt Enable.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The MstArbLoss interrupt is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The MstArbLoss interrupt is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTSTPERREN</name>
              <description>Master Start/Stop Error interrupt Enable.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The MstStStpErr interrupt is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The MstStStpErr interrupt is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVPENDINGEN</name>
              <description>Slave Pending interrupt Enable.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The SlvPending interrupt is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The SlvPending interrupt is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNOTSTREN</name>
              <description>Slave Not Stretching interrupt Enable.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The SlvNotStr interrupt is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The SlvNotStr interrupt is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDESELEN</name>
              <description>Slave Deselect interrupt Enable.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The SlvDeSel interrupt is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The SlvDeSel interrupt is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRDYEN</name>
              <description>Monitor data Ready interrupt Enable.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The MonRdy interrupt is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The MonRdy interrupt is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONOVEN</name>
              <description>Monitor Overrun interrupt Enable.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The MonOv interrupt is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The MonOv interrupt is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONIDLEEN</name>
              <description>Monitor Idle interrupt Enable.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The MonIdle interrupt is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The MonIdle interrupt is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EVENTTIMEOUTEN</name>
              <description>Event time-out interrupt Enable.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The Event time-out interrupt is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The Event time-out interrupt is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SCLTIMEOUTEN</name>
              <description>SCL time-out interrupt Enable.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The SCL time-out interrupt is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The SCL time-out interrupt is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENCLR</name>
          <description>Interrupt Enable Clear register.</description>
          <addressOffset>0x80C</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>MSTPENDINGCLR</name>
              <description>Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MSTARBLOSSCLR</name>
              <description>Master Arbitration Loss interrupt clear.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MSTSTSTPERRCLR</name>
              <description>Master Start/Stop Error interrupt clear.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVPENDINGCLR</name>
              <description>Slave Pending interrupt clear.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVNOTSTRCLR</name>
              <description>Slave Not Stretching interrupt clear.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SLVDESELCLR</name>
              <description>Slave Deselect interrupt clear.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONRDYCLR</name>
              <description>Monitor data Ready interrupt clear.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONOVCLR</name>
              <description>Monitor Overrun interrupt clear.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MONIDLECLR</name>
              <description>Monitor Idle interrupt clear.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>EVENTTIMEOUTCLR</name>
              <description>Event time-out interrupt clear.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SCLTIMEOUTCLR</name>
              <description>SCL time-out interrupt clear.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TIMEOUT</name>
          <description>Time-out value register.</description>
          <addressOffset>0x810</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFF</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>TOMIN</name>
              <description>Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TO</name>
              <description>Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CLKDIV</name>
          <description>Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.</description>
          <addressOffset>0x814</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>DIVVAL</name>
              <description>This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTSTAT</name>
          <description>Interrupt Status register for Master, Slave, and Monitor functions.</description>
          <addressOffset>0x818</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0x801</resetValue>
          <resetMask>0x30B8951</resetMask>
          <fields>
            <field>
              <name>MSTPENDING</name>
              <description>Master Pending.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MSTARBLOSS</name>
              <description>Master Arbitration Loss flag.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MSTSTSTPERR</name>
              <description>Master Start/Stop Error flag.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVPENDING</name>
              <description>Slave Pending.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVNOTSTR</name>
              <description>Slave Not Stretching status.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SLVDESEL</name>
              <description>Slave Deselected flag.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONRDY</name>
              <description>Monitor Ready.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONOV</name>
              <description>Monitor Overflow flag.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONIDLE</name>
              <description>Monitor Idle flag.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>EVENTTIMEOUT</name>
              <description>Event time-out Interrupt flag.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SCLTIMEOUT</name>
              <description>SCL time-out Interrupt flag.</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTCTL</name>
          <description>Master control register.</description>
          <addressOffset>0x820</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xE</resetMask>
          <fields>
            <field>
              <name>MSTCONTINUE</name>
              <description>Master Continue. This bit is write-only.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CONTINUE</name>
                  <description>Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTART</name>
              <description>Master Start control. This bit is write-only.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>START</name>
                  <description>Start. A Start will be generated on the I2C bus at the next allowed time.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSTOP</name>
              <description>Master Stop control. This bit is write-only.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STOP</name>
                  <description>Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTDMA</name>
              <description>Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disable. No DMA requests are generated for master operation.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTTIME</name>
          <description>Master timing configuration.</description>
          <addressOffset>0x824</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x77</resetValue>
          <resetMask>0x77</resetMask>
          <fields>
            <field>
              <name>MSTSCLLOW</name>
              <description>Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>_2_CLOCKS</name>
                  <description>2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_3_CLOCKS</name>
                  <description>3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_4_CLOCKS</name>
                  <description>4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_5_CLOCKS</name>
                  <description>5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_6_CLOCKS</name>
                  <description>6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_7_CLOCKS</name>
                  <description>7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_8_CLOCKS</name>
                  <description>8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_9_CLOCKS</name>
                  <description>9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTSCLHIGH</name>
              <description>Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>_2_CLOCKS</name>
                  <description>2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_3_CLOCKS</name>
                  <description>3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_4_CLOCKS</name>
                  <description>4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_5_CLOCKS</name>
                  <description>5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_6_CLOCKS</name>
                  <description>6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.</description>
                  <value>0x4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_7_CLOCKS</name>
                  <description>7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.</description>
                  <value>0x5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_8_CLOCKS</name>
                  <description>8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.</description>
                  <value>0x6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>_9_CLOCKS</name>
                  <description>9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.</description>
                  <value>0x7</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>MSTDAT</name>
          <description>Combined Master receiver and transmitter data register.</description>
          <addressOffset>0x828</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVCTL</name>
          <description>Slave control register.</description>
          <addressOffset>0x840</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x30B</resetMask>
          <fields>
            <field>
              <name>SLVCONTINUE</name>
              <description>Slave Continue.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CONTINUE</name>
                  <description>Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVNACK</name>
              <description>Slave NACK.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_EFFECT</name>
                  <description>No effect.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NACK</name>
                  <description>NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVDMA</name>
              <description>Slave DMA enable.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. No DMA requests are issued for Slave mode operation.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. DMA requests are issued for I2C slave data transmission and reception.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>AUTOACK</name>
              <description>Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NORMAL</name>
                  <description>Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored).</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>AUTOMATIC_ACK</name>
                  <description>A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>AUTOMATCHREAD</name>
              <description>When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>I2C_WRITE</name>
                  <description>The expected next operation in Automatic Mode is an I2C write.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>I2C_READ</name>
                  <description>The expected next operation in Automatic Mode is an I2C read.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVDAT</name>
          <description>Combined Slave receiver and transmitter data register.</description>
          <addressOffset>0x844</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <dim>4</dim>
          <dimIncrement>0x4</dimIncrement>
          <name>SLVADR[%s]</name>
          <description>Slave address register.</description>
          <addressOffset>0x848</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>SADISABLE</name>
              <description>Slave Address n Disable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. Slave Address n is enabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Ignored Slave Address n is ignored.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVADR</name>
              <description>Slave Address. Seven bit slave address that is compared to received addresses if enabled.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>AUTONACK</name>
              <description>Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations.</description>
              <bitOffset>15</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NORMAL</name>
                  <description>Normal operation, matching I2C addresses are not ignored.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>AUTOMATIC</name>
                  <description>Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SLVQUAL0</name>
          <description>Slave Qualification for address 0.</description>
          <addressOffset>0x858</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF</resetMask>
          <fields>
            <field>
              <name>QUALMODE0</name>
              <description>Qualify mode for slave address 0.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>MASK</name>
                  <description>Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EXTEND</name>
                  <description>Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SLVQUAL0</name>
              <description>Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] &amp;amp;lt;= received address &amp;amp;lt;= SLVQUAL0[7:1]).</description>
              <bitOffset>1</bitOffset>
              <bitWidth>7</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MONRXDAT</name>
          <description>Monitor receiver data register.</description>
          <addressOffset>0x880</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x7FF</resetMask>
          <fields>
            <field>
              <name>MONRXDAT</name>
              <description>Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MONSTART</name>
              <description>Monitor Received Start.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NO_START_DETECTED</name>
                  <description>No start detected. The Monitor function has not detected a Start event on the I2C bus.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>START_DETECTED</name>
                  <description>Start detected. The Monitor function has detected a Start event on the I2C bus.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONRESTART</name>
              <description>Monitor Received Repeated Start.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_DETECTED</name>
                  <description>No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DETECTED</name>
                  <description>Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MONNACK</name>
              <description>Monitor Received NACK.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ACKNOWLEDGED</name>
                  <description>Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NOT_ACKNOWLEDGED</name>
                  <description>Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>ID</name>
          <description>I2C module Identification. This value appears in the shared Flexcomm peripheral ID register when I2C is selected.</description>
          <addressOffset>0xFFC</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xE0300000</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>APERTURE</name>
              <description>Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MINOR_REV</name>
              <description>Minor revision of module implementation, starting at 0. Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MAJOR_REV</name>
              <description>Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ID</name>
              <description>Unique module identifier for this IP block.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="I2C0">
      <name>I2C1</name>
      <alternatePeripheral>FLEXCOMM2</alternatePeripheral>
      <description>i2c</description>
      <groupName>I2C</groupName>
      <baseAddress>0x40087000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
    </peripheral>
    <peripheral>
      <name>SPI0</name>
      <alternatePeripheral>FLEXCOMM2</alternatePeripheral>
      <description>spi</description>
      <groupName>SPI</groupName>
      <headerStructName>SPI</headerStructName>
      <baseAddress>0x40087000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CFG</name>
          <description>SPI Configuration register</description>
          <addressOffset>0x400</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFBD</resetMask>
          <fields>
            <field>
              <name>ENABLE</name>
              <description>SPI enable.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. The SPI is disabled and the internal state machine and counters are reset.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. The SPI is enabled for operation.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MASTER</name>
              <description>Master mode select.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SLAVE_MODE</name>
                  <description>Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>MASTER_MODE</name>
                  <description>Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LSBF</name>
              <description>LSB First mode enable.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>STANDARD</name>
                  <description>Standard. Data is transmitted and received in standard MSB first order.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>REVERSE</name>
                  <description>Reverse. Data is transmitted and received in reverse order (LSB first).</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CPHA</name>
              <description>Clock Phase select.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>CHANGE</name>
                  <description>Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>CAPTURE</name>
                  <description>Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CPOL</name>
              <description>Clock Polarity select.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>LOW</name>
                  <description>Low. The rest state of the clock (between transfers) is low.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH</name>
                  <description>High. The rest state of the clock (between transfers) is high.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LOOP</name>
              <description>Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SPOL0</name>
              <description>SSEL0 Polarity select.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>LOW</name>
                  <description>Low. The SSEL0 pin is active low.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH</name>
                  <description>High. The SSEL0 pin is active high.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SPOL1</name>
              <description>SSEL1 Polarity select.</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>LOW</name>
                  <description>Low. The SSEL1 pin is active low.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH</name>
                  <description>High. The SSEL1 pin is active high.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SPOL2</name>
              <description>SSEL2 Polarity select.</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>LOW</name>
                  <description>Low. The SSEL2 pin is active low.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH</name>
                  <description>High. The SSEL2 pin is active high.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SPOL3</name>
              <description>SSEL3 Polarity select.</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>LOW</name>
                  <description>Low. The SSEL3 pin is active low.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>HIGH</name>
                  <description>High. The SSEL3 pin is active high.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>DLY</name>
          <description>SPI Delay register</description>
          <addressOffset>0x404</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>PRE_DELAY</name>
              <description>Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>POST_DELAY</name>
              <description>Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FRAME_DELAY</name>
              <description>If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TRANSFER_DELAY</name>
              <description>Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STAT</name>
          <description>SPI Status. Some status flags can be cleared by writing a 1 to that bit position.</description>
          <addressOffset>0x408</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x100</resetValue>
          <resetMask>0x1C0</resetMask>
          <fields>
            <field>
              <name>SSA</name>
              <description>Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SSD</name>
              <description>Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>STALLED</name>
              <description>Stalled status flag. This indicates whether the SPI is currently in a stall condition.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ENDTRANSFER</name>
              <description>End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MSTIDLE</name>
              <description>Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENSET</name>
          <description>SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.</description>
          <addressOffset>0x40C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x130</resetMask>
          <fields>
            <field>
              <name>SSAEN</name>
              <description>Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SSDEN</name>
              <description>Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MSTIDLEEN</name>
              <description>Master idle interrupt enable.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>No interrupt will be generated when the SPI master function is idle.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>An interrupt will be generated when the SPI master function is fully idle.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENCLR</name>
          <description>SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.</description>
          <addressOffset>0x410</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>SSAEN</name>
              <description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SSDEN</name>
              <description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MSTIDLE</name>
              <description>Writing 1 clears the corresponding bit in the INTENSET register.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DIV</name>
          <description>SPI clock Divider</description>
          <addressOffset>0x424</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>DIVVAL</name>
              <description>Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTSTAT</name>
          <description>SPI Interrupt Status</description>
          <addressOffset>0x428</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x130</resetMask>
          <fields>
            <field>
              <name>SSA</name>
              <description>Slave Select Assert.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SSD</name>
              <description>Slave Select Deassert.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MSTIDLE</name>
              <description>Master Idle status flag.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOCFG</name>
          <description>FIFO configuration and enable register.</description>
          <addressOffset>0xE00</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x4F033</resetMask>
          <fields>
            <field>
              <name>ENABLETX</name>
              <description>Enable the transmit FIFO.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>The transmit FIFO is not enabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>The transmit FIFO is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ENABLERX</name>
              <description>Enable the receive FIFO.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>The transmit FIFO is not enabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>The transmit FIFO is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SIZE</name>
              <description>FIFO size configuration. This is a read-only field. 0x1 = FIFO is configured as 8 entries of 16 bits. 0x0, 0x2, 0x3 = not applicable to SPI.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>DMATX</name>
              <description>DMA configuration for transmit.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_TRIGGERED</name>
                  <description>DMA is not used for the transmit function.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TRIGGERED</name>
                  <description>Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DMARX</name>
              <description>DMA configuration for receive.</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_TRIGGERED</name>
                  <description>DMA is not used for the receive function.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TRIGGERED</name>
                  <description>Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EMPTYTX</name>
              <description>Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>EMPTYRX</name>
              <description>Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOSTAT</name>
          <description>FIFO status register.</description>
          <addressOffset>0xE04</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x30</resetValue>
          <resetMask>0x1F1FFB</resetMask>
          <fields>
            <field>
              <name>TXERR</name>
              <description>TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXERR</name>
              <description>RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PERINT</name>
              <description>Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral' STAT register.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXEMPTY</name>
              <description>Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXNOTFULL</name>
              <description>Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow.</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXNOTEMPTY</name>
              <description>Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXFULL</name>
              <description>Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow.</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXLVL</name>
              <description>Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXLVL</name>
              <description>Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>5</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOTRIG</name>
          <description>FIFO trigger settings for interrupt and DMA request.</description>
          <addressOffset>0xE08</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF0F03</resetMask>
          <fields>
            <field>
              <name>TXLVLENA</name>
              <description>Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Transmit FIFO level does not generate a FIFO level trigger.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RXLVLENA</name>
              <description>Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>Receive FIFO level does not generate a FIFO level trigger.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TXLVL</name>
              <description>Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See -Hardware Wake-up control register-. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 7 = 1 = trigger when the TX FIFO level decreases to 7 entries (is no longer full).</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXLVL</name>
              <description>Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See -Hardware Wake-up control register-. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 7 = trigger when the RX FIFO has received 8 entries (has become full).</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOINTENSET</name>
          <description>FIFO interrupt enable set (enable) and read register.</description>
          <addressOffset>0xE10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>TXERR</name>
              <description>Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>No interrupt will be generated for a transmit error.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>An interrupt will be generated when a transmit error occurs.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RXERR</name>
              <description>Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>No interrupt will be generated for a receive error.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>An interrupt will be generated when a receive error occurs.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TXLVL</name>
              <description>Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>No interrupt will be generated based on the TX FIFO level.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RXLVL</name>
              <description>Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLED</name>
                  <description>No interrupt will be generated based on the RX FIFO level.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ENABLED</name>
                  <description>If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOINTENCLR</name>
          <description>FIFO interrupt enable clear (disable) and read register.</description>
          <addressOffset>0xE14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xF</resetMask>
          <fields>
            <field>
              <name>TXERR</name>
              <description>Writing one clears the corresponding bits in the FIFOINTENSET register.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXERR</name>
              <description>Writing one clears the corresponding bits in the FIFOINTENSET register.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TXLVL</name>
              <description>Writing one clears the corresponding bits in the FIFOINTENSET register.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>RXLVL</name>
              <description>Writing one clears the corresponding bits in the FIFOINTENSET register.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOINTSTAT</name>
          <description>FIFO interrupt status register.</description>
          <addressOffset>0xE18</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1F</resetMask>
          <fields>
            <field>
              <name>TXERR</name>
              <description>TX FIFO error.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXERR</name>
              <description>RX FIFO error.</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>TXLVL</name>
              <description>Transmit FIFO level interrupt.</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXLVL</name>
              <description>Receive FIFO level interrupt.</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>PERINT</name>
              <description>Peripheral interrupt.</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFOWR</name>
          <description>FIFO write data.</description>
          <addressOffset>0xE20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>TXDATA</name>
              <description>Transmit data to the FIFO.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>TXSSEL0_N</name>
              <description>Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ASSERTED</name>
                  <description>SSEL0 asserted.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NOT_ASSERTED</name>
                  <description>SSEL0 not asserted.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TXSSEL1_N</name>
              <description>Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ASSERTED</name>
                  <description>SSEL1 asserted.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NOT_ASSERTED</name>
                  <description>SSEL1 not asserted.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TXSSEL2_N</name>
              <description>Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ASSERTED</name>
                  <description>SSEL2 asserted.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NOT_ASSERTED</name>
                  <description>SSEL2 not asserted.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TXSSEL3_N</name>
              <description>Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>ASSERTED</name>
                  <description>SSEL3 asserted.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NOT_ASSERTED</name>
                  <description>SSEL3 not asserted.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EOT</name>
              <description>End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_DEASSERTED</name>
                  <description>SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DEASSERTED</name>
                  <description>SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>EOF</name>
              <description>End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NOT_EOF</name>
                  <description>Data not EOF. This piece of data transmitted is not treated as the end of a frame.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>EOF</name>
                  <description>Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>RXIGNORE</name>
              <description>Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>READ</name>
                  <description>Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>IGNORE</name>
                  <description>Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>LEN</name>
              <description>Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. Note: when LEN = 0, the underrun status is not meaningful. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. 0xF = Data transfer is 16 bits in length.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFORD</name>
          <description>FIFO read data.</description>
          <addressOffset>0xE30</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFFF</resetMask>
          <fields>
            <field>
              <name>RXDATA</name>
              <description>Received data from the FIFO.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXSSEL0_N</name>
              <description>Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXSSEL1_N</name>
              <description>Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXSSEL2_N</name>
              <description>Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXSSEL3_N</name>
              <description>Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SOT</name>
              <description>Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIFORDNOPOP</name>
          <description>FIFO data read with no FIFO pop.</description>
          <addressOffset>0xE40</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFFF</resetMask>
          <fields>
            <field>
              <name>RXDATA</name>
              <description>Received data from the FIFO.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXSSEL0_N</name>
              <description>Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXSSEL1_N</name>
              <description>Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXSSEL2_N</name>
              <description>Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>RXSSEL3_N</name>
              <description>Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SOT</name>
              <description>Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ID</name>
          <description>SPI module Identification. This value appears in the shared Flexcomm peripheral ID register when SPI is selected.</description>
          <addressOffset>0xFFC</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xE0200000</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>APERTURE</name>
              <description>Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MINOR_REV</name>
              <description>Minor revision of module implementation, starting at 0. Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions.</description>
              <bitOffset>8</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>MAJOR_REV</name>
              <description>Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions.</description>
              <bitOffset>12</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>ID</name>
              <description>Unique module identifier for this IP block.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="SPI0">
      <name>SPI1</name>
      <alternatePeripheral>FLEXCOMM3</alternatePeripheral>
      <description>spi</description>
      <groupName>SPI</groupName>
      <baseAddress>0x4008F000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
    </peripheral>
    <peripheral>
      <name>FSP</name>
      <description>fsp</description>
      <groupName>FSP</groupName>
      <baseAddress>0x40088000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x1A0</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>SYS_CTRL</name>
          <description>FSP system control register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>TE_ABORT</name>
              <description>Transform Engine abort write 1 to abort</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>MOU_ABORT</name>
              <description>Matrix Operation Unit abort write 1 to abort</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SCF_ABORT</name>
              <description>SE COR FIR abort write 1 to abort</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>STATUS</name>
          <description>FSP status register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0x7</resetMask>
          <fields>
            <field>
              <name>FPU0_BUSY</name>
              <description>SE COR FIR is in processing busy</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FPU1_BUSY</name>
              <description>TE MOU is in processing busy</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>FIR_READY</name>
              <description>FIR output buffer is not empty which is valid for read</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INT</name>
          <description>FSP interrupt register</description>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x877F1F0F</resetMask>
          <fields>
            <field>
              <name>TE_DONE_INT</name>
              <description>Transform engine done interrupt</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>MOU_DONE_INT</name>
              <description>Matrix operation unit done interrupt</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>SE_DONE_INT</name>
              <description>Statistic engine done interrupt</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>COR_DONE_INT</name>
              <description>Correlation done interrupt</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FPU0_CALC_IN_ERR_INT</name>
              <description>SE COR FIR calculation input data error interrupt</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FPU0_CALC_OUT_ERR_INT</name>
              <description>SE COR FIR calculation output data error interrupt</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FPU0_DIN_OV_INT</name>
              <description>SE COR FIR input data overflow interrupt (always 0)</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FPU0_DOUT_OV_INT</name>
              <description>SE COR FIR output data overflow interrupt</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>SINGULAR_INT</name>
              <description>MOU singular interrupt</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FPU1_CALC_IN_ERR_INT</name>
              <description>MOU TE calculation input data error interrupt</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FPU1_CALC_OUT_ERR_INT</name>
              <description>MOU TE calculation output data error interrupt</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FPU1_DIN_OV_INT</name>
              <description>MOU TE input data overflow interrupt</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FPU1_DOUT_OV_INT</name>
              <description>MOU TE output data overflow interrupt</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FINV_DIN_ERR_INT</name>
              <description>FINV input data is inf or nan</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FINV_DOUT_OV_INT</name>
              <description>FINV output data overflow</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FINV_ZERO_INT</name>
              <description>FINV input data is zero</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CORDIC_DIN_ERR</name>
              <description>CORDIC input data error interrupt</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CORDIC_DOUT_ERR_INT</name>
              <description>CORDIC output data error interrupt</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>CORDIC_CALC_ERR_INT</name>
              <description>CORDIC calculation error interrupt</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
            <field>
              <name>FSP_INT</name>
              <description>Or signal of all FSP function interrupt in this register</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTEN</name>
          <description>FSP interrupt enable register</description>
          <addressOffset>0xC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>TE_DONE_INTEN</name>
              <description>Transform engine done interrupt enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MOU_DONE_INTEN</name>
              <description>Matrix operation unit done interrupt enable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SE_DONE_INTEN</name>
              <description>Statistic engine done interrupt enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COR_DONE_INTEN</name>
              <description>Correlation done interrupt enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FPU0_CALC_IN_ERR_INTEN</name>
              <description>SE COR FIR calculation input data error interrupt enable</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FPU0_CALC_OUT_ERR_INTEN</name>
              <description>SE COR FIR calculation output data error interrupt enable</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FPU0_DIN_OV_INTEN</name>
              <description>SE COR FIR input data overflow interrupt enable</description>
              <bitOffset>10</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FPU0_DOUT_OV_INTEN</name>
              <description>SE COR FIR output data overflow interrupt enable</description>
              <bitOffset>11</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SINGULAR_INTEN</name>
              <description>MOU singular interrupt enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FPU1_CALC_IN_ERR_INTEN</name>
              <description>MOU TE calculation input data error interrupt enable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FPU1_CALC_OUT_ERR_INTEN</name>
              <description>MOU TE calculation output data error interrupt enable</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FPU1_DIN_OV_INTEN</name>
              <description>MOU TE input data overflow interrupt enable</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FPU1_DOUT_OV_INTEN</name>
              <description>MOU TE output data overflow interrupt enable</description>
              <bitOffset>19</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FINV_DIN_ERR_INTEN</name>
              <description>FINV data input is inf or nan interrupt enable</description>
              <bitOffset>20</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FINV_DOUT_OV_INTEN</name>
              <description>FINV data output overflow interrupt enable</description>
              <bitOffset>21</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FINV_ZERO_INTEN</name>
              <description>FINV input is zero interrupt enable</description>
              <bitOffset>22</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORDIC_DIN_ERR_INTEN</name>
              <description>CORDIC input data error interrupt enable</description>
              <bitOffset>24</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORDIC_DOUT_ERR_INTEN</name>
              <description>CORDIC output data error interrupt enable</description>
              <bitOffset>25</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CORDIC_CALC_ERR_INTEN</name>
              <description>CORDIC calculation error interrupt enable</description>
              <bitOffset>26</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FSP_INTEN</name>
              <description>Or signal of all FSP function interrupt in this register enable</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TE_CTRL</name>
          <description>transmit engine control register</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x700FFFF</resetMask>
          <fields>
            <field>
              <name>TE_MODE</name>
              <description>TE compute mode</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>TE_FFT</name>
                  <description>FFT</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TE_IFFT</name>
                  <description>IFFT</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TE_DCT</name>
                  <description>DCT</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TE_IDCT</name>
                  <description>IDCT</description>
                  <value>0x3</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TE_IO_MODE</name>
              <description>TE input &amp;amp; output mode select</description>
              <bitOffset>2</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>TE_RICO</name>
                  <description>real input, complex output</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TE_CICO</name>
                  <description>complex input, complex output</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TE_RIRO</name>
                  <description>real input, real output</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TE_PTS</name>
              <description>TE compute point</description>
              <bitOffset>4</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>TE64PTS</name>
                  <description>64 points</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TE128PTS</name>
                  <description>128 points</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TE256PTS</name>
                  <description>256 points</description>
                  <value>0x2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TE_DIN_FP_SEL</name>
              <description>TE input data format select</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>FIX</name>
                  <description>fix</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>FLT</name>
                  <description>float</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TE_DOUT_FP_SEL</name>
              <description>TE output data format select</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>FIX</name>
                  <description>fix</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>FLT</name>
                  <description>float</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TE_SCALE</name>
              <description>TE scale</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>TE_PAUSE_LVL</name>
              <description>Transfer Engine stop level for debug use only.</description>
              <bitOffset>24</bitOffset>
              <bitWidth>3</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TE_SRC_BASE</name>
          <description>transfer engine source data memory base register</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFF</resetMask>
          <fields>
            <field>
              <name>TE_SRC_BASE</name>
              <description>TE source data memory base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>TE_DST_BASE</name>
          <description>transfer engine destination data memory base register</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFF</resetMask>
          <fields>
            <field>
              <name>TE_DST_BASE</name>
              <description>TE destination data memory base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MOU_CTRL</name>
          <description>matrix operation unit control register</description>
          <addressOffset>0x40</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x1110000</resetValue>
          <resetMask>0xFFFF030F</resetMask>
          <fields>
            <field>
              <name>OP_MODE</name>
              <description>MOU operation mode</description>
              <bitOffset>0</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>INV</name>
                  <description>inversion</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>MULT</name>
                  <description>matrix multiply</description>
                  <value>0x1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>TRANS</name>
                  <description>transposition</description>
                  <value>0x2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>LINEAR</name>
                  <description>linear operation</description>
                  <value>0x3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DOTMULT</name>
                  <description>dot multiply</description>
                  <value>0x4</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MOU_DIN_FP_SEL</name>
              <description>MOU data input format select</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>MOU_FLT</name>
                  <description>float</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>MOU_FIX</name>
                  <description>fix</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MOU_DOUT_FP_SEL</name>
              <description>MOU data output format select</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>MOU_FLT</name>
                  <description>float</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>MOU_FIX</name>
                  <description>fix</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MAT_M</name>
              <description>MOU Matrix column</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAT_N</name>
              <description>MOU Matrix row only valid when matrix's column is not equal to row</description>
              <bitOffset>20</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAT_K</name>
              <description>MOU Matrix row only valid when matrix mult operation</description>
              <bitOffset>24</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>DIV_EPSILON</name>
              <description>When the data exponent is small than DIV_EPSILON the inverse operation will output a error signal.</description>
              <bitOffset>28</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>LU_STOP</name>
              <description>Stop at LU</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>UINV_STOP</name>
              <description>stop at U-Matrix inverse</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MA_SRC_BASE</name>
          <description>matrix A source data memory base register</description>
          <addressOffset>0x44</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFF</resetMask>
          <fields>
            <field>
              <name>MA_SRC_BASE</name>
              <description>Matrix A source data memory base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MB_SRC_BASE</name>
          <description>matrix B source data memory base register</description>
          <addressOffset>0x48</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFF</resetMask>
          <fields>
            <field>
              <name>MB_SRC_BASE</name>
              <description>Matrix B source data memory base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MO_DST_BASE</name>
          <description>matrix output data memory base register</description>
          <addressOffset>0x4C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFF</resetMask>
          <fields>
            <field>
              <name>MO_DST_BASE</name>
              <description>Matrix Operation Unit output data destination memory base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MOU_SCALEA</name>
          <description>scale coefficient A register</description>
          <addressOffset>0x50</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MOU_SCALEA</name>
              <description>MOU scale coefficient A</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>MOU_SCALEB</name>
          <description>scale coefficient B register</description>
          <addressOffset>0x54</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>MOU_SCALEB</name>
              <description>MOU scale coefficient B</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SE_CTRL</name>
          <description>stastic engine control register</description>
          <addressOffset>0x60</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xC0</resetValue>
          <resetMask>0xFF00FF</resetMask>
          <fields>
            <field>
              <name>MIN_SEL</name>
              <description>Minimum value selection</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>FIRST_ONE</name>
                  <description>first one</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>LAST_ONE</name>
                  <description>last one</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>MAX_SEL</name>
              <description>Maximum value selection0 the first one1 the last one</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MIN_IDX_EN</name>
              <description>Minimum value index calculation enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>MAX_IDX_EN</name>
              <description>Maximum value index calculation enable</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SUM_EN</name>
              <description>Summary calculation enable</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>PWR_EN</name>
              <description>Power calculation enable</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SE_DIN_FP_SEL</name>
              <description>SE data input format select</description>
              <bitOffset>6</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>SE_FLT</name>
                  <description>float</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>SE_FIX</name>
                  <description>fix</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>SE_DOUT_FP_SEL</name>
              <description>SE data output format select</description>
              <bitOffset>7</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>SE_LEN</name>
              <description>Statistic engine length</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SE_SRC_BASE</name>
          <description>statistic engine source data base register</description>
          <addressOffset>0x64</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFF</resetMask>
          <fields>
            <field>
              <name>SE_SRC_BASE</name>
              <description>Statistic engine source data base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SE_IDX</name>
          <description>max or min data index register</description>
          <addressOffset>0x68</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFF00FF</resetMask>
          <fields>
            <field>
              <name>SE_MIN_IDX</name>
              <description>Minimum data index of an array</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
            <field>
              <name>SE_MAX_IDX</name>
              <description>Maximum data index of an array</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SE_SUM</name>
          <description>array summary result register</description>
          <addressOffset>0x6C</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SE_SUM</name>
              <description>Summary of an array</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SE_PWR</name>
          <description>array power result register</description>
          <addressOffset>0x70</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>SE_PWR</name>
              <description>Power value of an array</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COR_CTRL</name>
          <description>correlation control register</description>
          <addressOffset>0x80</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0x300</resetValue>
          <resetMask>0xFFFF0300</resetMask>
          <fields>
            <field>
              <name>COR_DIN_FP_SEL</name>
              <description>COR input data format select</description>
              <bitOffset>8</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>COR_FLT</name>
                  <description>float</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>COR_FIX</name>
                  <description>fix</description>
                  <value>0x1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>COR_DOUT_FP_SEL</name>
              <description>COR output data format select</description>
              <bitOffset>9</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COR_X_LEN</name>
              <description>The length of X sequence to be Correlator 0-255</description>
              <bitOffset>16</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COR_Y_LEN</name>
              <description>The length of Y sequence to be Correlator 0-255</description>
              <bitOffset>24</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CX_SRC_BASE</name>
          <description>correlation x sequence base register</description>
          <addressOffset>0x84</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFF</resetMask>
          <fields>
            <field>
              <name>COR_X_ADDR</name>
              <description>The base address of X sequence to be Correlator</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CY_SRC_BASE</name>
          <description>correlation y sequence base register</description>
          <addressOffset>0x88</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFF</resetMask>
          <fields>
            <field>
              <name>COR_Y_ADDR</name>
              <description>The base address of Y sequence to be Correlator</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CO_DST_BASE</name>
          <description>correlation output sequence base register</description>
          <addressOffset>0x8C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x1FFFF</resetMask>
          <fields>
            <field>
              <name>COR_DST_BASE</name>
              <description>correlation output data destination address base</description>
              <bitOffset>0</bitOffset>
              <bitWidth>17</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>COR_OFFSET</name>
          <description>correlation offset register</description>
          <addressOffset>0x90</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFF</resetMask>
          <fields>
            <field>
              <name>COR_X_OFFSET</name>
              <description>COR input X SEQ offset 0-255</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>COR_Y_OFFSET</name>
              <description>COR input Y SEQ offset 0-255</description>
              <bitOffset>8</bitOffset>
              <bitWidth>8</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_CFG_CH0</name>
          <description>FIR channel 0 configuration register</description>
          <addressOffset>0xA0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_CH0_COEF_BASE</name>
              <description>FIR channel 0 coefficient base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH0_TAP_LEN</name>
              <description>FIR channel 0 tap length the register value equals to real tap length minus 1.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_BUF_CLR_ALL</name>
              <description>clear all FIR buffer</description>
              <bitOffset>30</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>FIR_CH0_BUF_CLR</name>
              <description>FIR channel 0 buffer clear</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_CFG_CH1</name>
          <description>FIR channel 1 configuration register</description>
          <addressOffset>0xA4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_CH1_COEF_BASE</name>
              <description>FIR channel 1 coefficient base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH1_TAP_LEN</name>
              <description>FIR channel 1 tap length</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH1_BUF_CLR</name>
              <description>FIR channel 1 buffer clear</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_CFG_CH2</name>
          <description>FIR channel 2 configuration register</description>
          <addressOffset>0xA8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_CH2_COEF_BASE</name>
              <description>FIR channel 2 coefficient base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH2_TAP_LEN</name>
              <description>FIR channel 2 tap length</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH2_BUF_CLR</name>
              <description>FIR channel 2 buffer clear</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_CFG_CH3</name>
          <description>FIR channel 3 configuration register</description>
          <addressOffset>0xAC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_CH3_COEF_BASE</name>
              <description>FIR channel 3 coefficient base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH3_TAP_LEN</name>
              <description>FIR channel 3 tap length</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH3_BUF_CLR</name>
              <description>FIR channel 3 buffer clear</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_CFG_CH4</name>
          <description>FIR channel 4 configuration register</description>
          <addressOffset>0xB0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_CH4_COEF_BASE</name>
              <description>FIR channel 4 coefficient base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH4_TAP_LEN</name>
              <description>FIR channel 4 tap length</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH4_BUF_CLR</name>
              <description>FIR channel 4 buffer clear</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_CFG_CH5</name>
          <description>FIR channel 5 configuration register</description>
          <addressOffset>0xB4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_CH5_COEF_BASE</name>
              <description>FIR channel 5 coefficient base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH5_TAP_LEN</name>
              <description>FIR channel 5 tap length</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH5_BUF_CLR</name>
              <description>FIR channel 5 buffer clear</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_CFG_CH6</name>
          <description>FIR channel 6 configuration register</description>
          <addressOffset>0xB8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_CH6_COEF_BASE</name>
              <description>FIR channel 6 coefficient base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH6_TAP_LEN</name>
              <description>FIR channel 6 tap length</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH6_BUF_CLR</name>
              <description>FIR channel 6 buffer clear</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_CFG_CH7</name>
          <description>FIR channel 7 configuration register</description>
          <addressOffset>0xBC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_CH7_COEF_BASE</name>
              <description>FIR channel 7 coefficient base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH7_TAP_LEN</name>
              <description>FIR channel 7 tap length</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH7_BUF_CLR</name>
              <description>FIR channel 7 buffer clear</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_CFG_CH8</name>
          <description>FIR channel 8 configuration register</description>
          <addressOffset>0xC0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_CH8_COEF_BASE</name>
              <description>FIR channel 8 coefficient base address</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH8_TAP_LEN</name>
              <description>FIR channel 8 tap length</description>
              <bitOffset>16</bitOffset>
              <bitWidth>4</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>FIR_CH8_BUF_CLR</name>
              <description>FIR channel 8 buffer clear</description>
              <bitOffset>31</bitOffset>
              <bitWidth>1</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT0_FX</name>
          <description>FIR channel 0 fix point data input &amp;amp; output register</description>
          <addressOffset>0xD0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT0_FX</name>
              <description>FIR channel 0 fix data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT1_FX</name>
          <description>FIR channel 1 fix point data input &amp;amp; output register</description>
          <addressOffset>0xD4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT1_FX</name>
              <description>FIR channel1 fix data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT2_FX</name>
          <description>FIR channel 2 fix point data input &amp;amp; output register</description>
          <addressOffset>0xD8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT2_FX</name>
              <description>FIR channel2 fix data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT3_FX</name>
          <description>FIR channel 3 fix point data input &amp;amp; output register</description>
          <addressOffset>0xDC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT3_FX</name>
              <description>FIR channel3 fix data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT4_FX</name>
          <description>FIR channel 4 fix point data input &amp;amp; output register</description>
          <addressOffset>0xE0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT4_FX</name>
              <description>FIR channel4 fix data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT5_FX</name>
          <description>FIR channel 5 fix point data input &amp;amp; output register</description>
          <addressOffset>0xE4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT5_FX</name>
              <description>FIR channel5 fix data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT6_FX</name>
          <description>FIR channel 6 fix point data input &amp;amp; output register</description>
          <addressOffset>0xE8</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT6_FX</name>
              <description>FIR channel6 fix data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT7_FX</name>
          <description>FIR channel 7 fix point data input &amp;amp; output register</description>
          <addressOffset>0xEC</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT7_FX</name>
              <description>FIR channel7 fix data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT8_FX</name>
          <description>FIR channel 8 fix point data input &amp;amp; output register</description>
          <addressOffset>0xF0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT8_FX</name>
              <description>FIR channel8 fix data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT0_FL</name>
          <description>FIR channel 0 float point data input &amp;amp; output register</description>
          <addressOffset>0x100</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT0_FL</name>
              <description>FIR channel 0 float data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT1_FL</name>
          <description>FIR channel 1 float point data input &amp;amp; output register</description>
          <addressOffset>0x104</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT1_FL</name>
              <description>FIR channel1 float data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT2_FL</name>
          <description>FIR channel 2 float point data input &amp;amp; output register</description>
          <addressOffset>0x108</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT2_FL</name>
              <description>FIR channel2 float data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT3_FL</name>
          <description>FIR channel 3 float point data input &amp;amp; output register</description>
          <addressOffset>0x10C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT3_FL</name>
              <description>FIR channel3 float data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT4_FL</name>
          <description>FIR channel 4 float point data input &amp;amp; output register</description>
          <addressOffset>0x110</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT4_FL</name>
              <description>FIR channel4 float data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT5_FL</name>
          <description>FIR channel 5 float point data input &amp;amp; output register</description>
          <addressOffset>0x114</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT5_FL</name>
              <description>FIR channel5 float data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT6_FL</name>
          <description>FIR channel 6 float point data input &amp;amp; output register</description>
          <addressOffset>0x118</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT6_FL</name>
              <description>FIR channel6 float data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT7_FL</name>
          <description>FIR channel 7 float point data input &amp;amp; output register</description>
          <addressOffset>0x11C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT7_FL</name>
              <description>FIR channel7 float data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>FIR_DAT8_FL</name>
          <description>FIR channel 8 float point data input &amp;amp; output register</description>
          <addressOffset>0x120</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>FIR_DAT8_FL</name>
              <description>FIR channel8 float data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIN_COS_IXOX</name>
          <description>sin &amp;amp; cos input fix output fix mode data address register</description>
          <addressOffset>0x140</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>SIN_COS_IXOX_SRC</name>
              <description>SIN_COS input data source address. Input fix output fix</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SIN_COS_IXOX_DST</name>
              <description>SIN_COS output data destination address. Input fix output fix.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIN_COS_IXOL</name>
          <description>sin &amp;amp; cos input fix output float mode data address register</description>
          <addressOffset>0x144</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>SIN_COS_IXOL_SRC</name>
              <description>SIN_COS input data source word address. Input fix output float</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SIN_COS_IXOL_DST</name>
              <description>SIN_COS output data destination word address. Input fix output float.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIN_COS_ILOX</name>
          <description>sin &amp;amp; cos input float output fix mode data address register</description>
          <addressOffset>0x148</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>SIN_COS_ILOX_SRC</name>
              <description>SIN_COS input data source word address. Input float output fix</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SIN_COS_ILOX_DST</name>
              <description>SIN_COS output data destination word address. Input float output fix.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIN_COS_ILOL</name>
          <description>sin &amp;amp; cos input float output float mode data address register</description>
          <addressOffset>0x14C</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>SIN_COS_ILOL_SRC</name>
              <description>SIN_COS input data source word address. Input float output float</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>SIN_COS_ILOL_DST</name>
              <description>SIN_COS output data destination word address. Input float output float</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LN_SQRT_IXOX</name>
          <description>LN &amp;amp; sqrt input fix output fix mode data address register</description>
          <addressOffset>0x150</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>LN_SQRT_IXOX_SRC</name>
              <description>LN_SQRT input data source word address. Input fix output fix</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>LN_SQRT_IXOX_DST</name>
              <description>LN_SQRT output data destination word address. Input fix output fix.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LN_SQRT_IXOL</name>
          <description>LN &amp;amp; sqrt input fix output float mode data address register</description>
          <addressOffset>0x154</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>LN_SQRT_IXOL_SRC</name>
              <description>LN_SQRT input data source word address. Input fix output float</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>LN_SQRT_IXOL_DST</name>
              <description>LN_SQRT output data destination word address. Input fix output float.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LN_SQRT_ILOX</name>
          <description>LN &amp;amp; sqrt input float output fix mode data address register</description>
          <addressOffset>0x158</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>LN_SQRT_ILOX_SRC</name>
              <description>LN_SQRT input data source word address. Input float output fix</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>LN_SQRT_ILOX_DST</name>
              <description>LN_SQRT output data destination word address. Input float output fix.</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>LN_SQRT_ILOL</name>
          <description>LN &amp;amp; sqrt input float output float mode data address register</description>
          <addressOffset>0x15C</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>LN_SQRT_ILOL_SRC</name>
              <description>LN_SQRT input data source word address. Input float output float</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>LN_SQRT_ILOL_DST</name>
              <description>LN_SQRT output data destination word address. Input float output float</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T0UP_IXOX</name>
          <description>native cordic input fix output fix, t=0, u=1 mode data address register</description>
          <addressOffset>0x160</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T0UP_IXOX_SRC</name>
              <description>CORDIC_T0UP_IXOX input data source word address. Input fix output fix</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T0UP_IXOX_DST</name>
              <description>CORDIC_T0UP_IXOX output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UP_IXOX_DST+1. Input fix output fix</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T0UP_IXOL</name>
          <description>native cordic input fix output float, t=0, u=1 mode data address register</description>
          <addressOffset>0x164</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T0UP_IXOL_SRC</name>
              <description>CORDIC_T0UP_IXOL input data source word address. Input fix output float</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T0UP_IXOL_DST</name>
              <description>CORDIC_T0UP_IXOL output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UP_IXOL_DST+1. Input fix output float</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T0UP_ILOX</name>
          <description>native cordic input float output fix, t=0, u=1 mode data address register</description>
          <addressOffset>0x168</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T0UP_ILOX_SRC</name>
              <description>CORDIC_T0UP_ILOX input data source word address. Input float output fix</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T0UP_ILOX_DST</name>
              <description>CORDIC_T0UP_ILOX output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UP_ILOX_DST+1. Input float output fix</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T0UP_ILOL</name>
          <description>native cordic input float output float, t=0, u=1 mode data address register</description>
          <addressOffset>0x16C</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T0UP_ILOL_SRC</name>
              <description>CORDIC_T0UN_ILOL input data source word address. Input float output float</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T0UP_ILOL_DST</name>
              <description>CORDIC_T0UN_ILOL output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UN_ILOL_DST+1. Input float output float</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T0UN_IXOX</name>
          <description>native cordic input fix output fix, t=0, u=-1 mode data address register</description>
          <addressOffset>0x170</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T0UN_IXOX_SRC</name>
              <description>CORDIC_T0UN_IXOX input data source word address. Input fix output fix</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T0UN_IXOX_DST</name>
              <description>CORDIC_T0UN_IXOX output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UN_IXOX_DST+1. Input fix output fix</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T0UN_IXOL</name>
          <description>native cordic input fix output float, t=0, u=-1 mode data address register</description>
          <addressOffset>0x174</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T0UN_IXOL_SRC</name>
              <description>CORDIC_T0UN_IXOL input data source word address. Input fix output float</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T0UN_IXOL_DST</name>
              <description>CORDIC_T0UN_IXOL output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UN_IXOL_DST+1. Input fix output float</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T0UN_ILOX</name>
          <description>native cordic input float output fix, t=0, u=-1 mode data address register</description>
          <addressOffset>0x178</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T0UN_ILOX_SRC</name>
              <description>CORDIC_T0UN_ILOX input data source word address. Input float output fix</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T0UN_ILOX_DST</name>
              <description>CORDIC_T0UN_ILOX output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UN_ILOX_DST+1. Input float output fix</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T0UN_ILOL</name>
          <description>native cordic input float output float, t=0, u=-1 mode data address register</description>
          <addressOffset>0x17C</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T0UN_ILOL_SRC</name>
              <description>CORDIC_T0UN_ILOL input data source word address. Input float output float</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T0UN_ILOL_DST</name>
              <description>CORDIC_T0UN_ILOL output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UN_ILOL_DST+1. Input float output float</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T1UP_IXOX</name>
          <description>native cordic input fix output fix, t=1, u=1 mode data address register</description>
          <addressOffset>0x180</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T1UP_IXOX_SRC</name>
              <description>CORDIC_T1UP_IXOX input data source word address. Input fix output fix</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T1UP_IXOX_DST</name>
              <description>CORDIC_T1UP_IXOX output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UP_IXOX_DST+1. Input fix output fix</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T1UP_IXOL</name>
          <description>native cordic input fix output float, t=1, u=1 mode data address register</description>
          <addressOffset>0x184</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T1UP_IXOL_SRC</name>
              <description>CORDIC_T1UP_IXOL input data source word address. Input fix output float</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T1UP_IXOL_DST</name>
              <description>CORDIC_T1UP_IXOL output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UP_IXOL_DST+1. Input fix output float</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T1UP_ILOX</name>
          <description>native cordic input float output fix, t=1, u=1 mode data address register</description>
          <addressOffset>0x188</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T1UP_ILOX_SRC</name>
              <description>CORDIC_T1UP_ILOX input data source word address. Input float output fix</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T1UP_ILOX_DST</name>
              <description>CORDIC_T1UP_ILOX output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UP_ILOX_DST+1. Input float output fix</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T1UP_ILOL</name>
          <description>native cordic input float output float, t=1, u=1 mode data address register</description>
          <addressOffset>0x18C</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T1UP_ILOL_SRC</name>
              <description>CORDIC_T1UP_ILOL input data source word address. Input float output float</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T1UP_ILOL_DST</name>
              <description>CORDIC_T1UP_ILOL output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UP_ILOL_DST+1. Input float output float</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T1UN_IXOX</name>
          <description>native cordic input fix output fix, t=1, u=-1 mode data address register</description>
          <addressOffset>0x190</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T1UN_IXOX_SRC</name>
              <description>CORDIC_T1UN_IXOX input data source word address. Input fix output fix</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T1UN_IXOX_DST</name>
              <description>CORDIC_T1UN_IXOX output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UN_IXOX_DST+1. Input fix output fix</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T1UN_IXOL</name>
          <description>native cordic input fix output float, t=1, u=-1 mode data address register</description>
          <addressOffset>0x194</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T1UN_IXOL_SRC</name>
              <description>CORDIC_T1UN_IXOL input data source word address. Input fix output float</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T1UN_IXOL_DST</name>
              <description>CORDIC_T1UN_IXOL output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UN_IXOL_DST+1. Input fix output float</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T1UN_ILOX</name>
          <description>native cordic input float output fix, t=1, u=-1 mode data address register</description>
          <addressOffset>0x198</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T1UN_ILOX_SRC</name>
              <description>CORDIC_T1UN_ILOX input data source word address. Input float output fix</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T1UN_ILOX_DST</name>
              <description>CORDIC_T1UN_ILOX output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UN_ILOX_DST+1. Input float output fix</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>CORDIC_T1UN_ILOL</name>
          <description>native cordic input float output float, t=1, u=-1 mode data address register</description>
          <addressOffset>0x19C</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CORDIC_T1UN_ILOL_SRC</name>
              <description>CORDIC_T1UN_ILOL input data source word address. Input float output float</description>
              <bitOffset>0</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
            <field>
              <name>CORDIC_T1UN_ILOL_DST</name>
              <description>CORDIC_T1UN_ILOL output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UN_ILOL_DST+1. Input float output float</description>
              <bitOffset>16</bitOffset>
              <bitWidth>16</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>GPIOA</name>
      <description>gpio</description>
      <groupName>GPIO</groupName>
      <headerStructName>GPIO</headerStructName>
      <baseAddress>0x4008C000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x3C</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>DATA</name>
          <description>GPIO value register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATA</name>
              <description>data value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>DATAOUT</name>
          <description>GPIO output status register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>DATAOUT</name>
              <description>Data output register value</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUTENSET</name>
          <description>GPIO output enable set register</description>
          <addressOffset>0x10</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>OUTENSET</name>
              <description>output enable clear</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>OUTENCLR</name>
          <description>GPIO output clear register</description>
          <addressOffset>0x14</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>OUTENCLR</name>
              <description>output enable clear</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENSET</name>
          <description>GPIO interrupt enable set register</description>
          <addressOffset>0x20</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>INTENSET</name>
              <description>interrupt enable set</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTENCLR</name>
          <description>GPIO interrupt enable clear register</description>
          <addressOffset>0x24</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>INTENCLR</name>
              <description>interrupt enable clear</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTTYPESET</name>
          <description>GPIO interrupt type set register</description>
          <addressOffset>0x28</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>INTTYPESET</name>
              <description>interrupt type set</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTTYPECLR</name>
          <description>GPIO interrupt type set register</description>
          <addressOffset>0x2C</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>INTTYPECLR</name>
              <description>interrupt type clear</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTPOLSET</name>
          <description>GPIO interrupt polarity set register</description>
          <addressOffset>0x30</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>INTPOLSET</name>
              <description>interrupt polarity set</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>INTPOLCLR</name>
          <description>GPIO interrupt polarity clear register</description>
          <addressOffset>0x34</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>INTPOLCLR</name>
              <description>interrupt polarity clear</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
          </fields>
        </register>
        <register>
          <name>INTSTATUS</name>
          <description>GPIO interrupt status register</description>
          <addressOffset>0x38</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>INTSTATUS</name>
              <description>interrupt status</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
              <modifiedWriteValues>oneToClear</modifiedWriteValues>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral derivedFrom="GPIOA">
      <name>GPIOB</name>
      <description>gpio</description>
      <groupName>GPIO</groupName>
      <baseAddress>0x4008D000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x3C</size>
        <usage>registers</usage>
      </addressBlock>
    </peripheral>
    <peripheral>
      <name>CRC_ENGINE</name>
      <description>crc</description>
      <groupName>CRC</groupName>
      <baseAddress>0x4008E000</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0xC</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>MODE</name>
          <description>CRC mode register</description>
          <addressOffset>0</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0x3F</resetMask>
          <fields>
            <field>
              <name>CRC_POLY</name>
              <description>CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial</description>
              <bitOffset>0</bitOffset>
              <bitWidth>2</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIT_RVS_WR</name>
              <description>Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CMPL_WR</name>
              <description>Data complement: 1 = 1'-s complement for CRC_WR_DATA 0 = No 1'-s complement for CRC_WR_DATA</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>BIT_RVS_SUM</name>
              <description>CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
            <field>
              <name>CMPL_SUM</name>
              <description>CRC sum complement: 1 = 1'-s complement for CRC_SUM 0 = No 1'-s complement for CRC_SUM</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SEED</name>
          <description>CRC seed register</description>
          <addressOffset>0x4</addressOffset>
          <size>32</size>
          <access>read-write</access>
          <resetValue>0xFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CRC_SEED</name>
              <description>A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1'-s complement pre-processes. A write access to this register will overrule the CRC calculation in progresses.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SUM</name>
          <description>CRC checksum register</description>
          <alternateGroup>SUM_WR_DATA</alternateGroup>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>read-only</access>
          <resetValue>0xFFFF</resetValue>
          <resetMask>0xFFFFFFFF</resetMask>
          <fields>
            <field>
              <name>CRC_SUM</name>
              <description>The most recent CRC sum can be read through this register with selected bit order and 1'-s complement post-processes.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>WR_DATA</name>
          <description>CRC data register</description>
          <alternateGroup>SUM_WR_DATA</alternateGroup>
          <addressOffset>0x8</addressOffset>
          <size>32</size>
          <access>write-only</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CRC_WR_DATA</name>
              <description>Data written to this register will be taken to perform CRC calculation with selected bit order and 1'-s complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.</description>
              <bitOffset>0</bitOffset>
              <bitWidth>32</bitWidth>
              <access>write-only</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
  </peripherals>
</device>