nxp.com QN908XC 1.0 QN9080C, QN9083C CM4 r0p1 little true true true 3 false 8 32 SYSCON syscon SYSCON 0x40000000 0 0x894 registers RST_SW_SET block software reset set register 0 32 read-write 0x7E5FFFFF 0xFE5FFFFF SET_FC0_RST Write 1 to set FLEXCOMM0 reset 0 1 write-only SET_FC1_RST Write 1 to set FLEXCOMM1 reset 1 1 write-only SET_FC2_RST Write 1 to set FLEXCOMM2 reset 2 1 write-only SET_FC3_RST Write 1 to set FLEXCOMM3 reset 3 1 write-only SET_TIM0_RST Write 1 to set CTIMER0 reset 4 1 write-only SET_TIM1_RST Write 1 to set CTIMER1 reset 5 1 write-only SET_TIM2_RST Write 1 to set CTIMER2 reset 6 1 write-only SET_TIM3_RST Write 1 to set CTIMER3 reset 7 1 write-only SET_SCT_RST Write 1 to set SCT reset 8 1 write-only SET_WDT_RST Write 1 to set Watch Dog reset 9 1 write-only SET_USB_RST Write 1 to set USB reset 10 1 write-only SET_GPIO_RST Write 1 to set GPIO reset 11 1 write-only SET_RTC_RST Write 1 to set RTC reset 12 1 write-only SET_ADC_RST Write 1 to set ADC interface reset 13 1 write-only SET_DAC_RST Write 1 to set DAC interface reset 14 1 write-only SET_CS_RST Write 1 to set Cap sensor interface reset 15 1 write-only SET_FSP_RST Write 1 to set FSP reset 16 1 write-only SET_DMA_RST Write 1 to set DMA reset 17 1 write-only SET_QDEC0_RST Write 1 to set QDEC 0 reset 19 1 write-only SET_QDEC1_RST Write 1 to set QDEC 1 reset 20 1 write-only SET_SPIFI_RST Write 1 to set SPIFI reset 22 1 write-only SET_CPU_RST Write 1 to set CPU reset 26 1 write-only SET_BLE_RST Write 1 to set BLE reset 27 1 write-only SET_FLASH_RST Write 1 to set flash controller reset 28 1 write-only SET_DP_RST Write 1 to set DataPath reset 29 1 write-only SET_REG_RST Write 1 to reset retention register 30 1 write-only SET_REBOOT Write 1 to Reboot entire system 31 1 write-only RST_SW_CLR block software reset clear register 0x4 32 read-write 0x7E5FFFFF 0x7E5FFFFF CLR_FC0_RST Write 1 to clear FLEXCOMM0 reset 0 1 read-write oneToClear CLR_FC1_RST Write 1 to clear FLEXCOMM1 reset 1 1 read-write oneToClear CLR_FC2_RST Write 1 to clear FLEXCOMM2 reset 2 1 read-write oneToClear CLR_FC3_RST Write 1 to clear FLEXCOMM3 reset 3 1 read-write oneToClear CLR_TIM0_RST Write 1 to clear CTIMER0 reset 4 1 read-write oneToClear CLR_TIM1_RST Write 1 to clear CTIMER1 reset 5 1 read-write oneToClear CLR_TIM2_RST Write 1 to clear CTIMER2 reset 6 1 read-write oneToClear CLR_TIM3_RST Write 1 to clear CTIMER3 reset 7 1 read-write oneToClear CLR_SCT_RST Write 1 to clear SCT reset 8 1 read-write oneToClear CLR_WDT_RST Write 1 to clear Watch Dog reset 9 1 read-write oneToClear CLR_USB_RST Write 1 to clear USB reset 10 1 read-write oneToClear CLR_GPIO_RST Write 1 to clear GPIO reset 11 1 read-write oneToClear CLR_RTC_RST Write 1 to clear RTC reset 12 1 read-write oneToClear CLR_ADC_RST Write 1 to clear ADC interface reset 13 1 read-write oneToClear CLR_DAC_RST Write 1 to clear DAC interface reset 14 1 read-write oneToClear CLR_CS_RST Write 1 to clear cap sensor interface reset 15 1 read-write oneToClear CLR_FSP_RST Write 1 to clear FSP reset 16 1 read-write oneToClear CLR_DMA_RST Write 1 to clear DMA reset 17 1 read-write oneToClear CLR_QDEC0_RST Write 1 to clear QDEC 0 reset 19 1 read-write oneToClear CLR_QDEC1_RST Write 1 to clear QDEC 1 reset 20 1 read-write oneToClear CLR_SPIFI_RST Write 1 to clear SPIFI reset 22 1 read-write oneToClear CLR_CPU_RST Write 1 to clear CPU reset 26 1 read-write oneToClear CLR_BLE_RST Write 1 to clear BLE reset 27 1 read-write oneToClear CLR_FLASH_RST Write 1 to clear flash controller reset 28 1 read-write oneToClear CLR_DP_RST Write 1 to clear DataPath reset 29 1 read-write oneToClear CLR_REG_RST Write 1 to clear retention register reset 30 1 read-write oneToClear CLK_DIS clock disable register 0x8 32 read-write 0xC0001200 0xEA7FFFFF CLK_FC0_DIS Write 1 to disable FLEXCOMM0 clock 0 1 read-write oneToClear CLK_FC1_DIS Write 1 to disable FLEXCOMM1 clock 1 1 read-write oneToClear CLK_FC2_DIS Write 1 to disable FLEXCOMM2 clock 2 1 read-write oneToClear CLK_FC3_DIS Write 1 to disable FLEXCOMM3 clock 3 1 read-write oneToClear CLK_TIM0_DIS Write 1 to disable CTIMER0 clock 4 1 read-write oneToClear CLK_TIM1_DIS Write 1 to disable CTIMER1 clock 5 1 read-write oneToClear CLK_TIM2_DIS Write 1 to disable CTIMER2 clock 6 1 read-write oneToClear CLK_TIM3_DIS Write 1 to disable CTIMER3 clock 7 1 read-write oneToClear CLK_SCT_DIS Write 1 to disable SCT clock 8 1 read-write oneToClear CLK_WDT_DIS Write 1 to disable Watch Dog clock 9 1 read-write oneToClear CLK_USB_DIS Write 1 to disable USB clock; 10 1 read-write oneToClear CLK_GPIO_DIS Write 1 to disable GPIO clock 11 1 read-write oneToClear CLK_BIV_DIS Write 1 to disable BIV APB clock include RTC BiV register. 12 1 read-write oneToClear CLK_ADC_DIS Write 1 to disable ADC clock; 13 1 read-write oneToClear CLK_DAC_DIS Write 1 to disable DAC clock; 14 1 read-write oneToClear CLK_CS_DIS Write 1 to disable Cap sensor clock; 15 1 read-write oneToClear CLK_FSP_DIS Write 1 to disable FSP clock; 16 1 read-write oneToClear CLK_DMA_DIS Write 1 to disable DMA clock 17 1 read-write oneToClear CLK_QDEC0_DIS Write 1 to disable QDEC0 clock; 19 1 read-write oneToClear CLK_QDEC1_DIS Write 1 to disable QDEC1 clock; 20 1 read-write oneToClear CLK_DP_DIS Write 1 to disable Data Path 16/8MHz clock; 21 1 read-write oneToClear CLK_SPIFI_DIS Write 1 to disable SPIFI clock; 22 1 read-write oneToClear CLK_CAL_DIS Write 1 to disable Calibration clock; 25 1 read-write oneToClear CLK_BLE_DIS Write 1 to disable BLE clock 27 1 read-write oneToClear PCLK_DIS Write 1 to disable PCLK of some logic; 30 1 read-write oneToClear FCLK_DIS Write 1 to disable CPU FCLK; 31 1 read-write oneToClear CLK_EN clock enable register 0xC 32 read-write 0xC0001200 0xEA7FFFFF CLK_FC0_EN Write 1 to enable FLEXCOMM0 clock 0 1 write-only CLK_FC1_EN Write 1 to enable FLEXCOMM1 clock 1 1 write-only CLK_FC2_EN Write 1 to enable FLEXCOMM2 clock 2 1 write-only CLK_FC3_EN Write 1 to enable FLEXCOMM3 clock 3 1 write-only CLK_TIM0_EN Write 1 to enable CTIMER0 clock 4 1 write-only CLK_TIM1_EN Write 1 to enable CTIMER1 clock 5 1 write-only CLK_TIM2_EN Write 1 to enable CTIMER2 clock 6 1 write-only CLK_TIM3_EN Write 1 to enable CTIMER3 clock 7 1 write-only CLK_SCT_EN Write 1 to enable SCT clock 8 1 write-only CLK_WDT_EN Write 1 to enable Watch Dog clock 9 1 write-only CLK_USB_EN Write 1 to enable USB clock; 10 1 write-only CLK_GPIO_EN Write 1 to enable GPIO clock 11 1 write-only CLK_BIV_EN Write 1 to enable BIV APB clock include RTC BiV register. 12 1 write-only CLK_ADC_EN Write 1 to enable ADC clock; 13 1 write-only CLK_DAC_EN Write 1 to enable DAC clock; 14 1 write-only CLK_CS_EN Write 1 to enable Cap sensor clock; 15 1 write-only CLK_FSP_EN Write 1 to enable FSP clock; 16 1 write-only CLK_DMA_EN Write 1 to enable DMA clock 17 1 write-only CLK_QDEC0_EN Write 1 to enable QDEC0 clock; 19 1 write-only CLK_QDEC1_EN Write 1 to enable QDEC1 clock; 20 1 write-only CLK_DP_EN Write 1 to enable Data Path 16/8MHz clock; 21 1 write-only CLK_SPIFI_EN Write 1 to enable SPIFI clock; 22 1 write-only CLK_CAL_EN Write 1 to enable Calibration clock; 25 1 write-only CLK_BLE_EN Write 1 to enable BLE clock 27 1 write-only CLK_CTRL system clock source and divider register 0x10 32 read-write 0x103C0000 0xDFFFFFFF APB_DIV APB_CLK = AHB_CLK/(APB_DIV+1) 0 4 read-write AHB_DIV AHB_CLK = SYS_CLK / (AHB_DIV+1);Note Before enable BLE clock (CLK_BLE_EN =1) It is mandatory to set AHB_CLK = 32 or 16 or 8 MHz. 4 13 read-write CLK_BLE_SEL BLE frequency indicator 17 1 read-write CLK_BLE_SEL_8M BLE run at 8M 0 CLK_BLE_SEL_16M BLE run at 16M 0x1 CLK_WDT_SEL Select Watch Dog clock 18 1 read-write CLK_WDT_SEL_32K watch dog run at 32K 0 APB watch dog run at APB clock 0x1 CLK_XTAL_SEL Crytal clock selection 19 1 read-write XTAL16M external crystal is 16M 0 XTAL32M external crystal is 32M 0x1 CLK_OSC32M_DIV digital OSC clock input selection 20 1 read-write BY1 use original 32M RCO clock 0 BY2 divide 32M OSC clock into 16M 0x1 CLK_32K_SEL 32K clock source selection 21 1 read-write XTAL32K digital 32K clock source is external 32K crystal 0 RCO32K digital 32K clock source is internal 32K RCO 0x1 CLK_XTAL_OE system clock output enable 22 1 read-write CLK_32K_OE 32K clock output enable 23 1 read-write XTAL_OUT_DIV high frequency xtal clock output divider 24 4 read-write CGBYPASS If it is 0, it can save CPU power in active mode 28 1 read-write SYS_CLK_SEL Select SYS_CLK source 30 2 read-write CLK_OSC 32M internal clock 0 CLK_XTAL external crystal clock 0x1 CLK_32K 32K clock 0x2 SYS_MODE_CTRL system mode and address remap register 0x14 32 read-write 0 0xFF000007 REMAP software remap system address 0 2 read-write ROM address 0 is mapped to ROM 0 FLASH address 0 is mapped to FLASH 0x1 RAM address 0 is mapped to RAM 0x2 LOCKUP_EN lock up enable 2 1 read-write XTAL_RDY 16/32 MHz xtal ready readout 25 1 read-only XTAL32K_RDY 32KHz xtal ready readout 26 1 read-only PLL48M_RDY 48MHz PLL ready readout 27 1 read-only OSC32M_RDY 32MHz oscillator ready readout 28 1 read-only BG_RDY BG ready readout 29 1 read-only BOOT_MODE boot mode pin status 31 1 read-only ISP when BOOT_MODE pin is 0, bootloader enter ISP 0 NORMAL when BOOT_MODE pin is 1, bootloader jump to flash without ISP 0x1 SYS_STAT system status register 0x80 32 read-only 0x3000 0xB0037FFF FREQ_WORD BLE Frequency word; 0 8 read-only BLE_FREQ_HOP BLE frequency word change flag; 8 1 read-only EVENT_IN_PROCESS BLE event indicator 9 1 read-only BLE_NONE_ENV BLE is not in event process 0 BLE_IN_ENV BLE is in event process 0x1 RX_EN when 1, system is in RX state 10 1 read-only TX_EN when 1, system is in TX state 11 1 read-only OSC_EN BLE osc_en output; 12 1 read-only RADIO_EN BLE radio_en output; 13 1 read-only CLK_STATUS BLE status 14 1 read-only BLE_IP_ACT BLE is active 0 BLE_IP_SLP BLE is in sleep mode 0x1 SYS_TICK systick timer control register 0x100 32 read-write 0x81000147 0x83FFFFFF TENMS system tick timer calibration value 0 24 read-write SKEW whether THE TENMS value will generate a precise 10 millisencod time or an approximation 24 1 read-write PRECISE TENMS is considered to be precise 0 NOT_PRECISE TENMS is not considered to be precise 0x1 NOREF whether an external reference clock is available 25 1 read-write AVAILABLE external reference clock is available 0 NOT_AVAILABLE external reference clock is not available 0x1 EN_STCLKEN 1 is enable STCLKEN; 31 1 read-write SRAM_CTRL Exchange memory base address register 0x104 32 read-write 0x2400 0x7FFF EM_BASE_ADDR Exchange memory base address in system memory. Default value is 9K word. 0 15 read-write CHIP_ID chip id register 0x108 32 read-only 0xFC001010 0xFC00FFFF CID0 CHIP ID for manufacture fab 0 3 read-only CID1 CHIP ID for product family 3 3 read-only CID2 CHIP ID for minor revision 6 2 read-only CID3 CHIP ID for product ID 8 6 read-only QN9020 QN9020 0 QN9030 QN9030 0x1 QN9080 QN9080 0x2 CID4 CHIP ID for major revision 14 2 read-only A revision A 0 B revision B 0x1 C revision C 0x2 D revision D 0x3 MEM_OPTION memory bond indicator 26 1 read-only MEM_OPTION_64K chip memory size is 64K 0 MEM_OPTION_128K chip memory size is 128K 0x1 ADC_OPTION adc bond indicator 27 1 read-only LOW adc low resolution 0 HIGH adc high resolution 0x1 FLASH_OPTION flash bond indicator 28 1 read-only FLASH_OPTION_256K chip flash size is 256K 0 FLASH_OPTION_512K chip flash size is 512K 0x1 FPU_OPTION fpu bond indicator 29 1 read-only NONE fpu is not exist 0 EXIST fpu is exist 0x1 USB_OPTION usb bond indicator 30 1 read-only NONE chip doesnot have USB 0 EXIST chip has USB 0x1 FSP_OPTION fsp bond indicator 31 1 read-only NONE chip doesnot have FSP 0 EXIST chip has FSP 0x1 ANA_CTRL0 crystal and PA register 0x110 32 read-write 0x820007F 0xDFF000FF PA_POWER PA power control (all of below is minus data) 0 8 read-write PA_POWER_20DBM 20dBm 0x10 PA_POWER_18DBM 18dBm 0x12 PA_POWER_16DBM 16dBm 0x14 PA_POWER_14DBM 14dBm 0x19 PA_POWER_12DBM 12dBm 0x20 PA_POWER_10DBM 10dBm 0x28 PA_POWER_8DBM 8dBm 0x32 PA_POWER_6DBM 6dBm 0x40 PA_POWER_4DBM 4dBm 0x50 PA_POWER_2DBM 2dBm 0x65 PA_POWER_0DBM 0dBm 0x7F XTAL_AMP crystal amplitude set register 20 2 read-write XTAL_LOAD_CAP Register controlled load cap of the XTAL in normal modeLOAD_CAP=5pF+0.35pF*CSEL+5pF*XADD_C 22 6 read-write XTAL_EXTRA_CAP Add extra 16/32 MHz xtal load cap 28 1 read-write XTAL_MODE Injection mode of the XTAL 30 2 read-write XTAL High frequency crystal oscillator 0 DIG Inject digital clock 0x1 SINGLE Inject single-end sine-wave signal 0x2 DIFF inject differential sine-wave signal 0x3 XTAL_CTRL crystal control register 0x180 32 read-write 0x20200800 0xFF3F0FE0 XTAL_XCUR_BOOST_REG 1 to increase 16/32 MHz xtal current 5 1 read-write XTAL_BPXDLY Bypass the power up delay in the XTAL core. 6 1 read-write XTAL_BP_HYSRES_REG 1 to bypass the degeneration resistor in order to reduce the hysteresis voltage 7 1 read-write XTAL_XSMT_EN_REG 1 to use hysteresis buffer 8 1 read-write XTAL_XRDY_REG 1 to set xtal ready signal by register 9 1 read-write XTAL_XOUT_DIS_REG 1 not to send 16/32 MHz xtal clk out 10 1 read-write DIV_DIFF_CLK_DIG_DIS disable differential clock of digital 11 1 read-write XTAL_SU_CB_REG Register controlled load cap of the XTAL_B in speed up modeCB=2pF+0.35pF*SU_CB+5pF*XADD_C 16 6 read-write XTAL_SU_CA_REG Register controlled load cap of the XTAL_A in speed up modeCA=2pF+0.35pF*SU_CA+5pF*XADD_C 24 6 read-write XTAL_INV Inverse crystal clock 30 1 read-write XTAL_DIV Divide crystal clock when external crystal is 32M this bit should be configured into 1 otherwise 0. 31 1 read-write BUCK buck control register 0x184 32 read-write 0x302B03 0xFFFFFFFF BUCK_DRIVER_PART_EN 1 to short external inductor 0 1 read-write BUCK_IND_USE_EN 1 to turn on buck output stage gradually 1 1 read-write BUCK_ISEL buck current bias control 8 2 read-write BUCK_VREF_SEL buck current setting 10 2 read-write BUCK_VBG_SEL buck reference setting 12 2 read-write BUCK_TMOS buck constant on time control 16 5 read-write BUCK_IC frequency compensation versus BVDD variation 21 1 read-write FC_FRG flexcomm 0 and 1 clock divider register 0x200 32 read-write 0xFF00FF 0xFFFFFFFF FRG_DIV0 flexcomm0 clock generator, Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator. 0 8 read-write FRG_MULT0 flexcomm0 clock generator, Numerator of the fractional divider. MULT is equal to the programmed value 8 8 read-write FRG_DIV1 flexcomm1 clock generator, Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator. 16 8 read-write FRG_MULT1 flexcomm1 clock generator, Numerator of the fractional divider. MULT is equal to the programmed value 24 8 read-write PIO_PULL_CFG0 pad pull control register 0 0x800 32 read-write 0xAAAAAAAA 0xFFFFFFFF PA00_PULL PA00 pull control register 0 2 read-write PA01_PULL PA01 pull control register 2 2 read-write PA02_PULL PA02 pull control register 4 2 read-write PA03_PULL PA03 pull control register 6 2 read-write PA04_PULL PA04 pull control register 8 2 read-write PA05_PULL PA05 pull control register 10 2 read-write PA06_PULL PA06 pull control register 12 2 read-write PA07_PULL PA07 pull control register 14 2 read-write PA08_PULL PA08 pull control register 16 2 read-write PA09_PULL PA09 pull control register 18 2 read-write PA10_PULL PA10 pull control register 20 2 read-write PA11_PULL PA11 pull control register 22 2 read-write PA12_PULL PA12 pull control register 24 2 read-write PA13_PULL PA13 pull control register 26 2 read-write PA14_PULL PA14 pull control register 28 2 read-write PA15_PULL PA15 pull control register 30 2 read-write PIO_PULL_CFG1 pad pull control register 1 0x804 32 read-write 0xAAAAAAAA 0xFFFFFFFF PA16_PULL PA16 pull control register 0 2 read-write PA17_PULL PA17 pull control register 2 2 read-write PA18_PULL PA18 pull control register 4 2 read-write PA19_PULL PA19 pull control register 6 2 read-write PA20_PULL PA20 pull control register 8 2 read-write PA21_PULL PA21 pull control register 10 2 read-write PA22_PULL PA22 pull control register 12 2 read-write PA23_PULL PA23 pull control register 14 2 read-write PA24_PULL PA24 pull control register 16 2 read-write PA25_PULL PA25 pull control register 18 2 read-write PA26_PULL PA26 pull control register 20 2 read-write PA27_PULL PA27 pull control register 22 2 read-write PA28_PULL PA28 pull control register 24 2 read-write PA29_PULL PA29 pull control register 26 2 read-write PA30_PULL PA30 pull control register 28 2 read-write PA31_PULL PA31 pull control register 30 2 read-write PIO_PULL_CFG2 pad pull control register 2 0x808 32 read-write 0x2A 0xFFFFFFFF PB00_PULL PB00 pull control register 0 2 read-write PB01_PULL PB01 pull control register 2 2 read-write PB02_PULL PB02 pull control register 4 2 read-write IO_CAP io status capture register 0x80C 32 read-write 0 0 PIN_RETENTION Write 1 to capture pad output and output enable and the status will be saved in PIN_SLP_OEN0 PIN_SLP_OEN1 PIN_SLP_OUT0 and PIN_SLP_OUT1. 0 1 write-only PIO_DRV_CFG0 pad drive strength register 0 0x810 32 read-write 0 0xFFFFFFFF PA00_DRV PA00 drive strength register 0 1 read-write PA01_DRV PA01 drive strength register 1 1 read-write PA02_DRV PA02 drive strength register 2 1 read-write PA03_DRV PA03 drive strength register 3 1 read-write PA04_DRV PA04 drive strength register 4 1 read-write PA05_DRV PA05 drive strength register 5 1 read-write PA06_DRV PA06 drive strength register 6 1 read-write PA07_DRV PA07 drive strength register 7 1 read-write PA08_DRV PA08 drive strength register 8 1 read-write PA09_DRV PA09 drive strength register 9 1 read-write PA10_DRV PA10 drive strength register 10 1 read-write PA11_DRV PA11 drive strength register 11 1 read-write PA12_DRV PA12 drive strength register 12 1 read-write PA13_DRV PA13 drive strength register 13 1 read-write PA14_DRV PA14 drive strength register 14 1 read-write PA15_DRV PA15 drive strength register 15 1 read-write PA16_DRV PA16 drive strength register 16 1 read-write PA17_DRV PA17 drive strength register 17 1 read-write PA18_DRV PA18 drive strength register 18 1 read-write PA19_DRV PA19 drive strength register 19 1 read-write PA20_DRV PA20 drive strength register 20 1 read-write PA21_DRV PA21 drive strength register 21 1 read-write PA22_DRV PA22 drive strength register 22 1 read-write PA23_DRV PA23 drive strength register 23 1 read-write PA24_DRV PA24 drive strength register 24 1 read-write PA25_DRV PA25 drive strength register 25 1 read-write PA26_DRV PA26 drive strength register 26 1 read-write PA27_DRV PA27 drive strength register 27 1 read-write PA28_DRV PA28 drive strength register 28 1 read-write PA29_DRV PA29 drive strength register 29 1 read-write PA30_DRV PA30 drive strength register 30 1 read-write PA31_DRV PA31 drive strength register 31 1 read-write PIO_DRV_CFG1 pad drive strength register 1 0x814 32 read-write 0 0xFFFFFFFF PB00_DRV PB00 drive strengh register 0 1 read-write PB01_DRV PB01 drive strengh register 1 1 read-write PB02_DRV PB02 drive strengh register 2 1 read-write PIO_DRV_CFG2 pad drive extra register 0x818 32 read-write 0 0xFFFFFFFF PA06_DRV_EXTRA Write 1 to enable extra driven on PA06 6 1 read-write PA11_DRV_EXTRA Write 1 to enable extra driven on PA11 11 1 read-write PA19_DRV_EXTRA Write 1 to enable extra driven on PA19 19 1 read-write PA26_DRV_EXTRA Write 1 to enable extra driven on PA26 26 1 read-write PA27_DRV_EXTRA Write 1 to enable extra driven on PA27 27 1 read-write PIO_CFG_MISC pin misc control register 0x81C 32 read-write 0x3 0xFFFFFFFF PB00_AE Enable PB00 analog function 0 1 read-write PB01_AE Enable PB01 analog function 1 1 read-write PSYNC when 1, bypass first stage of synchronization of DMA pin trigger 15 1 read-write PB02_MODE chip mode pin function select 16 1 read-write BOOT_MODE PB02 is used as chip mode input 0 ANTENNA PB02 is used as antena output 0x1 TRX_EN_INV inverse TX_EN & RX_EN pin mux output polarity 18 1 read-write TRX_EN_POL inverse TX_EN & RX_EN pin mux output polarity 0 RFE_INV Inverse RFE polarity 19 1 read-write RFE_POL Inverse RFE polarity 0 PIO_WAKEUP_LVL0 pin wakeup polarity register 0 0x820 32 read-write 0 0xFFFFFFFF PA00_WAKEUP_LVL Control the wake up polarity of PA00 in sleep mode. 0: high level wakeup, 1: low level wakeup 0 1 read-write PA01_WAKEUP_LVL Control the wake up polarity of PA01 in sleep mode. 1 1 read-write PA02_WAKEUP_LVL Control the wake up polarity of PA02 in sleep mode. 2 1 read-write PA03_WAKEUP_LVL Control the wake up polarity of PA03 in sleep mode. 3 1 read-write PA04_WAKEUP_LVL Control the wake up polarity of PA04 in sleep mode. 4 1 read-write PA05_WAKEUP_LVL Control the wake up polarity of PA05 in sleep mode. 5 1 read-write PA06_WAKEUP_LVL Control the wake up polarity of PA06 in sleep mode. 6 1 read-write PA07_WAKEUP_LVL Control the wake up polarity of PA07 in sleep mode. 7 1 read-write PA08_WAKEUP_LVL Control the wake up polarity of PA08 in sleep mode. 8 1 read-write PA09_WAKEUP_LVL Control the wake up polarity of PA09 in sleep mode. 9 1 read-write PA10_WAKEUP_LVL Control the wake up polarity of PA10 in sleep mode. 10 1 read-write PA11_WAKEUP_LVL Control the wake up polarity of PA11 in sleep mode. 11 1 read-write PA12_WAKEUP_LVL Control the wake up polarity of PA12 in sleep mode. 12 1 read-write PA13_WAKEUP_LVL Control the wake up polarity of PA13 in sleep mode. 13 1 read-write PA14_WAKEUP_LVL Control the wake up polarity of PA14 in sleep mode. 14 1 read-write PA15_WAKEUP_LVL Control the wake up polarity of PA15 in sleep mode. 15 1 read-write PA16_WAKEUP_LVL Control the wake up polarity of PA16 in sleep mode. 16 1 read-write PA17_WAKEUP_LVL Control the wake up polarity of PA17 in sleep mode. 17 1 read-write PA18_WAKEUP_LVL Control the wake up polarity of PA18 in sleep mode. 18 1 read-write PA19_WAKEUP_LVL Control the wake up polarity of PA19 in sleep mode. 19 1 read-write PA20_WAKEUP_LVL Control the wake up polarity of PA20 in sleep mode. 20 1 read-write PA21_WAKEUP_LVL Control the wake up polarity of PA21 in sleep mode. 21 1 read-write PA22_WAKEUP_LVL Control the wake up polarity of PA22 in sleep mode. 22 1 read-write PA23_WAKEUP_LVL Control the wake up polarity of PA23 in sleep mode. 23 1 read-write PA24_WAKEUP_LVL Control the wake up polarity of PA24 in sleep mode. 24 1 read-write PA25_WAKEUP_LVL Control the wake up polarity of PA25 in sleep mode. 25 1 read-write PA26_WAKEUP_LVL Control the wake up polarity of PA26 in sleep mode. 26 1 read-write PA27_WAKEUP_LVL Control the wake up polarity of PA27 in sleep mode. 27 1 read-write PA28_WAKEUP_LVL Control the wake up polarity of PA28 in sleep mode. 28 1 read-write PA29_WAKEUP_LVL Control the wake up polarity of PA29 in sleep mode. 29 1 read-write PA30_WAKEUP_LVL Control the wake up polarity of PA30 in sleep mode. 30 1 read-write PA31_WAKEUP_LVL Control the wake up polarity of PA31 in sleep mode. 31 1 read-write PIO_WAKEUP_LVL1 pin wakeup polarity register 1 0x824 32 read-write 0 0x7 PB00_WAKEUP_LVL Control the wake up polarity of PB01 in sleep mode. 0 1 read-write PB01_WAKEUP_LVL Control the wake up polarity of PB02 in sleep mode. 1 1 read-write PB02_WAKEUP_LVL Control the wake up polarity of PB03 in sleep mode. 2 1 read-write PIO_IE_CFG0 pad input enable register 0 0x828 32 read-write 0xFFFFFFFF 0xFFFFFFFF PA00_IE PA00 digital input enable 0 1 read-write PA01_IE PA01 digital input enable 1 1 read-write PA02_IE PA02 digital input enable 2 1 read-write PA03_IE PA03 digital input enable 3 1 read-write PA04_IE PA04 digital input enable 4 1 read-write PA05_IE PA05 digital input enable 5 1 read-write PA06_IE PA06 digital input enable 6 1 read-write PA07_IE PA07 digital input enable 7 1 read-write PA08_IE PA08 digital input enable 8 1 read-write PA09_IE PA09 digital input enable 9 1 read-write PA10_IE PA10 digital input enable 10 1 read-write PA11_IE PA11 digital input enable 11 1 read-write PA12_IE PA12 digital input enable 12 1 read-write PA13_IE PA13 digital input enable 13 1 read-write PA14_IE PA14 digital input enable 14 1 read-write PA15_IE PA15 digital input enable 15 1 read-write PA16_IE PA16 digital input enable 16 1 read-write PA17_IE PA17 digital input enable 17 1 read-write PA18_IE PA18 digital input enable 18 1 read-write PA19_IE PA19 digital input enable 19 1 read-write PA20_IE PA20 digital input enable 20 1 read-write PA21_IE PA21 digital input enable 21 1 read-write PA22_IE PA22 digital input enable 22 1 read-write PA23_IE PA23 digital input enable 23 1 read-write PA24_IE PA24 digital input enable 24 1 read-write PA25_IE PA25 digital input enable 25 1 read-write PA26_IE PA26 digital input enable 26 1 read-write PA27_IE PA27 digital input enable 27 1 read-write PA28_IE PA28 digital input enable 28 1 read-write PA29_IE PA29 digital input enable 29 1 read-write PA30_IE PA30 digital input enable 30 1 read-write PA31_IE PA31 digital input enable 31 1 read-write PIO_IE_CFG1 pad input enable register 1 0x82C 32 read-write 0x7 0x7 PB00_IE PB00 digital input enable 0 1 read-write PB01_IE PB01 digital input enable 1 1 read-write BOOT_MODE_IE PB02 input enable 2 1 read-write PIO_FUNC_CFG0 pin mux control register 0 0x830 32 read-write 0 0xFFFFFFFF PA00_FUNC PA00 function control register 0 3 read-write PA01_FUNC PA01 function control register 4 3 read-write PA02_FUNC PA02 function control register 8 3 read-write PA03_FUNC PA03 function control register 12 3 read-write PA04_FUNC PA04 function control register 16 3 read-write PA05_FUNC PA05 function control register 20 3 read-write PA06_FUNC PA06 function control register 24 3 read-write PA07_FUNC PA07 function control register 28 3 read-write PIO_FUNC_CFG1 pin mux control register 1 0x834 32 read-write 0 0xFFFFFFFF PA08_FUNC PA08 function control register 0 3 read-write PA09_FUNC PA09 function control register 4 3 read-write PA10_FUNC PA10 function control register 8 3 read-write PA11_FUNC PA11 function control register 12 3 read-write PA12_FUNC PA12 function control register 16 3 read-write PA13_FUNC PA13 function control register 20 3 read-write PA14_FUNC PA14 function control register 24 3 read-write PA15_FUNC PA15 function control register 28 3 read-write PIO_FUNC_CFG2 pin mux control register 2 0x838 32 read-write 0 0xFFFFFFFF PA16_FUNC PA16 function control register 0 3 read-write PA17_FUNC PA17 function control register 4 3 read-write PA18_FUNC PA18 function control register 8 3 read-write PA19_FUNC PA19 function control register 12 3 read-write PA20_FUNC PA20 function control register 16 3 read-write PA21_FUNC PA21 function control register 20 3 read-write PA22_FUNC PA22 function control register 24 3 read-write PA23_FUNC PA23 function control register 28 3 read-write PIO_FUNC_CFG3 pin mux control register 3 0x83C 32 read-write 0 0xFFFFFFFF PA24_FUNC PA24 function control register 0 3 read-write PA25_FUNC PA25 function control register 4 3 read-write PA26_FUNC PA26 function control register 8 3 read-write PA27_FUNC PA27 function control register 12 3 read-write PA28_FUNC PA28 function control register 16 3 read-write PA29_FUNC PA29 function control register 20 3 read-write PA30_FUNC PA30 function control register 24 3 read-write PA31_FUNC PA31 function control register 28 3 read-write PIO_WAKEUP_EN0 pin function selection in power down mode register 0 0x840 32 read-write 0 0xFFFFFFFF PA00_WAKEUP_EN Control GPIOA[31-0] as Wakeup source. 0 1 read-write PA01_WAKEUP_EN no description available 1 1 read-write PA02_WAKEUP_EN no description available 2 1 read-write PA03_WAKEUP_EN no description available 3 1 read-write PA04_WAKEUP_EN no description available 4 1 read-write PA05_WAKEUP_EN no description available 5 1 read-write PA06_WAKEUP_EN no description available 6 1 read-write PA07_WAKEUP_EN no description available 7 1 read-write PA08_WAKEUP_EN no description available 8 1 read-write PA09_WAKEUP_EN no description available 9 1 read-write PA10_WAKEUP_EN no description available 10 1 read-write PA11_WAKEUP_EN no description available 11 1 read-write PA12_WAKEUP_EN no description available 12 1 read-write PA13_WAKEUP_EN no description available 13 1 read-write PA14_WAKEUP_EN no description available 14 1 read-write PA15_WAKEUP_EN no description available 15 1 read-write PA16_WAKEUP_EN no description available 16 1 read-write PA17_WAKEUP_EN no description available 17 1 read-write PA18_WAKEUP_EN no description available 18 1 read-write PA19_WAKEUP_EN no description available 19 1 read-write PA20_WAKEUP_EN no description available 20 1 read-write PA21_WAKEUP_EN no description available 21 1 read-write PA22_WAKEUP_EN no description available 22 1 read-write PA23_WAKEUP_EN no description available 23 1 read-write PA24_WAKEUP_EN no description available 24 1 read-write PA25_WAKEUP_EN no description available 25 1 read-write PA26_WAKEUP_EN no description available 26 1 read-write PA27_WAKEUP_EN no description available 27 1 read-write PA28_WAKEUP_EN no description available 28 1 read-write PA29_WAKEUP_EN no description available 29 1 read-write PA30_WAKEUP_EN no description available 30 1 read-write PA31_WAKEUP_EN no description available 31 1 read-write PIO_WAKEUP_EN1 pin function selection in power down mode register 1 0x844 32 read-write 0 0x830C0C37 PB00_WAKEUP_EN Control GPIOB as Wakeup source. 0 1 read-write PB01_WAKEUP_EN no description available 1 1 read-write PB02_WAKEUP_EN no description available 2 1 read-write PA04_32K_OE 32K clock output enable. When this bit is set to 1 PA04 will output 32k clock. At this time PIN_CTRL register is not effective to control this IO's function. 4 1 read-write PA05_XTAL_OE XTAL clock output enable. When this bit is set to 1 PA05 will output XTAL clock. At this time PIN_CTRL register is not effective to control this IO's function. 5 1 read-write PA10_32K_OE 32K clock output enable. When this bit is set to 1 PA10 (GPIO10) will output 32k clock. At this time PIN_CTRL register is not effective to control this IO's function. 10 1 read-write PA11_XTAL_OE XTAL clock output enable. When this bit is set to 1 PA11 will output XTAL clock. At this time PIN_CTRL register is not effective to control this IO's function. 11 1 read-write PA18_32K_OE 32K clock output enable. When this bit is set to 1 PA18 will output 32k clock. At this time PIN_CTRL register is not effective to control this IO's function. 18 1 read-write PA19_XTAL_OE XTAL clock output enable. When this bit is set to 1 PA19 will output XTAL clock. At this time PIN_CTRL register is not effective to control this IO's function. 19 1 read-write PA24_32K_OE 32K clock output enable. When this bit is set to 1 PA24 will output 32k clock. At this time PIN_CTRL register is not effective to control this IO's function. 24 1 read-write PA25_XTAL_OE XTAL clock output enable. When this bit is set to 1 PA25 will output XTAL clock. At this time PIN_CTRL register is not effective to control this IO's function. 25 1 read-write PDM_IO_SEL pin status selection in power down mode 31 1 read-write PIO_CAP_OE0 pin output enable status register 0 while captured by writing 1 to IO_CAP 0x848 32 read-only 0 0xFFFFFFFF PA00_CAP_OE PA00 output enable status captured by writing 1 to IO_CAP 0 1 read-only PA01_CAP_OE PA01 output enable status captured by writing 1 to IO_CAP 1 1 read-only PA02_CAP_OE PA02 output enable status captured by writing 1 to IO_CAP 2 1 read-only PA03_CAP_OE PA03 output enable status captured by writing 1 to IO_CAP 3 1 read-only PA04_CAP_OE PA04 output enable status captured by writing 1 to IO_CAP 4 1 read-only PA05_CAP_OE PA05 output enable status captured by writing 1 to IO_CAP 5 1 read-only PA06_CAP_OE PA06 output enable status captured by writing 1 to IO_CAP 6 1 read-only PA07_CAP_OE PA07 output enable status captured by writing 1 to IO_CAP 7 1 read-only PA08_CAP_OE PA08 output enable status captured by writing 1 to IO_CAP 8 1 read-only PA09_CAP_OE PA09 output enable status captured by writing 1 to IO_CAP 9 1 read-only PA10_CAP_OE PA10 output enable status captured by writing 1 to IO_CAP 10 1 read-only PA11_CAP_OE PA11 output enable status captured by writing 1 to IO_CAP 11 1 read-only PA12_CAP_OE PA12 output enable status captured by writing 1 to IO_CAP 12 1 read-only PA13_CAP_OE PA13 output enable status captured by writing 1 to IO_CAP 13 1 read-only PA14_CAP_OE PA14 output enable status captured by writing 1 to IO_CAP 14 1 read-only PA15_CAP_OE PA15 output enable status captured by writing 1 to IO_CAP 15 1 read-only PA16_CAP_OE PA16 output enable status captured by writing 1 to IO_CAP 16 1 read-only PA17_CAP_OE PA17 output enable status captured by writing 1 to IO_CAP 17 1 read-only PA18_CAP_OE PA18 output enable status captured by writing 1 to IO_CAP 18 1 read-only PA19_CAP_OE PA19 output enable status captured by writing 1 to IO_CAP 19 1 read-only PA20_CAP_OE PA20 output enable status captured by writing 1 to IO_CAP 20 1 read-only PA21_CAP_OE PA21 output enable status captured by writing 1 to IO_CAP 21 1 read-only PA22_CAP_OE PA22 output enable status captured by writing 1 to IO_CAP 22 1 read-only PA23_CAP_OE PA23 output enable status captured by writing 1 to IO_CAP 23 1 read-only PA24_CAP_OE PA24 output enable status captured by writing 1 to IO_CAP 24 1 read-only PA25_CAP_OE PA25 output enable status captured by writing 1 to IO_CAP 25 1 read-only PA26_CAP_OE PA26 output enable status captured by writing 1 to IO_CAP 26 1 read-only PA27_CAP_OE PA27 output enable status captured by writing 1 to IO_CAP 27 1 read-only PA28_CAP_OE PA28 output enable status captured by writing 1 to IO_CAP 28 1 read-only PA29_CAP_OE PA29 output enable status captured by writing 1 to IO_CAP 29 1 read-only PA30_CAP_OE PA30 output enable status captured by writing 1 to IO_CAP 30 1 read-only PA31_CAP_OE PA31 output enable status captured by writing 1 to IO_CAP 31 1 read-only PIO_CAP_OE1 pin output enable status register 1 while captured by writing 1 to IO_CAP 0x84C 32 read-only 0 0x7 PB00_CAP_OE PB00 output enable status captured by writing 1 to IO_CAP 0 1 read-only PB01_CAP_OE PB01 output enable status captured by writing 1 to IO_CAP 1 1 read-only PB02_CAP_OE PB02 output enable status captured by writing 1 to IO_CAP 2 1 read-only PIO_CAP_OUT0 pin output status register 0 while captured by writing 1 to IO_CAP 0x850 32 read-only 0 0xFFFFFFFF PA00_CAP_OUT PA00 output status captured by writing 1 to IO_CAP 0 1 read-only PA01_CAP_OUT PA01 output status captured by writing 1 to IO_CAP 1 1 read-only PA02_CAP_OUT PA02 output status captured by writing 1 to IO_CAP 2 1 read-only PA03_CAP_OUT PA03 output status captured by writing 1 to IO_CAP 3 1 read-only PA04_CAP_OUT PA04 output status captured by writing 1 to IO_CAP 4 1 read-only PA05_CAP_OUT PA05 output status captured by writing 1 to IO_CAP 5 1 read-only PA06_CAP_OUT PA06 output status captured by writing 1 to IO_CAP 6 1 read-only PA07_CAP_OUT PA07 output status captured by writing 1 to IO_CAP 7 1 read-only PA08_CAP_OUT PA08 output status captured by writing 1 to IO_CAP 8 1 read-only PA09_CAP_OUT PA09 output status captured by writing 1 to IO_CAP 9 1 read-only PA10_CAP_OUT PA10 output status captured by writing 1 to IO_CAP 10 1 read-only PA11_CAP_OUT PA11 output status captured by writing 1 to IO_CAP 11 1 read-only PA12_CAP_OUT PA12 output status captured by writing 1 to IO_CAP 12 1 read-only PA13_CAP_OUT PA13 output status captured by writing 1 to IO_CAP 13 1 read-only PA14_CAP_OUT PA14 output status captured by writing 1 to IO_CAP 14 1 read-only PA15_CAP_OUT PA15 output status captured by writing 1 to IO_CAP 15 1 read-only PA16_CAP_OUT PA16 output status captured by writing 1 to IO_CAP 16 1 read-only PA17_CAP_OUT PA17 output status captured by writing 1 to IO_CAP 17 1 read-only PA18_CAP_OUT PA18 output status captured by writing 1 to IO_CAP 18 1 read-only PA19_CAP_OUT PA19 output status captured by writing 1 to IO_CAP 19 1 read-only PA20_CAP_OUT PA20 output status captured by writing 1 to IO_CAP 20 1 read-only PA21_CAP_OUT PA21 output status captured by writing 1 to IO_CAP 21 1 read-only PA22_CAP_OUT PA22 output status captured by writing 1 to IO_CAP 22 1 read-only PA23_CAP_OUT PA23 output status captured by writing 1 to IO_CAP 23 1 read-only PA24_CAP_OUT PA24 output status captured by writing 1 to IO_CAP 24 1 read-only PA25_CAP_OUT PA25 output status captured by writing 1 to IO_CAP 25 1 read-only PA26_CAP_OUT PA26 output status captured by writing 1 to IO_CAP 26 1 read-only PA27_CAP_OUT PA27 output status captured by writing 1 to IO_CAP 27 1 read-only PA28_CAP_OUT PA28 output status captured by writing 1 to IO_CAP 28 1 read-only PA29_CAP_OUT PA29 output status captured by writing 1 to IO_CAP 29 1 read-only PA30_CAP_OUT PA30 output status captured by writing 1 to IO_CAP 30 1 read-only PA31_CAP_OUT PA31 output status captured by writing 1 to IO_CAP 31 1 read-only PIO_CAP_OUT1 pin output status register 0 while captured by writing 1 to IO_CAP 0x854 32 read-only 0 0x7 PB00_CAP_OUT PB00 output status while captured by writing 1 to IO_CAP 0 1 read-only PB01_CAP_OUT PB01 output status while captured by writing 1 to IO_CAP 1 1 read-only PB02_CAP_OUT PB02 output status while captured by writing 1 to IO_CAP 2 1 read-only RST_CAUSE_SRC reset source status register 0x858 32 read-write 0 0x1FF RESET_CAUSE reset source indicator. xxxxxxxx1b = Power-on Reset; xxxxxxx1xb = Brown-Down Reset; xxxxxx1xxb = External pin Reset; xxxxx1xxxb = Watch Dog Reset; xxxx1xxxxb = Lock Up Reset; xxx1xxxxxb = Reboot Reset; xx1000000b = CPU system Reset requirement; x10000000b = Wake Up reset 10000000b = CPU software Reset; 0 9 read-only RST_CAUSE_CLR Write '1' clear RESET_CAUSE bits; 31 1 write-only PMU_CTRL0 power management uinit control register 0 0x85C 32 read-write 0x80000000 0xFC1703FF MEM0_DIS power down sram memory block 0 0 1 read-write MEM1_DIS power down sram memory block 1 1 1 read-write MEM2_DIS power down sram memory block 2 2 1 read-write MEM3_DIS power down sram memory block 3 3 1 read-write MEM4_DIS power down sram memory block 4 4 1 read-write MEM5_DIS power down sram memory block 5 5 1 read-write MEM6_DIS power down sram memory block 6 6 1 read-write MEM7_DIS power down sram memory block 7 7 1 read-write MEM8_DIS power down sram memory block 8 8 1 read-write MEM9_DIS power down sram memory block 9 9 1 read-write BLE_DIS power down BLE 16 1 read-write FIR_DIS power down FIR buffer 17 1 read-write FSP_DIS power down FSP 18 1 read-write MCU_MODE power control of BG, V2I, VREG_A, VREG_D 20 1 read-write ANA_PWRON power on BG, V2I, VREG_A, VREG_D 0 ANA_PWROFF power off BG, V2I, VREG_A, VREG_D 0x1 OSC_INT_EN 1 to enable OSC_EN as interrupt and wakeup source 26 1 read-write RTC_SEC_WAKEUP_EN 1 to enable RTC interrupt as wakeup source 27 1 read-write WAKEUP_EN 1 to enable sleep wake up source 28 1 read-write PMU_EN 1 to enable chip power down mode 29 1 read-write RETENTION_EN 1 to enable all CPU registers to be retentioned in sleep mode 30 1 read-write BOND_EN 1 to enable FSP_BOND_EN bond option 31 1 read-write PMU_CTRL1 power management uinit control register 1 0x860 32 read-write 0xFF0 0xC30F0FFF RCO32K_DIS 1 to switch off 32K RCO power 0 1 read-write XTAL32K_DIS 1 to switch off 32K XTAL power 1 1 read-write XTAL_DIS 1 to switch off XTAL of digital power 2 1 read-write OSC32M_DIS 1 to switch off 32M OSC power 3 1 read-write USBPLL_DIS 1 to switch off USB 48M PLL power 4 1 read-write ADC_BUF_DIS 1 to switch off buffer in SD ADC 5 1 read-write ADC_BG_DIS 1 to switch off bandgap in SD ADC 6 1 read-write ADC_DIS 1 to switch off SD ADC 7 1 read-write ADC_VCM_DIS 1 to switch off VCM DRV in SD ADC 8 1 read-write ADC_VREF_DIS 1 to switch off VREF DRV in SD ADC 9 1 read-write DAC_DIS 1 to switch off DAC 10 1 read-write CAP_SEN_DIS 1 to switch off CAP_SEN 11 1 read-write BUCK_CTRL BUCK power control, 0x00 to power on, and 0x0F to power down 16 4 read-write RCO32K_PDM_DIS In sleep mode this bit ORs with DIS_RCO_32K to control the RCO 32K power 30 1 read-write XTAL32K_PDM_DIS In sleep mode this bit ORs with DIS_XTAL32K to control the XTAL32 power 31 1 read-write ANA_EN analog setting register 0x864 32 read-write 0 0xFF7FFF7F BOD_AMP_EN Enable the AMP of browned out detector 0 1 read-write BOD_EN Enable browned out detector 1 1 read-write BAT_MON_EN Enable battery monitor 2 1 read-write ACMP0_EN Enable comparator 0 3 1 read-write ACMP1_EN Enable comparator 1 4 1 read-write BOR_AMP_EN Enable the AMP of browned reset detector 5 1 read-write BOR_EN Enable browned reset detector 6 1 read-write ACMP0_REF acmp0 reference voltage selection, vref0=Acmp_vref*ACMP0_REF/16 8 4 read-write ACMP1_REF acmp1 reference voltage selection, vref1=Acmp_vref*ACMP1_REF/16 12 4 read-write ACMP0_HYST_EN Hysteresis enable of ACMP0 when 1 16 1 read-write ACMP1_HYST_EN Hysteresis enable of ACMP1 when 1 17 1 read-write ACMP_VREF_SEL Acmp_vref selection 18 1 read-write BOD_THR Browned-out detector threshold voltages, when VDD is lower than this voltage, BOD_OUT interrupt happens. And the detector has a hysteresis. 19 2 read-write BOD_THR0 trigger at 2.06V, with 295mV hysteresis 0 BOD_THR1 trigger at 2.45V, with 350mV hysteresis 0x1 BOD_THR2 trigger at 2.72V, with 388mV hysteresis 0x2 BOD_THR3 trigger at 3.04V, with 435mV hysteresis 0x3 BOR_THR Browned-out reset threshold voltages 21 2 read-write BOR_THR0 trigger at 1.5V 0 BOR_THR1 trigger at 1.85V 0x1 BOR_THR2 trigger at 2V 0x2 BOR_THR3 trigger at 2.3V 0x3 ACMP0_OUT Comparator 0 output. 24 1 read-only ACMP1_OUT Comparator 1 output. 25 1 read-only ACMP0_EDGE_SEL ACMP0 interrupt edge selection 26 2 read-write POSEDGE posedge 0 NEGEDGE negedge 0x1 BOTHEDGE both edge 0x2 ACMP1_EDGE_SEL ACMP1 interrupt edge selection 28 2 read-write ACMP0_INTEN 1 to enable ACMP0 interrupt 30 1 read-write ACMP1_INTEN 1 to enable ACMP1 interrupt 31 1 read-write XTAL32K_CTRL crystal 32K control register 0x868 32 read-write 0x3023 0x7FFF XTAL32K_ICTRL Xtal 32 gm cell current bias Y 0 6 read-write XTAL32K_INJ Xtal 32KHz clk injection mode1xb = external sine wave clock 6 2 read-write ONCHIP_OSC on-chip oscillator 0 EXT_DIG_CLK external digital clock 0x1 XTAL32K_LOAD_CAP load cap selection of xtal32 8 6 read-write XTAL32K_EXTRA_CAP add extra xtal32 load cap 14 1 read-write USB_CFG USB configuration register 0x86C 32 read-write 0x32 0x3B DPPUEN_B_PHY_POL drive high to inverse the polarity of the connection 0 1 read-write DPPUEN_B_PHY_SEL The control source selection for pull-up resistor 1 1 read-write BY_REG connection controlled by register 0 BY_USBCTRL connection controlled by USB controller 0x1 USB_VBUS USB connection voltage selection 3 1 read-write USB_PHYSTDBY 1 to enable USB_PHY in standby mode 4 1 read-write ON USB PHY power is on 0 OFF USB PHY power is off 0x1 USB_PHYSTDBY_WEN 1 to enable USB_PHYSTDBY control by register 5 1 read-write PMU_CTRL2 power management uinit control register 2 0x880 32 read-write 0x403FF0FF 0xF03FFFFF BG_PDM_DIS 1 to power down bandcap in power down mode 0 1 read-write V2I_PDM_DIS 1 to power down V2I in power down mode 1 1 read-write VREG_A_PDM_DIS 1 to power down VREG_A in power down mode 2 1 read-write VREG_D_PDM_DIS 1 to power down VREG_D in power down mode 3 1 read-write XTAL_PDM_DIS 1 to power down XTAL in power down mode 4 1 read-write OSC32M_PDM_DIS 1 to power down OSC32M in power down mode 5 1 read-write RFAGC_ON 1 to enable RFAGC 6 1 read-write RX_EN_SEL RX_EN width selection 7 1 read-write EX_NOISE exclude noise phase 0 IN_NOISE include noise phase 0x1 BG_DIS 1 to switch off bandcap power 8 1 read-write V2I_DIS 1 to switch off V2I power 9 1 read-write VREG_A_DIS 1 to switch off VREG_A power 10 1 read-write VREG_D_DIS 1 to switch off VREG_D power 11 1 read-write LO_DIS 1 to switch off LO power 12 1 read-write VCO_DIS 1 to switch off VCO power 13 1 read-write PA_PK_DIS 1 to switch off PA peek detector power 14 1 read-write PA_DIS 1 to switch off PA power 15 1 read-write LNA_DIS 1 to switch off LNA power 16 1 read-write MIXER_DIS 1 to switch off MIXER power 17 1 read-write PKDET_DIS 1 to switch off RRF and PPF peek detector power 18 1 read-write PPF_DIS 1 to switch off PPF power 19 1 read-write SAR_DIS 1 to switch off SAR ADC power 20 1 read-write RC_CAL_DIS 1 to switch off RCCAL power 21 1 read-write FLSH_DIS 1 to switch off flash power 29 1 read-write FLSH_PDM_DIS 1 to power down flash VDD25 in power down mode 30 1 read-write SEL_PD power control selection 31 1 read-write HW_PWR hardware control power 0 SW_PWR software control power 0x1 ANA_CTRL1 IVREF and DVREG setting register 0x884 32 read-write 0xE4D98000 0xFFFFFFFF VDD_PMU_SET_PDM Vdd_pmu while in power down 0 2 read-write VDD_PMU_SET Vdd_pmu while wakeup 2 2 read-write VDD_MEM_SET_PDM Vdd_mem while in power down mode 4 2 read-write VDD_MEM_SET Vdd_mem while wakeup 6 2 read-write VDD_PMU_SET_EXTRA extra high setting for vdd_pmu 8 1 read-write VDD_MEM_SET_EXTRA extra high setting for vdd_mem 9 1 read-write VDD_PMU_SET_ULTRA_LOW ultra low setting for vdd_pmu 10 1 read-write VDD_PMU_MEM_SW 1 to close the switch betwwen vdd_omu and vdd_mem 11 1 read-write IV_BG_SEL VBG voltage select- 12 4 read-write PDM_DIS_BUCK 1 to power off buck in power down mode 16 1 read-write BUCK_PD_CCM 0 buck in CCM mode 17 1 read-write BUCK_PD_DCM 0 buck in DCM mode 18 1 read-write IV_IREF_SEL Reference current select 19 2 read-write IV_VREG11_SET VREG11 setting 21 3 read-write XTAL32K_FORCE_RDY Xtal32k ready from register 24 1 read-write X32_SMT_EN 1 to enable schmidt trigger in xtal32 25 1 read-write BM_X32BUF Xtal 32 buffer current bias 26 2 read-write DVREG11_SET_DIG Vregd set 28 3 read-write BUCK_DPD ZC control select 31 1 read-write MISC MISC register 0x890 32 read-write 0x3000000 0x3000000 RCO_PWR_MODE RCO VDD selection 0 2 read-write RCO_PWR_HIGH The highest RCO VDD setting, RCO current 630nA 0 RCO_PWR_MIDDLE The middle RCO VDD setting, RCO current 350nA 0x2 RCO_PWR_LOW The lowest RCO VDD setting, RCO current 200nA 0x3 EN_SWD enable swd register when SWD is selected in PIO_FUNC_CTRL 16 1 read-write DISABLE disable SWD 0 ENABLE enable SWD 0x1 DIS_FLSH_POWER flash power disable 17 1 read-write ENABLE flash power is depend on the value DIS_FLSH of PMU_CTRL2 0 DISABLE flash power is off 0x1 DIS_USB_PULLUP USB pull resister connection 18 1 read-write CONNECT USB pull up resistor state depend on other 3 USB control register 0 DISCONNECT USB pull up resister is disconnected 0x1 DPPU_OPT_SEL pull up strength source. 0: from DPPU_OPT_POL, 1: from usb device 24 1 read-write RES1P2K 1.2kohm 0 RES2P3K 2.3kohm 0x1 DPPU_OPT_POL swap pull up strength value 25 1 read-write WDT wdog WDT 0x40001000 0 0x24 registers LOAD watch dog counter start value register 0 32 read-write 0xFFFF 0xFFFFFFFF LOAD Contain the value from which the counter is to decrement. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1. 0 32 read-write VALUE watch dog counter value register 0x4 32 read-write 0x1FFFFFFF 0xFFFFFFFF VALUE The current value of the decrementing counter. 0 32 read-write CTRL watch dog control register 0x8 32 read-write 0 0x3 INTEN Enable the interrupt event WDOGINT. Set HIGH to enable the counter and the interrupt and set LOW to disable the counter and interrupt. Reloads the counter from the value in WDOGLOAD when the interrupt is enabled, and was previously disabled. 0 1 read-write RESEN Enable watchdog reset output WDOGRES. Acts as a mask for the reset output. Set HIGH to enablethe reset and LOW to disable the reset. 1 1 read-write INT_CLR interrupt clear register 0xC 32 read-write 0 0x1 INTCLR A write of any value to the Register clears the watchdog interrupt and reloads the counter from the value in WDOGLOAD. 0 1 read-write INT_RAW raw interrupt status register 0x10 32 read-only 0 0x1 RAWINTSTAT Raw interrupt status from the counter 0 1 read-only MIS interrupt mask register 0x14 32 read-write 0 0x1 MASKINTSTAT Enabled interrupt status from the counter 0 1 read-write LOCK watch dog lock register 0x20 32 read-write 0 0xFFFFFFFF LOCK_31_0 Writing 0x1ACCE551to this register enables write access to all other registers. 0 32 read-write CTIMER0 timer CTIMER CTIMER 0x40002000 0 0x78 registers IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0 32 read-write 0 0xFF MR0INT Interrupt flag for match channel 0. 0 1 read-write MR1INT Interrupt flag for match channel 1. 1 1 read-write MR2INT Interrupt flag for match channel 2. 2 1 read-write MR3INT Interrupt flag for match channel 3. 3 1 read-write CR0INT Interrupt flag for capture channel 0 event. 4 1 read-write CR1INT Interrupt flag for capture channel 1 event. 5 1 read-write CR2INT Interrupt flag for capture channel 2 event. 6 1 read-write TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x4 32 read-write 0 0x3 CEN Counter enable. 0 1 read-write DISABLED Disabled.The counters are disabled. 0 ENABLED Enabled. The Timer Counter and Prescale Counter are enabled. 0x1 CRST Counter reset. 1 1 read-write DISABLED Disabled. Do nothing. 0 ENABLED Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. 0x1 TC Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. 0x8 32 read-write 0 0xFFFFFFFF TCVAL Timer counter value. 0 32 read-write PR Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. 0xC 32 read-write 0 0xFFFFFFFF PRVAL Prescale counter value. 0 32 read-write PC Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x10 32 read-write 0 0xFFFFFFFF PCVAL Prescale counter value. 0 32 read-write MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x14 32 read-write 0 0xFFF MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled. 0 1 read-write MR0R Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled. 1 1 read-write MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled. 2 1 read-write MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = disabled. 1 = enabled. 0 = disabled. 1 = enabled. 3 1 read-write MR1R Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled. 4 1 read-write MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled. 5 1 read-write MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled. 6 1 read-write MR2R Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled. 7 1 read-write MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled. 8 1 read-write MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled. 9 1 read-write MR3R Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled. 10 1 read-write MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled. 11 1 read-write 4 0x4 MR[%s] Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x18 32 read-write 0 0xFFFFFFFF MATCH Timer counter match value. 0 32 read-write CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x28 32 read-write 0 0xFFF CAP0RE Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 0 1 read-write CAP0FE Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 1 1 read-write CAP0I Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. 2 1 read-write CAP1RE Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 3 1 read-write CAP1FE Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 4 1 read-write CAP1I Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. 5 1 read-write CAP2RE Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 6 1 read-write CAP2FE Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled. 7 1 read-write CAP2I Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. 8 1 read-write 3 0x4 CR[%s] Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. 0x2C 32 read-only 0 0xFFFFFFFF CAP Timer counter capture value. 0 32 read-only EMR External Match Register. The EMR controls the match function and the external match pins. 0x3C 32 read-write 0 0xFFF EM0 External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 0 1 read-write EM1 External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1 1 read-write EM2 External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 2 1 read-write EM3 External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 3 1 read-write EMC0 External Match Control 0. Determines the functionality of External Match 0. 4 2 read-write DO_NOTHING Do Nothing. 0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. 6 2 read-write DO_NOTHING Do Nothing. 0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. 8 2 read-write DO_NOTHING Do Nothing. 0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. 10 2 read-write DO_NOTHING Do Nothing. 0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x70 32 read-write 0 0xFF CTMODE Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer'-s Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. 0 2 read-write TIMER Timer Mode. Incremented every rising APB bus clock edge. 0 COUNTER_RISING_EDGE Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 COUNTER_FALLING_EDGE Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 COUNTER_DUAL_EDGE Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CINSEL Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. 2 2 read-write CHANNEL_0 Channel 0. CAPn.0 for CT32Bn 0 CHANNEL_1 Channel 1. CAPn.1 for CT32Bn 0x1 CHANNEL_2 Channel 2. CAPn.2 for CT32Bn 0x2 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. 4 1 read-write SELCC Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. 5 3 read-write CHANNEL_0_RISING Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 0 CHANNEL_0_FALLING Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 0x1 CHANNEL_1_RISING Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 0x2 CHANNEL_1_FALLING Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 0x3 CHANNEL_2_RISING Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 0x4 CHANNEL_2_FALLING Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 0x5 PWMC PWM Control Register. The PWMCON enables PWM mode for the external match pins. 0x74 32 read-write 0 0xF PWMEN0 PWM mode enable for channel0. 0 1 read-write MATCH Match. CT32Bn_MAT0 is controlled by EM0. 0 PWM PWM. PWM mode is enabled for CT32Bn_MAT0. 0x1 PWMEN1 PWM mode enable for channel1. 1 1 read-write MATCH Match. CT32Bn_MAT01 is controlled by EM1. 0 PWM PWM. PWM mode is enabled for CT32Bn_MAT1. 0x1 PWMEN2 PWM mode enable for channel2. 2 1 read-write MATCH Match. CT32Bn_MAT2 is controlled by EM2. 0 PWM PWM. PWM mode is enabled for CT32Bn_MAT2. 0x1 PWMEN3 PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. 3 1 read-write MATCH Match. CT32Bn_MAT3 is controlled by EM3. 0 PWM PWM. PWM mode is enabled for CT132Bn_MAT3. 0x1 CTIMER1 timer CTIMER 0x40003000 0 0x78 registers CTIMER2 timer CTIMER 0x40004000 0 0x78 registers CTIMER3 timer CTIMER 0x40005000 0 0x78 registers PINT QN908X Pin interrupt and pattern match (PINT) PINT 0x40006000 0 0x34 registers ISEL Pin Interrupt Mode register 0 32 read-write 0 0xF PMODE Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive 0 4 read-write IENR Pin interrupt level or rising edge interrupt enable register 0x4 32 read-write 0 0xF ENRL Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. 0 4 read-write SIENR Pin interrupt level or rising edge interrupt set register 0x8 32 write-only 0 0xF SETENRL Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. 0 4 write-only CIENR Pin interrupt level (rising edge interrupt) clear register 0xC 32 write-only 0 0xF CENRL Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. 0 4 write-only IENF Pin interrupt active level or falling edge interrupt enable register 0x10 32 read-write 0 0xF ENAF Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. 0 4 read-write SIENF Pin interrupt active level or falling edge interrupt set register 0x14 32 write-only 0 0xF SETENAF Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. 0 4 write-only CIENF Pin interrupt active level or falling edge interrupt clear register 0x18 32 write-only 0 0xF CENAF Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. 0 4 write-only RISE Pin interrupt rising edge register 0x1C 32 read-write 0 0xF RDET Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. 0 4 read-write FALL Pin interrupt falling edge register 0x20 32 read-write 0 0xF FDET Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. 0 4 read-write IST Pin interrupt status register 0x24 32 read-write 0 0xF PSTAT Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). 0 4 read-write PMCTRL Pattern match interrupt control register 0x28 32 read-write 0 0xFF000003 SEL_PMATCH Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. 0 1 read-write PIN_INTERRUPT Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. 0 PATTERN_MATCH Pattern match. Interrupts are driven in response to pattern matches. 0x1 ENA_RXEV Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. 1 1 read-write DISABLED Disabled. RXEV output to the CPU is disabled. 0 ENABLED Enabled. RXEV output to the CPU is enabled. 0x1 PMAT This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. 24 8 read-write PMSRC Pattern match interrupt bit-slice source register 0x2C 32 read-write 0 0xFFFFFF00 SRC0 Selects the input source for bit slice 0 8 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. 0x7 SRC1 Selects the input source for bit slice 1 11 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. 0x7 SRC2 Selects the input source for bit slice 2 14 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. 0x7 SRC3 Selects the input source for bit slice 3 17 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. 0x7 SRC4 Selects the input source for bit slice 4 20 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. 0x7 SRC5 Selects the input source for bit slice 5 23 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. 0x7 SRC6 Selects the input source for bit slice 6 26 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. 0x7 SRC7 Selects the input source for bit slice 7 29 3 read-write INPUT0 Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. 0 INPUT1 Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. 0x1 INPUT2 Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. 0x2 INPUT3 Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. 0x3 INPUT4 Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. 0x4 INPUT5 Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. 0x5 INPUT6 Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. 0x6 INPUT7 Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. 0x7 PMCFG Pattern match interrupt bit slice configuration register 0x30 32 read-write 0 0xFFFFFF7F PROD_ENDPTS0 Determines whether slice 0 is an endpoint. 0 1 read-write NO_EFFECT No effect. Slice 0 is not an endpoint. 0 ENDPOINT endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS1 Determines whether slice 1 is an endpoint. 1 1 read-write NO_EFFECT No effect. Slice 1 is not an endpoint. 0 ENDPOINT endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS2 Determines whether slice 2 is an endpoint. 2 1 read-write NO_EFFECT No effect. Slice 2 is not an endpoint. 0 ENDPOINT endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS3 Determines whether slice 3 is an endpoint. 3 1 read-write NO_EFFECT No effect. Slice 3 is not an endpoint. 0 ENDPOINT endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS4 Determines whether slice 4 is an endpoint. 4 1 read-write NO_EFFECT No effect. Slice 4 is not an endpoint. 0 ENDPOINT endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS5 Determines whether slice 5 is an endpoint. 5 1 read-write NO_EFFECT No effect. Slice 5 is not an endpoint. 0 ENDPOINT endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. 0x1 PROD_ENDPTS6 Determines whether slice 6 is an endpoint. 6 1 read-write NO_EFFECT No effect. Slice 6 is not an endpoint. 0 ENDPOINT endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. 0x1 CFG0 Specifies the match contribution condition for bit slice 0. 8 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG1 Specifies the match contribution condition for bit slice 1. 11 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG2 Specifies the match contribution condition for bit slice 2. 14 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG3 Specifies the match contribution condition for bit slice 3. 17 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG4 Specifies the match contribution condition for bit slice 4. 20 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG5 Specifies the match contribution condition for bit slice 5. 23 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG6 Specifies the match contribution condition for bit slice 6. 26 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 CFG7 Specifies the match contribution condition for bit slice 7. 29 3 read-write CONSTANT_HIGH Constant HIGH. This bit slice always contributes to a product term match. 0 STICKY_RISING_EDGE Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x1 STICKY_FALLING_EDGE Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 STICKY_RISING_FALLING_EDGE Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 HIGH_LEVEL High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x4 LOW_LEVEL Low level. Match occurs when there is a low level on the specified input. 0x5 CONSTANT_ZERO Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 0x6 EVENT Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. 0x7 INPUTMUX dmamux INPUTMUX 0x40006200 0 0x810 registers 4 0x4 PINTSEL[%s] Pin interrupt select register 0 32 read-write 0 0xFFFFFFFF INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO1_31 correspond to numbers 0 to 63). 0 5 read-write 20 0x4 DMA_ITRIG_INMUX[%s] Trigger select register for DMA channel 0x200 32 read-write 0x1F 0xFFFFFFFF INP Trigger input number (decimal value) for DMA channel n (n = 0 to 21). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4 = Timer CT32B0 Match 0 5 = Timer CT32B0 Match 1 6 = Timer CT32B1 Match 0 7 = Timer CT32B2 Match 0 8 = Timer CT32B2 Match 1 9 = Timer CT32B3 Match 0 10 = Timer CT32B4 Match 0 11 = Timer CT32B4 Match 1 12 = Pin interrupt 0 13 = Pin interrupt 1 14 = Pin interrupt 2 15 = Pin interrupt 3 16 = DMA output trigger mux 0 17 = DMA output trigger mux 1 18 = DMA output trigger mux 2 19 = DMA output trigger mux 3 0 5 read-write 4 0x4 DMA_OTRIG_INMUX[%s] DMA output trigger selection to become DMA trigger 0x800 32 read-write 0x1F 0xFFFFFFFF INP DMA trigger output number (decimal value) for DMA channel n (n = 0 to 19). 0 5 read-write ADC adc ADC 0x40007000 0 0x100 registers CTRL ADC control register 0 32 read-write 0x1000 0x1FBCFF0F ENABLE ADC enable. Write 1 to Writing 1 before starting conversion and 0 to end conversion. 0 1 read-write CONV_MODE ADC conversion mode 1 1 read-write BURST burst conversion 0 SINGLE single conversion 0x1 SCAN_EN 1 to enable scan mode 2 1 read-write WCMP_EN 1 to enable window compare 3 1 read-write SW_START Software start ADC conversion write1 to trigger one time ADC conversion, no need clear. 7 1 write-only CLKSEL Sigma-Delta ADC clock select 8 5 read-write CLKSEL_31P25K 31P25K 0 CLKSEL_62P5K 62P5K 0x4 CLKSEL_125K 125K 0x8 CLKSEL_250K 250K 0xC CLKSEL_500K 500K 0x10 CLKSEL_1M 1M 0x14 CLKSEL_2M 2M 0x18 CLKSEL_32K 32K 0x1D SIG_INV_EN 1 to invert Signma-Delta input signal 13 1 read-write VREF_SEL Sigma-Delta ADC Reference source selection. 14 2 read-write INT_1P2V Internal vref 1.2V 0 EXT_DRV External VREF 0x1 EXT_NO_DRV Vext without driver 0x2 VCC VCC 0x3 CH_IDX_EN 1 to append channel index in data result to be used in scan mode 18 1 read-write DATA_FORMAT Data output format. When DATA_FORMAT ==0, When CH_IDX_EN ==0, the ADC_DATA[31:0] is adc data, signed data, 31 bit frac. When CH_IDX_EN ==1, the ADC_DATA[4:0] is channel output, {ADC_DATA[31:5],5'h0} is adc data, signed data, 31 bit frac. When DATA_FORMAT ==1, When CH_IDX_EN ==0, the ADC_DATA[22:0] is adc data, signed data, 22 bit frac. When CH_IDX_EN ==1, the ADC_DATA[31:27] is channel output, ADC_DATA[22:0] is adc data, signed data, 22 bit frac. 19 1 read-write VREFO_EN 1 to enable bandgap out-chip capacitor 20 1 read-write SRST_DIS 1 to disable adc reset. 21 1 read-write TRIGGER Adc start trigger. 0 to 31 PA00 to PA31; 32 to 34 GPIOB0 to GPIOB2; 35, software trigger; 36, rng trigger; 56 to 59, timer 0 to timer 3; 60 to 63 pwm 0 to pwm 3 23 6 read-write CH_SEL ADC channel selection register 0x4 32 read-write 0x1 0xFFFFFFFF CH_SEL In scan conversion mode, the channels with 1 set will be scanned, from LSB to MSB. In none scan conversion mode, only the first channel from LSB with 1 set will be converted. If all bits are set to 0, no ADC conversion will be started. 0 32 read-write CH_CFG ADC channel configuration register 0x8 32 read-write 0 0xFFFFFFFF CH_CFG whenCH_CONFIG[N] is 0, the N channelwill select the configure 0 option(seeregister SD_CONFIG0). whenCH_CONFIG[N] is 1, the N channelwill select the configure 1 option(seeregister SD_CONFIG1). 0 32 read-write WCMP_THR Window compare threshold register 0xC 32 read-write 0x7FFF8000 0xFFFFFFFF WCMP_THR_LOW <s 0 15> Windows compare low threshold. 0 16 read-write WCMP_THR_HIGH <s 0 15> Windows compare high threshold If ADC decimation result is out of the window one compare interrupt will be triggered. 16 16 read-write INTEN ADC interrupt enable register 0x10 32 read-write 0 0x80000007 DAT_RDY_INTEN 1 to enable Data ready interrupt 0 1 read-write WCMP_INTEN 1 to enable Window compare interrupt. 1 1 read-write FIFO_OF_INTEN 1 to enalble FIFO overflow interrupt. 2 1 read-write ADC_INTEN 1 to enable ADC interrupt 31 1 read-write INT ADC interrupt status register 0x14 32 read-write 0 0x80000007 DAT_RDY_INT Data ready interrupt will be cleared after fifo data is read can not be cleared by write 1. 0 1 read-only WCMP_INT Window compare interrupt. 1 1 read-write oneToClear FIFO_OF_INT FIFO overflow interrupt. 2 1 read-write oneToClear ADC_INT ADC interrupt. 31 1 read-only DATA ADC converted data output 0x18 32 read-only 0 0xFFFFFFFF DATA ADC data read from FIFO. 0 32 read-only 2 0x4 CFG[%s] ADC configuration register 0x20 32 read-write 0x83802950 0xFFFFFFFF PGA_GAIN SD ADC input PGA gain=2^value the range is 1-16. 0 3 read-write PGA_BP 1 to bypass SD ADC input PGA 3 1 read-write PGA_VINN SD ADC PGA VIN input offset selection 4 2 read-write VREF VREF 0 VREF_0P75 3/4 VREF 0x1 VREF_0P5 1/2 VREF 0x2 AVSS AVSS 0x3 ADC_GAIN SD ADC gain selection. 6 2 read-write ADC_GAIN_0P5X 0.5x 0 ADC_GAIN_1X 1x 0x1 ADC_GAIN_1P5X 1.5x 0x2 ADC_GAIN_2X 2x 0x3 VREF_GAIN SD ADC Reference Gain seletion 8 1 read-write VREF_GAIN_1X 1x 0 VREF_GAIN_1P5X 1.5x 0x1 ADC_VCM SD ADC input common voltage selection. 9 3 read-write ADC_VCM_1D16 1/16 VCC 0 ADC_VCM_1D8 1/8 VCC 0x1 ADC_VCM_2D8 2/8 VCC 0x2 ADC_VCM_3D8 3/8 VCC 0x3 ADC_VCM_4D8 4/8 VCC 0x4 ADC_VCM_5D8 5/8 VCC 0x5 ADC_VCM_6D8 6/8 VCC 0x6 ADC_VCM_7D8 7/8 VCC 0x7 PGA_VCM_EN SD ADC PGA output common voltage control enable signal. 12 1 read-write PGA_VCM_DIR SD ADC PGA output common voltage control direction signal. 13 1 read-write DOWN down 0 UP up 0x1 PGA_VCM SD ADC PGA output common voltage, adjustment = (PGA_VCM0[5]+1)*(PGA_VCM0[3:0]+1)*40mv 14 6 read-write DOWN_SAMPLE_RATE Down sample rate 20 3 read-write DOWN_SAMPLE_32 down sample 32 0x1 DOWN_SAMPLE_64 down sample 64 0x3 DOWN_SAMPLE_256 down sample 256 0x4 DOWN_SAMPLE_128 down sample 128 0x5 DS_DATA_STABLE Down sample date stable number. you can keep the bit 1:0 to 2'b11. DS_DATA_STABLE0[5:2]+1 23 6 read-write SCAN_INTV Interval when switching ADC source; 2/4/8/16/32/64/128/256 clock cycle. 29 3 read-write SCAN_INTV_2CLK 2 clock cycle 0 SCAN_INTV_4CLK 4 clock cycle 0x1 SCAN_INTV_8CLK 8 clock cycle 0x2 SCAN_INTV_16CLK 16 clock cycle 0x3 SCAN_INTV_32CLK 32 clock cycle 0x4 SCAN_INTV_64CLK 64 clock cycle 0x5 SCAN_INTV_128CLK 128 clock cycle 0x6 SCAN_INTV_256CLK 256 clock cycle 0x7 BG_BF ADC bandcap and buffer setting register 0x28 32 read-write 0x82 0x30F7 PGA_BM SD ADC buffer bias current selection. 0 3 read-write PGA_BM_50PCNT 50% 0 PGA_BM_75PCNT 75% 0x1 PGA_BM_100PCNT 100% 0x2 PGA_BM_150PCNT 150% 0x3 PGA_BM_200PCNT 200% 0x4 PGA_BM_300PCNT 300% 0x5 BG_SEL Bandgap voltage selection to compensate PVT variations8 steps with 5mV each upward. VBG=1205+5*BGSEL(mV) 4 4 read-write TEMP_EN 1 to enable temperature sensor 12 1 read-write PGA_CHOP_EN 1 to enable chopper in PGA 13 1 read-write PGA_BM_DIV2 1 to half PGA bias current 14 1 read-write ANA_CTRL ADC core and reference setting regsiter 0x2C 32 read-write 0x55564 0xF77F7 ADC_BM ADC bias current selection. 0 3 read-write ADC_BM_50PCNT 50% 0 ADC_BM_75PCNT 75% 0x1 ADC_BM_100PCNT 100% 0x2 ADC_BM_150PCNT 150% 0x3 ADC_BM_200PCNT 200% 0x4 ADC_BM_300PCNT 300% 0x5 ADC_ORDER 1 to enable SD ADC 2 order mode selection 4 1 read-write ADC_ORDER_3ORDER 3 order 0 ADC_ORDER_2ORDER 2 order 0x1 DITHER_EN 1 to enable SD ADC PN Sequence in chopper mode 5 1 read-write CHOP_EN 1 to enable SD ADC chopper 6 1 read-write INV_CLK 1 to invert SD ADC Output Clock 7 1 read-write VREF_BM SD ADC Reference Driver bias current selection. 8 3 read-write VREF_BM_50PCNT 50% 0 VREF_BM_75PCNT 75% 0x1 VREF_BM_100PCNT 100% 0x2 VREF_BM_150PCNT 150% 0x3 VREF_BM_200PCNT 200% 0x4 VREF_BM_300PCNT 300% 0x5 VREF_BM_X3 SD ADC Reference Driver bias current triple. 11 1 read-write VINN_IN_BM PGA VlNN Input Driver bias current selection. 12 3 read-write VINN_IN_BM_50PCNT 50% 0 VINN_IN_BM_75PCNT 75% 0x1 VINN_IN_BM_100PCNT 100% 0x2 VINN_IN_BM_150PCNT 150% 0x3 VINN_IN_BM_200PCNT 200% 0x4 VINN_IN_BM_300PCNT 300% 0x5 VINN_OUT_BM PGA VlNN Output Driver bias current selection. 16 3 read-write VINN_OUT_BM_50PCNT 50% 0 VINN_OUT_BM_75PCNT 75% 0x1 VINN_OUT_BM_100PCNT 100% 0x2 VINN_OUT_BM_150PCNT 150% 0x3 VINN_OUT_BM_200PCNT 200% 0x4 VINN_OUT_BM_300PCNT 300% 0x5 VINN_OUT_BM_X3 PGA VlNN Output Driver bias current triple. 19 1 read-write ADC_BM_DIV2 SD ADC bias current half. 20 1 read-write DAC dac DAC 0x40007400 0 0x2C registers ANA_CFG reserved 0 32 read-write 0x71022 0xF1377 FILTER_BM Set the filter bias current 0 3 read-write DAC_AMP Set the current bias of the DAC 4 3 read-write FILTER_BW Set the Miller compensation capacitance of the OPAMP. This compensation capacitance is determined by the off-chip load resistance 8 2 read-write FILTER_150K_EN Set the filter type and bandwidth 12 1 read-write VCM Set the common mode I of the driver. 16 4 read-write CTRL DAC clock invert 0x4 32 read-write 0 0xFF3F1FFF ENABLE DAC module enable 0 1 read-write SIN_EN Sin wave enable 1 1 read-write MOD_EN Modulator enable 2 1 read-write MOD_WD Modulator output width 3 1 read-write SMPL_RATE sigma delta modulator down sample rate 4 3 read-write SGN_INV Sign bit inverse 7 1 read-write BUF_IN_ALGN FIFO input data align 8 1 read-write BUF_OUT_ALGN FIFO output data and Sine wave generator output align mode when no modulation mode 9 1 read-write TRG_MODE Trigger mode 10 1 read-write TRG_EDGE Trigger edge select 11 2 read-write TRG_SEL Trigger select 16 6 read-write CLK_DIV DAC clock divider 24 7 read-write CLK_INV DAC clock invert 31 1 read-write SIN_CFG0 sin amplitude 0x8 32 read-write 0 0xFFFFFFFF SIN_FREQ sin frequency 0 16 read-write SIN_AMP sin amplitude 16 16 read-write SIN_CFG1 reserved 0xC 32 read-write 0 0xFFFFF SIN_DC DC value of sin wave 0 20 read-write GAIN_CTRL reserved 0x10 32 read-write 0x10 0xFF GAIN_CTRL digital FIFO output multiply with GAIN_CTRL to scale to certain range. Where GAIN_CTRL is a <u 4 4> value. 0 8 read-write CLR_TRG Reserved 0x14 32 read-write 0 0 BUF_CLR clear buffer signal write 1 to clear. 0 1 write-only SW_TRG Software trigger 1 1 write-only DIN DAC data input 0x18 32 write-only 0 0 DIN DAC data input 0 32 write-only INT Reserved 0x1C 32 read-write 0 0x7F BUF_NFUL_INT Buffer not full interrupt 0 1 read-only BUF_FUL_INT Buffer full interrupt 1 1 read-only BUF_EMT_INT Buffer empty interrupt 2 1 read-only BUF_HEMT_INT buffer half empty interrupt 3 1 read-only BUF_OV_INT Buffer overflow interrupt write 1 to clear 4 1 read-write oneToClear BUF_UD_INT Buffer underflow interrupt write 1 to clear 5 1 read-write oneToClear BUF_HFUL_INT Buffer half full interrupt 6 1 read-only INTEN Reserved 0x20 32 read-write 0 0x7F BUF_NFUL_INTEN buffer not full interrupt enable 0 1 read-write BUF_FUL_INTEN buffer full interrupt enable 1 1 read-write BUF_EMT_INTEN buffer empty interrupt enable 2 1 read-write BUF_HEMT_INTEN buffer half empty interrupt enable 3 1 read-write BUF_OV_INTEN buffer over flow interrupt enable 4 1 read-write BUF_UD_INTEN Buffer under flow interrupt enable 5 1 read-write BUF_HFUL_INTEN buffer half full interrupt enable 6 1 read-write INT_STAT Reserved 0x24 32 read-only 0 0x1007F BUF_NFUL_INT_STAT buffer not full interrupt status 0 1 read-only BUF_FUL_INT_STAT buffer full interrupt status 1 1 read-only BUF_EMT_INT_STAT buffer empty interrupt status 2 1 read-only BUF_HEMT_INT_STAT buffer half empty interrupt status 3 1 read-only BUF_OV_INT_STAT buffer over flow interrupt status 4 1 read-only BUF_UD_INT_STAT Buffer under flow interrupt status 5 1 read-only BUF_HFUL_INT_STAT buffer half full interrupt status 6 1 read-only DAC_INT_STAT DAC all interrupt status 16 1 read-only STATUS Reserved 0x28 32 read-only 0 0x770001 BUSY busy 0 1 read-only BUF_WR_PTR Buffer write pointer 16 3 read-only BUF_RD_PTR Buffer read pointer 20 3 read-only CS tsc CS 0x40007800 0 0x24 registers CTRL0 CapSense control register 0 0 32 read-write 0 0x1FF00FF ENABLE CapSense enable. Write 1 to start work, 0 to stop. 0 1 read-write DISABLE OSC work disable. 0 ENABLE OSC work enable. 0x1 SRST Soft reset. Set 1 to reset, and 0 to de-assert. 1 1 read-write OSC_FREQ Oscillation frequency control. The driving current will change accordingly. 2 6 read-write CLK_DIV Clock divider from CLK_APB : CLK_CS_DIV = CLK_APB/(CLK_DIV + 1) 16 9 read-write CTRL1 CapSense control register 1 0x4 32 read-write 0 0xFFFFFF PERIOD The scan period for one channel, which is PERIOD/(CLK_DIV+1) clock cycles of CLK_APB. 0 16 read-write CH Channel enable, each bit represent one channel, with CH[0] for CS0, CH[1] for CS1 16 8 read-write INT Interrupt status register 0x8 32 read-write 0 0xF FIFO_NOTEMPTY_INT FIFO not empty status indicator. Will clear automatically if no data available. 0 1 read-only FIFO_HFULL_INT FIFO half full status indicator. Will clear automatically once less than half. 1 1 read-only FIFO_FULL_INT FIFO full status indicator. Will clear automatically once not full. 2 1 read-only SCAN_INT Scan done status flag for all enabled channels. Write 1 to clear. 3 1 read-write oneToClear INTEN Interrupt mask register 0xC 32 read-write 0 0xF FIFO_NOTEMPTY_INTEN Interrupt mask of FIFO_NOTEMPTY_INT. Set 1 to enable the interrupt. 0 1 read-write FIFO_HFULL_INTEN Interrupt mask of FIFO_HFULL_INT. Set 1 to enable the interrupt. 1 1 read-write FIFO_FULL_INTEN Interrupt mask of FIFO_FULL_INT. Set 1 to enable the interrupt. 2 1 read-write SCAN_INTEN Interrupt mask of SCAN_INT. Set 1 to enable the interrupt. 3 1 read-write DATA Output data register 0x10 32 read-only 0 0xFFFFFFFF DATA Output data to MCU: DATA[18:16]: channel index, DATA[15:0]: counter output for that channel. 0 19 read-only LP_CTRL Control register for low power mode 0x14 32 read-write 0 0xFFFF00FF DEBONCE_NUM (DEBONCE_NUM+1) consecutive samples to judge one touch action. 0 4 read-write LP_EN Enable for low power mode. 4 1 read-write DISABLE Low power mode disable. 0 ENABLE Low power mode enable. 0x1 LP_CH The index of the channel to monitor in low power mode, representing 0~7. 5 3 read-write THR Threshold to decide the touch action. 16 16 read-write LP_INT Low power interrupt register 0x18 32 read-only 0 0x1 LP_INT Interrupt in low power mode when counter output is less than THR. 0 1 read-only LP_INTEN low power interrupt enable register 0x1C 32 read-write 0 0x1 LP_INTEN Interrupt enable of LP_INT. Set 1 to enable. 0 1 read-write IDLE_PERIOD Idle preiod number register 0x20 32 read-write 0 0xFFFF IDLE_PERIOD Number of idle period. Zero represents no idle time between consecutive scan. 0 16 read-write RNG rng RNG 0x40007C00 0 0x14 registers CTRL control register 0 32 read-write 0 0x31 ENABLE write 1 to enable randome number generator 0 1 read-write START write 1 to start random number generation, auto clear 1 1 write-only NUM total bits 4 2 read-write STAT status register 0x4 32 read-only 0 0x1 BUSY module in processing 0 1 read-only DATA random data output register 0x8 32 read-only 0 0xFFFFFFFF DATA final random data read by SW 0 32 read-only INT interrupt register 0xC 32 read-write 0 0x1 DONE random data generate done 0 1 read-write oneToClear INTEN interrupt mask register 0x10 32 read-write 0 0x1 DONE_INTEN random data generate done mask 0 1 read-write QDEC0 qdec QDEC QDEC 0x40009000 0 0x28 registers CTRL control register 0 32 read-write 0 0x71 QDEC_EN no description available 0 1 read-write START no description available 1 1 write-only STOP no description available 2 1 write-only SOFT_CLR no description available 3 1 write-only AUTO_CLR_EN no description available 4 1 read-write SINGLE_SAMPLE_SRST_EN no description available 5 1 read-write DB_FILTER_EN no description available 6 1 read-write SAMP_CTRL QDEC sample settting register 0x4 32 read-write 0 0xF0F1F DIVIDE divide number to APB clk 0~20 total 21modes 0 5 read-write PTS total sample points 0~11 total 12modes cf. 8.2 8 4 read-write PTS0 5 points 0 PTS1 10 points 0x1 PTS2 40 points 0x2 PTS3 80 points 0x3 PTS4 120 points 0x4 PTS5 160 points 0x5 PTS6 200 points 0x6 PTS7 240 points 0x7 PTS8 280 points 0x8 PTS9 320 points 0x9 PTS10 360 points 0xA PTS11 400 points 0xB DB_SAMP_DIV Debounce filter sample clk devide cf. 8.3 16 4 read-write SAMPLE QDEC sample result register 0x8 32 read-only 0 0x3 SAMPLE Sample value each time (2's complement) 0 2 read-only ACC QDEC accumulate register 0xC 32 read-only 0 0x7FF ACC shift counter (-1 & +1 ) normal case 0 11 read-only ACC_R QDEC accumulate snapshot register 0x10 32 read-only 0 0x7FF ACC_R ACC RO snapshot when END event is valid 0 11 read-only DB double sample register 0x14 32 read-only 0 0xF DB 2 trans counter ERROR case max value 15. 0 4 read-only DB_R DB snapshot register 0x18 32 read-only 0 0xF DB_R DB_R RO snapshot when END event is valid 0 4 read-only INT interrupt register 0x1C 32 read-write 0 0xF SINGLE_SAMPLE Each time when normal sample is done 0 1 read-write oneToClear SAMPLE_END END event triggered 1 1 read-write oneToClear ACC_OF Normal sample (+1/-1) number is overflow 2 1 read-write oneToClear DB_OF Double sample (2 trans )number is overflow 3 1 read-write oneToClear INTEN interrupt mask register 0x20 32 read-write 0 0xF SINGLE_SAMPLE_INTEN single sample done interrupt enable 0 1 read-write SAMPLE_END_INTEN sample end interrupt enable 1 1 read-write ACC_OF_INTEN normal sample overflow interrupt enable 2 1 read-write DB_OF_INTEN double sample overflow interrupt enable 3 1 read-write STAT QDEC is running 0x24 32 read-only 0 0x1 BUSY QDEC is running 0 1 read-only QDEC1 qdec QDEC 0x40009800 0 0x28 registers RTC rtc RTC 0x4000B000 0 0x30 registers CTRL RTC control register 0 32 read-write 0x100 0x175 SEC_INT_EN RTC second interrupt enable 0 1 read-write CFG RTC second configuration control. This bit is self-cleared after synchronization 2 1 read-write CAL_EN Calibration enable 8 1 read-write STATUS RTC status register 0x4 32 read-write 0 0x80071711 SEC_INT Second interrupt flag 0 1 read-write oneToClear CTRL_SYNC Control Register synchronization busy indicator 8 1 read-only STATUS_SYNC Status Register synchronization busy indicator 9 1 read-only SEC_SYNC Second configuration Register synchronization busy indicator 10 1 read-only CALIB_SYNC Calibration Register synchronization busy indicator 12 1 read-only FREE_SYNC Free running counter control Register synchronization busy indicator 16 1 read-only THR_INT_SYNC Free running counter interrupt Threshold Register synchronization busy indicator 17 1 read-only THR_RST_SYNC Free running counter Reset Threshold Register synchronization busy indicator 18 1 read-only FREE_RUNNING_INT Free running interrupt status. 31 1 read-only SEC RTC second register 0x8 32 read-write 0 0xFFFFFFFF SEC Second configuration register. 0 32 read-write CAL RTC calibration register 0x10 32 read-write 0 0x1FFFF PPM RTC calibration ppm value the precision is 1 ppm. 0 16 read-write DIR RTC calibration direction indicator 16 1 read-write FORWARD forward calibrate 0 BACKWARD backward calibrate 0x1 CNT_VAL RTC count value register 0x14 32 read-only 0 0x7FFF CNT RTC counter current value read only. 0 15 read-only CNT2_CTRL Free running control register 0x20 32 read-write 0 0xF CNT2_EN 1 to enable free running counter 0 1 read-write CNT2_INT_EN 1 to enable free running interrupt 1 1 read-write CNT2_WAKEUP 1 to enable free running wakeup 2 1 read-write CNT2_RST 1 to enable free running reset 3 1 read-write THR_INT interrupt threshold of free running counter register 0x24 32 read-write 0xF000000 0xFFFFFFFF THR_INT The Threshold of free running counter is to generate free running interrupt. 0 32 read-write THR_RST reset threshold of free running counter register 0x28 32 read-write 0xFF000000 0xFFFFFFFF THR_RST The Threshold of free running counter is to generate free running reset. 0 32 read-write CNT2 free running count value 0x2C 32 read-only 0 0xFFFFFFFF CNT2 The current value of free running counter 0 32 read-only AGC agc AGC 0x4000C000 0 0x1C registers CTRL0 AGC control register 0 0 32 read-write 0x3954001 0xFFFFFFF PPF_INTRPT_MOD Control whether fsm can interrupt 0 2 read-write FREZ_MOD Control whether fsm can restore last value when correalation trigh happens 2 2 read-write RRF_GAIN_SEL LNA gain controlGAIN=26-12*LNA_GAIN_SEL 4 3 read-write RRF_WEN Lna gain write enable 7 1 read-write PPF_GAIN PPF gain controlGain=36-3*PPF_GAIN 8 4 read-write PPF_WEN Ppf gain write enable 12 1 read-write PKWT_TH_DIG_1 PKWT_TH_DIG + PKWT_TH_DIG_ADD in ccode 13 5 read-write PD_CLR_EN Force clear analog PD 18 1 read-write PD_RST_LEN Pd disable time when reset0h0us 1h8us 2h16us 7h56us 19 3 read-write RFAGC_FSYNC_DET_DIS Use to control rfagc gain adjust0brfagc stops when sync 1brfagc always on 22 1 read-write RFAGC_DIRECTION_FREEZE Use to disable rfagc gain adjust when switching antenna at direction found mode0b rfagc enable 1brfagc disable 23 1 read-write DOWN_24_EN Lna decrease 24dbm0bdisable 1benable 24 1 read-write SWITCH_PD_RST_LEN Pd disable time when direction found rfagc reset00b2us 01b4us 10b8us 11b16us 25 2 read-write GLNA_MAX_REDU Lna max gain reduce 12dbm0bdisable 1benable 27 1 read-write CTRL1 AGC control register 1 0x4 32 read-write 0x5A10831 0xFFFFFFF PD3_TH_REG Pd3 threshold 0 3 read-write PD3_TH_HYST_REG Desired upper boundary 3 4 read-write PKWT_TH_ANA_1 PKWT_TH_ANA + PKWT_TH_ANA_ADD 7 6 read-write PKWT_TH_ANA_0 PKWT_TH_ANA in ccode 13 5 read-write PKWT_TH_DIG_0 PKWT_TH_DIG in ccode 18 5 read-write SETL_TH_PPF_2 SETL_TH_PPF_2 + DLY_DIG 1 in ccode 23 5 read-write CTRL2 AGC control register 2 0x8 32 read-write 0x4800 0x7F00 PPF_PDVTH_LOW PPF peak detect threshold select 8 1 read-write RRF_MG_PK LNA medium gain peak detect threshold selectAMP=(400-25* LNA_MG_PK)mv 9 3 read-write RRF_HG_PK LNA high gain peak detect threshold selectAMP=(100-8* LNA_HG_PK)mv 12 3 read-write CTRL3 AGC control register 3 0xC 32 read-write 0x12CC6C 0x1FFFFF GF2_PAR00 no description available 0 4 read-write GF2_PAR01 no description available 4 4 read-write GF2_PAR10 no description available 8 4 read-write SETL_TH_OVSHT_DIG no description available 12 3 read-write SETL_TH_OVSHT_INTRPT no description available 15 3 read-write SETL_TH_OVSHT no description available 18 3 read-write CTRL4 AGC control register 4 0x10 32 read-write 0xC49974 0xFFFFFF SETL_TH_PD1 no description available 0 4 read-write SETL_TH_PD2 no description available 4 4 read-write SETL_TH_PD3_1 no description available 8 6 read-write SETL_TH_PD3_2 no description available 14 6 read-write GF2_STAT24_TH no description available 20 4 read-write CTRL5 AGC control register 5 0x14 32 read-write 0 0xF TEST_CTRL no description available 0 4 read-write STAT AGC status register 0x18 32 read-only 0x5700 0x7FFFFF GLNA_CODE_OUT no description available 0 3 read-only GF2_CODE_OUT no description available 3 4 read-only RFAGC_TRIGGER_O no description available 7 1 read-only RF_GAIN no description available 8 7 read-only NUM_GAIN_ADJ no description available 15 5 read-only CUR_STAT no description available 20 3 read-only PROP prop PROP 0x4000D000 0 0xC registers TX_BUF transmit data buffer input port register 0 32 read-write 0 0xFF TX_BUF TX BUF 0 8 read-write RX_BUF received data buffer output register 0x4 32 read-only 0 0xFF RX_BUF RX BUF 0 8 read-only STAT status register 0x8 32 read-write 0x6 0xFF BIT_ORDER no description available 0 1 read-write TX_INTEN TX interrupt enable 1 1 read-write RX_INTEN RX interrupt enable 2 1 read-write RX_INT RX interrupt 3 1 read-only TX_INT TX interrupt 4 1 read-only RX_BUSY RX is busy 5 1 read-only TX_BUSY TX is busy 6 1 read-only CLR Clear intf control register. 7 1 read-write BLEDP bledp BLEDP 0x4000E000 0 0xA4 registers DP_TOP_SYSTEM_CTRL datapath system control register 0 32 read-write 0x808000F0 0xFFFFFFFF RX_PDU_LEN_IN pdu length user programmed header+payload unit is bit. 0 14 read-write AA_SEL access address selection 14 1 read-write PDU_LEN_SEL pdu length selection 15 1 read-write H_IDX h index from 0.25 to 0.75 default is 0.5. 16 8 read-write RX_EN_SEL rx enable select signal 24 1 read-write TX_EN_SEL tx enable select signal 25 1 read-write RX_REQ rx request. 26 1 read-write TX_REQ tx request. 27 1 read-write RX_MODE rx mode 28 2 read-write ANT_DATA_START ant mode data start signal need write 0 first then to 1. 30 1 read-write DET_MODE detection mode 0low ppwer mode 1high performance mode. 31 1 read-write PROP_MODE_CTRL properity mode control register 0x4 32 read-write 0x50002300 0xFFF733FF PROP_AA_ADDR_IN prop mode when access address is 5 byte the access address is {prop_aa_addr_in aa_addr_in} otherwise is aa_addr_in 0 8 read-write PROP_CRC_NUM prop mode crc number 8 2 read-write PROP_AA_NUM prop mode network address number 12 2 read-write PROP_PRE_NUM prop mode preamble number 16 3 read-write PROP_DATA_RATE prop mode data rate 20 2 read-write PROP_DIRECTION_RATE prop direction find mode sample rate 22 2 read-write PROP_DIRECTION_MODE prop direction find mode just work at prop mode. 24 1 read-write RX_ALWAYS_ON rx always on 25 1 read-write TX_ALWAYS_ON tx always on 26 1 read-write TX_POWER_DONE_TIME tx power down time in ant mode and prop mode unit is us. 27 5 read-write ACCESS_ADDRESS access address register 0x8 32 read-write 0x8E89BED6 0xFFFFFFFF AA_ADDR_IN access address user programmed. 0 32 read-write ANT_PDU_DATA0 pdu data 0 to 1 byte, and preamble register 0xC 32 read-write 0x5502FF3B 0xFF9FFFFF PDU_DATA0 pdu data 0 to 1 byte 0 16 read-write PATTERN_SEL pattern selection 16 4 read-write TEST_PATTERN_EN enable test pattern. 20 1 read-write PROP_PREAMBLE_WEN when high enable manual prop mode preamble. 23 1 read-write PROP_PREAMBLE prop mode preamble. 24 8 read-write ANT_PDU_DATA1 pdu data 2 to 5 byte 0x10 32 read-write 0x7BE2E64 0xFFFFFFFF PDU_DATA1 pdu data 2 to 5 byte 0 32 read-write ANT_PDU_DATA2 pdu data 6 to 9 byte 0x14 32 read-write 0x129DA3CF 0xFFFFFFFF PDU_DATA2 pdu data 6 to 9 byte 0 32 read-write ANT_PDU_DATA3 pdu data 10 to 13 byte 0x18 32 read-write 0x9B15238D 0xFFFFFFFF PDU_DATA3 pdu data 10 to 13 byte 0 32 read-write ANT_PDU_DATA4 pdu data 14 to 17 byte 0x1C 32 read-write 0xAB898880 0xFFFFFFFF PDU_DATA4 pdu data 14 to 17 byte 0 32 read-write ANT_PDU_DATA5 pdu data 18 to 21 byte 0x20 32 read-write 0x42309CAB 0xFFFFFFFF PDU_DATA5 pdu data 18 to 21 byte 0 32 read-write ANT_PDU_DATA6 pdu data 22 to 25 byte 0x24 32 read-write 0xDE9B914 0xFFFFFFFF PDU_DATA6 pdu data 22 to 25 byte 0 32 read-write ANT_PDU_DATA7 pdu data 26 to 29 byte 0x28 32 read-write 0x2B4FD925 0xFFFFFFFF PDU_DATA7 pdu data 26 to 29 byte 0 32 read-write CRCSEED crc seed 0x2C 32 read-write 0xFFFFFF 0x1FFFFFF CRC_SEED_IN user programmed crc seed. 0 24 read-write CRC_SEED_WEN when high enable manual program crc seed. 24 1 read-write DP_FUNCTION_CTRL datapath function control register 0x30 32 read-write 0x1C273A40 0xFFFF7FFF DP_STATISTICS_SEL datapath statistics selection. 0 3 read-write CHF_COEF_WEN manual select channel filter coefficent. 3 1 read-write CHF_COEF_IDX no description available 4 2 read-write LP_SNR_LEN_AUTO when enable auto adjust lp mode snr acc length otherwise the legnth fixed. 6 1 read-write DOUT_ADJ_DIS data delay adjust disable. 7 1 read-write LP_ADJ_MODE lp mode delay adjust mode 8 1 read-write FR_OFFSET_EN pdu frequency offset track enable. 9 1 read-write DC_AVE_EN when high enable cfo estimation average. 10 1 read-write FIX_DELAY_EN no description available 11 1 read-write TRACK_LEN track length 12 2 read-write TRACK_LEN_WEN when high manual track length. 14 1 read-write XCORR_FILT_EN when high enable xcorr filter. 16 1 read-write XCORR_FULLWIN_EN when xcorr_win_auto_en low full sync enable. 17 1 read-write XCORR_AA_LEN select access address bit number 18 1 read-write XCORR_AA_LEN_WEN enable manual correlation aa length. 19 1 read-write XCORR_WIN_AUTO_EN correlation window size auto selection enable. 20 1 read-write RESAMPLER_TAP resampler tap number 21 1 read-write RESAMPLER_TAP_WEN when high enable manual resampler tap number otherwise auto selection. 22 1 read-write RESAMPLER_BP resampler enable or bypass 23 1 read-write FAGC_WIN_LEN select estimation length 24 1 read-write FAGC_WEN when high enable manual fine agc gain. 25 1 read-write HP_CFO_EN when hp mode cfo estimation enable 26 1 read-write CFO_TRACK_EN tracking cfo enable. 27 1 read-write CFO_INI_EN initial cfo enable. 28 1 read-write ADC_IN_FLIP when 1 exchange i and q signals. 29 1 read-write TX_EN_MODE transmit mode 30 1 read-write RX_EN_MODE receiver mode 31 1 read-write DP_TEST_CTRL datapath test iinterface register 0x34 32 read-write 0 0xFFBFFBFF TIF_SEL test interface selection. 0 8 read-write TIF_CLK_SEL test interface clock selection 8 2 read-write CORDIC_DAC_OUT when high cordic to dac 11 1 read-write TIF_EN test interface enable 12 1 read-write IMR_INV datapath mixer nco if selection 13 1 read-write CLK_TX_GATE_DIS clock tx gate disable 14 1 read-write BUF_FULL_OFFRF_DIS (new standard)______when high rf always on in rx_en other wise when buffer full rf will be off. 15 1 read-write CLK_BUST_GATE_DIS clock burst gate disable 16 1 read-write CLK_RX_GATE_DIS clock rx gate disable 17 1 read-write CLK_LPDET_GATE_DIS clock lp mode detector gate disable 18 1 read-write CLK_HPDET_GATE_DIS clock hp mode detector gate disable 19 1 read-write CLK_RFE_GATE_DIS clock rfe gate disable 20 1 read-write IQSWAP_XOR iq swap xor. 21 1 read-write DAC_TEST_EN dac test enable dac input comes from register 23 1 read-write DAC_TEST dac input data value 24 8 read-write BLE_DP_STATUS1 datapath status register 1 0x38 32 read-only 0 0xFFF3FFF SNR_EST snr estimation 0 8 read-only CNR_EST cnr estimation 8 6 read-only AGC_RSSI signal rssi db value. 16 8 read-only AGC_RSSI_READY signal rssi valid. 24 1 read-only SNR_VLD snr estimation valid. 25 1 read-only CNR_VLD cnr estimation valid. 26 1 read-only TX_BUSY tx busy signal. 27 1 read-only BLE_DP_STATUS2 datapath status register 2 0x3C 32 read-only 0 0xE03FFFFF VALID_PCK_NUM received valid packet number. 0 16 read-only AA_ERR_NUM access address error number. 16 6 read-only CRC_ERROR indicator of packet crc error. 29 1 read-only BURST_DET indicator of burst detection 30 1 read-only DP_STATUS_VLD_0 data path status valid after access address valid. 31 1 read-only BLE_DP_STATUS3 datapath status register 3 0x40 32 read-only 0 0x7FF07FF FD_CFO_TRACK normalized cfo tracking estimation. 0 11 read-only CFO_EST_FD normalized lp cfo initial estimation. 16 11 read-only BLE_DP_STATUS4 datapath status register 4 0x44 32 read-only 0 0x8FFF03FF RESAMPLER_PH resampler phase. 0 10 read-only HP_CFO normalized hp cfo estimation. 16 12 read-only HP_CFO_VLD hp mode cfo estimation result valid 31 1 read-only RX_FRONT_END_CTRL1 rx front end control register 1 0x48 32 read-write 0x10000 0x37FFF CFO_COMP ______cfo user programmed. 0 15 read-write DCNOTCH_GIN dc notch coefficient 16 2 read-write RX_FRONT_END_CTRL2 rx front end control register 2 0x4C 32 read-write 0x10403000 0xFFFFFFFF FAGC_GAIN fine agc gain. 0 11 read-write FAGC_INI_VAL fagc gain initial value 11 1 read-write CNR_IDX_DELTA cnr index delta. 12 4 read-write FAGC_REF fine agc signal reference. 16 8 read-write CORDIC_MIN_VIN_TH cordic input signal min threshold 24 4 read-write FREQ_TRADE_EN enable frequency trade when cordic input signal small than cordic_min_vin_th 28 1 read-write CHN_SHIFT channel filter shift 29 3 read-write FREQ_DOMAIN_CTRL1 frequency domain control register 1 0x50 32 read-write 0x7F068000 0xFF0E81FF SYNC_WORD_IN0 manul sync word [3932] 0 8 read-write SYNC_WORD_WEN when high enable manul sync word 8 1 read-write SYNC_P_SEL no description available 15 1 read-write RD_EXBIT_EN read extra 8 samples after sync 16 1 read-write RFAGC_TRACK_DLY buffer settle threshold from 1us to 127us step is 1us 17 3 read-write PROP_DF_16US prop mode direct found waiting 16 us. 24 8 read-write FREQ_DOMAIN_CTRL2 frequency domain control register 2 0x54 32 read-write 0 0xFFFFFFFF SYNC_WORD_IN1 manul sync word [310] 0 32 read-write FREQ_DOMAIN_CTRL3 frequency domain control register 3 0x58 32 read-write 0xF101816 0x3F3F3F3F XCORR_PAR_TH3 xcorr trigger par threshold3 0 6 read-write XCORR_PAR_TH2 xcorr trigger par threshold2 8 6 read-write XCORR_PAR_TH1 xcorr trigger par threshold1 16 6 read-write XCORR_PAR_TH0 xcorr trigger par threshold0 24 6 read-write FREQ_DOMAIN_CTRL4 frequency domain control register 4 0x5C 32 read-write 0x304090B 0x3F3F3F3F XCORR_POW_TH3 xcorr power threshold3 0 6 read-write XCORR_POW_TH2 xcorr power threshold2 8 6 read-write XCORR_POW_TH1 xcorr power threshold1 16 6 read-write XCORR_POW_TH0 xcorr power threshold0 24 6 read-write FREQ_DOMAIN_CTRL5 frequency domain control register 5 0x60 32 read-write 0x457A8001 0xFFFFF7F3 GAIN_TED ted gain 0 2 read-write SYNC_DIN_SAT_VALUE <u 1 2>sync din amplitude limit value 0 to 1.75 correspond to 2 to 3.75 4 3 read-write SYNC_DIN_SAT_EN sync din amplitude limit enable 7 1 read-write CNT_SETTLE_IDX buffer settle threshold from 32 to 256 step is 32 8 3 read-write TRIG_XCORR_CNT correlation search window size. 12 4 read-write XCORR_RSSI_TH3 xcorr triger rssi threshold0 16 4 read-write XCORR_RSSI_TH2 xcorr triger rssi threshold0 20 4 read-write XCORR_RSSI_TH1 xcorr triger rssi threshold0 24 4 read-write XCORR_RSSI_TH0 xcorr triger rssi threshold0 28 4 read-write FREQ_DOMAIN_CTRL6 frequency domain control register 5 0x64 32 read-write 0x11207B09 0x333FFF1F HP_TRAIN_SIZ hp mode training size. 0 5 read-write HP_HIDX_GAIN h index reference gain when hp mode default is 1.0 8 8 read-write H_REF_GAIN h index reference gain when frequency offset track default is 1.0 16 6 read-write DET_FR_IDX pdu cfo tracking loop gain 24 2 read-write CFO_FR_IDX aa cfo tracking loop gain 28 2 read-write HP_MODE_CTRL1 when high hp mode training size same as cfo tracking. 0x68 32 read-write 0x80120D0A 0xFF3F3F3F HP_BMC_P_TRACK p paramter in search period of frequency offset iir of bmc 0 6 read-write HP_BMC_P_TRAIN p paramter in training period of frequency offset iir of bmc 8 6 read-write HP_BMC_CZ1 cz1 parameter. 16 6 read-write BUF_IDX_DELTA buffer index delta 24 4 read-write WMF2_DSAMP_IDX wmf2 down sampling position -4 to 3 28 3 read-write HP_TRAIN_SIZ_FIX when high hp mode training size same as cfo tracking. 31 1 read-write HP_MODE_CTRL2 q paramter in training period of phase offset iir of bmc 0x6C 32 read-write 0x717B1122 0xFFFF13FF SNR_EST_REF signal amplitude used in snr estimation whose unit is db 0 8 read-write SNR_EST_LEN symbol number used in snr estimation when pdu length is less than 4 8 32 will be used otherwise the value configured from register will be used 8 2 read-write SNR_EST_EN snr estimation in time domain enable 12 1 read-write HP_BMC_Q_TRACK q paramter in search period of phase offset iir of bmc 16 8 read-write HP_BMC_Q_TRAIN q paramter in training period of phase offset iir of bmc 24 8 read-write FREQ_DOMAIN_STATUS1 frequency domain status register 1 0x70 32 read-only 0 0xF1FF03FF MAX_XCORR xcorr_org value at the max par position 0 10 read-only PKT_OFFSET_COM time from access addres last bit to trigger finish. 16 9 read-only NIDX noise db buffer index 28 4 read-only FREQ_DOMAIN_STATUS2 frequency domain status register 2 0x74 32 read-only 0 0x3FF03FF MAX_PAR_SPWR spwr value at the max par position 0 10 read-only MAX_PAR_XCORR xcorr*xcorr value at the max par position 16 10 read-only DP_AA_ERROR_CTRL AA error control register 0x84 32 read-write 0xF 0xF IQSWAP_SEL when high adc data iq swap with analog iqswap. datapath mixer nco if selection changed with analog iqswap. 0 1 read-write AA_ERROR_EN when high it will reset datapath when aa error. 1 1 read-write AA_ERROR_CNR_EN when high the aa error reset condition is cnr > threshold and aa error. when low it don care cnr. 2 1 read-write AA_ERROR_CNR_SEL when high the cnr threshold is 24. when low the cnr threshold is 32. 3 1 read-write DP_INT data path interrupt register 0x88 32 read-write 0xC0000000 0xFFFF000F DP_INTERRUPT0 datapath interrupt0 0 1 read-only DP_INTERRUPT1 datapath interrupt1 1 1 read-only DP_INTERRUPT2 datapath interrupt2 2 1 read-only DP_INTERRUPT datapath interrupt 3 1 read-only DP_INTERRUPT0_SEL datapath interrupt0 selection 16 4 read-write DP_INTERRUPT1_SEL datapath interrupt1 selection 20 4 read-write DP_INTERRUPT2_SEL datapath interrupt2 selection 24 4 read-write DP_INTERRUPT0_MSK datapath interrupt0 msk 28 1 read-write DP_INTERRUPT1_MSK datapath interrupt1 msk 29 1 read-write DP_INTERRUPT2_MSK datapath interrupt2 msk 30 1 read-write DP_INTERRUPT_MSK datapath interrupt msk 31 1 read-write DP_AA_ERROR_TH AA error threshold register 0x8C 32 read-write 0x35351820 0xFFFF3F7F HP_TRAIN_POSITION when high use the bits just ahead of pdu for rsve training. when low the training bit starts at the track bits. 0 1 read-write CORDIC_IN_SCALE when high cordic input will be auto scaled(shift) according to the magnitude of real/imag data. 1 1 read-write PAR_AUTO_HIGHER_SEL when high par auto higher 1/4 when low par auto higher 1/8 it will work together with par_auto_higher_en and rssi_good_dbm. 2 1 read-write PAR_AUTO_HIGHER_EN when high when signal is good ( rssi large than rssi_good_dbm) it will auto higher the par threshold. 3 1 read-write SNR_GOOD_TH threshold for snr(fd mode calculated use aa) to reset datapath cooperate with cnr snr and aa error. 4 3 read-write CNR_GOOD_TH threshold for cnr to reset datapath cooperate with cnr snr and aa error. 8 6 read-write RSSI_GOOD_TH threshold for rssi to reset datapath cooperate with cnr snr and aa error. 16 8 read-write RSSI_GOOD_DBM when rssi dbm large than the -rssi_good_dbm the signal is good enough to higher the par threshold if the function enable. 24 8 read-write DF_ANTENNA_CTRL antenna register 0x90 32 read-write 0x6 0xFFFF01FF SWITCH_MAP_SEL_8F switch antenna map selection 8 to f 0 2 read-write SWITCH_MAP_SEL_07 switch antenna map selection 0 to 7 2 2 read-write EXT_ANTENNA_NUM user programmed switch antenna number 4 4 read-write EXT_ANTENNA_NUM_WEN user programmed switch antenna enable 8 1 read-write BUFFER_BP when high, bypass buffer, and not write/read buffer for datapath power test 16 1 read-write TEST_TD_POWER when high, test rfe,td detector power, other module don't work, the cordic work or not decided by resampler_bp 17 1 read-write TEST_FD_POWER when high, test rfe, cordic and fd detector power, other module don't work 18 1 read-write TEST_SYNC_POWER when high, test rfe. Cordic and sync power. Other module don't work 19 1 read-write TEST_RFE_CORDIC_POWER when high, test rfe and cordic power, other module don't work 20 1 read-write TEST_RFE_POWER when high, test rfe power, other module don't work 21 1 read-write ADC01_SAMPLE_TIME when high, will exchange the adc0/adc1 sample time, to avoid the error sample time for adc0/adc1 22 1 read-write PHY_RATE_MUX ble data rate used in datapath, 0: 1mbps 1: 2mbps 23 1 read-only PHY_RATE_REG user programmed phy data rate 24 1 read-write PHY_RATE_WEN 0: phy rate comes from ble ip 1:phy rate comes from regsiter phy_rate_reg 25 1 read-write PDU_RSSI_WAIT_TIME 0:wait 0us 1: wait 4us 26 1 read-write PDU_RSSI_WIN_LEN select estimation length for pdu rssi calculate 27 1 read-write CAL_PDU_RSSI_EN calculate rssi use pdu data enbale. 28 1 read-write PROP_CRC_AA_DIS prop mode crc check disable check access address. 29 1 read-write PROP_AA_LSB_FIRST prop mode access address lsb first for cbt test. 30 1 read-write PRE_NUM_WEN preamble number write enable 31 1 read-write ANTENNA_MAP01 antenna switch map register 0 0x94 32 read-write 0x18801840 0x3FFF3FFF SWITCH_MAP_1 switch antenna map 1 0 14 read-write SWITCH_MAP_0 switch antenna map 0 16 14 read-write ANTENNA_MAP23 antenna switch map register 1 0x98 32 read-write 0x14201410 0x3FFF3FFF SWITCH_MAP_3 switch antenna map 3 0 14 read-write SWITCH_MAP_2 switch antenna map 2 16 14 read-write ANTENNA_MAP45 antenna switch map register 2 0x9C 32 read-write 0x22082204 0x3FFF3FFF SWITCH_MAP_5 switch antenna map 5 0 14 read-write SWITCH_MAP_4 switch antenna map 4 16 14 read-write ANTENNA_MAP67 antenna switch map register 3 0xA0 32 read-write 0x21022101 0x3FFF3FFF SWITCH_MAP_7 switch antenna map 7 0 14 read-write SWITCH_MAP_6 switch antenna map 6 16 14 read-write CALIB calib CALIB 0x4000F000 0 0x83C registers START calibration start register 0 32 read-write 0 0 PO_CLB_START Power on calibration start 0 1 write-only HOP_CLB_START Frequency hop calibration start 1 1 write-only OSC_CLB_START OSC calibration start 2 1 write-only REF_CLB_START REF PLL calibration start 3 1 write-only RCO_CLB_START RCO calibration start 4 1 write-only XTL_CLB_START XTAL calibration start 5 1 write-only STATUS calibration FSM status register 0x4 32 read-only 0 0x3FFFFFFF TOP_FSM TOP FSM 0 5 read-only DC_FSM DC FSM 5 4 read-only VCOA_FSM VCOA FSM 9 3 read-only VCOF_FSM VCOF FSM 12 5 read-only KVCO_FSM KVCO FSM 17 4 read-only RCO_FSM RCO FSM 21 3 read-only OSC_FSM OSC FSM 24 3 read-only REF_FSM REF FSM 27 3 read-only DC_CODE DC code status register 0x8 32 read-only 0x20200088 0x3F3F00FF PPF_DCCAL2_I Power on DC calibration i code 0 4 read-only PPF_DCCAL2_Q Power on DC calibration q code 4 4 read-only PPF_DCCAL_I DC re-calibration i code 16 6 read-only PPF_DCCAL_Q DC re-calibration q code 24 6 read-only DC_CFG DC code configured code register 0xC 32 read-write 0x400000 0xFF7F03FF PPF_DCCAL2_CFG_I Power on DC calibration i code configured 0 4 read-write PPF_DCCAL2_CFG_Q Power on DC calibration q code configured 4 4 read-write DC_2NDCAL_DIS DC calibration disable 8 1 read-write DC_2NDCAL_REQ DC calibration request 9 1 read-write PPF_DCCAL_CFG_I DC re-calibration i code configured 16 6 read-write DC_HOP_CAL_BP DC hop calibration bypass 22 1 read-write PPF_DCCAL_CFG_Q DC re-calibration q code configured 24 6 read-write DC_1STCAL_DIS DC hop calibration disable 30 1 read-write DC_1STCAL_REQ DC hop calibration request 31 1 read-write RCO_RC_REF_OSC_CODE RCO RC PLL48M OSC code status register 0x10 32 read-only 0x8001F00 0xF0F1F0F CAU_RCO_CAP RCO calibration output code 0 4 read-only CAU_OSC_CUR OSC calibration output code 8 5 read-only CAU_RC_CAL_OUT2REG RC calibration output code 16 4 read-only PLL48_ENREF REF calibration output code 24 4 read-only RCO_RC_REF_OSC_CFG RCO RC PLL48M OSC configured code register 0x14 32 read-write 0 0x3F3F7F3F CAU_RCO_CAP_CFG RCO calibration code configured 0 4 read-write RCO_CAL_DIS RCO calibration disable 4 1 read-write RCO_CAL_REQ RCO calibration request 5 1 read-write CAU_OSC_CUR_CFG OSC calibration output code configured 8 5 read-write OSC_CAL_DIS OSC calibration disable 13 1 read-write OSC_CAL_REQ OSC calibration request 14 1 read-write CAU_RC_CAL_REG_IN RC calibration code to analog 16 4 read-write CAU_RC_CAL_DIS RC calibration disable 20 1 read-write RC_CAL_REQ RC calibration request 21 1 read-write PLL48_ENREF_CFG REF calibration output code configured 24 4 read-write REF_CAL_DIS REF PLL calibration disable 28 1 read-write REF_CAL_REQ REF PLL calibration request 29 1 read-write VCOA_KVCO2M_CODE reserved 0x18 32 read-only 0x400 0x1F1F07FF KCALF2M_PO KVCO 2M mode calibration power on code 0 11 read-only TX_VCO_AMP VCO TX amplitude calibration output code 16 5 read-only RX_VCO_AMP VCO RX amplitude calibration output code 24 5 read-only VCOA_KVCO2M_CFG reserved 0x1C 32 read-write 0 0x1F7F7FFF KCALF2M_CFG KVCO 2M mode calibration code configure 0 11 read-write KCALF2M_BP bypass KVCO 2M mode power on calibration 11 1 read-write KVCO_CAL_E no description available 12 3 read-write TX_VCO_AMP_CFG TX VCO amplitude calibration output code configured 16 5 read-write VCOA_CAL_DIS VCO amplitude calibration disable 21 1 read-write VCOA_CAL_REQ VCO amplitude calibration request 22 1 read-write RX_VCO_AMP_CFG RX VCO amplitude calibration output code configured 24 5 read-write VCOF_KVCO_PO_CODE reserved 0x20 32 read-only 0x20200400 0x3F3F07FF KCALF_PO KVCO power up calibration result 0 11 read-only TX_VCO_CBANK_PO TX VCO frequency power on calibration output code 16 6 read-only RX_VCO_CBANK_PO RX VCO frequency power on calibration output code 24 6 read-only VCOF_KVCO_CFG VCOF hop calibration bypass 0x24 32 read-write 0 0xFFFF3FFF KCALF_CFG KVCO calibration code configure 0 11 read-write KVCO_REQ KVCO calibration request 11 1 read-write KVCO_DIS KVCO calibration disable 12 1 read-write KVCO_SKIP KVCO hop calibration calculation skip 13 1 read-write TX_VCO_CBANK_CFG TX VCO frequency calibration output code configured 16 6 read-write VCOF_CAL_DIS VCO frequency calibration disable 22 1 read-write VCOF_CAL_REQ VCO frequency calibration request 23 1 read-write RX_VCO_CBANK_CFG RX VCO frequency calibration output code configured 24 6 read-write VCOF_SKIP VCOF hop calibration calculation skip 30 1 read-write VCOF_HOP_BP VCOF hop calibration bypass 31 1 read-write VCOF_KVCO_CODE reserved 0x28 32 read-only 0x20200400 0x3F3F07FF KCALF KVCO calibration output at carrier frequency 0 11 read-only TX_VCO_CBANK TX VCO frequency calibration output code 16 6 read-only RX_VCO_CBANK RX VCO frequency calibration output code 24 6 read-only KVCO_HOP_CODE reserved 0x2C 32 read-only 0x4000400 0x7FF07FF KCALF1M KVCO hop calibration output at carrier frequency in 1M mode 0 11 read-only KCALF2M KVCO hop calibration output at carrier frequency in 2M mode 16 11 read-only VCOF_CNT_SLOPE reserved 0x30 32 read-write 0 0x1F3F1F3F TX_VCOF_CNT TX VCO frequency power up calibration 8us count value 0 8 read-write TX_SLOPE TX frequency curve slope 8 6 read-write RX_VCOF_CNT RX VCO frequency power up calibration 8us count value 16 8 read-write RX_SLOPE RX frequency curve slope 24 6 read-write XTL_CODE Reserved 0x34 32 read-only 0x3F 0x13F XTL_XICTRL_CODE crystal calibration code 0 6 read-only XTL_AMP_DET_OUT crystal comparator output result 8 1 read-only XTL_CFG Reserved 0x38 32 read-write 0x3F 0xFF XTL_XICTRL_CFG crystal calibration CFG 0 6 read-write XTL_CAL_DIS crystal code disable 6 1 read-write XTL_CAL_REQ crystal calibration request 7 1 read-write CAL_DLY hop calibration delay bypass 0x3C 32 read-write 0x36464113 0xFFFFFFBF HOP_DLY hop calibration delay time 0 6 read-write HOP_DLY_BP hop calibration delay bypass 7 1 read-write TX_DLY_DIG1M no description available 8 2 read-write TX_DLY_DIG2M no description available 10 2 read-write TX_DLY_DAC_1M no description available 12 2 read-write TX_DLY_DAC_2M no description available 14 2 read-write RX_PWRUP_CNT_TH1M no description available 16 8 read-write RX_PWRUP_CNT_TH2M no description available 24 8 read-write DONE Reserved 0x40 32 read-only 0x1FDC 0x1FFC OSC_CAL_DONE OSC calibration done 2 1 read-only REF_CAL_DONE REF PLL calibration done 3 1 read-only RCO_CAL_DONE RCO calibration done 4 1 read-only RC_CAL_DONE RC calibration done 5 1 read-only VCOF_CAL_DONE VCO frequency calibration done 6 1 read-only VCOA_CAL_DONE VCO amplitude calibration done 7 1 read-only DC2ND_CAL_DONE DC 2nd stage calibration done 8 1 read-only DC1ST_CAL_DONE DC 1st stage calibration done 9 1 read-only XTL_CAL_DONE XTL calibration done 10 1 read-only KVCO_CAL_DONE KVCO calibration done 11 1 read-only KVCO_HOP_DONE KVCO calibration done 12 1 read-only RRF1 Amplitude of LO buffer for active mixer 0x400 32 read-write 0xA8AADC44 0xFFFFFFFF RRF_INCAP2 LNA input LC cap bank 0 3 read-write RRF_LOAD_CAP LNA load LC cap bank 3 4 read-write RRF_TX_INCAP1 LNA&PA matching cap bank 7 3 read-write RRF_RX_INCAP1 LNA&PA matching cap bank 10 3 read-write RRF_VGATE11_LNA LNA vrega voltage 13 3 read-write RRF_BM_GM Constant gm current control 16 2 read-write RRF_BM_LNA LNA bias current control- 18 2 read-write RRF_BM_MIXER Mixer current bias 20 2 read-write PPF_DCCAL_RES Input res selection of ppf for dccal 22 2 read-write RRF_CAL_MIX_EN no description available 24 1 read-write RRF_CAL_MIX1_EN no description available 25 1 read-write RRF_LO_SEL_P Dc voltage bias control for the pmos switch of active mixer 26 2 read-write RRF_LO_SEL_N Dc voltage bias control for the nmos switch of active mixer 28 2 read-write RRF_LO_AMP Amplitude of LO buffer for active mixer 30 2 read-write PLL48_PPF reserved 0x404 32 read-write 0x5A 0xFF PPF_BM Ppf current control- 0 2 read-write PPF_IQSW no description available 2 1 read-write PLL48_DIFF_CLK_48M_DIS no description available 3 1 read-write PLL48_TST_CPREF CP current selecting 4 4 read-write LO0 reserved 0x408 32 read-write 0x8A8F50 0xFF8FFFFF VCO_DAC_IPTAT Set the temperature characteristic of TX DAC in order to compensate the modulation gain error of the VCO 0 4 read-write VCO_TST_CP LO CP current control- 4 4 read-write VCO_VTUN_SET Set VTUNE voltage change in order to properly compensate the VUNE error introduced by charge injection when the PLL loop is broken;VTUNE change introduced by this register is around 50uV*(VTUNE_SET-16) 8 5 read-write VCO_ACAL_SET Set the threshold (differential peak) in VCO amplitude calibration-VTH=0.2+0.05*ACAL_SET 13 3 read-write VCO_BM_TXFIL Set the bias current of the TX filter 16 2 read-write VCO_BM_TXDAC Set the bias current of the TX DAC 18 2 read-write VCO_SAMP_EN no description available 23 1 read-write VCO_CAP_HALF_EN no description available 24 1 read-write VCO_SET_VCO_VDD_LOW no description available 25 1 read-write VCO_8OR16M_INV_EN no description available 26 1 read-write VCO_DIV_PD_EN no description available 27 1 read-write VCO_TXDLY1M no description available 28 1 read-write VCO_TXDLY2M no description available 29 1 read-write VCO_RX_CK_TST no description available 30 1 read-write VCO_DSM_INT_EN no description available 31 1 read-write LO1 Reserved 0x40C 32 read-write 0xBA010 0xFFFFF SPEED_UP_TIME LO speed up time 0 5 read-write SW_LO_SPEED_UP software LO speed up 5 1 read-write RX_PLLPFD_EN PLL pfd enable in RX mode 6 1 read-write TX_PLLPFD_EN PLL pfd enable in TX mode 7 1 read-write LO_SET_TIME LO settle time 8 6 read-write MOD_TEST LO open loop or close loop select 14 1 read-write DIV_DIFF_CLK_LO_DIS no description available 15 1 read-write TX_VCO_FTC_SET no description available 16 2 read-write RX_VCO_FTC_SET no description available 18 2 read-write PA_CTRL Reserved 0x410 32 read-write 0xAC040A 0x1FF0F3F PA_ON_DLY PA turn on delay time 0 6 read-write PA_OFF_DLY PA turn off delay time 8 4 read-write PA_INCREASE_SEL PA output power increasing control 16 3 read-write PA_SEL_BIAS PA duty cycle voltage bias 19 1 read-write PA_BM_CUR Pa bias current control 20 2 read-write PA_VDUTY_CYCLE_SEL PA duty cycle control voltage select 22 2 read-write PA_VCDCG PA duty cycle control 24 1 read-write CTRL Reserved 0x800 32 read-write 0x50000 0x7F0113 RC_TIM RC calibration reset time 0 2 read-write VCO_TEST_INT no description available 4 1 read-write HOP_CLB_SEL Frequency hop calibration start select 8 1 read-write XTL_PO_TIM crystal calibration power on wait time 16 2 read-write XTL_CAL_TIM crystal calibration code wait time 18 2 read-write XTL_AMP_DET_PWR_SEL crystal amplitude detector power select 20 2 read-write PO1MS power on detector only 1ms each code 0 POCAL power on detector during all calibration time 0x1 POALWAYS always power on detector 0x2 PDALWAYS always power down detector 0x3 XTL_SWCAL_EN crystal software calibration enable 22 1 read-write INT_RAW Reserved 0x804 32 read-write 0 0x1013F PO_CAL_DONE_INT power on calibration done interrupt 0 1 read-write oneToClear HOP_CAL_DONE_INT hop calibration done interrupt 1 1 read-write oneToClear OSC_CAL_DONE_INT OSC calibration done interrupt 2 1 read-write oneToClear REF_CAL_DONE_INT REF PLL calibration done interrupt 3 1 read-write oneToClear RCO_CAL_DONE_INT RCO calibration done interrupt 4 1 read-write oneToClear XTL_CAL_DONE_INT XTL calibration done interrupt 5 1 read-write oneToClear PO_ALL_DONE_INT RCO & REF & OSC & Power on calibration all done interrupt. And signal of above interrupt 8 1 read-only CAL_INT or signal of all calibration interrupt 16 1 read-only INTEN Reserved 0x808 32 read-write 0 0x13F PO_CAL_DONE_INTEN power on calibration done interrupt enable 0 1 read-write HOP_CAL_DONE_INTEN hop calibration done interrupt enable 1 1 read-write OSC_CAL_DONE_INTEN OSC calibration done interrupt enable 2 1 read-write REF_CAL_DONE_INTEN REF PLL calibration done interrupt enable 3 1 read-write RCO_CAL_DONE_INTEN RCO calibration done interrupt enable 4 1 read-write XTL_CAL_DONE_INTEN XTL calibration done interrupt enable 5 1 read-write PO_ALL_DONE_INTEN PO_ALL_DONE_INT enable 8 1 read-write INT_STAT Reserved 0x80C 32 read-only 0 0x1013F PO_CAL_DONE_INT_STAT power on calibration done interrupt status 0 1 read-only HOP_CAL_DONE_INT_STAT hop calibration done interrupt status 1 1 read-only OSC_CAL_DONE_INT_STAT OSC calibration done interrupt status 2 1 read-only REF_CAL_DONE_INT_STAT REF PLL calibration done interrupt status 3 1 read-only RCO_CAL_DONE_INT_STAT RCO calibration done interrupt status 4 1 read-only XTL_CAL_DONE_INT_STAT XTL calibration done interrupt status 5 1 read-only PO_ALL_DONE_INT_STAT PO_ALL_DONE_INT status 8 1 read-only CAL_INT_STAT calibration all interrupt status 16 1 read-only TIF reserved 0x810 32 read-write 0 0xF TEST_CTRL Test interface selection 0 4 read-write KVCO_MEAN reserved 0x814 32 read-only 0 0x1FFFFF KVCO_CNT_MEAN KVCO counter 1 and counter 2 mean 0 21 read-only KVCO_DLT reserved 0x818 32 read-only 0 0x1FF KVCO_CNT_DLT KVCO counter 1 and counter 2 delta 0 9 read-only LO_CFG no description available 0x81C 32 read-write 0x3B6DB6E 0xCFFFFFFF LO_INT_CFG no description available 0 6 read-write LO_FRAC_CFG no description available 6 22 read-write LO_SEL no description available 30 1 read-write LO_CHANGE no description available 31 1 read-write LO_TABLE no description available 0x820 32 read-only 0x3B6DB6E 0x3FFFFFF LO_INT_TABLE no description available 0 6 read-only LO_FRAC_TABLE no description available 6 20 read-only LO_RATIO no description available 0x824 32 read-only 0x3B6DB6E 0xFFFFFFF LO_INT no description available 0 6 read-only LO_FRAC no description available 6 22 read-only VCO_MOD_CFG TRX 2M mode selection signal 0x828 32 read-write 0 0x1F VCO_MOD_TX_CFG VCO_MOD_TX register configured value. See section 6.10.5 for detail. 0 1 read-write VCO_MOD_TX_SEL VCO_MOD_TX selection 1 1 read-write TRX2M_MODE_CFG TRX 2M mode software configured value 2 1 read-write TRX2M_MODE_SEL TRX 2M mode selection signal 3 1 read-write IMR no description available 4 1 read-write VCO_MOD_STAT no description available 0x82C 32 read-only 0 0x5 VCO_MOD_TX no description available 0 1 read-only TRX2M_MODE no description available 2 1 read-only CH_IDX no description available 0x830 32 read-only 0x1 0xFF CH_IDX no description available 0 8 read-only VCOF_CNT_UP reserved 0x834 32 read-only 0 0xFF00FF TX_VCOF_CNT_UP TX VCO frequency power up calibration 8us count value 0 8 read-only RX_VCOF_CNT_UP RX VCO frequency power up calibration 8us count value 16 8 read-only VCOF_CNT_DN reserved 0x838 32 read-only 0 0xFF00FF TX_VCOF_CNT_DN TX VCO frequency power up calibration 8us count value 0 8 read-only RX_VCOF_CNT_DN RX VCO frequency power up calibration 8us count value 16 8 read-only SPIFI0 spifi SPIFI 0x40080000 0 0x20 registers CTRL SPIFI control register 0 32 read-write 0x400FFFFF 0xF8EFFFFF TIMEOUT This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again. 0 16 read-write CSHIGH This field controls the minimum CS high time, expressed as a number of serial clock periods minus one. 16 4 read-write D_PRFTCH_DIS This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses. 21 1 read-write INTEN If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details. 22 1 read-write MODE3 SPI Mode 3 select. 23 1 read-write SCK_LOW SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH. 0 SCK_HIGH SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame. 0x1 PRFTCH_DIS Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines. 27 1 read-write ENABLE Enable. Cache prefetching enabled. 0 DISABLE Disable. Disables prefetching of cache lines. 0x1 DUAL Select dual protocol. 28 1 read-write QUAD Quad protocol. This protocol uses IO3:0. 0 DUAL Dual protocol. This protocol uses IO1:0. 0x1 RFCLK Select active clock edge for input data. 29 1 read-write RISING_EDGE Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation. 0 FALLING_EDGE Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame. 0x1 FBCLK Feedback clock select. 30 1 read-write INTERNAL_CLOCK Internal clock. The SPIFI samples read data using an internal clock. 0 FEEDBACK_CLOCK Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame. 0x1 DMAEN A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used in Command mode. 31 1 read-write CMD SPIFI command register 0x4 32 read-write 0 0xFFFFFFFF DATALEN Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field. 0 14 read-write POLL This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs 14 1 read-write DOUT If the DATALEN field is not zero, this bit controls the direction of the data: 15 1 read-write INPUT Input from serial flash. 0 OUTPUT Output to serial flash. 0x1 INTLEN This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes. 16 3 read-write FIELDFORM This field controls how the fields of the command are sent. 19 2 read-write ALL_SERIAL All serial. All fields of the command are serial. 0 QUAD_DUAL_DATA Quad/dual data. Data field is quad/dual, other fields are serial. 0x1 SERIAL_OPCODE Serial opcode. Opcode field is serial. Other fields are quad/dual. 0x2 ALL_QUAD_DUAL All quad/dual. All fields of the command are in quad/dual format. 0x3 FRAMEFORM This field controls the opcode and address fields. 21 3 read-write OPCODE Opcode. Opcode only, no address. 0x1 OPCODE_1_BYTE Opcode one byte. Opcode, least significant byte of address. 0x2 OPCODE_2_BYTES Opcode two bytes. Opcode, two least significant bytes of address. 0x3 OPCODE_3_BYTES Opcode three bytes. Opcode, three least significant bytes of address. 0x4 OPCODE_4_BYTES Opcode four bytes. Opcode, 4 bytes of address. 0x5 NO_OPCODE_3_BYTES No opcode three bytes. No opcode, 3 least significant bytes of address. 0x6 NO_OPCODE_4_BYTES No opcode four bytes. No opcode, 4 bytes of address. 0x7 OPCODE The opcode of the command (not used for some FRAMEFORM values). 24 8 read-write ADDR SPIFI address register 0x8 32 read-write 0 0xFFFFFFFF ADDRESS Address. 0 32 read-write IDATA SPIFI intermediate data register 0xC 32 read-write 0 0xFFFFFFFF IDATA Value of intermediate bytes. 0 32 read-write CLIMIT SPIFI limit register 0x10 32 read-write 0x8000000 0xFFFFFFFF CLIMIT Zero-based upper limit of cacheable memory 0 32 read-write DATA SPIFI data register 0x14 32 read-write 0 0xFFFFFFFF DATA Input or output data 0 32 read-write MCMD SPIFI memory command register 0x18 32 read-write 0 0xFFFFC000 POLL This bit should be written as 0. 14 1 read-write DOUT This bit should be written as 0. 15 1 read-write INTLEN This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes. 16 3 read-write FIELDFORM This field controls how the fields of the command are sent. 19 2 read-write ALL_SERIAL All serial. All fields of the command are serial. 0 QUAD_DUAL_DATA Quad/dual data. Data field is quad/dual, other fields are serial. 0x1 SERIAL_OPCODE Serial opcode. Opcode field is serial. Other fields are quad/dual. 0x2 ALL_QUAD_DUAL All quad/dual. All fields of the command are in quad/dual format. 0x3 FRAMEFORM This field controls the opcode and address fields. 21 3 read-write OPCODE Opcode. Opcode only, no address. 0x1 OPCODE_1_BYTE Opcode one byte. Opcode, least-significant byte of address. 0x2 OPCODE_2_BYTES Opcode two bytes. Opcode, 2 least-significant bytes of address. 0x3 OPCODE_3_BYTES Opcode three bytes. Opcode, 3 least-significant bytes of address. 0x4 OPCODE_4_BYTES Opcode four bytes. Opcode, 4 bytes of address. 0x5 NO_OPCODE_3_BYTES No opcode three bytes. No opcode, 3 least-significant bytes of address. 0x6 NO_OPCODE_4_BYTES No opcode, 4 bytes of address. 0x7 OPCODE The opcode of the command (not used for some FRAMEFORM values). 24 8 read-write STAT SPIFI status register 0x1C 32 read-write 0x2000000 0xFF000033 MCINIT This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register. 0 1 read-write CMD This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash. 1 1 read-write RESET Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register. 4 1 read-write INTRQ This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS. 5 1 read-write VERSION - 24 8 read-write FLASH flash FLASH 0x40081000 0 0xB0 registers INI_RD_EN flash initial read register 0 32 read-write 0 0x1FBCFF0F INI_RD_EN enable contoller to automatically read GDR repaired information and lock bit 0 1 read-write ERASE_CTRL flash erase control register 0x4 32 read-write 0 0xFFFFFFFF PAGE_IDXL Low 256KB page erase index 0 7 read-write PAGE_IDXH High 256KB page erase index 8 7 read-write HALF_ERASEL_EN Write '1' to Enable Mass Erase Low 256KB Flash; Write '0' is inactive. This bit is set by software and reset at the end of low 256KB flash mass erase operation by hardware. 28 1 read-write HALF_ERASEH_EN Write '1' to Enable Mass Erase High 256KB Flash; Write '0' is inactive. This bit is set by software and reset at the end of high 256KB flash mass erase operation by hardware. 29 1 read-write PAGE_ERASEL_EN Low 256KB block page erase enable. This bit initiates a page erase operation when set. This bit is set by software and reset at the end of page erase operation by hardware. 30 1 read-write PAGE_ERASEH_EN High 256KB block page erase enable. This bit initiates a page erase operation when set. This bit is set by software and reset at the end of page erase operation by hardware. 31 1 read-write ERASE_TIME flash erase time setting register 0x8 32 read-write 0x9C400 0xFFFFFFFF ERASE_TIME_BASE Erase time, which is used to control Terase, Tme and Tsme. An 8MHz clock is to count the erase time. The maximum time of erase is 100ms. Default value is 640000 cycles in 8 MHz, that's 80 ms. User should set a pessimistic value to avoid possible error in erase operation. 0 20 read-write TIME_CTRL flash operation time setting register 0xC 32 read-write 0x4001E 0xFFFFFFFF PRGM_CYCLE Time base of some flash timing parameters, which represents 2 us. Default value is 64 cycles in 32 MHz (ahb clock). It is used in write and erase operations. 0 12 read-write TIME_BASE Max write operation times in one program, which are used to control Terase and Tme. User should set a pessimistic value to avoid possible error in erase/page erase operation. When user do write operation: It is used to limit allowed write numbers. (Max 21 ms-Tnvs-Tpgs-Tpgh-Tnvh)/18us = 1167 This register is only used when common write. 12 8 read-write SMART_CTRL smart erase control register 0x10 32 read-write 0x553C 0x3FF3F PRGML_EN It enable Low 256KB Flash write operation; 0 1 read-write PRGMH_EN It enable High 256KB Flash write operation; 1 1 read-write SMART_WRITEL_EN It enable Low 256KB Flash Smart program flow. When smart write is done, hardware automatically clear it 2 1 read-write SMART_WRITEH_EN It enable High 256KB Flash Smart program flow. When smart write is done, hardware automatically clear it 3 1 read-write SMART_ERASEL_EN It enable Low 256KB Flash Smart erase flow; When smart erase is done, hardware automatically clear it 4 1 read-write SMART_ERASEH_EN It enable High 256KB Flash Smart erase flow; When smart erase is done, hardware automatically clear it 5 1 read-write MAX_WRITE When smart program is used, this is the maximum retry number for one write operation. 8 4 read-write MAX_ERASE When smart erase is used, this is the maximum retry number for one erase operation. 12 6 read-write INTEN interrupt enable register 0x14 32 read-write 0 0x80000007 AHBL_INTEN low 256K flash AHB error interrupt enable 0 1 read-write LOCKL_INTEN low 256K flash lock error interrupt enable 1 1 read-write ERASEL_INTEN low 256K flash erase status interrupt enable 2 1 read-write WRITEL_INTEN low 256K flash write status interrupt enable 3 1 read-write WRBUFL_INTEN low 256K flash write buffer status interrupt enable 4 1 read-write AHBH_INTEN high 256K flash AHB error interrupt enable 8 1 read-write LOCKH_INTEN high 256K flash lock error interrupt enable 9 1 read-write ERASEH_INTEN high 256K flash erase status interrupt enable 10 1 read-write WRITEH_INTEN high 256K flash write status interrupt enable 11 1 read-write WRBUFH_INTEN high 256K flash write buffer status interrupt enable 12 1 read-write FLASH_INTEN flash total interrupt enable 31 1 read-write INT_STAT interrupt status register 0x18 32 read-write 0 0xFFFFFFFF AHBL_INT It is low 256KB Flash AHB error interrupt stat. 1 indicates AHB operation error AHB error include: Write/read unmapped space; AHB align rules violation; Byte/half-word Flash write operation; 0 1 read-write LOCKL_INT It is low 256KB Flash Lock page be accessed interrupt status 1 1 read-write ERASEL_INT It is low 256KB Erase operation done interrupt status If erase is used, it indicates one erase is done. 2 1 read-write WRITEL_INT It is low 256KB write operation done interrupt status If write is used, it indicates one program is done. 3 1 read-write WRBUFL_INT It is low 256KB Write Buffer empty interrupt status 0 = write buffer is not empty 1 = write buffer is empty It is auto cleared when write buffer is written. It is enabled only when PRGML_EN is enabled and write buffer is empty 4 1 read-write WRITE_FAIL_L_INT When smart write of low 256KB Flash is enable, 0 = Smart write is successful, 1 = Smart write is fail. 5 1 read-write ERASE_FAIL_L_INT When smart erase of low 256KB Flash is enable, 0 = Smart erase is successful, 1 = Smart erase is fail. 6 1 read-write AHBH_INT it is high 256KB Flash AHB error interrupt stat 1 indicates AHB operation error AHB error include: Write/read unmapped space; AHB align rules violation; Byte/half-word Flash write operation; 8 1 read-write LOCKH_INT it is high 256KB Flash Lock page be accessed interrupt status 9 1 read-write ERASEH_INT it is high 256KB Flash Erase operation done interrupt status If erase is used, it indicates one erase is done. 10 1 read-write WRITEH_INT it is high 256KB Flash write operation done interrupt status If write is used, it indicates one program is done. 11 1 read-write WRBUFH_INT it is high 256KB Flash Write Buffer empty interrupt status 0 = write buffer is not empty 1 = write buffer is empty It is auto cleared when write buffer is written. It is enabled only when PRGMH_EN is enabled and write buffer is empty 12 1 read-write WRITE_FAIL_H_INT When smart write of high 256KB Flash is enable, 0 = Smart write is successful, 1 = Smart write is fail. 13 1 read-write ERASE_FAIL_H_INT When smart erase of high 256KB Flash is enable, 0 = Smart erase is successful, 1 = Smart erase is fail. 14 1 read-write INTCLR interrupt clear register 0x1C 32 read-write 0 0xFFFFFFFF AHBL_INTCLR low 256K flash AHB error interrupt clear 0 1 read-write oneToClear LOCKL_INTCLR low 256K flash lock error interrupt clear 1 1 read-write oneToClear ERASEL_INTCLR low 256K flash erase status interrupt clear 2 1 read-write oneToClear WRITEL_INTCLR low 256K flash write status interrupt clear 3 1 read-write oneToClear AHBH_INTCLR high 256K flash AHB error interrupt clear 8 1 read-write oneToClear LOCKH_INTCLR high 256K flash lock error interrupt clear 9 1 read-write oneToClear ERASEH_INTCLR high 256K flash erase status interrupt clear 10 1 read-write oneToClear WRITEH_INTCLR high 256K flash write status interrupt clear 11 1 read-write oneToClear LOCK_STAT0 lock control register 0 0x20 32 read-only 0xFFFFFFFF 0xFFFFFFFF PAGE_LOCK0 Low 256K flash main memory page 0-31 write and erase lock status 0 32 read-only LOCK_STAT1 no description available 0x24 32 read-only 0xFFFFFFFF 0xFFFFFFFF PAGE_LOCK1 Low 256K flash main memory page 32-63 write and erase lock status 0 32 read-only LOCK_STAT2 no description available 0x28 32 read-only 0xFFFFFFFF 0xFFFFFFFF PAGE_LOCK2 Low 256K flash main memory page 64-95 write and erase lock status 0 32 read-only LOCK_STAT3 no description available 0x2C 32 read-only 0xFFFFFFFF 0xFFFFFFFF PAGE_LOCK3 Low 256K flash main memory page 96-127 write and erase lock status 0 32 read-only LOCK_STAT4 no description available 0x30 32 read-only 0xFFFFFFFF 0xFFFFFFFF PAGE_LOCK4 high 256K flash main memory page 0-31 write and erase lock status 0 32 read-only LOCK_STAT5 no description available 0x34 32 read-only 0xFFFFFFFF 0xFFFFFFFF PAGE_LOCK5 high 256K flash main memory page 32-63 write and erase lock status 0 32 read-only LOCK_STAT6 no description available 0x38 32 read-only 0xFFFFFFFF 0xFFFFFFFF PAGE_LOCK6 high 256K flash main memory page 64-95 write and erase lock status 0 32 read-only LOCK_STAT7 no description available 0x3C 32 read-only 0xFFFFFFFF 0xFFFFFFFF PAGE_LOCK7 high 256K flash main memory page 96-127 write and erase lock status 0 32 read-only LOCK_STAT8 no description available 0x40 32 read-write 0xF 0xFFFFFFFF MASS_ERASE_LOCK Mass erase operation lock status 0 : Mass erase operation is locked 1 : Mass erase operation is unlocked 0 1 read-write FSH_PROTECT SWD flash protection status 0 : flash is unprotected 1 : flash is protected 1 1 read-write MEM_PROTECT SWD memory protection status 0 : Memory is unprotected 1 : Memory is protected 2 1 read-write STATUS1 no description available 0x48 32 read-only 0x4010001 0xFFFFFFFF FSH_ERA_BUSY_L flash block 0 erase operation status 0 : no flash block 0 erase operation in progress. 1 : flash block 0 erase operation is in progress. 9 1 read-only FSH_WR_BUSY_L flash block 0 write operation status: 0 : no flash block 0 write operation in progress. 1 : flash block 0 write operation is in progress. 10 1 read-only DBG_ERA_DONE_L A flash block 0 debug initiated smart mass erase status. 0 : no debug port initiated flash block 0 smart mass erase operation in progress. 1 : debug port initiated flash block 0 smart mass erase operation in progress. 11 1 read-only FSH_ERA_BUSY_H flash block 1 erase operation status 0 : no flash block 1 erase operation in progress. 1 : flash block 1 erase operation is in progress. 12 1 read-only FSH_WR_BUSY_H flash block 1 write operation status: 0 : no flash block 1 write operation in progress. 1 : flash block 1 write operation is in progress. 13 1 read-only DBG_ERA_DONE_H A flash block 1 debug initiated smart mass erase status. 0 : no debug port initiated flash block 1 smart mass erase operation in progress. 1 : debug port initiated flash block 1 smart mass erase operation in progress. 14 1 read-only INI_RD_DONE flash initial read done. 15 1 read-only FSH_STA when 0 means data information is 0x55AA. 26 1 read-only RESERVED reserved 27 5 read-only ERR_INFOL1 no description available 0x5C 32 read-only 0 0xFFFFFFFF WR_FAILEDL_ADDR When a flash block 0 smart write fails, the address is stored in this bit filed 0 18 read-only SMART_FAILL_CTR The amount of fails during a smart write or smart erase is stored in this bit field 18 6 read-only ERR_INFOL2 no description available 0x60 32 read-only 0 0xFFFFFFFF WR_FAILEDL_DATA When a flash block 0 smart write fails, the data is stored in this bit field 0 32 read-only ERR_INFOL3 no description available 0x64 32 read-only 0 0xFFFFFFFF ERA_FAILEDL_INFO When a smart erase on flash block 0 fails, the address is stored in this bit field 0 18 read-only ERR_INFOH1 no description available 0x68 32 read-only 0 0xFFFFFFFF WR_FAILEDH_ADDR When a flash block 1 smart write fails, the address is stored in this bit field 0 18 read-only SMART_FAILH_CTR The amount of fails during a msart write or smart erase is stored int his bit field 18 6 read-only ERR_INFOH2 no description available 0x6C 32 read-only 0 0xFFFFFFFF WR_FAILEDH_DATA When a flash block 1 smart write fails, the data is stored in this bit field 0 32 read-only ERR_INFOH3 no description available 0x70 32 read-only 0 0xFFFFFFFF ERA_FAILEDH_INFO when a smart erase on flash block 1 fails, the address is stored in this bit field 0 18 read-only DEBUG_PASSWORD no description available 0xA8 32 read-write 0 0xFFFFFFFF DEBUG_PASSWORD An SWD initiated smart mass erase operation will only be issued if this register is programmed with the value 0xCA1E093F. 0 32 read-write ERASE_PASSWORD no description available 0xAC 32 read-write 0 0xFFFFFFFF ERASE_PASSWORD When this register is programmed with the value 0xCA1E093F, a FW initiated mass erase or page erase operation will bypass the current lock and protection scheme. 0 32 read-write DMA0 LPC5411x DMA controller DMA 0x40082000 0 0x53C registers CTRL DMA control. 0 32 read-write 0 0x1 ENABLE DMA controller master enable. 0 1 read-write DISABLED Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. 0 ENABLED Enabled. The DMA controller is enabled. 0x1 INTSTAT Interrupt status. 0x4 32 read-only 0 0x6 ACTIVEINT Summarizes whether any enabled interrupts (other than error interrupts) are pending. 1 1 read-only NOT_PENDING Not pending. No enabled interrupts are pending. 0 PENDING Pending. At least one enabled interrupt is pending. 0x1 ACTIVEERRINT Summarizes whether any error interrupts are pending. 2 1 read-only NOT_PENDING Not pending. No error interrupts are pending. 0 PENDING Pending. At least one error interrupt is pending. 0x1 SRAMBASE SRAM address of the channel configuration table. 0x8 32 read-write 0 0xFFFFFE00 OFFSET Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary. 9 23 read-write ENABLESET0 Channel Enable read and Set for all DMA channels. 0x20 32 read-write 0 0xFFFFFFFF ENA Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. 0 32 read-write ENABLECLR0 Channel Enable Clear for all DMA channels. 0x28 32 write-only 0 0 CLR Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 32 write-only ACTIVE0 Channel Active status for all DMA channels. 0x30 32 read-only 0 0xFFFFFFFF ACT Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. 0 32 read-only BUSY0 Channel Busy status for all DMA channels. 0x38 32 read-only 0 0xFFFFFFFF BSY Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. 0 32 read-only ERRINT0 Error Interrupt status for all DMA channels. 0x40 32 read-write 0 0xFFFFFFFF ERR Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is not active. 1 = error interrupt is active. 0 32 read-write INTENSET0 Interrupt Enable read and Set for all DMA channels. 0x48 32 read-write 0 0xFFFFFFFF INTEN Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. 0 32 read-write INTENCLR0 Interrupt Enable Clear for all DMA channels. 0x50 32 write-only 0 0 CLR Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 32 write-only INTA0 Interrupt A status for all DMA channels. 0x58 32 read-write 0 0xFFFFFFFF IA Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active. 0 32 read-write INTB0 Interrupt B status for all DMA channels. 0x60 32 read-write 0 0xFFFFFFFF IB Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active. 0 32 read-write SETVALID0 Set ValidPending control bits for all DMA channels. 0x68 32 write-only 0 0 SV SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n 0 32 write-only SETTRIG0 Set Trigger control bits for all DMA channels. 0x70 32 write-only 0 0 TRIG Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the TRIG bit for DMA channel n. 0 32 write-only ABORT0 Channel Abort control for all DMA channels. 0x78 32 write-only 0 0 ABORTCTRL Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n. 0 32 write-only 20 0x10 CHANNEL[%s] no description available 0x400 CFG Configuration register for DMA channel . 0 32 read-write 0 0x7CF73 PERIPHREQEN Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. 0 1 read-write DISABLED Disabled. Peripheral DMA requests are disabled. 0 ENABLED Enabled. Peripheral DMA requests are enabled. 0x1 HWTRIGEN Hardware Triggering Enable for this channel. 1 1 read-write DISABLED Disabled. Hardware triggering is not used. 0 ENABLED Enabled. Use hardware triggering. 0x1 TRIGPOL Trigger Polarity. Selects the polarity of a hardware trigger for this channel. 4 1 read-write ACTIVE_LOW_FALLING Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. 0 ACTIVE_HIGH_RISING Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. 0x1 TRIGTYPE Trigger Type. Selects hardware trigger as edge triggered or level triggered. 5 1 read-write EDGE Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. 0 LEVEL Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. 0x1 TRIGBURST Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. 6 1 read-write SINGLE Single transfer. Hardware trigger causes a single transfer. 0 BURST Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. 0x1 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size. 8 4 read-write SRCBURSTWRAP Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. 14 1 read-write DISABLED Disabled. Source burst wrapping is not enabled for this DMA channel. 0 ENABLED Enabled. Source burst wrapping is enabled for this DMA channel. 0x1 DSTBURSTWRAP Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. 15 1 read-write DISABLED Disabled. Destination burst wrapping is not enabled for this DMA channel. 0 ENABLED Enabled. Destination burst wrapping is enabled for this DMA channel. 0x1 CHPRIORITY Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority. 16 3 read-write CTLSTAT Control and status register for DMA channel . 0x4 32 read-only 0 0x5 VALIDPENDING Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. 0 1 read-only NO_EFFECT No effect. No effect on DMA operation. 0 VALID_PENDING Valid pending. 0x1 TRIG Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. 2 1 read-only NOT_TRIGGERED Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. 0 TRIGGERED Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. 0x1 XFERCFG Transfer configuration register for DMA channel . 0x8 32 read-write 0 0x3FFF33F CFGVALID Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. 0 1 read-write NOT_VALID Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. 0 VALID Valid. The current channel descriptor is considered valid. 0x1 RELOAD Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. 1 1 read-write DISABLED Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. 0 ENABLED Enabled. Reload the channels' control structure when the current descriptor is exhausted. 0x1 SWTRIG Software Trigger. 2 1 read-write NOT_SET Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. 0 SET Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. 0x1 CLRTRIG Clear Trigger. 3 1 read-write NOT_CLEARED Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. 0 CLEARED Cleared. The trigger is cleared when this descriptor is exhausted 0x1 SETINTA Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 4 1 read-write NO_EFFECT No effect. 0 SET Set. The INTA flag for this channel will be set when the current descriptor is exhausted. 0x1 SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. 5 1 read-write NO_EFFECT No effect. 0 SET Set. The INTB flag for this channel will be set when the current descriptor is exhausted. 0x1 WIDTH Transfer width used for this DMA channel. 8 2 read-write BIT_8 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). 0 BIT_16 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). 0x1 BIT_32 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). 0x2 SRCINC Determines whether the source address is incremented for each DMA transfer. 12 2 read-write NO_INCREMENT No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. 0 WIDTH_X_1 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. 0x1 WIDTH_X_2 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. 0x2 WIDTH_X_4 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. 0x3 DSTINC Determines whether the destination address is incremented for each DMA transfer. 14 2 read-write NO_INCREMENT No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. 0 WIDTH_X_1 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. 0x1 WIDTH_X_2 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. 0x2 WIDTH_X_4 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. 0x3 XFERCOUNT Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed. 16 10 read-write FLEXCOMM0 flexcomm FLEXCOMM FLEXCOMM 0x40083000 0 0x1000 registers IOMODE io mode register 0xF00 32 read-write 0 0x3 DIO_MODE IO mode register, SPI share MISO/MOSI at MOSI, USART share TXD/RXD at RXD 0 1 read-write NOSHAREPIN do not share pin 0 SHAREPIN share pin 0x1 DIO_OEN shared pin direction register 1 1 read-write SP_NOEN shared pin do not output 0 SP_OEN shared pin output enable 0x1 PSELID Peripheral Select and Flexcomm ID register. 0xFF8 32 read-write 0x101000 0xFFFFF1FF PERSEL Peripheral Select. This field is writable by software. 0 3 read-write NO_PERIPH_SELECTED No peripheral selected. 0 USART USART function selected. 0x1 SPI SPI function selected. 0x2 I2C I2C function selected. 0x3 I2S_TRANSMIT I2S transmit function selected. 0x4 I2S_RECEIVE I2S receive function selected. 0x5 LOCK Lock the peripheral select. This field is writable by software. 3 1 read-write UNLOCKED Peripheral select can be changed by software. 0 LOCKED Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. 0x1 USARTPRESENT USART present indicator. This field is Read-only. 4 1 read-only NOT_PRESENT This Flexcomm does not include the USART function. 0 PRESENT This Flexcomm includes the USART function. 0x1 SPIPRESENT SPI present indicator. This field is Read-only. 5 1 read-only NOT_PRESENT This Flexcomm does not include the SPI function. 0 PRESENT This Flexcomm includes the SPI function. 0x1 I2CPRESENT I2C present indicator. This field is Read-only. 6 1 read-only NOT_PRESENT This Flexcomm does not include the I2C function. 0 PRESENT This Flexcomm includes the I2C function. 0x1 I2SPRESENT I 2S present indicator. This field is Read-only. 7 1 read-only NOT_PRESENT This Flexcomm does not include the I2S function. 0 PRESENT This Flexcomm includes the I2S function. 0x1 SC3W Smart card/SPI 3 wire mode feature indicator. This field is Read-only 8 1 read-only NOT_PRESENT This Flexcomm does not support smart card/SPI 3 wire mdoe feature 0 PRESENT This Flexcomm support smart card/SPI 3 wire mode feature 0x1 ID Flexcomm ID. 12 20 read-only PID Peripheral identification register. 0xFFC 32 read-only 0 0xFFFFFF00 Minor_Rev Minor revision of module implementation. 8 4 read-only Major_Rev Major revision of module implementation. 12 4 read-only ID Module identifier for the selected function. 16 16 read-only FLEXCOMM1 flexcomm FLEXCOMM 0x40086000 0 0x1000 registers FLEXCOMM2 flexcomm FLEXCOMM 0x40087000 0 0x1000 registers FLEXCOMM3 flexcomm FLEXCOMM 0x4008F000 0 0x1000 registers USART0 FLEXCOMM0 usart USART USART 0x40083000 0 0x1000 registers CFG USART Configuration register. Basic USART configuration settings that typically are not changed during operation. 0 32 read-write 0 0xFDDBFD ENABLE USART Enable. 0 1 read-write DISABLED Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. 0 ENABLED Enabled. The USART is enabled for operation. 0x1 DATALEN Selects the data size for the USART. 2 2 read-write _7_BIT 7 bit Data length. 0 _8_BIT 8 bit Data length. 0x1 _9_BIT 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. 0x2 PARITYSEL Selects what type of parity is used by the USART. 4 2 read-write NO_PARITY No parity. 0 EVEN_PARITY Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. 0x2 ODD_PARITY Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. 0x3 STOPLEN Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 6 1 read-write _1_BIT 1 stop bit. 0 _2_BITS 2 stop bits. This setting should only be used for asynchronous communication. 0x1 MODE32K Selects standard or 32 kHz clocking mode. 7 1 read-write DISABLED Disabled. USART uses standard clocking. 0 ENABLED Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. 0x1 LINMODE LIN break mode enable. 8 1 read-write DISABLED Disabled. Break detect and generate is configured for normal operation. 0 ENABLED Enabled. Break detect and generate is configured for LIN bus operation. 0x1 CTSEN CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART'-s own RTS if loopback mode is enabled. 9 1 read-write DISABLED No flow control. The transmitter does not receive any automatic flow control signal. 0 ENABLED Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. 0x1 SYNCEN Selects synchronous or asynchronous operation. 11 1 read-write ASYNCHRONOUS_MODE Asynchronous mode. 0 SYNCHRONOUS_MODE Synchronous mode. 0x1 CLKPOL Selects the clock polarity and sampling edge of received data in synchronous mode. 12 1 read-write FALLING_EDGE Falling edge. Un_RXD is sampled on the falling edge of SCLK. 0 RISING_EDGE Rising edge. Un_RXD is sampled on the rising edge of SCLK. 0x1 SYNCMST Synchronous mode Master select. 14 1 read-write SLAVE Slave. When synchronous mode is enabled, the USART is a slave. 0 MASTER Master. When synchronous mode is enabled, the USART is a master. 0x1 LOOP Selects data loopback mode. 15 1 read-write NORMAL Normal operation. 0 LOOPBACK Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. 0x1 OETA Output Enable Turnaround time enable for RS-485 operation. 18 1 read-write DISABLED Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. 0 ENABLED Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. 0x1 AUTOADDR Automatic Address matching enable. 19 1 read-write DISABLED Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). 0 ENABLED Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. 0x1 OESEL Output Enable Select. 20 1 read-write STANDARD Standard. The RTS signal is used as the standard flow control function. 0 RS_485 RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. 0x1 OEPOL Output Enable Polarity. 21 1 read-write LOW Low. If selected by OESEL, the output enable is active low. 0 HIGH High. If selected by OESEL, the output enable is active high. 0x1 RXPOL Receive data polarity. 22 1 read-write STANDARD Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. 0 INVERTED Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. 0x1 TXPOL Transmit data polarity. 23 1 read-write STANDARD Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. 0 INVERTED Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. 0x1 CTL USART Control register. USART control settings that are more likely to change during operation. 0x4 32 read-write 0 0x10346 TXBRKEN Break Enable. 1 1 read-write NORMAL Normal operation. 0 CONTINOUS Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. 0x1 ADDRDET Enable address detect mode. 2 1 read-write DISABLED Disabled. The USART presents all incoming data. 0 ENABLED Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. 0x1 TXDIS Transmit Disable. 6 1 read-write ENABLED Not disabled. USART transmitter is not disabled. 0 DISABLED Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. 0x1 CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 8 1 read-write CLOCK_ON_CHARACTER Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. 0 CONTINOUS_CLOCK Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). 0x1 CLRCCONRX Clear Continuous Clock. 9 1 read-write NO_EFFECT No effect. No effect on the CC bit. 0 AUTO_CLEAR Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. 0x1 AUTOBAUD Autobaud enable. 16 1 read-write DISABLED Disabled. USART is in normal operating mode. 0 ENABLED Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. 0x1 STAT USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x8 32 read-write 0xA 0x45A RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. 1 1 read-only TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. 3 1 read-only CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. 4 1 read-only DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. 5 1 write-only TXDISSTAT Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). 6 1 read-only RXBRK Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. 10 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. Cleared by software. 11 1 write-only START This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software. 12 1 write-only FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 write-only PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. 14 1 write-only RXNOISEINT Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. 15 1 write-only ABERR Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out. 16 1 write-only INTENSET Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0xC 32 read-write 0 0x1F868 TXIDLEEN When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). 3 1 read-write DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. 5 1 read-write TXDISEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 6 1 read-write DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). 11 1 read-write STARTEN When 1, enables an interrupt when a received start bit has been detected. 12 1 read-write FRAMERREN When 1, enables an interrupt when a framing error has been detected. 13 1 read-write PARITYERREN When 1, enables an interrupt when a parity error has been detected. 14 1 read-write RXNOISEEN When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. 15 1 read-write ABERREN When 1, enables an interrupt when an auto baud error occurs. 16 1 read-write INTENCLR Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. 0x10 32 write-only 0 0 TXIDLECLR Writing 1 clears the corresponding bit in the INTENSET register. 3 1 write-only DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. 5 1 write-only TXDISCLR Writing 1 clears the corresponding bit in the INTENSET register. 6 1 write-only DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. 11 1 write-only STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. 12 1 write-only FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 13 1 write-only PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 14 1 write-only RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. 15 1 write-only ABERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 16 1 write-only BRG Baud Rate Generator register. 16-bit integer baud rate divisor value. 0x20 32 read-write 0 0xFFFF BRGVAL This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. 0 16 read-write INTSTAT Interrupt status register. Reflects interrupts that are currently enabled. 0x24 32 read-only 0 0x1F968 TXIDLE Transmitter Idle status. 3 1 read-only DELTACTS This bit is set when a change in the state of the CTS input is detected. 5 1 read-only TXDISINT Transmitter Disabled Interrupt flag. 6 1 read-only DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. 11 1 read-only START This bit is set when a start is detected on the receiver input. 12 1 read-only FRAMERRINT Framing Error interrupt flag. 13 1 read-only PARITYERRINT Parity Error interrupt flag. 14 1 read-only RXNOISEINT Received Noise interrupt flag. 15 1 read-only ABERRINT Auto baud Error Interrupt flag. 16 1 read-only OSR Oversample selection register for asynchronous communication. 0x28 32 read-write 0xF 0xF OSRVAL Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. 0 4 read-write ADDR Address register for automatic address matching. 0x2C 32 read-write 0 0xFF ADDRESS 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). 0 8 read-write FIFOCFG FIFO configuration and enable register. 0xE00 32 read-write 0 0x7F033 ENABLETX Enable the transmit FIFO. 0 1 read-write DISABLED The transmit FIFO is not enabled. 0 ENABLED The transmit FIFO is enabled. 0x1 ENABLERX Enable the receive FIFO. 1 1 read-write DISABLED The receive FIFO is not enabled. 0 ENABLED The receive FIFO is enabled. 0x1 SIZE FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. 4 2 read-only DMATX DMA configuration for transmit. 12 1 read-write DISABLED DMA is not used for the transmit function. 0 ENABLED Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 0x1 DMARX DMA configuration for receive. 13 1 read-write DISABLED DMA is not used for the receive function. 0 ENABLED Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 0x1 EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 16 1 read-write EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 17 1 read-write FIFOSTAT FIFO status register. 0xE04 32 read-write 0x30 0x1F1FFB TXERR TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. 0 1 read-write RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral'-s STAT register. 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. 16 5 read-only FIFOTRIG FIFO trigger settings for interrupt and DMA request. 0xE08 32 read-write 0 0xF0F03 TXLVLENA Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 0 1 read-write DISABLED Transmit FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 0x1 RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 1 1 read-write DISABLED Receive FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 0x1 TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full). 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full). 16 4 read-write FIFOINTENSET FIFO interrupt enable set (enable) and read register. 0xE10 32 read-write 0 0xF TXERR Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 0 1 read-write DISABLED No interrupt will be generated for a transmit error. 0 ENABLED An interrupt will be generated when a transmit error occurs. 0x1 RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 1 1 read-write DISABLED No interrupt will be generated for a receive error. 0 ENABLED An interrupt will be generated when a receive error occurs. 0x1 TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 2 1 read-write DISABLED No interrupt will be generated based on the TX FIFO level. 0 ENABLED If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. 0x1 RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 3 1 read-write DISABLED No interrupt will be generated based on the RX FIFO level. 0 ENABLED If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. 0x1 FIFOINTENCLR FIFO interrupt enable clear (disable) and read register. 0xE14 32 read-write 0 0xF TXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 0 1 read-write RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 3 1 read-write FIFOINTSTAT FIFO interrupt status register. 0xE18 32 read-only 0 0x1F TXERR TX FIFO error. 0 1 read-only RXERR RX FIFO error. 1 1 read-only TXLVL Transmit FIFO level interrupt. 2 1 read-only RXLVL Receive FIFO level interrupt. 3 1 read-only PERINT Peripheral interrupt. 4 1 read-only FIFOWR FIFO write data. 0xE20 32 read-write 0 0 TXDATA Transmit data to the FIFO. 0 9 write-only FIFORD FIFO read data. 0xE30 32 read-only 0 0xE1FF RXDATA Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. 0 9 read-only FRAMERR Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-only PARITYERR Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. 14 1 read-only RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 354. 15 1 read-only FIFORDNOPOP FIFO data read with no FIFO pop. 0xE40 32 read-only 0 0xE1FF RXDATA Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. 0 9 read-only FRAMERR Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 13 1 read-only PARITYERR Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character. 14 1 read-only RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 354. 15 1 read-only ID USART module Identification. This value appears in the shared Flexcomm peripheral ID register when USART is selected. 0xFFC 32 read-only 0xE0100000 0xFFFFFFFF APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only MINOR_REV Minor revision of module implementation, starting at 0. Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions. 8 4 read-only MAJOR_REV Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions. 12 4 read-only ID Unique module identifier for this IP block. 16 16 read-only USART1 FLEXCOMM1 usart USART 0x40086000 0 0x1000 registers USB0 usb USB 0x40084000 0 0x38 registers DEVCMDSTAT USB Device Command/Status register 0 32 read-write 0x800 0x171BFBFF DEV_ADDR USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request. 0 7 read-write DEV_EN USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. 7 1 read-write SETUP SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. 8 1 read-write FORCE_NEEDCLK Forces the NEEDCLK output to always be on: 9 1 read-write NORMAL USB_NEEDCLK has normal function. 0 ALWAYS_ON USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. 0x1 LPM_SUP LPM Supported: 11 1 read-write NO LPM not supported. 0 YES LPM supported. 0x1 INTONNAK_AO Interrupt on NAK for interrupt and bulk OUT EP 12 1 read-write DISABLED Only acknowledged packets generate an interrupt 0 ENABLED Both acknowledged and NAKed packets generate interrupts. 0x1 INTONNAK_AI Interrupt on NAK for interrupt and bulk IN EP 13 1 read-write DISABLED Only acknowledged packets generate an interrupt 0 ENABLED Both acknowledged and NAKed packets generate interrupts. 0x1 INTONNAK_CO Interrupt on NAK for control OUT EP 14 1 read-write DISABLED Only acknowledged packets generate an interrupt 0 ENABLED Both acknowledged and NAKed packets generate interrupts. 0x1 INTONNAK_CI Interrupt on NAK for control IN EP 15 1 read-write DISABLED Only acknowledged packets generate an interrupt 0 ENABLED Both acknowledged and NAKed packets generate interrupts. 0x1 DCON Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one. 16 1 read-write DSUS Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn'-t seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect. 17 1 read-write LPM_SUS Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one. 19 1 read-write LPM_REWP LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction. 20 1 read-only DCON_C Device status - connect change. The Connect Change bit is set when the device'-s pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. 24 1 read-write DSUS_C Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it. 25 1 read-write DRES_C Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it. 26 1 read-write VBUSDEBOUNCED This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. 28 1 read-only INFO USB Info register 0x4 32 read-write 0 0x7FFF FRAME_NR Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device. 0 11 read-only ERR_CODE The error code which last occurred: 11 4 read-write NO_ERROR No error 0 PID_ENCODING_ERROR PID encoding error 0x1 PID_UNKNOWN PID unknown 0x2 PACKET_UNEXPECTED Packet unexpected 0x3 TOKEN_CRC_ERROR Token CRC error 0x4 DATA_CRC_ERROR Data CRC error 0x5 TIMEOUT Time out 0x6 BABBLE Babble 0x7 TRUNCATED_EOP Truncated EOP 0x8 SENT_RECEIVED_NAK Sent/Received NAK 0x9 SENT_STALL Sent Stall 0xA OVERRUN Overrun 0xB SENT_EMPTY_PACKET Sent empty packet 0xC BITSTUFF_ERROR Bitstuff error 0xD SYNC_ERROR Sync error 0xE WRONG_DATA_TOGGLE Wrong data toggle 0xF EPLISTSTART USB EP Command/Status List start address 0x8 32 read-write 0 0xFFFFFF00 EP_LIST Start address of the USB EP Command/Status List. 8 24 read-write DATABUFSTART USB Data buffer start address 0xC 32 read-write 0 0xFFC00000 DA_BUF Start address of the buffer pointer page where all endpoint data buffers are located. 22 10 read-write LPM USB Link Power Management register 0x10 32 read-write 0 0x1FF HIRD_HW Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token 0 4 read-only HIRD_SW Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. 4 4 read-write DATA_PENDING As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1. 8 1 read-write EPSKIP USB Endpoint skip 0x14 32 read-write 0 0x3FFFFFFF SKIP Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. 0 30 read-write EPINUSE USB Endpoint Buffer in use 0x18 32 read-write 0 0x3FC BUF Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1. 2 8 read-write EPBUFCFG USB Endpoint Buffer Configuration register 0x1C 32 read-write 0 0x3FC BUF_SB Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer. 2 8 read-write INTSTAT USB interrupt status register 0x20 32 read-write 0 0xC000FFFF EP0OUT Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it. 0 1 read-write EP0IN Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it. 1 1 read-write EP1OUT Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it. 2 1 read-write EP1IN Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it. 3 1 read-write EP2OUT Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it. 4 1 read-write EP2IN Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it. 5 1 read-write EP3OUT Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it. 6 1 read-write EP3IN Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it. 7 1 read-write EP4OUT Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it. 8 1 read-write EP4IN Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it. 9 1 read-write EP5OUT Interrupt status register bit for the EP5 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP5 OUT direction. Software can clear this bit by writing a one to it. 10 1 read-write EP5IN Interrupt status register bit for the EP5 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP5 IN direction. Software can clear this bit by writing a one to it. 11 1 read-write EP6OUT Interrupt status register bit for the EP6 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP6 OUT direction. Software can clear this bit by writing a one to it. 12 1 read-write EP6IN Interrupt status register bit for the EP6 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP6 IN direction. Software can clear this bit by writing a one to it. 13 1 read-write EP7OUT Interrupt status register bit for the EP7 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP7 OUT direction. Software can clear this bit by writing a one to it. 14 1 read-write EP7IN Interrupt status register bit for the EP7 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP7 IN direction. Software can clear this bit by writing a one to it. 15 1 read-write FRAME_INT Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it. 30 1 read-write DEV_INT Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it. 31 1 read-write INTEN USB interrupt enable register 0x24 32 read-write 0 0xC000FFFF EP_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. 0 16 read-write FRAME_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. 30 1 read-write DEV_INT_EN If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit. 31 1 read-write INTSETSTAT USB set interrupt status register 0x28 32 read-write 0 0xC000FFFF EP_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. 0 16 read-write FRAME_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. 30 1 read-write DEV_SET_INT If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned. 31 1 read-write EPTOGGLE USB Endpoint toggle register 0x34 32 read-only 0 0xFFFF TOGGLE Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. 0 16 read-only SCT0 LPC5411x SCTimer/PWM (SCT) SCT 0x40085000 0 0x800 registers CONFIG SCT configuration register 0 32 read-write 0x1E00 0x61FFF UNIFY SCT operation 0 1 read-write DUAL_COUNTER The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. 0 UNIFIED_COUNTER The SCT operates as a unified 32-bit counter. 0x1 CLKMODE SCT clock mode 1 2 read-write SYSTEM_CLOCK_MODE System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. 0 SAMPLED_SYSTEM_CLOCK_MODE Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. 0x1 SCT_INPUT_CLOCK_MODE SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. 0x2 ASYNCHRONOUS_MODE Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. 0x3 CKSEL SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. 3 4 read-write INPUT_0_RISING_EDGES Rising edges on input 0. 0 INPUT_0_FALLING_EDGE Falling edges on input 0. 0x1 INPUT_1_RISING_EDGES Rising edges on input 1. 0x2 INPUT_1_FALLING_EDGE Falling edges on input 1. 0x3 INPUT_2_RISING_EDGES Rising edges on input 2. 0x4 INPUT_2_FALLING_EDGE Falling edges on input 2. 0x5 INPUT_3_RISING_EDGES Rising edges on input 3. 0x6 INPUT_3_FALLING_EDGE Falling edges on input 3. 0x7 NORELAOD_L A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 7 1 read-write NORELOAD_H A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. 8 1 read-write INSYNC Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field. 9 4 read-write AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 17 1 read-write AUTOLIMIT_H A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. 18 1 read-write CTRL SCT control register 0x4 32 read-write 0x40004 0x1FFF1FFF DOWN_L This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. 0 1 read-write STOP_L When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. 1 1 read-write HALT_L When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. 2 1 read-write CLRCTR_L Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. 3 1 read-write BIDIR_L L or unified counter direction select 4 1 read-write UP Up. The counter counts up to a limit condition, then is cleared to zero. 0 UP_DOWN Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. 0x1 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 5 8 read-write DOWN_H This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. 16 1 read-write STOP_H When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. 17 1 read-write HALT_H When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. 18 1 read-write CLRCTR_H Writing a 1 to this bit clears the H counter. This bit always reads as 0. 19 1 read-write BIDIR_H Direction select 20 1 read-write UP The H counter counts up to its limit condition, then is cleared to zero. 0 UP_DOWN The H counter counts up to its limit, then counts down to a limit condition or to 0. 0x1 PRE_H Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 21 8 read-write LIMIT SCT limit event select register 0x8 32 read-write 0 0xFFFFFFFF LIMMSK_L If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write LIMMSK_H If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 16 read-write HALT SCT halt event select register 0xC 32 read-write 0 0xFFFFFFFF HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 16 read-write STOP SCT stop event select register 0x10 32 read-write 0 0xFFFFFFFF STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write STOPMSK_H If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 16 read-write START SCT start event select register 0x14 32 read-write 0 0xFFFFFFFF STARTMSK_L If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write STARTMSK_H If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. 16 16 read-write COUNT SCT counter register 0x40 32 read-write 0 0xFFFFFFFF CTR_L When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. 0 16 read-write CTR_H When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. 16 16 read-write STATE SCT state register 0x44 32 read-write 0 0x1F001F STATE_L State variable. 0 5 read-write STATE_H State variable. 16 5 read-write INPUT SCT input register 0x48 32 read-only 0 0xFFFFFFFF AIN0 Input 0 state. Input 0 state on the last SCT clock edge. 0 1 read-only AIN1 Input 1 state. Input 1 state on the last SCT clock edge. 1 1 read-only AIN2 Input 2 state. Input 2 state on the last SCT clock edge. 2 1 read-only AIN3 Input 3 state. Input 3 state on the last SCT clock edge. 3 1 read-only AIN4 Input 4 state. Input 4 state on the last SCT clock edge. 4 1 read-only AIN5 Input 5 state. Input 5 state on the last SCT clock edge. 5 1 read-only AIN6 Input 6 state. Input 6 state on the last SCT clock edge. 6 1 read-only AIN7 Input 7 state. Input 7 state on the last SCT clock edge. 7 1 read-only AIN8 Input 8 state. Input 8 state on the last SCT clock edge. 8 1 read-only AIN9 Input 9 state. Input 9 state on the last SCT clock edge. 9 1 read-only AIN10 Input 10 state. Input 10 state on the last SCT clock edge. 10 1 read-only AIN11 Input 11 state. Input 11 state on the last SCT clock edge. 11 1 read-only AIN12 Input 12 state. Input 12 state on the last SCT clock edge. 12 1 read-only AIN13 Input 13 state. Input 13 state on the last SCT clock edge. 13 1 read-only AIN14 Input 14 state. Input 14 state on the last SCT clock edge. 14 1 read-only AIN15 Input 15 state. Input 15 state on the last SCT clock edge. 15 1 read-only SIN0 Input 0 state. Input 0 state following the synchronization specified by INSYNC. 16 1 read-only SIN1 Input 1 state. Input 1 state following the synchronization specified by INSYNC. 17 1 read-only SIN2 Input 2 state. Input 2 state following the synchronization specified by INSYNC. 18 1 read-only SIN3 Input 3 state. Input 3 state following the synchronization specified by INSYNC. 19 1 read-only SIN4 Input 4 state. Input 4 state following the synchronization specified by INSYNC. 20 1 read-only SIN5 Input 5 state. Input 5 state following the synchronization specified by INSYNC. 21 1 read-only SIN6 Input 6 state. Input 6 state following the synchronization specified by INSYNC. 22 1 read-only SIN7 Input 7 state. Input 7 state following the synchronization specified by INSYNC. 23 1 read-only SIN8 Input 8 state. Input 8 state following the synchronization specified by INSYNC. 24 1 read-only SIN9 Input 9 state. Input 9 state following the synchronization specified by INSYNC. 25 1 read-only SIN10 Input 10 state. Input 10 state following the synchronization specified by INSYNC. 26 1 read-only SIN11 Input 11 state. Input 11 state following the synchronization specified by INSYNC. 27 1 read-only SIN12 Input 12 state. Input 12 state following the synchronization specified by INSYNC. 28 1 read-only SIN13 Input 13 state. Input 13 state following the synchronization specified by INSYNC. 29 1 read-only SIN14 Input 14 state. Input 14 state following the synchronization specified by INSYNC. 30 1 read-only SIN15 Input 15 state. Input 15 state following the synchronization specified by INSYNC. 31 1 read-only REGMODE SCT match/capture mode register 0x4C 32 read-write 0 0xFFFFFFFF REGMOD_L Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register. 0 16 read-write REGMOD_H Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers. 16 16 read-write OUTPUT SCT output register 0x50 32 read-write 0 0xFFFF OUT Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. 0 16 read-write OUTPUTDIRCTRL SCT output counter direction control register 0x54 32 read-write 0 0xFFFFFFFF SETCLR0 Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. 0 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR1 Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. 2 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. 4 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR3 Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. 6 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR4 Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. 8 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR5 Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. 10 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR6 Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. 12 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR7 Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. 14 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR8 Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. 16 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR9 Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. 18 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR10 Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. 20 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR11 Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. 22 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR12 Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. 24 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR13 Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. 26 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR14 Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. 28 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR15 Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. 30 2 read-write INDEPENDENT Set and clear do not depend on the direction of any counter. 0 L_REVERSED Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_REVERSED Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 RES SCT conflict resolution register 0x58 32 read-write 0 0xFFFFFFFF O0RES Effect of simultaneous set and clear on output 0. 0 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR0 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O1RES Effect of simultaneous set and clear on output 1. 2 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR1 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O2RES Effect of simultaneous set and clear on output 2. 4 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output n (or set based on the SETCLR2 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O3RES Effect of simultaneous set and clear on output 3. 6 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR3 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O4RES Effect of simultaneous set and clear on output 4. 8 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR4 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O5RES Effect of simultaneous set and clear on output 5. 10 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR5 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O6RES Effect of simultaneous set and clear on output 6. 12 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR6 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O7RES Effect of simultaneous set and clear on output 7. 14 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output n (or set based on the SETCLR7 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O8RES Effect of simultaneous set and clear on output 8. 16 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR8 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O9RES Effect of simultaneous set and clear on output 9. 18 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR9 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O10RES Effect of simultaneous set and clear on output 10. 20 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR10 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O11RES Effect of simultaneous set and clear on output 11. 22 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR11 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O12RES Effect of simultaneous set and clear on output 12. 24 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR12 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O13RES Effect of simultaneous set and clear on output 13. 26 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR13 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O14RES Effect of simultaneous set and clear on output 14. 28 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR14 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O15RES Effect of simultaneous set and clear on output 15. 30 2 read-write NO_CHANGE No change. 0 SET Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). 0x1 CLEAR Clear output (or set based on the SETCLR15 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 DMA0REQUEST SCT DMA request 0 register 0x5C 32 read-write 0 0xC000FFFF DEV_0 If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write DRL0 A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. 30 1 read-write DRQ0 This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. 31 1 read-write DMA1REQUEST SCT DMA request 1 register 0x60 32 read-write 0 0xC000FFFF DEV_1 If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write DRL1 A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. 30 1 read-write DRQ1 This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup. 31 1 read-write EVEN SCT event interrupt enable register 0xF0 32 read-write 0 0xFFFF IEN The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write EVFLAG SCT event flag register 0xF4 32 read-write 0 0xFFFF FLAG Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. 0 16 read-write CONEN SCT conflict interrupt enable register 0xF8 32 read-write 0 0xFFFF NCEN The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. 0 16 read-write CONFLAG SCT conflict flag register 0xFC 32 read-write 0 0xC000FFFF NCFLAG Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT. 0 16 read-write BUSERRL The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. 30 1 read-write BUSERRH The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. 31 1 read-write 10 0x4 SCTCAP[%s] SCT capture register of capture channel CAP_MATCH 0x100 32 read-write 0 0xFFFFFFFF CAPn_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. 0 16 read-write CAPn_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. 16 16 read-write 10 0x4 SCTMATCH[%s] SCT match value register of match channels CAP_MATCH 0x100 32 read-write 0 0xFFFFFFFF MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 0 16 read-write MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 16 16 read-write 10 0x4 SCTCAPCTRL[%s] SCT capture control register CAPCTRL_MATCHREL 0x200 32 read-write 0 0xFFFFFFFF CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 16 read-write CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 16 16 read-write 10 0x4 SCTMATCHREL[%s] SCT match reload value register CAPCTRL_MATCHREL 0x200 32 read-write 0 0xFFFFFFFF RELOADn_L When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 16 read-write RELOADn_H When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 16 16 read-write 10 0x8 EVENT[%s] no description available 0x300 STATE SCT event state register 0 0 32 read-write 0 0xFFFF STATEMSKn If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT. 0 16 read-write CTRL SCT event control register 0 0x4 32 read-write 0 0x7FFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. 0 4 read-write HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. 4 1 read-write L_COUNTER Selects the L state and the L match register selected by MATCHSEL. 0 H_COUNTER Selects the H state and the H match register selected by MATCHSEL. 0x1 OUTSEL Input/output select 5 1 read-write INPUT Selects the inputs selected by IOSEL. 0 OUTPUT Selects the outputs selected by IOSEL. 0x1 IOSEL Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. 6 4 read-write IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 10 2 read-write LOW LOW 0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. 12 2 read-write OR OR. The event occurs when either the specified match or I/O condition occurs. 0 MATCH MATCH. Uses the specified match only. 0x1 IO IO. Uses the specified I/O condition only. 0x2 AND AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. 14 1 read-write ADD STATEV value is added into STATE (the carry-out is ignored). 0 LOAD STATEV value is loaded into STATE. 0x1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. 15 5 read-write MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. 20 1 read-write DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. 21 2 read-write DIRECTION_INDEPENDENT Direction independent. This event is triggered regardless of the count direction. 0 COUNTING_UP Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 8 0x8 OUT[%s] no description available 0x500 SET SCT output 0 set register 0 32 read-write 0 0xFFFF SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 16 read-write CLR SCT output 0 clear register 0x4 32 read-write 0 0xFFFF CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register. 0 16 read-write MODULECONTENT Reserved 0x7FC 32 read-write 0 0xFFFFFFFF I2C0 FLEXCOMM1 i2c I2C I2C 0x40086000 0 0x1000 registers CFG Configuration for shared functions. 0x800 32 read-write 0 0x3F MSTEN Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. 0 1 read-write DISABLED Disabled. The I2C Master function is disabled. 0 ENABLED Enabled. The I2C Master function is enabled. 0x1 SLVEN Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. 1 1 read-write DISABLED Disabled. The I2C slave function is disabled. 0 ENABLED Enabled. The I2C slave function is enabled. 0x1 MONEN Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. 2 1 read-write DISABLED Disabled. The I2C Monitor function is disabled. 0 ENABLED Enabled. The I2C Monitor function is enabled. 0x1 TIMEOUTEN I2C bus Time-out Enable. When disabled, the time-out function is internally reset. 3 1 read-write DISABLED Disabled. Time-out function is disabled. 0 ENABLED Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. 0x1 MONCLKSTR Monitor function Clock Stretching. 4 1 read-write DISABLED Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. 0 ENABLED Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. 0x1 STAT Status register for Master, Slave, and Monitor functions. 0x804 32 read-write 0x801 0x30FFF5F MSTPENDING Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. 0 1 read-only IN_PROGRESS In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. 0 PENDING Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. 0x1 MSTSTATE Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. 1 3 read-only IDLE Idle. The Master function is available to be used for a new transaction. 0 RECEIVE_READY Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. 0x1 TRANSMIT_READY Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. 0x2 NACK_ADDRESS NACK Address. Slave NACKed address. 0x3 NACK_DATA NACK Data. Slave NACKed transmitted data. 0x4 MSTARBLOSS Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 4 1 read-write NO_LOSS No Arbitration Loss has occurred. 0 ARBITRATION_LOSS Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. 0x1 MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 6 1 read-write NO_ERROR No Start/Stop Error has occurred. 0 ERROR The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. 0x1 SLVPENDING Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. 8 1 read-only IN_PROGRESS In progress. The Slave function does not currently need service. 0 PENDING Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. 0x1 SLVSTATE Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. 9 2 read-only SLAVE_ADDRESS Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. 0 SLAVE_RECEIVE Slave receive. Received data is available (Slave Receiver mode). 0x1 SLAVE_TRANSMIT Slave transmit. Data can be transmitted (Slave Transmitter mode). 0x2 SLVNOTSTR Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. 11 1 read-only STRETCHING Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. 0 NOT_STRETCHING Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. 0x1 SLVIDX Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. 12 2 read-only ADDRESS0 Address 0. Slave address 0 was matched. 0 ADDRESS1 Address 1. Slave address 1 was matched. 0x1 ADDRESS2 Address 2. Slave address 2 was matched. 0x2 ADDRESS3 Address 3. Slave address 3 was matched. 0x3 SLVSEL Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. 14 1 read-only NOT_SELECTED Not selected. The Slave function is not currently selected. 0 SELECTED Selected. The Slave function is currently selected. 0x1 SLVDESEL Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. 15 1 read-write NOT_DESELECTED Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. 0 DESELECTED Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. 0x1 MONRDY Monitor Ready. This flag is cleared when the MONRXDAT register is read. 16 1 read-only NO_DATA No data. The Monitor function does not currently have data available. 0 DATA_WAITING Data waiting. The Monitor function has data waiting to be read. 0x1 MONOV Monitor Overflow flag. 17 1 read-write NO_OVERRUN No overrun. Monitor data has not overrun. 0 OVERRUN Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. 0x1 MONACTIVE Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. 18 1 read-only INACTIVE Inactive. The Monitor function considers the I2C bus to be inactive. 0 ACTIVE Active. The Monitor function considers the I2C bus to be active. 0x1 MONIDLE Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. 19 1 read-write NOT_IDLE Not idle. The I2C bus is not idle, or this flag has been cleared by software. 0 IDLE Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. 0x1 EVENTTIMEOUT Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. 24 1 read-write NO_TIMEOUT No time-out. I2C bus events have not caused a time-out. 0 EVEN_TIMEOUT Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. 0x1 SCLTIMEOUT SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 25 1 read-write NO_TIMEOUT No time-out. SCL low time has not caused a time-out. 0 TIMEOUT Time-out. SCL low time has caused a time-out. 0x1 INTENSET Interrupt Enable Set and read register. 0x808 32 read-write 0 0x30B8951 MSTPENDINGEN Master Pending interrupt Enable. 0 1 read-write DISABLED Disabled. The MstPending interrupt is disabled. 0 ENABLED Enabled. The MstPending interrupt is enabled. 0x1 MSTARBLOSSEN Master Arbitration Loss interrupt Enable. 4 1 read-write DISABLED Disabled. The MstArbLoss interrupt is disabled. 0 ENABLED Enabled. The MstArbLoss interrupt is enabled. 0x1 MSTSTSTPERREN Master Start/Stop Error interrupt Enable. 6 1 read-write DISABLED Disabled. The MstStStpErr interrupt is disabled. 0 ENABLED Enabled. The MstStStpErr interrupt is enabled. 0x1 SLVPENDINGEN Slave Pending interrupt Enable. 8 1 read-write DISABLED Disabled. The SlvPending interrupt is disabled. 0 ENABLED Enabled. The SlvPending interrupt is enabled. 0x1 SLVNOTSTREN Slave Not Stretching interrupt Enable. 11 1 read-write DISABLED Disabled. The SlvNotStr interrupt is disabled. 0 ENABLED Enabled. The SlvNotStr interrupt is enabled. 0x1 SLVDESELEN Slave Deselect interrupt Enable. 15 1 read-write DISABLED Disabled. The SlvDeSel interrupt is disabled. 0 ENABLED Enabled. The SlvDeSel interrupt is enabled. 0x1 MONRDYEN Monitor data Ready interrupt Enable. 16 1 read-write DISABLED Disabled. The MonRdy interrupt is disabled. 0 ENABLED Enabled. The MonRdy interrupt is enabled. 0x1 MONOVEN Monitor Overrun interrupt Enable. 17 1 read-write DISABLED Disabled. The MonOv interrupt is disabled. 0 ENABLED Enabled. The MonOv interrupt is enabled. 0x1 MONIDLEEN Monitor Idle interrupt Enable. 19 1 read-write DISABLED Disabled. The MonIdle interrupt is disabled. 0 ENABLED Enabled. The MonIdle interrupt is enabled. 0x1 EVENTTIMEOUTEN Event time-out interrupt Enable. 24 1 read-write DISABLED Disabled. The Event time-out interrupt is disabled. 0 ENABLED Enabled. The Event time-out interrupt is enabled. 0x1 SCLTIMEOUTEN SCL time-out interrupt Enable. 25 1 read-write DISABLED Disabled. The SCL time-out interrupt is disabled. 0 ENABLED Enabled. The SCL time-out interrupt is enabled. 0x1 INTENCLR Interrupt Enable Clear register. 0x80C 32 write-only 0 0 MSTPENDINGCLR Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. 0 1 write-only MSTARBLOSSCLR Master Arbitration Loss interrupt clear. 4 1 write-only MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. 6 1 write-only SLVPENDINGCLR Slave Pending interrupt clear. 8 1 write-only SLVNOTSTRCLR Slave Not Stretching interrupt clear. 11 1 write-only SLVDESELCLR Slave Deselect interrupt clear. 15 1 write-only MONRDYCLR Monitor data Ready interrupt clear. 16 1 write-only MONOVCLR Monitor Overrun interrupt clear. 17 1 write-only MONIDLECLR Monitor Idle interrupt clear. 19 1 write-only EVENTTIMEOUTCLR Event time-out interrupt clear. 24 1 write-only SCLTIMEOUTCLR SCL time-out interrupt clear. 25 1 write-only TIMEOUT Time-out value register. 0x810 32 read-write 0xFFFF 0xFFFF TOMIN Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. 0 4 read-write TO Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. 4 12 read-write CLKDIV Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. 0x814 32 read-write 0 0xFFFF DIVVAL This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use. 0 16 read-write INTSTAT Interrupt Status register for Master, Slave, and Monitor functions. 0x818 32 read-only 0x801 0x30B8951 MSTPENDING Master Pending. 0 1 read-only MSTARBLOSS Master Arbitration Loss flag. 4 1 read-only MSTSTSTPERR Master Start/Stop Error flag. 6 1 read-only SLVPENDING Slave Pending. 8 1 read-only SLVNOTSTR Slave Not Stretching status. 11 1 read-only SLVDESEL Slave Deselected flag. 15 1 read-only MONRDY Monitor Ready. 16 1 read-only MONOV Monitor Overflow flag. 17 1 read-only MONIDLE Monitor Idle flag. 19 1 read-only EVENTTIMEOUT Event time-out Interrupt flag. 24 1 read-only SCLTIMEOUT SCL time-out Interrupt flag. 25 1 read-only MSTCTL Master control register. 0x820 32 read-write 0 0xE MSTCONTINUE Master Continue. This bit is write-only. 0 1 write-only NO_EFFECT No effect. 0 CONTINUE Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. 0x1 MSTSTART Master Start control. This bit is write-only. 1 1 read-write NO_EFFECT No effect. 0 START Start. A Start will be generated on the I2C bus at the next allowed time. 0x1 MSTSTOP Master Stop control. This bit is write-only. 2 1 read-write NO_EFFECT No effect. 0 STOP Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). 0x1 MSTDMA Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. 3 1 read-write DISABLED Disable. No DMA requests are generated for master operation. 0 ENABLED Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. 0x1 MSTTIME Master timing configuration. 0x824 32 read-write 0x77 0x77 MSTSCLLOW Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. 0 3 read-write _2_CLOCKS 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. 0 _3_CLOCKS 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. 0x1 _4_CLOCKS 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. 0x2 _5_CLOCKS 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. 0x3 _6_CLOCKS 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. 0x4 _7_CLOCKS 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. 0x5 _8_CLOCKS 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. 0x6 _9_CLOCKS 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. 0x7 MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. 4 3 read-write _2_CLOCKS 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. 0 _3_CLOCKS 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . 0x1 _4_CLOCKS 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. 0x2 _5_CLOCKS 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. 0x3 _6_CLOCKS 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. 0x4 _7_CLOCKS 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. 0x5 _8_CLOCKS 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. 0x6 _9_CLOCKS 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. 0x7 MSTDAT Combined Master receiver and transmitter data register. 0x828 32 read-write 0 0xFF DATA Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function. 0 8 read-write SLVCTL Slave control register. 0x840 32 read-write 0 0x30B SLVCONTINUE Slave Continue. 0 1 read-write NO_EFFECT No effect. 0 CONTINUE Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. 0x1 SLVNACK Slave NACK. 1 1 read-write NO_EFFECT No effect. 0 NACK NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). 0x1 SLVDMA Slave DMA enable. 3 1 read-write DISABLED Disabled. No DMA requests are issued for Slave mode operation. 0 ENABLED Enabled. DMA requests are issued for I2C slave data transmission and reception. 0x1 AUTOACK Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. 8 1 read-write NORMAL Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). 0 AUTOMATIC_ACK A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. 0x1 AUTOMATCHREAD When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. 9 1 read-write I2C_WRITE The expected next operation in Automatic Mode is an I2C write. 0 I2C_READ The expected next operation in Automatic Mode is an I2C read. 0x1 SLVDAT Combined Slave receiver and transmitter data register. 0x844 32 read-write 0 0xFF DATA Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. 0 8 read-write 4 0x4 SLVADR[%s] Slave address register. 0x848 32 read-write 0x1 0xFF SADISABLE Slave Address n Disable. 0 1 read-write ENABLED Enabled. Slave Address n is enabled. 0 DISABLED Ignored Slave Address n is ignored. 0x1 SLVADR Slave Address. Seven bit slave address that is compared to received addresses if enabled. 1 7 read-write AUTONACK Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. 15 1 read-write NORMAL Normal operation, matching I2C addresses are not ignored. 0 AUTOMATIC Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. 0x1 SLVQUAL0 Slave Qualification for address 0. 0x858 32 read-write 0 0xFF QUALMODE0 Qualify mode for slave address 0. 0 1 read-write MASK Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. 0 EXTEND Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. 0x1 SLVQUAL0 Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 1 7 read-write MONRXDAT Monitor receiver data register. 0x880 32 read-only 0 0x7FF MONRXDAT Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. 0 8 read-only MONSTART Monitor Received Start. 8 1 read-only NO_START_DETECTED No start detected. The Monitor function has not detected a Start event on the I2C bus. 0 START_DETECTED Start detected. The Monitor function has detected a Start event on the I2C bus. 0x1 MONRESTART Monitor Received Repeated Start. 9 1 read-only NOT_DETECTED No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. 0 DETECTED Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. 0x1 MONNACK Monitor Received NACK. 10 1 read-only ACKNOWLEDGED Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. 0 NOT_ACKNOWLEDGED Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. 0x1 ID I2C module Identification. This value appears in the shared Flexcomm peripheral ID register when I2C is selected. 0xFFC 32 read-only 0xE0300000 0xFFFFFFFF APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only MINOR_REV Minor revision of module implementation, starting at 0. Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions. 8 4 read-only MAJOR_REV Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions. 12 4 read-only ID Unique module identifier for this IP block. 16 16 read-only I2C1 FLEXCOMM2 i2c I2C 0x40087000 0 0x1000 registers SPI0 FLEXCOMM2 spi SPI SPI 0x40087000 0 0x1000 registers CFG SPI Configuration register 0x400 32 read-write 0 0xFBD ENABLE SPI enable. 0 1 read-write DISABLED Disabled. The SPI is disabled and the internal state machine and counters are reset. 0 ENABLED Enabled. The SPI is enabled for operation. 0x1 MASTER Master mode select. 2 1 read-write SLAVE_MODE Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 0 MASTER_MODE Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. 0x1 LSBF LSB First mode enable. 3 1 read-write STANDARD Standard. Data is transmitted and received in standard MSB first order. 0 REVERSE Reverse. Data is transmitted and received in reverse order (LSB first). 0x1 CPHA Clock Phase select. 4 1 read-write CHANGE Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. 0 CAPTURE Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. 0x1 CPOL Clock Polarity select. 5 1 read-write LOW Low. The rest state of the clock (between transfers) is low. 0 HIGH High. The rest state of the clock (between transfers) is high. 0x1 LOOP Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. 7 1 read-write DISABLED Disabled. 0 ENABLED Enabled. 0x1 SPOL0 SSEL0 Polarity select. 8 1 read-write LOW Low. The SSEL0 pin is active low. 0 HIGH High. The SSEL0 pin is active high. 0x1 SPOL1 SSEL1 Polarity select. 9 1 read-write LOW Low. The SSEL1 pin is active low. 0 HIGH High. The SSEL1 pin is active high. 0x1 SPOL2 SSEL2 Polarity select. 10 1 read-write LOW Low. The SSEL2 pin is active low. 0 HIGH High. The SSEL2 pin is active high. 0x1 SPOL3 SSEL3 Polarity select. 11 1 read-write LOW Low. The SSEL3 pin is active low. 0 HIGH High. The SSEL3 pin is active high. 0x1 DLY SPI Delay register 0x404 32 read-write 0 0xFFFF PRE_DELAY Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 0 4 read-write POST_DELAY Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 4 4 read-write FRAME_DELAY If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted. 8 4 read-write TRANSFER_DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. 12 4 read-write STAT SPI Status. Some status flags can be cleared by writing a 1 to that bit position. 0x408 32 read-write 0x100 0x1C0 SSA Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. 4 1 write-only SSD Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. 5 1 write-only STALLED Stalled status flag. This indicates whether the SPI is currently in a stall condition. 6 1 read-only ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. 7 1 read-write MSTIDLE Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data. 8 1 read-only INTENSET SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0x40C 32 read-write 0 0x130 SSAEN Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. 4 1 read-write DISABLED Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. 0 ENABLED Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. 0x1 SSDEN Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. 5 1 read-write DISABLED Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. 0 ENABLED Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. 0x1 MSTIDLEEN Master idle interrupt enable. 8 1 read-write DISABLED No interrupt will be generated when the SPI master function is idle. 0 ENABLED An interrupt will be generated when the SPI master function is fully idle. 0x1 INTENCLR SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. 0x410 32 write-only 0 0 SSAEN Writing 1 clears the corresponding bit in the INTENSET register. 4 1 write-only SSDEN Writing 1 clears the corresponding bit in the INTENSET register. 5 1 write-only MSTIDLE Writing 1 clears the corresponding bit in the INTENSET register. 8 1 write-only DIV SPI clock Divider 0x424 32 read-write 0 0xFFFF DIVVAL Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536. 0 16 read-write INTSTAT SPI Interrupt Status 0x428 32 read-only 0 0x130 SSA Slave Select Assert. 4 1 read-only SSD Slave Select Deassert. 5 1 read-only MSTIDLE Master Idle status flag. 8 1 read-only FIFOCFG FIFO configuration and enable register. 0xE00 32 read-write 0 0x4F033 ENABLETX Enable the transmit FIFO. 0 1 read-write DISABLED The transmit FIFO is not enabled. 0 ENABLED The transmit FIFO is enabled. 0x1 ENABLERX Enable the receive FIFO. 1 1 read-write DISABLED The transmit FIFO is not enabled. 0 ENABLED The transmit FIFO is enabled. 0x1 SIZE FIFO size configuration. This is a read-only field. 0x1 = FIFO is configured as 8 entries of 16 bits. 0x0, 0x2, 0x3 = not applicable to SPI. 4 2 read-only DMATX DMA configuration for transmit. 12 1 read-write NOT_TRIGGERED DMA is not used for the transmit function. 0 TRIGGERED Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. 0x1 DMARX DMA configuration for receive. 13 1 read-write NOT_TRIGGERED DMA is not used for the receive function. 0 TRIGGERED Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. 0x1 EMPTYTX Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. 16 1 write-only EMPTYRX Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. 17 1 write-only FIFOSTAT FIFO status register. 0xE04 32 read-write 0x30 0x1F1FFB TXERR TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit. 0 1 read-write RXERR RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. 1 1 read-write PERINT Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral' STAT register. 3 1 read-only TXEMPTY Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. 4 1 read-only TXNOTFULL Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow. 5 1 read-only RXNOTEMPTY Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. 6 1 read-only RXFULL Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow. 7 1 read-only TXLVL Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0. 8 5 read-only RXLVL Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1. 16 5 read-only FIFOTRIG FIFO trigger settings for interrupt and DMA request. 0xE08 32 read-write 0 0xF0F03 TXLVLENA Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. 0 1 read-write DISABLED Transmit FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. 0x1 RXLVLENA Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. 1 1 read-write DISABLED Receive FIFO level does not generate a FIFO level trigger. 0 ENABLED An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. 0x1 TXLVL Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See -Hardware Wake-up control register-. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 7 = 1 = trigger when the TX FIFO level decreases to 7 entries (is no longer full). 8 4 read-write RXLVL Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See -Hardware Wake-up control register-. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 7 = trigger when the RX FIFO has received 8 entries (has become full). 16 4 read-write FIFOINTENSET FIFO interrupt enable set (enable) and read register. 0xE10 32 read-write 0 0xF TXERR Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 0 1 read-write DISABLED No interrupt will be generated for a transmit error. 0 ENABLED An interrupt will be generated when a transmit error occurs. 0x1 RXERR Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 1 1 read-write DISABLED No interrupt will be generated for a receive error. 0 ENABLED An interrupt will be generated when a receive error occurs. 0x1 TXLVL Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 2 1 read-write DISABLED No interrupt will be generated based on the TX FIFO level. 0 ENABLED If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. 0x1 RXLVL Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 3 1 read-write DISABLED No interrupt will be generated based on the RX FIFO level. 0 ENABLED If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. 0x1 FIFOINTENCLR FIFO interrupt enable clear (disable) and read register. 0xE14 32 read-write 0 0xF TXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 0 1 read-write RXERR Writing one clears the corresponding bits in the FIFOINTENSET register. 1 1 read-write TXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 2 1 read-write RXLVL Writing one clears the corresponding bits in the FIFOINTENSET register. 3 1 read-write FIFOINTSTAT FIFO interrupt status register. 0xE18 32 read-only 0 0x1F TXERR TX FIFO error. 0 1 read-only RXERR RX FIFO error. 1 1 read-only TXLVL Transmit FIFO level interrupt. 2 1 read-only RXLVL Receive FIFO level interrupt. 3 1 read-only PERINT Peripheral interrupt. 4 1 read-only FIFOWR FIFO write data. 0xE20 32 read-write 0 0 TXDATA Transmit data to the FIFO. 0 16 write-only TXSSEL0_N Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register. 16 1 write-only ASSERTED SSEL0 asserted. 0 NOT_ASSERTED SSEL0 not asserted. 0x1 TXSSEL1_N Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register. 17 1 write-only ASSERTED SSEL1 asserted. 0 NOT_ASSERTED SSEL1 not asserted. 0x1 TXSSEL2_N Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register. 18 1 write-only ASSERTED SSEL2 asserted. 0 NOT_ASSERTED SSEL2 not asserted. 0x1 TXSSEL3_N Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register. 19 1 write-only ASSERTED SSEL3 asserted. 0 NOT_ASSERTED SSEL3 not asserted. 0x1 EOT End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register. 20 1 write-only NOT_DEASSERTED SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. 0 DEASSERTED SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. 0x1 EOF End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. 21 1 write-only NOT_EOF Data not EOF. This piece of data transmitted is not treated as the end of a frame. 0 EOF Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted. 0x1 RXIGNORE Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA. 22 1 write-only READ Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received. 0 IGNORE Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. 0x1 LEN Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. Note: when LEN = 0, the underrun status is not meaningful. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. 0xF = Data transfer is 16 bits in length. 24 4 write-only FIFORD FIFO read data. 0xE30 32 read-only 0 0x1FFFFF RXDATA Received data from the FIFO. 0 16 read-only RXSSEL0_N Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 16 1 read-only RXSSEL1_N Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 17 1 read-only RXSSEL2_N Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 18 1 read-only RXSSEL3_N Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 19 1 read-only SOT Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit. 20 1 read-only FIFORDNOPOP FIFO data read with no FIFO pop. 0xE40 32 read-only 0 0x1FFFFF RXDATA Received data from the FIFO. 0 16 read-only RXSSEL0_N Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 16 1 read-only RXSSEL1_N Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 17 1 read-only RXSSEL2_N Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 18 1 read-only RXSSEL3_N Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 19 1 read-only SOT Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit. 20 1 read-only ID SPI module Identification. This value appears in the shared Flexcomm peripheral ID register when SPI is selected. 0xFFC 32 read-only 0xE0200000 0xFFFFFFFF APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only MINOR_REV Minor revision of module implementation, starting at 0. Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions. 8 4 read-only MAJOR_REV Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions. 12 4 read-only ID Unique module identifier for this IP block. 16 16 read-only SPI1 FLEXCOMM3 spi SPI 0x4008F000 0 0x1000 registers FSP fsp FSP 0x40088000 0 0x1A0 registers SYS_CTRL FSP system control register 0 32 read-write 0 0 TE_ABORT Transform Engine abort write 1 to abort 0 1 write-only MOU_ABORT Matrix Operation Unit abort write 1 to abort 1 1 write-only SCF_ABORT SE COR FIR abort write 1 to abort 2 1 write-only STATUS FSP status register 0x4 32 read-only 0 0x7 FPU0_BUSY SE COR FIR is in processing busy 0 1 read-only FPU1_BUSY TE MOU is in processing busy 1 1 read-only FIR_READY FIR output buffer is not empty which is valid for read 2 1 read-only INT FSP interrupt register 0x8 32 read-write 0 0x877F1F0F TE_DONE_INT Transform engine done interrupt 0 1 read-write oneToClear MOU_DONE_INT Matrix operation unit done interrupt 1 1 read-write oneToClear SE_DONE_INT Statistic engine done interrupt 2 1 read-write oneToClear COR_DONE_INT Correlation done interrupt 3 1 read-write oneToClear FPU0_CALC_IN_ERR_INT SE COR FIR calculation input data error interrupt 8 1 read-write oneToClear FPU0_CALC_OUT_ERR_INT SE COR FIR calculation output data error interrupt 9 1 read-write oneToClear FPU0_DIN_OV_INT SE COR FIR input data overflow interrupt (always 0) 10 1 read-write oneToClear FPU0_DOUT_OV_INT SE COR FIR output data overflow interrupt 11 1 read-write oneToClear SINGULAR_INT MOU singular interrupt 12 1 read-write oneToClear FPU1_CALC_IN_ERR_INT MOU TE calculation input data error interrupt 16 1 read-write oneToClear FPU1_CALC_OUT_ERR_INT MOU TE calculation output data error interrupt 17 1 read-write oneToClear FPU1_DIN_OV_INT MOU TE input data overflow interrupt 18 1 read-write oneToClear FPU1_DOUT_OV_INT MOU TE output data overflow interrupt 19 1 read-write oneToClear FINV_DIN_ERR_INT FINV input data is inf or nan 20 1 read-write oneToClear FINV_DOUT_OV_INT FINV output data overflow 21 1 read-write oneToClear FINV_ZERO_INT FINV input data is zero 22 1 read-write oneToClear CORDIC_DIN_ERR CORDIC input data error interrupt 24 1 read-write oneToClear CORDIC_DOUT_ERR_INT CORDIC output data error interrupt 25 1 read-write oneToClear CORDIC_CALC_ERR_INT CORDIC calculation error interrupt 26 1 read-write oneToClear FSP_INT Or signal of all FSP function interrupt in this register 31 1 read-only INTEN FSP interrupt enable register 0xC 32 read-write 0 0xFFFFFFFF TE_DONE_INTEN Transform engine done interrupt enable 0 1 read-write MOU_DONE_INTEN Matrix operation unit done interrupt enable 1 1 read-write SE_DONE_INTEN Statistic engine done interrupt enable 2 1 read-write COR_DONE_INTEN Correlation done interrupt enable 3 1 read-write FPU0_CALC_IN_ERR_INTEN SE COR FIR calculation input data error interrupt enable 8 1 read-write FPU0_CALC_OUT_ERR_INTEN SE COR FIR calculation output data error interrupt enable 9 1 read-write FPU0_DIN_OV_INTEN SE COR FIR input data overflow interrupt enable 10 1 read-write FPU0_DOUT_OV_INTEN SE COR FIR output data overflow interrupt enable 11 1 read-write SINGULAR_INTEN MOU singular interrupt enable 12 1 read-write FPU1_CALC_IN_ERR_INTEN MOU TE calculation input data error interrupt enable 16 1 read-write FPU1_CALC_OUT_ERR_INTEN MOU TE calculation output data error interrupt enable 17 1 read-write FPU1_DIN_OV_INTEN MOU TE input data overflow interrupt enable 18 1 read-write FPU1_DOUT_OV_INTEN MOU TE output data overflow interrupt enable 19 1 read-write FINV_DIN_ERR_INTEN FINV data input is inf or nan interrupt enable 20 1 read-write FINV_DOUT_OV_INTEN FINV data output overflow interrupt enable 21 1 read-write FINV_ZERO_INTEN FINV input is zero interrupt enable 22 1 read-write CORDIC_DIN_ERR_INTEN CORDIC input data error interrupt enable 24 1 read-write CORDIC_DOUT_ERR_INTEN CORDIC output data error interrupt enable 25 1 read-write CORDIC_CALC_ERR_INTEN CORDIC calculation error interrupt enable 26 1 read-write FSP_INTEN Or signal of all FSP function interrupt in this register enable 31 1 read-write TE_CTRL transmit engine control register 0x20 32 read-write 0 0x700FFFF TE_MODE TE compute mode 0 2 read-write TE_FFT FFT 0 TE_IFFT IFFT 0x1 TE_DCT DCT 0x2 TE_IDCT IDCT 0x3 TE_IO_MODE TE input & output mode select 2 2 read-write TE_RICO real input, complex output 0 TE_CICO complex input, complex output 0x1 TE_RIRO real input, real output 0x2 TE_PTS TE compute point 4 2 read-write TE64PTS 64 points 0 TE128PTS 128 points 0x1 TE256PTS 256 points 0x2 TE_DIN_FP_SEL TE input data format select 6 1 read-write FIX fix 0 FLT float 0x1 TE_DOUT_FP_SEL TE output data format select 7 1 read-write FIX fix 0 FLT float 0x1 TE_SCALE TE scale 8 8 read-write TE_PAUSE_LVL Transfer Engine stop level for debug use only. 24 3 read-write TE_SRC_BASE transfer engine source data memory base register 0x24 32 read-write 0 0x1FFFF TE_SRC_BASE TE source data memory base address 0 17 read-write TE_DST_BASE transfer engine destination data memory base register 0x28 32 read-write 0 0x1FFFF TE_DST_BASE TE destination data memory base address 0 17 read-write MOU_CTRL matrix operation unit control register 0x40 32 read-write 0x1110000 0xFFFF030F OP_MODE MOU operation mode 0 4 read-write INV inversion 0 MULT matrix multiply 0x1 TRANS transposition 0x2 LINEAR linear operation 0x3 DOTMULT dot multiply 0x4 MOU_DIN_FP_SEL MOU data input format select 8 1 read-write MOU_FLT float 0 MOU_FIX fix 0x1 MOU_DOUT_FP_SEL MOU data output format select 9 1 read-write MOU_FLT float 0 MOU_FIX fix 0x1 MAT_M MOU Matrix column 16 4 read-write MAT_N MOU Matrix row only valid when matrix's column is not equal to row 20 4 read-write MAT_K MOU Matrix row only valid when matrix mult operation 24 4 read-write DIV_EPSILON When the data exponent is small than DIV_EPSILON the inverse operation will output a error signal. 28 2 read-write LU_STOP Stop at LU 30 1 read-write UINV_STOP stop at U-Matrix inverse 31 1 read-write MA_SRC_BASE matrix A source data memory base register 0x44 32 read-write 0 0x1FFFF MA_SRC_BASE Matrix A source data memory base address 0 17 read-write MB_SRC_BASE matrix B source data memory base register 0x48 32 read-write 0 0x1FFFF MB_SRC_BASE Matrix B source data memory base address 0 17 read-write MO_DST_BASE matrix output data memory base register 0x4C 32 read-write 0 0x1FFFF MO_DST_BASE Matrix Operation Unit output data destination memory base address 0 17 read-write MOU_SCALEA scale coefficient A register 0x50 32 read-write 0 0xFFFFFFFF MOU_SCALEA MOU scale coefficient A 0 32 read-write MOU_SCALEB scale coefficient B register 0x54 32 read-write 0 0xFFFFFFFF MOU_SCALEB MOU scale coefficient B 0 32 read-write SE_CTRL stastic engine control register 0x60 32 read-write 0xC0 0xFF00FF MIN_SEL Minimum value selection 0 1 read-write FIRST_ONE first one 0 LAST_ONE last one 0x1 MAX_SEL Maximum value selection0 the first one1 the last one 1 1 read-write MIN_IDX_EN Minimum value index calculation enable 2 1 read-write MAX_IDX_EN Maximum value index calculation enable 3 1 read-write SUM_EN Summary calculation enable 4 1 read-write PWR_EN Power calculation enable 5 1 read-write SE_DIN_FP_SEL SE data input format select 6 1 read-write SE_FLT float 0 SE_FIX fix 0x1 SE_DOUT_FP_SEL SE data output format select 7 1 read-write SE_LEN Statistic engine length 16 8 read-write SE_SRC_BASE statistic engine source data base register 0x64 32 read-write 0 0x1FFFF SE_SRC_BASE Statistic engine source data base address 0 17 read-write SE_IDX max or min data index register 0x68 32 read-only 0 0xFF00FF SE_MIN_IDX Minimum data index of an array 0 8 read-only SE_MAX_IDX Maximum data index of an array 16 8 read-only SE_SUM array summary result register 0x6C 32 read-only 0 0xFFFFFFFF SE_SUM Summary of an array 0 32 read-only SE_PWR array power result register 0x70 32 read-only 0 0xFFFFFFFF SE_PWR Power value of an array 0 32 read-only COR_CTRL correlation control register 0x80 32 read-write 0x300 0xFFFF0300 COR_DIN_FP_SEL COR input data format select 8 1 read-write COR_FLT float 0 COR_FIX fix 0x1 COR_DOUT_FP_SEL COR output data format select 9 1 read-write COR_X_LEN The length of X sequence to be Correlator 0-255 16 8 read-write COR_Y_LEN The length of Y sequence to be Correlator 0-255 24 8 read-write CX_SRC_BASE correlation x sequence base register 0x84 32 read-write 0 0x1FFFF COR_X_ADDR The base address of X sequence to be Correlator 0 17 read-write CY_SRC_BASE correlation y sequence base register 0x88 32 read-write 0 0x1FFFF COR_Y_ADDR The base address of Y sequence to be Correlator 0 17 read-write CO_DST_BASE correlation output sequence base register 0x8C 32 read-write 0 0x1FFFF COR_DST_BASE correlation output data destination address base 0 17 read-write COR_OFFSET correlation offset register 0x90 32 read-write 0 0xFFFF COR_X_OFFSET COR input X SEQ offset 0-255 0 8 read-write COR_Y_OFFSET COR input Y SEQ offset 0-255 8 8 read-write FIR_CFG_CH0 FIR channel 0 configuration register 0xA0 32 read-write 0 0xFFFFF FIR_CH0_COEF_BASE FIR channel 0 coefficient base address 0 16 read-write FIR_CH0_TAP_LEN FIR channel 0 tap length the register value equals to real tap length minus 1. 16 4 read-write FIR_BUF_CLR_ALL clear all FIR buffer 30 1 write-only FIR_CH0_BUF_CLR FIR channel 0 buffer clear 31 1 write-only FIR_CFG_CH1 FIR channel 1 configuration register 0xA4 32 read-write 0 0xFFFFF FIR_CH1_COEF_BASE FIR channel 1 coefficient base address 0 16 read-write FIR_CH1_TAP_LEN FIR channel 1 tap length 16 4 read-write FIR_CH1_BUF_CLR FIR channel 1 buffer clear 31 1 write-only FIR_CFG_CH2 FIR channel 2 configuration register 0xA8 32 read-write 0 0xFFFFF FIR_CH2_COEF_BASE FIR channel 2 coefficient base address 0 16 read-write FIR_CH2_TAP_LEN FIR channel 2 tap length 16 4 read-write FIR_CH2_BUF_CLR FIR channel 2 buffer clear 31 1 write-only FIR_CFG_CH3 FIR channel 3 configuration register 0xAC 32 read-write 0 0xFFFFF FIR_CH3_COEF_BASE FIR channel 3 coefficient base address 0 16 read-write FIR_CH3_TAP_LEN FIR channel 3 tap length 16 4 read-write FIR_CH3_BUF_CLR FIR channel 3 buffer clear 31 1 write-only FIR_CFG_CH4 FIR channel 4 configuration register 0xB0 32 read-write 0 0xFFFFF FIR_CH4_COEF_BASE FIR channel 4 coefficient base address 0 16 read-write FIR_CH4_TAP_LEN FIR channel 4 tap length 16 4 read-write FIR_CH4_BUF_CLR FIR channel 4 buffer clear 31 1 write-only FIR_CFG_CH5 FIR channel 5 configuration register 0xB4 32 read-write 0 0xFFFFF FIR_CH5_COEF_BASE FIR channel 5 coefficient base address 0 16 read-write FIR_CH5_TAP_LEN FIR channel 5 tap length 16 4 read-write FIR_CH5_BUF_CLR FIR channel 5 buffer clear 31 1 write-only FIR_CFG_CH6 FIR channel 6 configuration register 0xB8 32 read-write 0 0xFFFFF FIR_CH6_COEF_BASE FIR channel 6 coefficient base address 0 16 read-write FIR_CH6_TAP_LEN FIR channel 6 tap length 16 4 read-write FIR_CH6_BUF_CLR FIR channel 6 buffer clear 31 1 write-only FIR_CFG_CH7 FIR channel 7 configuration register 0xBC 32 read-write 0 0xFFFFF FIR_CH7_COEF_BASE FIR channel 7 coefficient base address 0 16 read-write FIR_CH7_TAP_LEN FIR channel 7 tap length 16 4 read-write FIR_CH7_BUF_CLR FIR channel 7 buffer clear 31 1 write-only FIR_CFG_CH8 FIR channel 8 configuration register 0xC0 32 read-write 0 0xFFFFF FIR_CH8_COEF_BASE FIR channel 8 coefficient base address 0 16 read-write FIR_CH8_TAP_LEN FIR channel 8 tap length 16 4 read-write FIR_CH8_BUF_CLR FIR channel 8 buffer clear 31 1 write-only FIR_DAT0_FX FIR channel 0 fix point data input & output register 0xD0 32 read-write 0 0xFFFFFFFF FIR_DAT0_FX FIR channel 0 fix data 0 32 read-write FIR_DAT1_FX FIR channel 1 fix point data input & output register 0xD4 32 read-write 0 0xFFFFFFFF FIR_DAT1_FX FIR channel1 fix data 0 32 read-write FIR_DAT2_FX FIR channel 2 fix point data input & output register 0xD8 32 read-write 0 0xFFFFFFFF FIR_DAT2_FX FIR channel2 fix data 0 32 read-write FIR_DAT3_FX FIR channel 3 fix point data input & output register 0xDC 32 read-write 0 0xFFFFFFFF FIR_DAT3_FX FIR channel3 fix data 0 32 read-write FIR_DAT4_FX FIR channel 4 fix point data input & output register 0xE0 32 read-write 0 0xFFFFFFFF FIR_DAT4_FX FIR channel4 fix data 0 32 read-write FIR_DAT5_FX FIR channel 5 fix point data input & output register 0xE4 32 read-write 0 0xFFFFFFFF FIR_DAT5_FX FIR channel5 fix data 0 32 read-write FIR_DAT6_FX FIR channel 6 fix point data input & output register 0xE8 32 read-write 0 0xFFFFFFFF FIR_DAT6_FX FIR channel6 fix data 0 32 read-write FIR_DAT7_FX FIR channel 7 fix point data input & output register 0xEC 32 read-write 0 0xFFFFFFFF FIR_DAT7_FX FIR channel7 fix data 0 32 read-write FIR_DAT8_FX FIR channel 8 fix point data input & output register 0xF0 32 read-write 0 0xFFFFFFFF FIR_DAT8_FX FIR channel8 fix data 0 32 read-write FIR_DAT0_FL FIR channel 0 float point data input & output register 0x100 32 read-write 0 0xFFFFFFFF FIR_DAT0_FL FIR channel 0 float data 0 32 read-write FIR_DAT1_FL FIR channel 1 float point data input & output register 0x104 32 read-write 0 0xFFFFFFFF FIR_DAT1_FL FIR channel1 float data 0 32 read-write FIR_DAT2_FL FIR channel 2 float point data input & output register 0x108 32 read-write 0 0xFFFFFFFF FIR_DAT2_FL FIR channel2 float data 0 32 read-write FIR_DAT3_FL FIR channel 3 float point data input & output register 0x10C 32 read-write 0 0xFFFFFFFF FIR_DAT3_FL FIR channel3 float data 0 32 read-write FIR_DAT4_FL FIR channel 4 float point data input & output register 0x110 32 read-write 0 0xFFFFFFFF FIR_DAT4_FL FIR channel4 float data 0 32 read-write FIR_DAT5_FL FIR channel 5 float point data input & output register 0x114 32 read-write 0 0xFFFFFFFF FIR_DAT5_FL FIR channel5 float data 0 32 read-write FIR_DAT6_FL FIR channel 6 float point data input & output register 0x118 32 read-write 0 0xFFFFFFFF FIR_DAT6_FL FIR channel6 float data 0 32 read-write FIR_DAT7_FL FIR channel 7 float point data input & output register 0x11C 32 read-write 0 0xFFFFFFFF FIR_DAT7_FL FIR channel7 float data 0 32 read-write FIR_DAT8_FL FIR channel 8 float point data input & output register 0x120 32 read-write 0 0xFFFFFFFF FIR_DAT8_FL FIR channel8 float data 0 32 read-write SIN_COS_IXOX sin & cos input fix output fix mode data address register 0x140 32 write-only 0 0 SIN_COS_IXOX_SRC SIN_COS input data source address. Input fix output fix 0 16 write-only SIN_COS_IXOX_DST SIN_COS output data destination address. Input fix output fix. 16 16 write-only SIN_COS_IXOL sin & cos input fix output float mode data address register 0x144 32 write-only 0 0 SIN_COS_IXOL_SRC SIN_COS input data source word address. Input fix output float 0 16 write-only SIN_COS_IXOL_DST SIN_COS output data destination word address. Input fix output float. 16 16 write-only SIN_COS_ILOX sin & cos input float output fix mode data address register 0x148 32 write-only 0 0 SIN_COS_ILOX_SRC SIN_COS input data source word address. Input float output fix 0 16 write-only SIN_COS_ILOX_DST SIN_COS output data destination word address. Input float output fix. 16 16 write-only SIN_COS_ILOL sin & cos input float output float mode data address register 0x14C 32 write-only 0 0 SIN_COS_ILOL_SRC SIN_COS input data source word address. Input float output float 0 16 write-only SIN_COS_ILOL_DST SIN_COS output data destination word address. Input float output float 16 16 write-only LN_SQRT_IXOX LN & sqrt input fix output fix mode data address register 0x150 32 write-only 0 0 LN_SQRT_IXOX_SRC LN_SQRT input data source word address. Input fix output fix 0 16 write-only LN_SQRT_IXOX_DST LN_SQRT output data destination word address. Input fix output fix. 16 16 write-only LN_SQRT_IXOL LN & sqrt input fix output float mode data address register 0x154 32 write-only 0 0 LN_SQRT_IXOL_SRC LN_SQRT input data source word address. Input fix output float 0 16 write-only LN_SQRT_IXOL_DST LN_SQRT output data destination word address. Input fix output float. 16 16 write-only LN_SQRT_ILOX LN & sqrt input float output fix mode data address register 0x158 32 write-only 0 0 LN_SQRT_ILOX_SRC LN_SQRT input data source word address. Input float output fix 0 16 write-only LN_SQRT_ILOX_DST LN_SQRT output data destination word address. Input float output fix. 16 16 write-only LN_SQRT_ILOL LN & sqrt input float output float mode data address register 0x15C 32 write-only 0 0 LN_SQRT_ILOL_SRC LN_SQRT input data source word address. Input float output float 0 16 write-only LN_SQRT_ILOL_DST LN_SQRT output data destination word address. Input float output float 16 16 write-only CORDIC_T0UP_IXOX native cordic input fix output fix, t=0, u=1 mode data address register 0x160 32 write-only 0 0 CORDIC_T0UP_IXOX_SRC CORDIC_T0UP_IXOX input data source word address. Input fix output fix 0 16 write-only CORDIC_T0UP_IXOX_DST CORDIC_T0UP_IXOX output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UP_IXOX_DST+1. Input fix output fix 16 16 write-only CORDIC_T0UP_IXOL native cordic input fix output float, t=0, u=1 mode data address register 0x164 32 write-only 0 0 CORDIC_T0UP_IXOL_SRC CORDIC_T0UP_IXOL input data source word address. Input fix output float 0 16 write-only CORDIC_T0UP_IXOL_DST CORDIC_T0UP_IXOL output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UP_IXOL_DST+1. Input fix output float 16 16 write-only CORDIC_T0UP_ILOX native cordic input float output fix, t=0, u=1 mode data address register 0x168 32 write-only 0 0 CORDIC_T0UP_ILOX_SRC CORDIC_T0UP_ILOX input data source word address. Input float output fix 0 16 write-only CORDIC_T0UP_ILOX_DST CORDIC_T0UP_ILOX output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UP_ILOX_DST+1. Input float output fix 16 16 write-only CORDIC_T0UP_ILOL native cordic input float output float, t=0, u=1 mode data address register 0x16C 32 write-only 0 0 CORDIC_T0UP_ILOL_SRC CORDIC_T0UN_ILOL input data source word address. Input float output float 0 16 write-only CORDIC_T0UP_ILOL_DST CORDIC_T0UN_ILOL output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UN_ILOL_DST+1. Input float output float 16 16 write-only CORDIC_T0UN_IXOX native cordic input fix output fix, t=0, u=-1 mode data address register 0x170 32 write-only 0 0 CORDIC_T0UN_IXOX_SRC CORDIC_T0UN_IXOX input data source word address. Input fix output fix 0 16 write-only CORDIC_T0UN_IXOX_DST CORDIC_T0UN_IXOX output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UN_IXOX_DST+1. Input fix output fix 16 16 write-only CORDIC_T0UN_IXOL native cordic input fix output float, t=0, u=-1 mode data address register 0x174 32 write-only 0 0 CORDIC_T0UN_IXOL_SRC CORDIC_T0UN_IXOL input data source word address. Input fix output float 0 16 write-only CORDIC_T0UN_IXOL_DST CORDIC_T0UN_IXOL output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UN_IXOL_DST+1. Input fix output float 16 16 write-only CORDIC_T0UN_ILOX native cordic input float output fix, t=0, u=-1 mode data address register 0x178 32 write-only 0 0 CORDIC_T0UN_ILOX_SRC CORDIC_T0UN_ILOX input data source word address. Input float output fix 0 16 write-only CORDIC_T0UN_ILOX_DST CORDIC_T0UN_ILOX output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UN_ILOX_DST+1. Input float output fix 16 16 write-only CORDIC_T0UN_ILOL native cordic input float output float, t=0, u=-1 mode data address register 0x17C 32 write-only 0 0 CORDIC_T0UN_ILOL_SRC CORDIC_T0UN_ILOL input data source word address. Input float output float 0 16 write-only CORDIC_T0UN_ILOL_DST CORDIC_T0UN_ILOL output data destination word address. X is saved at here Y is saved at word address CORDIC_T0UN_ILOL_DST+1. Input float output float 16 16 write-only CORDIC_T1UP_IXOX native cordic input fix output fix, t=1, u=1 mode data address register 0x180 32 write-only 0 0 CORDIC_T1UP_IXOX_SRC CORDIC_T1UP_IXOX input data source word address. Input fix output fix 0 16 write-only CORDIC_T1UP_IXOX_DST CORDIC_T1UP_IXOX output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UP_IXOX_DST+1. Input fix output fix 16 16 write-only CORDIC_T1UP_IXOL native cordic input fix output float, t=1, u=1 mode data address register 0x184 32 write-only 0 0 CORDIC_T1UP_IXOL_SRC CORDIC_T1UP_IXOL input data source word address. Input fix output float 0 16 write-only CORDIC_T1UP_IXOL_DST CORDIC_T1UP_IXOL output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UP_IXOL_DST+1. Input fix output float 16 16 write-only CORDIC_T1UP_ILOX native cordic input float output fix, t=1, u=1 mode data address register 0x188 32 write-only 0 0 CORDIC_T1UP_ILOX_SRC CORDIC_T1UP_ILOX input data source word address. Input float output fix 0 16 write-only CORDIC_T1UP_ILOX_DST CORDIC_T1UP_ILOX output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UP_ILOX_DST+1. Input float output fix 16 16 write-only CORDIC_T1UP_ILOL native cordic input float output float, t=1, u=1 mode data address register 0x18C 32 write-only 0 0 CORDIC_T1UP_ILOL_SRC CORDIC_T1UP_ILOL input data source word address. Input float output float 0 16 write-only CORDIC_T1UP_ILOL_DST CORDIC_T1UP_ILOL output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UP_ILOL_DST+1. Input float output float 16 16 write-only CORDIC_T1UN_IXOX native cordic input fix output fix, t=1, u=-1 mode data address register 0x190 32 write-only 0 0 CORDIC_T1UN_IXOX_SRC CORDIC_T1UN_IXOX input data source word address. Input fix output fix 0 16 write-only CORDIC_T1UN_IXOX_DST CORDIC_T1UN_IXOX output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UN_IXOX_DST+1. Input fix output fix 16 16 write-only CORDIC_T1UN_IXOL native cordic input fix output float, t=1, u=-1 mode data address register 0x194 32 write-only 0 0 CORDIC_T1UN_IXOL_SRC CORDIC_T1UN_IXOL input data source word address. Input fix output float 0 16 write-only CORDIC_T1UN_IXOL_DST CORDIC_T1UN_IXOL output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UN_IXOL_DST+1. Input fix output float 16 16 write-only CORDIC_T1UN_ILOX native cordic input float output fix, t=1, u=-1 mode data address register 0x198 32 write-only 0 0 CORDIC_T1UN_ILOX_SRC CORDIC_T1UN_ILOX input data source word address. Input float output fix 0 16 write-only CORDIC_T1UN_ILOX_DST CORDIC_T1UN_ILOX output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UN_ILOX_DST+1. Input float output fix 16 16 write-only CORDIC_T1UN_ILOL native cordic input float output float, t=1, u=-1 mode data address register 0x19C 32 write-only 0 0 CORDIC_T1UN_ILOL_SRC CORDIC_T1UN_ILOL input data source word address. Input float output float 0 16 write-only CORDIC_T1UN_ILOL_DST CORDIC_T1UN_ILOL output data destination word address. X is saved at here Z is saved at word address CORDIC_T1UN_ILOL_DST+1. Input float output float 16 16 write-only GPIOA gpio GPIO GPIO 0x4008C000 0 0x3C registers DATA GPIO value register 0 32 read-only 0 0xFFFFFFFF DATA data value 0 32 read-only DATAOUT GPIO output status register 0x4 32 read-write 0 0xFFFFFFFF DATAOUT Data output register value 0 32 read-write OUTENSET GPIO output enable set register 0x10 32 read-write 0 0xFFFFFFFF OUTENSET output enable clear 0 32 read-write OUTENCLR GPIO output clear register 0x14 32 read-write 0 0xFFFFFFFF OUTENCLR output enable clear 0 32 read-write oneToClear INTENSET GPIO interrupt enable set register 0x20 32 write-only 0 0xFFFFFFFF INTENSET interrupt enable set 0 32 write-only INTENCLR GPIO interrupt enable clear register 0x24 32 read-write 0 0xFFFFFFFF INTENCLR interrupt enable clear 0 32 read-write oneToClear INTTYPESET GPIO interrupt type set register 0x28 32 write-only 0 0xFFFFFFFF INTTYPESET interrupt type set 0 32 write-only INTTYPECLR GPIO interrupt type set register 0x2C 32 read-write 0 0xFFFFFFFF INTTYPECLR interrupt type clear 0 32 read-write oneToClear INTPOLSET GPIO interrupt polarity set register 0x30 32 write-only 0 0xFFFFFFFF INTPOLSET interrupt polarity set 0 32 write-only INTPOLCLR GPIO interrupt polarity clear register 0x34 32 read-write 0 0xFFFFFFFF INTPOLCLR interrupt polarity clear 0 32 read-write oneToClear INTSTATUS GPIO interrupt status register 0x38 32 read-write 0 0xFFFFFFFF INTSTATUS interrupt status 0 32 read-write oneToClear GPIOB gpio GPIO 0x4008D000 0 0x3C registers CRC_ENGINE crc CRC 0x4008E000 0 0xC registers MODE CRC mode register 0 32 read-write 0 0x3F CRC_POLY CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial 0 2 read-write BIT_RVS_WR Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) 2 1 read-write CMPL_WR Data complement: 1 = 1'-s complement for CRC_WR_DATA 0 = No 1'-s complement for CRC_WR_DATA 3 1 read-write BIT_RVS_SUM CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM 4 1 read-write CMPL_SUM CRC sum complement: 1 = 1'-s complement for CRC_SUM 0 = No 1'-s complement for CRC_SUM 5 1 read-write SEED CRC seed register 0x4 32 read-write 0xFFFF 0xFFFFFFFF CRC_SEED A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1'-s complement pre-processes. A write access to this register will overrule the CRC calculation in progresses. 0 32 read-write SUM CRC checksum register SUM_WR_DATA 0x8 32 read-only 0xFFFF 0xFFFFFFFF CRC_SUM The most recent CRC sum can be read through this register with selected bit order and 1'-s complement post-processes. 0 32 read-only WR_DATA CRC data register SUM_WR_DATA 0x8 32 write-only 0 0 CRC_WR_DATA Data written to this register will be taken to perform CRC calculation with selected bit order and 1'-s complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. 0 32 write-only