110309 lines
4.4 MiB
110309 lines
4.4 MiB
<?xml version="1.0" encoding="UTF-8"?>
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<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
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<vendor>nxp.com</vendor>
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<name>MIMXRT1011</name>
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<version>1.0</version>
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<description>MIMXRT1011DAE5A</description>
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<licenseText>
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Copyright 2016-2019 NXP
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All rights reserved.
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SPDX-License-Identifier: BSD-3-Clause
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</licenseText>
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<cpu>
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<name>CM7</name>
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<revision>r0p1</revision>
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<endian>little</endian>
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<mpuPresent>true</mpuPresent>
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<fpuPresent>true</fpuPresent>
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<vtorPresent>true</vtorPresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<peripherals>
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<peripheral>
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<name>AIPSTZ1</name>
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<description>AIPSTZ Control Registers</description>
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<groupName>AIPSTZ</groupName>
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<prependToName>AIPSTZ1_</prependToName>
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<headerStructName>AIPSTZ</headerStructName>
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<baseAddress>0x4007C000</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0x54</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>MPR</name>
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<description>Master Priviledge Registers</description>
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<addressOffset>0</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x77000000</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>MPROT5</name>
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<description>Master 5 Priviledge, Buffer, Read, Write Control.</description>
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<bitOffset>8</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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|
<name>MPL0</name>
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<description>Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.</description>
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<value>#xxx0</value>
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</enumeratedValue>
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<enumeratedValue>
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|
<name>MPL1</name>
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<description>Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.</description>
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<value>#xxx1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>MPROT3</name>
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<description>Master 3 Priviledge, Buffer, Read, Write Control.</description>
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<bitOffset>16</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>MPL0</name>
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<description>Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.</description>
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<value>#xxx0</value>
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</enumeratedValue>
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<enumeratedValue>
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|
<name>MPL1</name>
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<description>Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.</description>
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<value>#xxx1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>MPROT2</name>
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<description>Master 2 Priviledge, Buffer, Read, Write Control</description>
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<bitOffset>20</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>MPL0</name>
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|
<description>Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.</description>
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<value>#xxx0</value>
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</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>MPL1</name>
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|
<description>Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.</description>
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<value>#xxx1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>MPROT1</name>
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<description>Master 1 Priviledge, Buffer, Read, Write Control</description>
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<bitOffset>24</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
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<enumeratedValues>
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|
<enumeratedValue>
|
|
<name>MPL0</name>
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|
<description>Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.</description>
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<value>#xxx0</value>
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</enumeratedValue>
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|
<enumeratedValue>
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|
<name>MPL1</name>
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|
<description>Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.</description>
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|
<value>#xxx1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>MPROT0</name>
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<description>Master 0 Priviledge, Buffer, Read, Write Control</description>
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<bitOffset>28</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>MPL0</name>
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|
<description>Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.</description>
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|
<value>#xxx0</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
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|
<name>MPL1</name>
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|
<description>Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.</description>
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<value>#xxx1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>OPACR</name>
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<description>Off-Platform Peripheral Access Control Registers</description>
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<addressOffset>0x40</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x44444444</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>OPAC7</name>
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<description>Off-platform Peripheral Access Control 7</description>
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<bitOffset>0</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
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<enumeratedValues>
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<enumeratedValue>
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|
<name>TP0</name>
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<description>Accesses from an untrusted master are allowed.</description>
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<value>#xxx0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>TP1</name>
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<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
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<value>#xxx1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>OPAC6</name>
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<description>Off-platform Peripheral Access Control 6</description>
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<bitOffset>4</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
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|
<enumeratedValues>
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|
<enumeratedValue>
|
|
<name>TP0</name>
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|
<description>Accesses from an untrusted master are allowed.</description>
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|
<value>#xxx0</value>
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|
</enumeratedValue>
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|
<enumeratedValue>
|
|
<name>TP1</name>
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<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
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<value>#xxx1</value>
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|
</enumeratedValue>
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</enumeratedValues>
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|
</field>
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<field>
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|
<name>OPAC5</name>
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<description>Off-platform Peripheral Access Control 5</description>
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<bitOffset>8</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
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<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
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|
<description>Accesses from an untrusted master are allowed.</description>
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|
<value>#xxx0</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
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|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
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<value>#xxx1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>OPAC4</name>
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<description>Off-platform Peripheral Access Control 4</description>
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<bitOffset>12</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
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<enumeratedValues>
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|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
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|
<value>#xxx0</value>
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|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
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|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
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<value>#xxx1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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|
<name>OPAC3</name>
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<description>Off-platform Peripheral Access Control 3</description>
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<bitOffset>16</bitOffset>
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<bitWidth>4</bitWidth>
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<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
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<field>
|
|
<name>OPAC2</name>
|
|
<description>Off-platform Peripheral Access Control 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC1</name>
|
|
<description>Off-platform Peripheral Access Control 1</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC0</name>
|
|
<description>Off-platform Peripheral Access Control 0</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPACR1</name>
|
|
<description>Off-Platform Peripheral Access Control Registers</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x44444444</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OPAC15</name>
|
|
<description>Off-platform Peripheral Access Control 15</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC14</name>
|
|
<description>Off-platform Peripheral Access Control 14</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC13</name>
|
|
<description>Off-platform Peripheral Access Control 13</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC12</name>
|
|
<description>Off-platform Peripheral Access Control 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC11</name>
|
|
<description>Off-platform Peripheral Access Control 11</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC10</name>
|
|
<description>Off-platform Peripheral Access Control 10</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC9</name>
|
|
<description>Off-platform Peripheral Access Control 9</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC8</name>
|
|
<description>Off-platform Peripheral Access Control 8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPACR2</name>
|
|
<description>Off-Platform Peripheral Access Control Registers</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x44444444</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OPAC23</name>
|
|
<description>Off-platform Peripheral Access Control 23</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC22</name>
|
|
<description>Off-platform Peripheral Access Control 22</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC21</name>
|
|
<description>Off-platform Peripheral Access Control 21</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC20</name>
|
|
<description>Off-platform Peripheral Access Control 20</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC19</name>
|
|
<description>Off-platform Peripheral Access Control 19</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC18</name>
|
|
<description>Off-platform Peripheral Access Control 18</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC17</name>
|
|
<description>Off-platform Peripheral Access Control 17</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC16</name>
|
|
<description>Off-platform Peripheral Access Control 16</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPACR3</name>
|
|
<description>Off-Platform Peripheral Access Control Registers</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x44444444</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OPAC31</name>
|
|
<description>Off-platform Peripheral Access Control 31</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC30</name>
|
|
<description>Off-platform Peripheral Access Control 30</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC29</name>
|
|
<description>Off-platform Peripheral Access Control 29</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC28</name>
|
|
<description>Off-platform Peripheral Access Control 28</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC27</name>
|
|
<description>Off-platform Peripheral Access Control 27</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC26</name>
|
|
<description>Off-platform Peripheral Access Control 26</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC25</name>
|
|
<description>Off-platform Peripheral Access Control 25</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC24</name>
|
|
<description>Off-platform Peripheral Access Control 24</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPACR4</name>
|
|
<description>Off-Platform Peripheral Access Control Registers</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x44444444</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OPAC33</name>
|
|
<description>Off-platform Peripheral Access Control 33</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPAC32</name>
|
|
<description>Off-platform Peripheral Access Control 32</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TP0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#xxx0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TP1</name>
|
|
<description>Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.</description>
|
|
<value>#xxx1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="AIPSTZ1">
|
|
<name>AIPSTZ2</name>
|
|
<description>AIPSTZ Control Registers</description>
|
|
<groupName>AIPSTZ</groupName>
|
|
<prependToName>AIPSTZ2_</prependToName>
|
|
<baseAddress>0x4017C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x54</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DCDC</name>
|
|
<description>DCDC</description>
|
|
<groupName>DCDC</groupName>
|
|
<baseAddress>0x40080000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DCDC</name>
|
|
<value>69</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>REG0</name>
|
|
<description>DCDC Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x14030111</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWD_ZCD</name>
|
|
<description>power down the zero cross detection function for discontinuous conductor mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE_AUTO_CLK_SWITCH</name>
|
|
<description>Disable automatic clock switch from internal osc to xtal clock.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL_CLK</name>
|
|
<description>select 24 MHz Crystal clock for DCDC, when dcdc_disable_auto_clk_switch is set.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWD_OSC_INT</name>
|
|
<description>Power down internal osc. Only set this bit, when 24 MHz crystal osc is available</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWD_CUR_SNS_CMP</name>
|
|
<description>The power down signal of the current detector.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CUR_SNS_THRSH</name>
|
|
<description>Set the threshold of current detector, if the peak current of the inductor exceeds the threshold, the current detector will assert</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWD_OVERCUR_DET</name>
|
|
<description>power down overcurrent detection comparator</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OVERCUR_TRIG_ADJ</name>
|
|
<description>The threshold of over current detection in run mode and power save mode: run mode power save mode 0x0 1 A 0</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWD_CMP_BATT_DET</name>
|
|
<description>set to "1" to power down the low voltage detection comparator</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADJ_POSLIMIT_BUCK</name>
|
|
<description>adjust value to poslimit_buck register</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_LP_OVERLOAD_SNS</name>
|
|
<description>enable the overload detection in power save mode, if current is larger than the overloading threshold (typical value is 50 mA), DCDC will switch to the run mode automatically</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWD_HIGH_VOLT_DET</name>
|
|
<description>power down overvoltage detection comparator</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_OVERLOAD_THRSH</name>
|
|
<description>the threshold of the counting number of charging times during the period that lp_overload_freq_sel sets in power save mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_OVERLOAD_FREQ_SEL</name>
|
|
<description>the period of counting the charging times in power save mode 0: eight 32k cycle 1: sixteen 32k cycle</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_HIGH_HYS</name>
|
|
<description>Adjust hysteretic value in low power from 12.5mV to 25mV</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWD_CMP_OFFSET</name>
|
|
<description>power down output range comparator</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XTALOK_DISABLE</name>
|
|
<description>1'b1: Disable xtalok detection circuit 1'b0: Enable xtalok detection circuit</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CURRENT_ALERT_RESET</name>
|
|
<description>reset current alert signal</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_OK</name>
|
|
<description>set to 1 to switch internal ring osc to xtal 24M</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STS_DC_OK</name>
|
|
<description>Status register to indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG1</name>
|
|
<description>DCDC Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x111BA29C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG_FBK_SEL</name>
|
|
<description>select the feedback point of the internal regulator</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG_RLOAD_SW</name>
|
|
<description>control the load resistor of the internal regulator of DCDC, the load resistor is connected as default "1", and need set to "0" to disconnect the load resistor</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LP_CMP_ISRC_SEL</name>
|
|
<description>set the current bias of low power comparator 0x0: 50 nA 0x1: 100 nA 0x2: 200 nA 0x3: 400 nA</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPCTRL_HST_THRESH</name>
|
|
<description>increase the threshold detection for common mode analog comparator</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPCTRL_EN_HYST</name>
|
|
<description>Enable hysteresis in switching converter common mode analog comparators</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VBG_TRIM</name>
|
|
<description>trim bandgap voltage</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG2</name>
|
|
<description>DCDC Register 2</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x9</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOOPCTRL_DC_C</name>
|
|
<description>Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and can be used to optimize efficiency and loop response</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPCTRL_DC_R</name>
|
|
<description>Magnitude of proportional control parameter in the switching DC-DC converter control loop.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPCTRL_DC_FF</name>
|
|
<description>Two's complement feed forward step in duty cycle in the switching DC-DC converter</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPCTRL_EN_RCSCALE</name>
|
|
<description>Enable analog circuit of DC-DC converter to respond faster under transient load conditions.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPCTRL_RCSCALE_THRSH</name>
|
|
<description>Increase the threshold detection for RC scale circuit.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOOPCTRL_HYST_SIGN</name>
|
|
<description>Invert the sign of the hysteresis in DC-DC analog comparators.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BATTMONITOR_EN_BATADJ</name>
|
|
<description>This bit enables the DC-DC to improve efficiency and minimize ripple using the information from the BATT_VAL field</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE_PULSE_SKIP</name>
|
|
<description>Set to "0" : stop charging if the duty cycle is lower than what set by dcdc_neglimit_in</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DCM_SET_CTRL</name>
|
|
<description>Set high to improve the transition from heavy load to light load</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG3</name>
|
|
<description>DCDC Register 3</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10E</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRG</name>
|
|
<description>Target value of VDD_SOC, 25 mV each step 0x0: 0.8V 0xE: 1.15V 0x1F:1.575V</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TARGET_LP</name>
|
|
<description>Target value of standby (low power) mode 0x0: 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MINPWR_DC_HALFCLK</name>
|
|
<description>Set DCDC clock to half freqeuncy for continuous mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MISC_DELAY_TIMING</name>
|
|
<description>Ajust delay to reduce ground noise</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MISC_DISABLEFET_LOGIC</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE_STEP</name>
|
|
<description>Disable stepping for the output VDD_SOC of DCDC</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PIT</name>
|
|
<description>PIT</description>
|
|
<groupName>PIT</groupName>
|
|
<baseAddress>0x40084000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x140</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PIT</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>PIT Module Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRZ</name>
|
|
<description>Freeze</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRZ_0</name>
|
|
<description>Timers continue to run in Debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRZ_1</name>
|
|
<description>Timers are stopped in Debug mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDIS</name>
|
|
<description>Module Disable for PIT</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MDIS_0</name>
|
|
<description>Clock for standard PIT timers is enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDIS_1</name>
|
|
<description>Clock for standard PIT timers is disabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LTMR64H</name>
|
|
<description>PIT Upper Lifetime Timer Register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LTH</name>
|
|
<description>Life Timer value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LTMR64L</name>
|
|
<description>PIT Lower Lifetime Timer Register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LTL</name>
|
|
<description>Life Timer value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<cluster>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<name>TIMER[%s]</name>
|
|
<description>no description available</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<register>
|
|
<name>LDVAL</name>
|
|
<description>Timer Load Value Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSV</name>
|
|
<description>Timer Start Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CVAL</name>
|
|
<description>Current Timer Value Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TVL</name>
|
|
<description>Current Timer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCTRL</name>
|
|
<description>Timer Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Timer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TEN_0</name>
|
|
<description>Timer n is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEN_1</name>
|
|
<description>Timer n is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Timer Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIE_0</name>
|
|
<description>Interrupt requests from Timer n are disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIE_1</name>
|
|
<description>Interrupt is requested whenever TIF is set.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHN</name>
|
|
<description>Chain Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CHN_0</name>
|
|
<description>Timer is not chained.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHN_1</name>
|
|
<description>Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TFLG</name>
|
|
<description>Timer Flag Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>Timer Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIF_0</name>
|
|
<description>Timeout has not yet occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIF_1</name>
|
|
<description>Timeout has occurred.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC_ETC</name>
|
|
<description>ADC_ETC</description>
|
|
<groupName>ADC_ETC</groupName>
|
|
<baseAddress>0x40088000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x150</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC_ETC_IRQ0</name>
|
|
<value>75</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC_ETC_IRQ1</name>
|
|
<value>76</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC_ETC_IRQ2</name>
|
|
<value>77</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC_ETC_IRQ3</name>
|
|
<value>78</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC_ETC_ERROR_IRQ</name>
|
|
<value>79</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>ADC_ETC Global Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIG_ENABLE</name>
|
|
<description>TRIG enable register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EXT0_TRIG_ENABLE</name>
|
|
<description>TSC0 TRIG enable register. 1'b1: enable external TSC0 trigger. 1'b0: disable external TSC0 trigger.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EXT0_TRIG_PRIORITY</name>
|
|
<description>External TSC0 trigger priority, 7 is Highest, 0 is lowest .</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EXT1_TRIG_ENABLE</name>
|
|
<description>TSC1 TRIG enable register. 1'b1: enable external TSC1 trigger. 1'b0: disable external TSC1 trigger.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EXT1_TRIG_PRIORITY</name>
|
|
<description>External TSC1 trigger priority, 7 is Highest, 0 is lowest .</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRE_DIVIDER</name>
|
|
<description>Pre-divider for trig delay and interval .</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMA_MODE_SEL</name>
|
|
<description>1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSC_BYPASS</name>
|
|
<description>1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOFTRST</name>
|
|
<description>Software reset, high active. When write 1 ,all logical will be reset.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DONE0_1_IRQ</name>
|
|
<description>ETC DONE0 and DONE1 IRQ State Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIG0_DONE0</name>
|
|
<description>TRIG0 done0 interrupt detection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1_DONE0</name>
|
|
<description>TRIG1 done0 interrupt detection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2_DONE0</name>
|
|
<description>TRIG2 done0 interrupt detection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG3_DONE0</name>
|
|
<description>TRIG3 done0 interrupt detection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG4_DONE0</name>
|
|
<description>TRIG4 done0 interrupt detection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG5_DONE0</name>
|
|
<description>TRIG5 done0 interrupt detection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG6_DONE0</name>
|
|
<description>TRIG6 done0 interrupt detection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG7_DONE0</name>
|
|
<description>TRIG7 done0 interrupt detection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG0_DONE1</name>
|
|
<description>TRIG0 done1 interrupt detection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1_DONE1</name>
|
|
<description>TRIG1 done1 interrupt detection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2_DONE1</name>
|
|
<description>TRIG2 done1 interrupt detection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG3_DONE1</name>
|
|
<description>TRIG3 done1 interrupt detection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG4_DONE1</name>
|
|
<description>TRIG4 done1 interrupt detection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG5_DONE1</name>
|
|
<description>TRIG5 done1 interrupt detection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG6_DONE1</name>
|
|
<description>TRIG6 done1 interrupt detection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG7_DONE1</name>
|
|
<description>TRIG7 done1 interrupt detection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DONE2_ERR_IRQ</name>
|
|
<description>ETC DONE_2 and DONE_ERR IRQ State Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIG0_DONE2</name>
|
|
<description>TRIG0 done2 interrupt detection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1_DONE2</name>
|
|
<description>TRIG1 done2 interrupt detection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2_DONE2</name>
|
|
<description>TRIG2 done2 interrupt detection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG3_DONE2</name>
|
|
<description>TRIG3 done2 interrupt detection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG4_DONE2</name>
|
|
<description>TRIG4 done2 interrupt detection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG5_DONE2</name>
|
|
<description>TRIG5 done2 interrupt detection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG6_DONE2</name>
|
|
<description>TRIG6 done2 interrupt detection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG7_DONE2</name>
|
|
<description>TRIG7 done2 interrupt detection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG0_DONE3</name>
|
|
<description>TRIG0 done3 interrupt detection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1_DONE3</name>
|
|
<description>TRIG1 done3 interrupt detection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2_DONE3</name>
|
|
<description>TRIG2 done3 interrupt detection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG3_DONE3</name>
|
|
<description>TRIG3 done3 interrupt detection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG4_DONE3</name>
|
|
<description>TRIG4 done3 interrupt detection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG5_DONE3</name>
|
|
<description>TRIG5 done3 interrupt detection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG6_DONE3</name>
|
|
<description>TRIG6 done3 interrupt detection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG7_DONE3</name>
|
|
<description>TRIG7 done3 interrupt detection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG0_ERR</name>
|
|
<description>TRIG0 error interrupt detection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1_ERR</name>
|
|
<description>TRIG1 error interrupt detection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2_ERR</name>
|
|
<description>TRIG2 error interrupt detection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG3_ERR</name>
|
|
<description>TRIG3 error interrupt detection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG4_ERR</name>
|
|
<description>TRIG4 error interrupt detection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG5_ERR</name>
|
|
<description>TRIG5 error interrupt detection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG6_ERR</name>
|
|
<description>TRIG6 error interrupt detection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG7_ERR</name>
|
|
<description>TRIG7 error interrupt detection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CTRL</name>
|
|
<description>ETC DMA control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIG0_ENABLE</name>
|
|
<description>When TRIG0 done enable DMA request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1_ENABLE</name>
|
|
<description>When TRIG1 done enable DMA request</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2_ENABLE</name>
|
|
<description>When TRIG2 done enable DMA request</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG3_ENABLE</name>
|
|
<description>When TRIG3 done enable DMA request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG4_ENABLE</name>
|
|
<description>When TRIG4 done enable DMA request</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG5_ENABLE</name>
|
|
<description>When TRIG5 done enable DMA request</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG6_ENABLE</name>
|
|
<description>When TRIG6 done enable DMA request</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG7_ENABLE</name>
|
|
<description>When TRIG7 done enable DMA request</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG0_REQ</name>
|
|
<description>When TRIG0 done DMA request detection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1_REQ</name>
|
|
<description>When TRIG1 done DMA request detection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2_REQ</name>
|
|
<description>When TRIG2 done DMA request detection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG3_REQ</name>
|
|
<description>When TRIG3 done DMA request detection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG4_REQ</name>
|
|
<description>When TRIG4 done DMA request detection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG5_REQ</name>
|
|
<description>When TRIG5 done DMA request detection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG6_REQ</name>
|
|
<description>When TRIG6 done DMA request detection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG7_REQ</name>
|
|
<description>When TRIG7 done DMA request detection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG0_CTRL</name>
|
|
<description>ETC_TRIG Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW_TRIG</name>
|
|
<description>Software write 1 as the TRIGGER. This register is self-clearing.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_MODE</name>
|
|
<description>TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_CHAIN</name>
|
|
<description>TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_PRIORITY</name>
|
|
<description>External trigger priority, 7 is highest, 0 is lowest .</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_MODE</name>
|
|
<description>TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAINx_DONE</name>
|
|
<description>CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG0_COUNTER</name>
|
|
<description>ETC_TRIG Counter Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT_DELAY</name>
|
|
<description>TRIGGER initial delay counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE_INTERVAL</name>
|
|
<description>TRIGGER sampling interval counter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG0_CHAIN_1_0</name>
|
|
<description>ETC_TRIG Chain 0/1 Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL0</name>
|
|
<description>CHAIN0 CSEL ADC channel selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS0</name>
|
|
<description>CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B0</name>
|
|
<description>CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE0</name>
|
|
<description>CHAIN0 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE0_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL1</name>
|
|
<description>CHAIN1 CSEL ADC channel selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS1</name>
|
|
<description>CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B1</name>
|
|
<description>CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE1</name>
|
|
<description>CHAIN1 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE1_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG0_CHAIN_3_2</name>
|
|
<description>ETC_TRIG Chain 2/3 Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL2</name>
|
|
<description>CHAIN2 CSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS2</name>
|
|
<description>CHAIN2 HWTS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B2</name>
|
|
<description>CHAIN2 B2B</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE2</name>
|
|
<description>CHAIN2 IE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE2_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL3</name>
|
|
<description>CHAIN3 CSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS3</name>
|
|
<description>CHAIN3 HWTS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B3</name>
|
|
<description>CHAIN3 B2B</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE3</name>
|
|
<description>CHAIN3 IE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE3_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG0_CHAIN_5_4</name>
|
|
<description>ETC_TRIG Chain 4/5 Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL4</name>
|
|
<description>CHAIN4 CSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS4</name>
|
|
<description>CHAIN4 HWTS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B4</name>
|
|
<description>CHAIN4 B2B</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE4</name>
|
|
<description>CHAIN4 IE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE4_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL5</name>
|
|
<description>CHAIN5 CSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS5</name>
|
|
<description>CHAIN5 HWTS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B5</name>
|
|
<description>CHAIN5 B2B</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE5</name>
|
|
<description>CHAIN5 IE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE5_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG0_CHAIN_7_6</name>
|
|
<description>ETC_TRIG Chain 6/7 Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL6</name>
|
|
<description>CHAIN6 CSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS6</name>
|
|
<description>CHAIN6 HWTS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B6</name>
|
|
<description>CHAIN6 B2B</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE6</name>
|
|
<description>CHAIN6 IE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE6_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL7</name>
|
|
<description>CHAIN7 CSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS7</name>
|
|
<description>CHAIN7 HWTS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B7</name>
|
|
<description>CHAIN7 B2B</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE7</name>
|
|
<description>CHAIN7 IE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE7_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG0_RESULT_1_0</name>
|
|
<description>ETC_TRIG Result Data 1/0 Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA0</name>
|
|
<description>Result DATA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA1</name>
|
|
<description>Result DATA1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG0_RESULT_3_2</name>
|
|
<description>ETC_TRIG Result Data 3/2 Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA2</name>
|
|
<description>Result DATA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA3</name>
|
|
<description>Result DATA3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG0_RESULT_5_4</name>
|
|
<description>ETC_TRIG Result Data 5/4 Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA4</name>
|
|
<description>Result DATA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA5</name>
|
|
<description>Result DATA5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG0_RESULT_7_6</name>
|
|
<description>ETC_TRIG Result Data 7/6 Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA6</name>
|
|
<description>Result DATA6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA7</name>
|
|
<description>Result DATA7</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG1_CTRL</name>
|
|
<description>ETC_TRIG Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW_TRIG</name>
|
|
<description>Software write 1 as the TRIGGER. This register is self-clearing.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_MODE</name>
|
|
<description>TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_CHAIN</name>
|
|
<description>TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_PRIORITY</name>
|
|
<description>External trigger priority, 7 is highest, 0 is lowest .</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_MODE</name>
|
|
<description>TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAINx_DONE</name>
|
|
<description>CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG1_COUNTER</name>
|
|
<description>ETC_TRIG Counter Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT_DELAY</name>
|
|
<description>TRIGGER initial delay counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE_INTERVAL</name>
|
|
<description>TRIGGER sampling interval counter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG1_CHAIN_1_0</name>
|
|
<description>ETC_TRIG Chain 0/1 Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL0</name>
|
|
<description>CHAIN0 CSEL ADC channel selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS0</name>
|
|
<description>CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B0</name>
|
|
<description>CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE0</name>
|
|
<description>CHAIN0 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE0_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL1</name>
|
|
<description>CHAIN1 CSEL ADC channel selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS1</name>
|
|
<description>CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B1</name>
|
|
<description>CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE1</name>
|
|
<description>CHAIN1 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE1_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG1_CHAIN_3_2</name>
|
|
<description>ETC_TRIG Chain 2/3 Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL2</name>
|
|
<description>CHAIN2 CSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS2</name>
|
|
<description>CHAIN2 HWTS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B2</name>
|
|
<description>CHAIN2 B2B</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE2</name>
|
|
<description>CHAIN2 IE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE2_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL3</name>
|
|
<description>CHAIN3 CSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS3</name>
|
|
<description>CHAIN3 HWTS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B3</name>
|
|
<description>CHAIN3 B2B</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE3</name>
|
|
<description>CHAIN3 IE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE3_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG1_CHAIN_5_4</name>
|
|
<description>ETC_TRIG Chain 4/5 Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL4</name>
|
|
<description>CHAIN4 CSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS4</name>
|
|
<description>CHAIN4 HWTS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B4</name>
|
|
<description>CHAIN4 B2B</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE4</name>
|
|
<description>CHAIN4 IE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE4_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL5</name>
|
|
<description>CHAIN5 CSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS5</name>
|
|
<description>CHAIN5 HWTS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B5</name>
|
|
<description>CHAIN5 B2B</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE5</name>
|
|
<description>CHAIN5 IE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE5_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG1_CHAIN_7_6</name>
|
|
<description>ETC_TRIG Chain 6/7 Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL6</name>
|
|
<description>CHAIN6 CSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS6</name>
|
|
<description>CHAIN6 HWTS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B6</name>
|
|
<description>CHAIN6 B2B</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE6</name>
|
|
<description>CHAIN6 IE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE6_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL7</name>
|
|
<description>CHAIN7 CSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS7</name>
|
|
<description>CHAIN7 HWTS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B7</name>
|
|
<description>CHAIN7 B2B</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE7</name>
|
|
<description>CHAIN7 IE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE7_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG1_RESULT_1_0</name>
|
|
<description>ETC_TRIG Result Data 1/0 Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA0</name>
|
|
<description>Result DATA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA1</name>
|
|
<description>Result DATA1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG1_RESULT_3_2</name>
|
|
<description>ETC_TRIG Result Data 3/2 Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA2</name>
|
|
<description>Result DATA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA3</name>
|
|
<description>Result DATA3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG1_RESULT_5_4</name>
|
|
<description>ETC_TRIG Result Data 5/4 Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA4</name>
|
|
<description>Result DATA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA5</name>
|
|
<description>Result DATA5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG1_RESULT_7_6</name>
|
|
<description>ETC_TRIG Result Data 7/6 Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA6</name>
|
|
<description>Result DATA6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA7</name>
|
|
<description>Result DATA7</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG2_CTRL</name>
|
|
<description>ETC_TRIG Control Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW_TRIG</name>
|
|
<description>Software write 1 as the TRIGGER. This register is self-clearing.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_MODE</name>
|
|
<description>TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_CHAIN</name>
|
|
<description>TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_PRIORITY</name>
|
|
<description>External trigger priority, 7 is highest, 0 is lowest .</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_MODE</name>
|
|
<description>TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAINx_DONE</name>
|
|
<description>CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG2_COUNTER</name>
|
|
<description>ETC_TRIG Counter Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT_DELAY</name>
|
|
<description>TRIGGER initial delay counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE_INTERVAL</name>
|
|
<description>TRIGGER sampling interval counter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG2_CHAIN_1_0</name>
|
|
<description>ETC_TRIG Chain 0/1 Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL0</name>
|
|
<description>CHAIN0 CSEL ADC channel selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS0</name>
|
|
<description>CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B0</name>
|
|
<description>CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE0</name>
|
|
<description>CHAIN0 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE0_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL1</name>
|
|
<description>CHAIN1 CSEL ADC channel selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS1</name>
|
|
<description>CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B1</name>
|
|
<description>CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE1</name>
|
|
<description>CHAIN1 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE1_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG2_CHAIN_3_2</name>
|
|
<description>ETC_TRIG Chain 2/3 Register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL2</name>
|
|
<description>CHAIN2 CSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS2</name>
|
|
<description>CHAIN2 HWTS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B2</name>
|
|
<description>CHAIN2 B2B</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE2</name>
|
|
<description>CHAIN2 IE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE2_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL3</name>
|
|
<description>CHAIN3 CSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS3</name>
|
|
<description>CHAIN3 HWTS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B3</name>
|
|
<description>CHAIN3 B2B</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE3</name>
|
|
<description>CHAIN3 IE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE3_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG2_CHAIN_5_4</name>
|
|
<description>ETC_TRIG Chain 4/5 Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL4</name>
|
|
<description>CHAIN4 CSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS4</name>
|
|
<description>CHAIN4 HWTS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B4</name>
|
|
<description>CHAIN4 B2B</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE4</name>
|
|
<description>CHAIN4 IE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE4_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL5</name>
|
|
<description>CHAIN5 CSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS5</name>
|
|
<description>CHAIN5 HWTS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B5</name>
|
|
<description>CHAIN5 B2B</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE5</name>
|
|
<description>CHAIN5 IE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE5_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG2_CHAIN_7_6</name>
|
|
<description>ETC_TRIG Chain 6/7 Register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL6</name>
|
|
<description>CHAIN6 CSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS6</name>
|
|
<description>CHAIN6 HWTS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B6</name>
|
|
<description>CHAIN6 B2B</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE6</name>
|
|
<description>CHAIN6 IE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE6_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL7</name>
|
|
<description>CHAIN7 CSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS7</name>
|
|
<description>CHAIN7 HWTS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B7</name>
|
|
<description>CHAIN7 B2B</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE7</name>
|
|
<description>CHAIN7 IE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE7_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG2_RESULT_1_0</name>
|
|
<description>ETC_TRIG Result Data 1/0 Register</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA0</name>
|
|
<description>Result DATA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA1</name>
|
|
<description>Result DATA1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG2_RESULT_3_2</name>
|
|
<description>ETC_TRIG Result Data 3/2 Register</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA2</name>
|
|
<description>Result DATA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA3</name>
|
|
<description>Result DATA3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG2_RESULT_5_4</name>
|
|
<description>ETC_TRIG Result Data 5/4 Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA4</name>
|
|
<description>Result DATA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA5</name>
|
|
<description>Result DATA5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG2_RESULT_7_6</name>
|
|
<description>ETC_TRIG Result Data 7/6 Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA6</name>
|
|
<description>Result DATA6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA7</name>
|
|
<description>Result DATA7</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG3_CTRL</name>
|
|
<description>ETC_TRIG Control Register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW_TRIG</name>
|
|
<description>Software write 1 as the TRIGGER. This register is self-clearing.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_MODE</name>
|
|
<description>TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_CHAIN</name>
|
|
<description>TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIG_PRIORITY</name>
|
|
<description>External trigger priority, 7 is highest, 0 is lowest .</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_MODE</name>
|
|
<description>TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAINx_DONE</name>
|
|
<description>CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG3_COUNTER</name>
|
|
<description>ETC_TRIG Counter Register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT_DELAY</name>
|
|
<description>TRIGGER initial delay counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE_INTERVAL</name>
|
|
<description>TRIGGER sampling interval counter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG3_CHAIN_1_0</name>
|
|
<description>ETC_TRIG Chain 0/1 Register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL0</name>
|
|
<description>CHAIN0 CSEL ADC channel selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS0</name>
|
|
<description>CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B0</name>
|
|
<description>CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE0</name>
|
|
<description>CHAIN0 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE0_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL1</name>
|
|
<description>CHAIN1 CSEL ADC channel selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS1</name>
|
|
<description>CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B1</name>
|
|
<description>CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE1</name>
|
|
<description>CHAIN1 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE1_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG3_CHAIN_3_2</name>
|
|
<description>ETC_TRIG Chain 2/3 Register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL2</name>
|
|
<description>CHAIN2 CSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS2</name>
|
|
<description>CHAIN2 HWTS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B2</name>
|
|
<description>CHAIN2 B2B</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE2</name>
|
|
<description>CHAIN2 IE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE2_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL3</name>
|
|
<description>CHAIN3 CSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS3</name>
|
|
<description>CHAIN3 HWTS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B3</name>
|
|
<description>CHAIN3 B2B</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE3</name>
|
|
<description>CHAIN3 IE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE3_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG3_CHAIN_5_4</name>
|
|
<description>ETC_TRIG Chain 4/5 Register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL4</name>
|
|
<description>CHAIN4 CSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS4</name>
|
|
<description>CHAIN4 HWTS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B4</name>
|
|
<description>CHAIN4 B2B</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE4</name>
|
|
<description>CHAIN4 IE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE4_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL5</name>
|
|
<description>CHAIN5 CSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS5</name>
|
|
<description>CHAIN5 HWTS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B5</name>
|
|
<description>CHAIN5 B2B</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE5</name>
|
|
<description>CHAIN5 IE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE5_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG3_CHAIN_7_6</name>
|
|
<description>ETC_TRIG Chain 6/7 Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSEL6</name>
|
|
<description>CHAIN6 CSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS6</name>
|
|
<description>CHAIN6 HWTS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B6</name>
|
|
<description>CHAIN6 B2B</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE6</name>
|
|
<description>CHAIN6 IE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE6_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSEL7</name>
|
|
<description>CHAIN7 CSEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HWTS7</name>
|
|
<description>CHAIN7 HWTS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>B2B7</name>
|
|
<description>CHAIN7 B2B</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE7</name>
|
|
<description>CHAIN7 IE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IE7_EN</name>
|
|
<description>IRQ enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG3_RESULT_1_0</name>
|
|
<description>ETC_TRIG Result Data 1/0 Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA0</name>
|
|
<description>Result DATA0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA1</name>
|
|
<description>Result DATA1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG3_RESULT_3_2</name>
|
|
<description>ETC_TRIG Result Data 3/2 Register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA2</name>
|
|
<description>Result DATA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA3</name>
|
|
<description>Result DATA3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG3_RESULT_5_4</name>
|
|
<description>ETC_TRIG Result Data 5/4 Register</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA4</name>
|
|
<description>Result DATA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA5</name>
|
|
<description>Result DATA5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIG3_RESULT_7_6</name>
|
|
<description>ETC_TRIG Result Data 7/6 Register</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA6</name>
|
|
<description>Result DATA6</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA7</name>
|
|
<description>Result DATA7</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AOI</name>
|
|
<description>AND/OR/INVERT module</description>
|
|
<groupName>AOI</groupName>
|
|
<prependToName>AOI_</prependToName>
|
|
<baseAddress>0x40094000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>BFCRT01%s</name>
|
|
<description>Boolean Function Term 0 and 1 Configuration Register for EVENTn</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT1_DC</name>
|
|
<description>Product term 1, D input configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT1_DC_0</name>
|
|
<description>Force the D input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT1_DC_1</name>
|
|
<description>Pass the D input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT1_DC_2</name>
|
|
<description>Complement the D input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT1_DC_3</name>
|
|
<description>Force the D input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT1_CC</name>
|
|
<description>Product term 1, C input configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT1_CC_0</name>
|
|
<description>Force the C input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT1_CC_1</name>
|
|
<description>Pass the C input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT1_CC_2</name>
|
|
<description>Complement the C input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT1_CC_3</name>
|
|
<description>Force the C input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT1_BC</name>
|
|
<description>Product term 1, B input configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT1_BC_0</name>
|
|
<description>Force the B input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT1_BC_1</name>
|
|
<description>Pass the B input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT1_BC_2</name>
|
|
<description>Complement the B input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT1_BC_3</name>
|
|
<description>Force the B input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT1_AC</name>
|
|
<description>Product term 1, A input configuration</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT1_AC_0</name>
|
|
<description>Force the A input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT1_AC_1</name>
|
|
<description>Pass the A input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT1_AC_2</name>
|
|
<description>Complement the A input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT1_AC_3</name>
|
|
<description>Force the A input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT0_DC</name>
|
|
<description>Product term 0, D input configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT0_DC_0</name>
|
|
<description>Force the D input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT0_DC_1</name>
|
|
<description>Pass the D input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT0_DC_2</name>
|
|
<description>Complement the D input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT0_DC_3</name>
|
|
<description>Force the D input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT0_CC</name>
|
|
<description>Product term 0, C input configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT0_CC_0</name>
|
|
<description>Force the C input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT0_CC_1</name>
|
|
<description>Pass the C input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT0_CC_2</name>
|
|
<description>Complement the C input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT0_CC_3</name>
|
|
<description>Force the C input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT0_BC</name>
|
|
<description>Product term 0, B input configuration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT0_BC_0</name>
|
|
<description>Force the B input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT0_BC_1</name>
|
|
<description>Pass the B input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT0_BC_2</name>
|
|
<description>Complement the B input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT0_BC_3</name>
|
|
<description>Force the B input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT0_AC</name>
|
|
<description>Product term 0, A input configuration</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT0_AC_0</name>
|
|
<description>Force the A input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT0_AC_1</name>
|
|
<description>Pass the A input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT0_AC_2</name>
|
|
<description>Complement the A input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT0_AC_3</name>
|
|
<description>Force the A input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>BFCRT23%s</name>
|
|
<description>Boolean Function Term 2 and 3 Configuration Register for EVENTn</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT3_DC</name>
|
|
<description>Product term 3, D input configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT3_DC_0</name>
|
|
<description>Force the D input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT3_DC_1</name>
|
|
<description>Pass the D input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT3_DC_2</name>
|
|
<description>Complement the D input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT3_DC_3</name>
|
|
<description>Force the D input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT3_CC</name>
|
|
<description>Product term 3, C input configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT3_CC_0</name>
|
|
<description>Force the C input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT3_CC_1</name>
|
|
<description>Pass the C input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT3_CC_2</name>
|
|
<description>Complement the C input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT3_CC_3</name>
|
|
<description>Force the C input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT3_BC</name>
|
|
<description>Product term 3, B input configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT3_BC_0</name>
|
|
<description>Force the B input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT3_BC_1</name>
|
|
<description>Pass the B input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT3_BC_2</name>
|
|
<description>Complement the B input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT3_BC_3</name>
|
|
<description>Force the B input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT3_AC</name>
|
|
<description>Product term 3, A input configuration</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT3_AC_0</name>
|
|
<description>Force the A input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT3_AC_1</name>
|
|
<description>Pass the A input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT3_AC_2</name>
|
|
<description>Complement the A input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT3_AC_3</name>
|
|
<description>Force the A input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT2_DC</name>
|
|
<description>Product term 2, D input configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT2_DC_0</name>
|
|
<description>Force the D input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT2_DC_1</name>
|
|
<description>Pass the D input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT2_DC_2</name>
|
|
<description>Complement the D input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT2_DC_3</name>
|
|
<description>Force the D input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT2_CC</name>
|
|
<description>Product term 2, C input configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT2_CC_0</name>
|
|
<description>Force the C input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT2_CC_1</name>
|
|
<description>Pass the C input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT2_CC_2</name>
|
|
<description>Complement the C input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT2_CC_3</name>
|
|
<description>Force the C input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT2_BC</name>
|
|
<description>Product term 2, B input configuration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT2_BC_0</name>
|
|
<description>Force the B input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT2_BC_1</name>
|
|
<description>Pass the B input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT2_BC_2</name>
|
|
<description>Complement the B input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT2_BC_3</name>
|
|
<description>Force the B input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PT2_AC</name>
|
|
<description>Product term 2, A input configuration</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT2_AC_0</name>
|
|
<description>Force the A input in this product term to a logical zero</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT2_AC_1</name>
|
|
<description>Pass the A input in this product term</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT2_AC_2</name>
|
|
<description>Complement the A input in this product term</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT2_AC_3</name>
|
|
<description>Force the A input in this product term to a logical one</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>XBARA</name>
|
|
<description>Crossbar Switch</description>
|
|
<groupName>XBARA</groupName>
|
|
<prependToName>XBARA_</prependToName>
|
|
<baseAddress>0x40098000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x88</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SEL0</name>
|
|
<description>Crossbar A Select Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT0 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT1 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL1</name>
|
|
<description>Crossbar A Select Register 1</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL3</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT3 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL2</name>
|
|
<description>Crossbar A Select Register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL4</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT4 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL5</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT5 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL3</name>
|
|
<description>Crossbar A Select Register 3</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL6</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL7</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT7 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL4</name>
|
|
<description>Crossbar A Select Register 4</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL8</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT8 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL9</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT9 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL5</name>
|
|
<description>Crossbar A Select Register 5</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL10</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT10 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL11</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT11 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL6</name>
|
|
<description>Crossbar A Select Register 6</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL12</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT12 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL13</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL7</name>
|
|
<description>Crossbar A Select Register 7</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL14</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT14 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL15</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT15 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL8</name>
|
|
<description>Crossbar A Select Register 8</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL16</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT16 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL17</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL9</name>
|
|
<description>Crossbar A Select Register 9</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL18</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT18 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL19</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT19 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL10</name>
|
|
<description>Crossbar A Select Register 10</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL20</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT20 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL21</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL11</name>
|
|
<description>Crossbar A Select Register 11</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL22</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT22 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL23</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT23 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL12</name>
|
|
<description>Crossbar A Select Register 12</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL24</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT24 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL25</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL13</name>
|
|
<description>Crossbar A Select Register 13</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL26</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT26 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL27</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT27 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL14</name>
|
|
<description>Crossbar A Select Register 14</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL28</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT28 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL29</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL15</name>
|
|
<description>Crossbar A Select Register 15</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL30</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT30 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL31</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT31 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL16</name>
|
|
<description>Crossbar A Select Register 16</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL32</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT32 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL33</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL17</name>
|
|
<description>Crossbar A Select Register 17</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL34</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT34 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL35</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT35 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL18</name>
|
|
<description>Crossbar A Select Register 18</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL36</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT36 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL37</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL19</name>
|
|
<description>Crossbar A Select Register 19</description>
|
|
<addressOffset>0x26</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL38</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT38 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL39</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT39 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL20</name>
|
|
<description>Crossbar A Select Register 20</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL40</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT40 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL41</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL21</name>
|
|
<description>Crossbar A Select Register 21</description>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL42</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT42 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL43</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT43 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL22</name>
|
|
<description>Crossbar A Select Register 22</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL44</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT44 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL45</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL23</name>
|
|
<description>Crossbar A Select Register 23</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL46</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT46 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL47</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT47 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL24</name>
|
|
<description>Crossbar A Select Register 24</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL48</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT48 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL49</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL25</name>
|
|
<description>Crossbar A Select Register 25</description>
|
|
<addressOffset>0x32</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL50</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT50 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL51</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT51 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL26</name>
|
|
<description>Crossbar A Select Register 26</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL52</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT52 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL53</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL27</name>
|
|
<description>Crossbar A Select Register 27</description>
|
|
<addressOffset>0x36</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL54</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT54 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL55</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT55 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL28</name>
|
|
<description>Crossbar A Select Register 28</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL56</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT56 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL57</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL29</name>
|
|
<description>Crossbar A Select Register 29</description>
|
|
<addressOffset>0x3A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL58</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT58 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL59</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT59 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL30</name>
|
|
<description>Crossbar A Select Register 30</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL60</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT60 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL61</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT61 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL31</name>
|
|
<description>Crossbar A Select Register 31</description>
|
|
<addressOffset>0x3E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL62</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT62 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL63</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT63 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL32</name>
|
|
<description>Crossbar A Select Register 32</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL64</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT64 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL65</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT65 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL33</name>
|
|
<description>Crossbar A Select Register 33</description>
|
|
<addressOffset>0x42</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL66</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT66 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL67</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT67 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL34</name>
|
|
<description>Crossbar A Select Register 34</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL68</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT68 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL69</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT69 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL35</name>
|
|
<description>Crossbar A Select Register 35</description>
|
|
<addressOffset>0x46</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL70</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT70 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL71</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT71 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL36</name>
|
|
<description>Crossbar A Select Register 36</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL72</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT72 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL73</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT73 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL37</name>
|
|
<description>Crossbar A Select Register 37</description>
|
|
<addressOffset>0x4A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL74</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT74 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL75</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT75 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL38</name>
|
|
<description>Crossbar A Select Register 38</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL76</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT76 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL77</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT77 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL39</name>
|
|
<description>Crossbar A Select Register 39</description>
|
|
<addressOffset>0x4E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL78</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT78 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL79</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT79 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL40</name>
|
|
<description>Crossbar A Select Register 40</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL80</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT80 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL81</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT81 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL41</name>
|
|
<description>Crossbar A Select Register 41</description>
|
|
<addressOffset>0x52</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL82</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT82 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL83</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT83 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL42</name>
|
|
<description>Crossbar A Select Register 42</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL84</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT84 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL85</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT85 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL43</name>
|
|
<description>Crossbar A Select Register 43</description>
|
|
<addressOffset>0x56</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL86</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT86 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL87</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT87 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL44</name>
|
|
<description>Crossbar A Select Register 44</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL88</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT88 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL89</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT89 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL45</name>
|
|
<description>Crossbar A Select Register 45</description>
|
|
<addressOffset>0x5A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL90</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT90 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL91</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT91 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL46</name>
|
|
<description>Crossbar A Select Register 46</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL92</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT92 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL93</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT93 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL47</name>
|
|
<description>Crossbar A Select Register 47</description>
|
|
<addressOffset>0x5E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL94</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT94 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL95</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT95 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL48</name>
|
|
<description>Crossbar A Select Register 48</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL96</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT96 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL97</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT97 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL49</name>
|
|
<description>Crossbar A Select Register 49</description>
|
|
<addressOffset>0x62</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL98</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT98 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL99</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT99 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL50</name>
|
|
<description>Crossbar A Select Register 50</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL100</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT100 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL101</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT101 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL51</name>
|
|
<description>Crossbar A Select Register 51</description>
|
|
<addressOffset>0x66</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL102</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT102 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL103</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT103 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL52</name>
|
|
<description>Crossbar A Select Register 52</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL104</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT104 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL105</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT105 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL53</name>
|
|
<description>Crossbar A Select Register 53</description>
|
|
<addressOffset>0x6A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL106</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT106 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL107</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT107 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL54</name>
|
|
<description>Crossbar A Select Register 54</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL108</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT108 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL109</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT109 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL55</name>
|
|
<description>Crossbar A Select Register 55</description>
|
|
<addressOffset>0x6E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL110</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT110 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL111</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT111 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL56</name>
|
|
<description>Crossbar A Select Register 56</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL112</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT112 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL113</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT113 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL57</name>
|
|
<description>Crossbar A Select Register 57</description>
|
|
<addressOffset>0x72</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL114</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT114 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL115</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT115 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL58</name>
|
|
<description>Crossbar A Select Register 58</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL116</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT116 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL117</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT117 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL59</name>
|
|
<description>Crossbar A Select Register 59</description>
|
|
<addressOffset>0x76</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL118</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT118 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL119</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT119 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL60</name>
|
|
<description>Crossbar A Select Register 60</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL120</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT120 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL121</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT121 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL61</name>
|
|
<description>Crossbar A Select Register 61</description>
|
|
<addressOffset>0x7A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL122</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT122 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL123</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT123 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL62</name>
|
|
<description>Crossbar A Select Register 62</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL124</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT124 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL125</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT125 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL63</name>
|
|
<description>Crossbar A Select Register 63</description>
|
|
<addressOffset>0x7E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL126</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT126 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL127</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT127 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL64</name>
|
|
<description>Crossbar A Select Register 64</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL128</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT128 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL129</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT129 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEL65</name>
|
|
<description>Crossbar A Select Register 65</description>
|
|
<addressOffset>0x82</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL130</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT130 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL131</name>
|
|
<description>Input (XBARA_INn) to be muxed to XBARA_OUT131 (refer to Functional Description section for input/output assignment)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL0</name>
|
|
<description>Crossbar A Control Register 0</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEN0</name>
|
|
<description>DMA Enable for XBAR_OUT0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DEN0_0</name>
|
|
<description>DMA disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEN0_1</name>
|
|
<description>DMA enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IEN0</name>
|
|
<description>Interrupt Enable for XBAR_OUT0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IEN0_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IEN0_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE0</name>
|
|
<description>Active edge for edge detection on XBAR_OUT0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE0_0</name>
|
|
<description>STS0 never asserts</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE0_1</name>
|
|
<description>STS0 asserts on rising edges of XBAR_OUT0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE0_2</name>
|
|
<description>STS0 asserts on falling edges of XBAR_OUT0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE0_3</name>
|
|
<description>STS0 asserts on rising and falling edges of XBAR_OUT0</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STS0</name>
|
|
<description>Edge detection status for XBAR_OUT0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STS0_0</name>
|
|
<description>Active edge not yet detected on XBAR_OUT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STS0_1</name>
|
|
<description>Active edge detected on XBAR_OUT0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEN1</name>
|
|
<description>DMA Enable for XBAR_OUT1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DEN1_0</name>
|
|
<description>DMA disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEN1_1</name>
|
|
<description>DMA enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IEN1</name>
|
|
<description>Interrupt Enable for XBAR_OUT1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IEN1_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IEN1_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE1</name>
|
|
<description>Active edge for edge detection on XBAR_OUT1</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE1_0</name>
|
|
<description>STS1 never asserts</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE1_1</name>
|
|
<description>STS1 asserts on rising edges of XBAR_OUT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE1_2</name>
|
|
<description>STS1 asserts on falling edges of XBAR_OUT1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE1_3</name>
|
|
<description>STS1 asserts on rising and falling edges of XBAR_OUT1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STS1</name>
|
|
<description>Edge detection status for XBAR_OUT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STS1_0</name>
|
|
<description>Active edge not yet detected on XBAR_OUT1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STS1_1</name>
|
|
<description>Active edge detected on XBAR_OUT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL1</name>
|
|
<description>Crossbar A Control Register 1</description>
|
|
<addressOffset>0x86</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEN2</name>
|
|
<description>DMA Enable for XBAR_OUT2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DEN2_0</name>
|
|
<description>DMA disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEN2_1</name>
|
|
<description>DMA enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IEN2</name>
|
|
<description>Interrupt Enable for XBAR_OUT2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IEN2_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IEN2_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE2</name>
|
|
<description>Active edge for edge detection on XBAR_OUT2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE2_0</name>
|
|
<description>STS2 never asserts</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE2_1</name>
|
|
<description>STS2 asserts on rising edges of XBAR_OUT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE2_2</name>
|
|
<description>STS2 asserts on falling edges of XBAR_OUT2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE2_3</name>
|
|
<description>STS2 asserts on rising and falling edges of XBAR_OUT2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STS2</name>
|
|
<description>Edge detection status for XBAR_OUT2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STS2_0</name>
|
|
<description>Active edge not yet detected on XBAR_OUT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STS2_1</name>
|
|
<description>Active edge detected on XBAR_OUT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEN3</name>
|
|
<description>DMA Enable for XBAR_OUT3</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DEN3_0</name>
|
|
<description>DMA disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEN3_1</name>
|
|
<description>DMA enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IEN3</name>
|
|
<description>Interrupt Enable for XBAR_OUT3</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IEN3_0</name>
|
|
<description>Interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IEN3_1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE3</name>
|
|
<description>Active edge for edge detection on XBAR_OUT3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGE3_0</name>
|
|
<description>STS3 never asserts</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE3_1</name>
|
|
<description>STS3 asserts on rising edges of XBAR_OUT3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE3_2</name>
|
|
<description>STS3 asserts on falling edges of XBAR_OUT3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE3_3</name>
|
|
<description>STS3 asserts on rising and falling edges of XBAR_OUT3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STS3</name>
|
|
<description>Edge detection status for XBAR_OUT3</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STS3_0</name>
|
|
<description>Active edge not yet detected on XBAR_OUT3</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STS3_1</name>
|
|
<description>Active edge detected on XBAR_OUT3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLEXSPI</name>
|
|
<description>FlexSPI</description>
|
|
<groupName>FlexSPI</groupName>
|
|
<baseAddress>0x400A0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FLEXSPI</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MCR0</name>
|
|
<description>Module Control Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF80C2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SWRESET</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MDIS</name>
|
|
<description>Module Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCLKSRC</name>
|
|
<description>Sample Clock source selection for Flash Reading</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXCLKSRC_0</name>
|
|
<description>Dummy Read strobe generated by FlexSPI Controller and loopback internally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXCLKSRC_1</name>
|
|
<description>Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXCLKSRC_3</name>
|
|
<description>Flash provided Read strobe and input from DQS pad</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARDFEN</name>
|
|
<description>Enable AHB bus Read Access to IP RX FIFO.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARDFEN_0</name>
|
|
<description>IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARDFEN_1</name>
|
|
<description>IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATDFEN</name>
|
|
<description>Enable AHB bus Write Access to IP TX FIFO.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ATDFEN_0</name>
|
|
<description>IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ATDFEN_1</name>
|
|
<description>IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SERCLKDIV</name>
|
|
<description>The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SERCLKDIV_0</name>
|
|
<description>Divided by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCLKDIV_1</name>
|
|
<description>Divided by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCLKDIV_2</name>
|
|
<description>Divided by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCLKDIV_3</name>
|
|
<description>Divided by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCLKDIV_4</name>
|
|
<description>Divided by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCLKDIV_5</name>
|
|
<description>Divided by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCLKDIV_6</name>
|
|
<description>Divided by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERCLKDIV_7</name>
|
|
<description>Divided by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSEN</name>
|
|
<description>Half Speed Serial Flash access Enable.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HSEN_0</name>
|
|
<description>Disable divide by 2 of serial flash clock for half speed commands.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HSEN_1</name>
|
|
<description>Enable divide by 2 of serial flash clock for half speed commands.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEEN</name>
|
|
<description>Doze mode enable bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DOZEEN_0</name>
|
|
<description>Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOZEEN_1</name>
|
|
<description>Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINATIONEN</name>
|
|
<description>This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]).</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMBINATIONEN_0</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMBINATIONEN_1</name>
|
|
<description>Enable.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCKFREERUNEN</name>
|
|
<description>This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SCKFREERUNEN_0</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCKFREERUNEN_1</name>
|
|
<description>Enable.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IPGRANTWAIT</name>
|
|
<description>Time out wait cycle for IP command grant.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBGRANTWAIT</name>
|
|
<description>Timeout wait cycle for AHB command grant.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR1</name>
|
|
<description>Module Control Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AHBBUSWAIT</name>
|
|
<description>AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEQWAIT</name>
|
|
<description>Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR2</name>
|
|
<description>Module Control Register 2</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x200081F7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRAHBBUFOPT</name>
|
|
<description>This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLRAHBBUFOPT_0</name>
|
|
<description>AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLRAHBBUFOPT_1</name>
|
|
<description>AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRLEARNPHASE</name>
|
|
<description>The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAMEDEVICEEN</name>
|
|
<description>All external devices are same devices (both in types and size) for A1/A2/B1/B2.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAMEDEVICEEN_0</name>
|
|
<description>In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMEDEVICEEN_1</name>
|
|
<description>FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCKBDIFFOPT</name>
|
|
<description>B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SCKBDIFFOPT_0</name>
|
|
<description>B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCKBDIFFOPT_1</name>
|
|
<description>B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESUMEWAIT</name>
|
|
<description>Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBCR</name>
|
|
<description>AHB Bus Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>APAREN</name>
|
|
<description>Parallel mode enabled for AHB triggered Command (both read and write) .</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>APAREN_0</name>
|
|
<description>Flash will be accessed in Individual mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>APAREN_1</name>
|
|
<description>Flash will be accessed in Parallel mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRAHBRXBUF</name>
|
|
<description>Clear the status/pointers of AHB RX Buffer. Auto-cleared.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLRAHBTXBUF</name>
|
|
<description>Clear the status/pointers of AHB TX Buffer. Auto-cleared.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CACHABLEEN</name>
|
|
<description>Enable AHB bus cachable read access support.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CACHABLEEN_0</name>
|
|
<description>Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CACHABLEEN_1</name>
|
|
<description>Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUFFERABLEEN</name>
|
|
<description>Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BUFFERABLEEN_0</name>
|
|
<description>Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUFFERABLEEN_1</name>
|
|
<description>Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PREFETCHEN</name>
|
|
<description>AHB Read Prefetch Enable.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>READADDROPT</name>
|
|
<description>AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READADDROPT_0</name>
|
|
<description>There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READADDROPT_1</name>
|
|
<description>There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>READSZALIGN</name>
|
|
<description>AHB Read Size Alignment</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>READSZALIGN_0</name>
|
|
<description>AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN...</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READSZALIGN_1</name>
|
|
<description>AHB read size to up size to 8 bytes aligned, no prefetching</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPCMDDONEEN</name>
|
|
<description>IP triggered Command Sequences Execution finished interrupt enable.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IPCMDGEEN</name>
|
|
<description>IP triggered Command Sequences Grant Timeout interrupt enable.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBCMDGEEN</name>
|
|
<description>AHB triggered Command Sequences Grant Timeout interrupt enable.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IPCMDERREN</name>
|
|
<description>IP triggered Command Sequences Error Detected interrupt enable.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBCMDERREN</name>
|
|
<description>AHB triggered Command Sequences Error Detected interrupt enable.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IPRXWAEN</name>
|
|
<description>IP RX FIFO WaterMark available interrupt enable.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IPTXWEEN</name>
|
|
<description>IP TX FIFO WaterMark empty interrupt enable.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCKSTOPBYRDEN</name>
|
|
<description>SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCKSTOPBYWREN</name>
|
|
<description>SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBBUSERROREN</name>
|
|
<description>AHB Bus error interrupt enable.Refer Interrupts chapter for more details.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEQTIMEOUTEN</name>
|
|
<description>Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>KEYDONEEN</name>
|
|
<description>OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>KEYERROREN</name>
|
|
<description>OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTR</name>
|
|
<description>Interrupt Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPCMDDONE</name>
|
|
<description>IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IPCMDGE</name>
|
|
<description>IP triggered Command Sequences Grant Timeout interrupt.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>AHBCMDGE</name>
|
|
<description>AHB triggered Command Sequences Grant Timeout interrupt.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IPCMDERR</name>
|
|
<description>IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>AHBCMDERR</name>
|
|
<description>AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IPRXWA</name>
|
|
<description>IP RX FIFO watermark available interrupt.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IPTXWE</name>
|
|
<description>IP TX FIFO watermark empty interrupt.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>SCKSTOPBYRD</name>
|
|
<description>SCLK is stopped during command sequence because Async RX FIFO full interrupt.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>SCKSTOPBYWR</name>
|
|
<description>SCLK is stopped during command sequence because Async TX FIFO empty interrupt.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>AHBBUSERROR</name>
|
|
<description>AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>SEQTIMEOUT</name>
|
|
<description>Sequence execution timeout interrupt.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>KEYDONE</name>
|
|
<description>OTFAD key blob processing done interrupt.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>KEYERROR</name>
|
|
<description>OTFAD key blob processing error interrupt.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LUTKEY</name>
|
|
<description>LUT Key Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5AF05AF0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>The Key to lock or unlock LUT.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LUTCR</name>
|
|
<description>LUT Control Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock LUT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UNLOCK</name>
|
|
<description>Unlock LUT</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBRXBUF0CR0</name>
|
|
<description>AHB RX Buffer 0 Control Register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000020</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUFSZ</name>
|
|
<description>AHB RX Buffer Size in 64 bits.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTRID</name>
|
|
<description>This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRIORITY</name>
|
|
<description>This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PREFETCHEN</name>
|
|
<description>AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBRXBUF1CR0</name>
|
|
<description>AHB RX Buffer 1 Control Register 0</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80010020</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUFSZ</name>
|
|
<description>AHB RX Buffer Size in 64 bits.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTRID</name>
|
|
<description>This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRIORITY</name>
|
|
<description>This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PREFETCHEN</name>
|
|
<description>AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBRXBUF2CR0</name>
|
|
<description>AHB RX Buffer 2 Control Register 0</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80020020</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUFSZ</name>
|
|
<description>AHB RX Buffer Size in 64 bits.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTRID</name>
|
|
<description>This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRIORITY</name>
|
|
<description>This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PREFETCHEN</name>
|
|
<description>AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBRXBUF3CR0</name>
|
|
<description>AHB RX Buffer 3 Control Register 0</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80030020</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUFSZ</name>
|
|
<description>AHB RX Buffer Size in 64 bits.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTRID</name>
|
|
<description>This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRIORITY</name>
|
|
<description>This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PREFETCHEN</name>
|
|
<description>AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLSHA1CR0</name>
|
|
<description>Flash Control Register 0</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLSHSZ</name>
|
|
<description>Flash Size in KByte.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>23</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLSHA2CR0</name>
|
|
<description>Flash Control Register 0</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLSHSZ</name>
|
|
<description>Flash Size in KByte.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>23</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLSHB1CR0</name>
|
|
<description>Flash Control Register 0</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLSHSZ</name>
|
|
<description>Flash Size in KByte.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>23</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLSHB2CR0</name>
|
|
<description>Flash Control Register 0</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLSHSZ</name>
|
|
<description>Flash Size in KByte.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>23</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A1,A2,B1,B2</dimIndex>
|
|
<name>FLSHCR1%s</name>
|
|
<description>Flash Control Register 1</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x63</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCSS</name>
|
|
<description>Serial Flash CS setup time.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCSH</name>
|
|
<description>Serial Flash CS Hold time.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WA</name>
|
|
<description>Word Addressable.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAS</name>
|
|
<description>Column Address Size.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSINTERVALUNIT</name>
|
|
<description>CS interval unit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CSINTERVALUNIT_0</name>
|
|
<description>The CS interval unit is 1 serial clock cycle</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CSINTERVALUNIT_1</name>
|
|
<description>The CS interval unit is 256 serial clock cycle</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSINTERVAL</name>
|
|
<description>This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A1,A2,B1,B2</dimIndex>
|
|
<name>FLSHCR2%s</name>
|
|
<description>Flash Control Register 2</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARDSEQID</name>
|
|
<description>Sequence Index for AHB Read triggered Command in LUT.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARDSEQNUM</name>
|
|
<description>Sequence Number for AHB Read triggered Command in LUT.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AWRSEQID</name>
|
|
<description>Sequence Index for AHB Write triggered Command.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AWRSEQNUM</name>
|
|
<description>Sequence Number for AHB Write triggered Command.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AWRWAIT</name>
|
|
<description>For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AWRWAITUNIT</name>
|
|
<description>AWRWAIT unit</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AWRWAITUNIT_0</name>
|
|
<description>The AWRWAIT unit is 2 ahb clock cycle</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWRWAITUNIT_1</name>
|
|
<description>The AWRWAIT unit is 8 ahb clock cycle</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWRWAITUNIT_2</name>
|
|
<description>The AWRWAIT unit is 32 ahb clock cycle</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWRWAITUNIT_3</name>
|
|
<description>The AWRWAIT unit is 128 ahb clock cycle</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWRWAITUNIT_4</name>
|
|
<description>The AWRWAIT unit is 512 ahb clock cycle</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWRWAITUNIT_5</name>
|
|
<description>The AWRWAIT unit is 2048 ahb clock cycle</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWRWAITUNIT_6</name>
|
|
<description>The AWRWAIT unit is 8192 ahb clock cycle</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWRWAITUNIT_7</name>
|
|
<description>The AWRWAIT unit is 32768 ahb clock cycle</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRINSTRPTR</name>
|
|
<description>Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLSHCR4</name>
|
|
<description>Flash Control Register 4</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WMOPT1</name>
|
|
<description>Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WMOPT1_0</name>
|
|
<description>DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WMOPT1_1</name>
|
|
<description>DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WMENA</name>
|
|
<description>Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WMENA_0</name>
|
|
<description>Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WMENA_1</name>
|
|
<description>Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WMENB</name>
|
|
<description>Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WMENB_0</name>
|
|
<description>Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WMENB_1</name>
|
|
<description>Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPCR0</name>
|
|
<description>IP Control Register 0</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SFAR</name>
|
|
<description>Serial Flash Address for IP command.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPCR1</name>
|
|
<description>IP Control Register 1</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IDATSZ</name>
|
|
<description>Flash Read/Program Data Size (in Bytes) for IP command.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISEQID</name>
|
|
<description>Sequence Index in LUT for IP command.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISEQNUM</name>
|
|
<description>Sequence Number for IP command: ISEQNUM+1.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IPAREN</name>
|
|
<description>Parallel mode Enabled for IP command.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IPAREN_0</name>
|
|
<description>Flash will be accessed in Individual mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IPAREN_1</name>
|
|
<description>Flash will be accessed in Parallel mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPCMD</name>
|
|
<description>IP Command Register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRG</name>
|
|
<description>Setting this bit will trigger an IP Command.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPRXFCR</name>
|
|
<description>IP RX FIFO Control Register</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRIPRXF</name>
|
|
<description>Clear all valid data entries in IP RX FIFO.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDMAEN</name>
|
|
<description>IP RX FIFO reading by DMA enabled.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXDMAEN_0</name>
|
|
<description>IP RX FIFO would be read by processor.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXDMAEN_1</name>
|
|
<description>IP RX FIFO would be read by DMA.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXWMRK</name>
|
|
<description>Watermark level is (RXWMRK+1)*64 Bits.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPTXFCR</name>
|
|
<description>IP TX FIFO Control Register</description>
|
|
<addressOffset>0xBC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRIPTXF</name>
|
|
<description>Clear all valid data entries in IP TX FIFO.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAEN</name>
|
|
<description>IP TX FIFO filling by DMA enabled.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXDMAEN_0</name>
|
|
<description>IP TX FIFO would be filled by processor.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXDMAEN_1</name>
|
|
<description>IP TX FIFO would be filled by DMA.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXWMRK</name>
|
|
<description>Watermark level is (TXWMRK+1)*64 Bits.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B</dimIndex>
|
|
<name>DLLCR%s</name>
|
|
<description>DLL Control Register 0</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLLEN</name>
|
|
<description>DLL calibration enable.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DLLRESET</name>
|
|
<description>Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SLVDLYTARGET</name>
|
|
<description>The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1, OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRDEN</name>
|
|
<description>Slave clock delay line delay cell number selection override enable.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OVRDVAL</name>
|
|
<description>Slave clock delay line delay cell number selection override value.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STS0</name>
|
|
<description>Status Register 0</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEQIDLE</name>
|
|
<description>This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBIDLE</name>
|
|
<description>This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARBCMDSRC</name>
|
|
<description>This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARBCMDSRC_0</name>
|
|
<description>Triggered by AHB read command (triggered by AHB read).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARBCMDSRC_1</name>
|
|
<description>Triggered by AHB write command (triggered by AHB Write).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARBCMDSRC_2</name>
|
|
<description>Triggered by IP command (triggered by setting register bit IPCMD.TRG).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARBCMDSRC_3</name>
|
|
<description>Triggered by suspended command (resumed).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STS1</name>
|
|
<description>Status Register 1</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AHBCMDERRID</name>
|
|
<description>Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBCMDERRCODE</name>
|
|
<description>Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AHBCMDERRCODE_0</name>
|
|
<description>No error.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHBCMDERRCODE_2</name>
|
|
<description>AHB Write command with JMP_ON_CS instruction used in the sequence.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHBCMDERRCODE_3</name>
|
|
<description>There is unknown instruction opcode in the sequence.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHBCMDERRCODE_4</name>
|
|
<description>Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHBCMDERRCODE_5</name>
|
|
<description>Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHBCMDERRCODE_14</name>
|
|
<description>Sequence execution timeout.</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IPCMDERRID</name>
|
|
<description>Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IPCMDERRCODE</name>
|
|
<description>Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IPCMDERRCODE_0</name>
|
|
<description>No error.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IPCMDERRCODE_2</name>
|
|
<description>IP command with JMP_ON_CS instruction used in the sequence.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IPCMDERRCODE_3</name>
|
|
<description>There is unknown instruction opcode in the sequence.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IPCMDERRCODE_4</name>
|
|
<description>Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IPCMDERRCODE_5</name>
|
|
<description>Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IPCMDERRCODE_6</name>
|
|
<description>Flash access start address exceed the whole flash address range (A1/A2/B1/B2).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IPCMDERRCODE_14</name>
|
|
<description>Sequence execution timeout.</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IPCMDERRCODE_15</name>
|
|
<description>Flash boundary crossed.</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STS2</name>
|
|
<description>Status Register 2</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1000100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASLVLOCK</name>
|
|
<description>Flash A sample clock slave delay line locked.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AREFLOCK</name>
|
|
<description>Flash A sample clock reference delay line locked.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ASLVSEL</name>
|
|
<description>Flash A sample clock slave delay line delay cell number selection .</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AREFSEL</name>
|
|
<description>Flash A sample clock reference delay line delay cell number selection.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BSLVLOCK</name>
|
|
<description>Flash B sample clock slave delay line locked.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BREFLOCK</name>
|
|
<description>Flash B sample clock reference delay line locked.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BSLVSEL</name>
|
|
<description>Flash B sample clock slave delay line delay cell number selection.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BREFSEL</name>
|
|
<description>Flash B sample clock reference delay line delay cell number selection.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBSPNDSTS</name>
|
|
<description>AHB Suspend Status Register</description>
|
|
<addressOffset>0xEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Indicates if an AHB read prefetch command sequence has been suspended.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUFID</name>
|
|
<description>AHB RX BUF ID for suspended command sequence.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DATLFT</name>
|
|
<description>Left Data size for suspended command sequence (in byte).</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPRXFSTS</name>
|
|
<description>IP RX FIFO Status Register</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILL</name>
|
|
<description>Fill level of IP RX FIFO.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RDCNTR</name>
|
|
<description>Total Read Data Counter: RDCNTR * 64 Bits.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPTXFSTS</name>
|
|
<description>IP TX FIFO Status Register</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILL</name>
|
|
<description>Fill level of IP TX FIFO.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WRCNTR</name>
|
|
<description>Total Write Data Counter: WRCNTR * 64 Bits.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>RFDR[%s]</name>
|
|
<description>IP RX FIFO Data Register 0</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>TFDR[%s]</name>
|
|
<description>IP TX FIFO Data Register 0</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TX Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>64</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>LUT[%s]</name>
|
|
<description>LUT 0</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OPERAND0</name>
|
|
<description>OPERAND0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NUM_PADS0</name>
|
|
<description>NUM_PADS0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPCODE0</name>
|
|
<description>OPCODE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPERAND1</name>
|
|
<description>OPERAND1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NUM_PADS1</name>
|
|
<description>NUM_PADS1</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPCODE1</name>
|
|
<description>OPCODE1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OTFAD</name>
|
|
<description>OTFAD</description>
|
|
<alternatePeripheral>FLEXSPI</alternatePeripheral>
|
|
<groupName>OTFAD</groupName>
|
|
<baseAddress>0x400A0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xDE0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0xC00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQE</name>
|
|
<description>IRQE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IRQE_0</name>
|
|
<description>SR[KBERR] = 1 does not generate an interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRQE_1</name>
|
|
<description>SR[KBERR] = 1 generates an interrupt request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Force Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FERR_0</name>
|
|
<description>No effect on the SR[KBERE] indicator.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FERR_1</name>
|
|
<description>SR[KBERR] is immediately set after a write with this data bit set.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSVM</name>
|
|
<description>Force Security Violation Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FSVM_0</name>
|
|
<description>No effect on the operating mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FSVM_1</name>
|
|
<description>Force entry into SVM after a write with this data bit set and the data bit associated with FLDM cleared. SR[MODE] signals the operating mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLDM</name>
|
|
<description>Force Logically Disabled Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLDM_0</name>
|
|
<description>No effect on the operating mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLDM_1</name>
|
|
<description>Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBSE</name>
|
|
<description>Key Blob Scramble Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KBSE_0</name>
|
|
<description>Key blob KEK scrambling is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KBSE_1</name>
|
|
<description>Key blob KEK scrambling is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBPE</name>
|
|
<description>Key Blob Processing Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KBPE_0</name>
|
|
<description>Key blob processing is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KBPE_1</name>
|
|
<description>Key blob processing is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBCE</name>
|
|
<description>Key Blob CRC Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KBCE_0</name>
|
|
<description>CRC-32 during key blob processing is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KBCE_1</name>
|
|
<description>CRC-32 during key blob processing is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRAE</name>
|
|
<description>Restricted Register Access Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RRAE_0</name>
|
|
<description>Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RRAE_1</name>
|
|
<description>Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SKBP</name>
|
|
<description>Start key blob processing</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SKBP_0</name>
|
|
<description>Key blob processing is not initiated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SKBP_1</name>
|
|
<description>Properly-enabled key blob processing is initiated.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>Global OTFAD Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GE_0</name>
|
|
<description>OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GE_1</name>
|
|
<description>OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0xC04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KBERR</name>
|
|
<description>Key Blob Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KBERR_0</name>
|
|
<description>No key blob error detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KBERR_1</name>
|
|
<description>One or more key blob errors has been detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDPCP</name>
|
|
<description>MDPC Present</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Operating Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE_0</name>
|
|
<description>Operating in Normal mode (NRM)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1</name>
|
|
<description>Unused (reserved)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_2</name>
|
|
<description>Operating in Security Violation Mode (SVM)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_3</name>
|
|
<description>Operating in Logically Disabled Mode (LDM)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCTX</name>
|
|
<description>Number of Contexts</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTXER0</name>
|
|
<description>Context Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERROR</name>
|
|
<description>No key blob error was detected for context "n".</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERROR</name>
|
|
<description>Either a key blob integrity error or a key blob CRC error was detected in context "n".</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTXER1</name>
|
|
<description>Context Error</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERROR</name>
|
|
<description>No key blob error was detected for context "n".</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERROR</name>
|
|
<description>Either a key blob integrity error or a key blob CRC error was detected in context "n".</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTXER2</name>
|
|
<description>Context Error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERROR</name>
|
|
<description>No key blob error was detected for context "n".</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERROR</name>
|
|
<description>Either a key blob integrity error or a key blob CRC error was detected in context "n".</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTXER3</name>
|
|
<description>Context Error</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOERROR</name>
|
|
<description>No key blob error was detected for context "n".</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERROR</name>
|
|
<description>Either a key blob integrity error or a key blob CRC error was detected in context "n".</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTXIE0</name>
|
|
<description>Context Integrity Error</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOINTEGRITYERR</name>
|
|
<description>No key blob integrity error was detected for context "n".</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTEGRITYERR</name>
|
|
<description>A key blob integrity error was detected in context "n".</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTXIE1</name>
|
|
<description>Context Integrity Error</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOINTEGRITYERR</name>
|
|
<description>No key blob integrity error was detected for context "n".</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTEGRITYERR</name>
|
|
<description>A key blob integrity error was detected in context "n".</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTXIE2</name>
|
|
<description>Context Integrity Error</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOINTEGRITYERR</name>
|
|
<description>No key blob integrity error was detected for context "n".</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTEGRITYERR</name>
|
|
<description>A key blob integrity error was detected in context "n".</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTXIE3</name>
|
|
<description>Context Integrity Error</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOINTEGRITYERR</name>
|
|
<description>No key blob integrity error was detected for context "n".</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTEGRITYERR</name>
|
|
<description>A key blob integrity error was detected in context "n".</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRL</name>
|
|
<description>Hardware Revision Level</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RRAM</name>
|
|
<description>Restricted Register Access Mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RRAM_0</name>
|
|
<description>Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RRAM_1</name>
|
|
<description>Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GEM</name>
|
|
<description>Global Enable Mode</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GEM_0</name>
|
|
<description>OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GEM_1</name>
|
|
<description>OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBPE</name>
|
|
<description>Key Blob Processing Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KBPE_0</name>
|
|
<description>Key blob processing is not enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KBPE_1</name>
|
|
<description>Key blob processing is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KBD</name>
|
|
<description>Key Blob Processing Done</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KBD_0</name>
|
|
<description>Key blob processing was not enabled, or is not complete.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KBD_1</name>
|
|
<description>Key blob processing was enabled and is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<cluster>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x40</dimIncrement>
|
|
<name>CTX[%s]</name>
|
|
<description>no description available</description>
|
|
<addressOffset>0xD00</addressOffset>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>CTX_KEY%s</name>
|
|
<description>AES Key Word</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>AES Key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CTX_CTR%s</name>
|
|
<description>AES Counter Word</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>AES Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTX_RGD_W0</name>
|
|
<description>AES Region Descriptor Word0</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRTADDR</name>
|
|
<description>Start Address</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>22</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTX_RGD_W1</name>
|
|
<description>AES Region Descriptor Word1</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3F8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VLD</name>
|
|
<description>Valid</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VLD_0</name>
|
|
<description>Context is invalid.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VLD_1</name>
|
|
<description>Context is valid.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADE</name>
|
|
<description>AES Decryption Enable.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADE_0</name>
|
|
<description>Bypass the fetched data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADE_1</name>
|
|
<description>Perform the CTR-AES128 mode decryption on the fetched data.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RO</name>
|
|
<description>Read-Only</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RO_0</name>
|
|
<description>The context registers can be accessed normally (as defined by SR[RRAM]).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RO_1</name>
|
|
<description>The context registers are read-only and accesses may be further restricted based on SR[RRAM].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENDADDR</name>
|
|
<description>End Address</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>22</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</cluster>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IOMUXC_SNVS_GPR</name>
|
|
<description>IOMUXC</description>
|
|
<groupName>IOMUXC_SNVS_GPR</groupName>
|
|
<prependToName>IOMUXC_SNVS_GPR_</prependToName>
|
|
<baseAddress>0x400A4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>GPR0</name>
|
|
<description>GPR0 General Purpose Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR1</name>
|
|
<description>GPR1 General Purpose Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR2</name>
|
|
<description>GPR2 General Purpose Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR3</name>
|
|
<description>GPR3 General Purpose Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPSR_MODE_ENABLE</name>
|
|
<description>Set to enable LPSR mode.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDC_STATUS_CAPT_CLR</name>
|
|
<description>DCDC captured status clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POR_PULL_TYPE</name>
|
|
<description>POR_B pad control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDC_IN_LOW_VOL</name>
|
|
<description>DCDC_IN low voltage detect.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDC_OVER_CUR</name>
|
|
<description>DCDC output over current alert</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDC_OVER_VOL</name>
|
|
<description>DCDC output over voltage alert</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DCDC_STS_DC_OK</name>
|
|
<description>DCDC status OK</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IOMUXC_SNVS</name>
|
|
<description>IOMUXC_SNVS</description>
|
|
<groupName>IOMUXC_SNVS</groupName>
|
|
<prependToName>IOMUXC_SNVS_</prependToName>
|
|
<baseAddress>0x400A8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_PMIC_ON_REQ</name>
|
|
<description>SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad PMIC_ON_REQ</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_TEST_MODE</name>
|
|
<description>SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_POR_B</name>
|
|
<description>SW_PAD_CTL_PAD_POR_B SW PAD Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1B0A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_ONOFF</name>
|
|
<description>SW_PAD_CTL_PAD_ONOFF SW PAD Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1B0A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_PMIC_ON_REQ</name>
|
|
<description>SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xB8A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IOMUXC_GPR</name>
|
|
<description>IOMUXC_GPR</description>
|
|
<groupName>IOMUXC_GPR</groupName>
|
|
<prependToName>IOMUXC_GPR_</prependToName>
|
|
<baseAddress>0x400AC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x78</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>GPR0</name>
|
|
<description>GPR0 General Purpose Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR1</name>
|
|
<description>GPR1 General Purpose Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SAI1_MCLK1_SEL</name>
|
|
<description>SAI1 MCLK1 source select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK1_SEL_0</name>
|
|
<description>ccm.ssi1_clk_root</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK1_SEL_2</name>
|
|
<description>ccm.ssi3_clk_root</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK1_SEL_3</name>
|
|
<description>iomux.sai1_ipg_clk_sai_mclk</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK1_SEL_5</name>
|
|
<description>iomux.sai3_ipg_clk_sai_mclk</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI1_MCLK2_SEL</name>
|
|
<description>SAI1 MCLK2 source select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK2_SEL_0</name>
|
|
<description>ccm.ssi1_clk_root</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK2_SEL_2</name>
|
|
<description>ccm.ssi3_clk_root</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK2_SEL_3</name>
|
|
<description>iomux.sai1_ipg_clk_sai_mclk</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK2_SEL_5</name>
|
|
<description>iomux.sai3_ipg_clk_sai_mclk</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI1_MCLK3_SEL</name>
|
|
<description>SAI1 MCLK3 source select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK3_SEL_0</name>
|
|
<description>ccm.spdif0_clk_root</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK3_SEL_1</name>
|
|
<description>SPDIF_EXT_CLK</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK3_SEL_2</name>
|
|
<description>spdif.spdif_srclk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK3_SEL_3</name>
|
|
<description>spdif.spdif_outclock</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI3_MCLK3_SEL</name>
|
|
<description>SAI3 MCLK3 source select</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI3_MCLK3_SEL_0</name>
|
|
<description>ccm.spdif0_clk_root</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_MCLK3_SEL_1</name>
|
|
<description>SPDIF_EXT_CLK</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_MCLK3_SEL_2</name>
|
|
<description>spdif.spdif_srclk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_MCLK3_SEL_3</name>
|
|
<description>spdif.spdif_outclock</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GINT</name>
|
|
<description>Global Interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GINT_0</name>
|
|
<description>Global interrupt request is not asserted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GINT_1</name>
|
|
<description>Global interrupt request is asserted.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI1_MCLK_DIR</name>
|
|
<description>sai1.MCLK signal direction control</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK_DIR_0</name>
|
|
<description>sai1.MCLK is input signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_MCLK_DIR_1</name>
|
|
<description>sai1.MCLK is output signal</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI3_MCLK_DIR</name>
|
|
<description>sai3.MCLK signal direction control</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI3_MCLK_DIR_0</name>
|
|
<description>sai3.MCLK is input signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_MCLK_DIR_1</name>
|
|
<description>sai3.MCLK is output signal</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXC_MON</name>
|
|
<description>Exclusive monitor response select of illegal command</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EXC_MON_0</name>
|
|
<description>OKAY response</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXC_MON_1</name>
|
|
<description>SLVError response</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CM7_FORCE_HCLK_EN</name>
|
|
<description>ARM CM7 platform AHB clock enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CM7_FORCE_HCLK_EN_0</name>
|
|
<description>AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_FORCE_HCLK_EN_1</name>
|
|
<description>AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR2</name>
|
|
<description>GPR2 General Purpose Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AXBS_P_M0_HIGH_PRIORITY</name>
|
|
<description>AXBS_P M0 master has higher priority.Do not set both M1 and M0 to high priority.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AXBS_P_M0_HIGH_PRIORITY_0</name>
|
|
<description>AXBS_P M0 master doesn't have high priority</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AXBS_P_M0_HIGH_PRIORITY_1</name>
|
|
<description>AXBS_P M0 master has high priority</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AXBS_P_M1_HIGH_PRIORITY</name>
|
|
<description>AXBS_P M1 master has higher priority.Do not set both M1 and M0 to high priority.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AXBS_P_M1_HIGH_PRIORITY_0</name>
|
|
<description>AXBS_P M1 master does not have high priority</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AXBS_P_M1_HIGH_PRIORITY_1</name>
|
|
<description>AXBS_P M1 master has high priority</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AXBS_P_FORCE_ROUND_ROBIN</name>
|
|
<description>Force Round Robin in AXBS_P. This bit can override master M0 M1 high priority configuration.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AXBS_P_FORCE_ROUND_ROBIN_0</name>
|
|
<description>AXBS_P masters are not arbitored in round robin, depending on M0/M1 master priority settings.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AXBS_P_FORCE_ROUND_ROBIN_1</name>
|
|
<description>AXBS_P masters are arbitored in round robin</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L2_MEM_EN_POWERSAVING</name>
|
|
<description>Enable power saving features on L2 memory</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L2_MEM_EN_POWERSAVING_0</name>
|
|
<description>Enters power saving mode only when chip is in SUSPEND mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L2_MEM_EN_POWERSAVING_1</name>
|
|
<description>Controlled by L2_MEM_DEEPSLEEP bitfield</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAM_AUTO_CLK_GATING_EN</name>
|
|
<description>Automatically gate off RAM clock when RAM is not accessed.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RAM_AUTO_CLK_GATING_EN_0</name>
|
|
<description>disable automatically gate off RAM clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAM_AUTO_CLK_GATING_EN_1</name>
|
|
<description>enable automatically gate off RAM clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L2_MEM_DEEPSLEEP</name>
|
|
<description>This bit controls how memory (OCRAM) enters Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L2_MEM_DEEPSLEEP_0</name>
|
|
<description>No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L2_MEM_DEEPSLEEP_1</name>
|
|
<description>Force memory into deep sleep mode (OCRAM in power saving mode)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MQS_CLK_DIV</name>
|
|
<description>Divider ratio control for mclk from hmclk</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MQS_CLK_DIV_0</name>
|
|
<description>mclk frequency = hmclk frequency</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MQS_CLK_DIV_1</name>
|
|
<description>mclk frequency = 1/2 * hmclk frequency</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MQS_CLK_DIV_2</name>
|
|
<description>mclk frequency = 1/3 * hmclk frequency</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MQS_CLK_DIV_255</name>
|
|
<description>mclk frequency = 1/256 * hmclk frequency</description>
|
|
<value>0xFF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MQS_SW_RST</name>
|
|
<description>MQS software reset</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MQS_SW_RST_0</name>
|
|
<description>Exit software reset for MQS</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MQS_SW_RST_1</name>
|
|
<description>Enable software reset for MQS</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MQS_EN</name>
|
|
<description>MQS enable.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MQS_EN_0</name>
|
|
<description>Disable MQS</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MQS_EN_1</name>
|
|
<description>Enable MQS</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MQS_OVERSAMPLE</name>
|
|
<description>Medium Quality Sound (MQS) Oversample</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MQS_OVERSAMPLE_0</name>
|
|
<description>32</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MQS_OVERSAMPLE_1</name>
|
|
<description>64</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR3</name>
|
|
<description>GPR3 General Purpose Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCP_KEY_SEL</name>
|
|
<description>Select 128-bit DCP key from 256-bit key from SNVS Master Key</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DCP_KEY_SEL_0</name>
|
|
<description>Select [127:0] from SNVS Master Key as DCP key</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCP_KEY_SEL_1</name>
|
|
<description>Select [255:128] from SNVS Master Key as DCP key</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR4</name>
|
|
<description>GPR4 General Purpose Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDMA_STOP_REQ</name>
|
|
<description>EDMA stop request.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDMA_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDMA_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_STOP_REQ</name>
|
|
<description>TRNG stop request.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRNG_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRNG_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI1_STOP_REQ</name>
|
|
<description>SAI1 stop request.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI1_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI3_STOP_REQ</name>
|
|
<description>SAI3 stop request.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI3_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIT_STOP_REQ</name>
|
|
<description>PIT stop request.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PIT_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIT_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXSPI_STOP_REQ</name>
|
|
<description>FlexSPI stop request.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXIO1_STOP_REQ</name>
|
|
<description>FlexIO1 stop request.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDMA_STOP_ACK</name>
|
|
<description>EDMA stop acknowledge. This is a status (read-only) bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDMA_STOP_ACK_0</name>
|
|
<description>EDMA stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDMA_STOP_ACK_1</name>
|
|
<description>EDMA stop acknowledge is asserted (EDMA is in STOP mode).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRNG_STOP_ACK</name>
|
|
<description>TRNG stop acknowledge</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRNG_STOP_ACK_0</name>
|
|
<description>TRNG stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRNG_STOP_ACK_1</name>
|
|
<description>TRNG stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI1_STOP_ACK</name>
|
|
<description>SAI1 stop acknowledge</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI1_STOP_ACK_0</name>
|
|
<description>SAI1 stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_STOP_ACK_1</name>
|
|
<description>SAI1 stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI3_STOP_ACK</name>
|
|
<description>SAI3 stop acknowledge</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI3_STOP_ACK_0</name>
|
|
<description>SAI3 stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_STOP_ACK_1</name>
|
|
<description>SAI3 stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIT_STOP_ACK</name>
|
|
<description>PIT stop acknowledge</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PIT_STOP_ACK_0</name>
|
|
<description>PIT stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIT_STOP_ACK_1</name>
|
|
<description>PIT stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXSPI_STOP_ACK</name>
|
|
<description>FLEXSPI stop acknowledge</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_STOP_ACK_0</name>
|
|
<description>FLEXSPI stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_STOP_ACK_1</name>
|
|
<description>FLEXSPI stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXIO1_STOP_ACK</name>
|
|
<description>FLEXIO1 stop acknowledge</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_STOP_ACK_0</name>
|
|
<description>FLEXIO1 stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_STOP_ACK_1</name>
|
|
<description>FLEXIO1 stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR5</name>
|
|
<description>GPR5 General Purpose Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDOG1_MASK</name>
|
|
<description>WDOG1 Timeout Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDOG1_MASK_0</name>
|
|
<description>WDOG1 Timeout behaves normally</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDOG1_MASK_1</name>
|
|
<description>WDOG1 Timeout is masked</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDOG2_MASK</name>
|
|
<description>WDOG2 Timeout Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDOG2_MASK_0</name>
|
|
<description>WDOG2 Timeout behaves normally</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDOG2_MASK_1</name>
|
|
<description>WDOG2 Timeout is masked</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREF_1M_CLK_GPT1</name>
|
|
<description>GPT1 1 MHz clock source select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VREF_1M_CLK_GPT1_0</name>
|
|
<description>GPT1 ipg_clk_highfreq driven by IPG_PERCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VREF_1M_CLK_GPT1_1</name>
|
|
<description>GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VREF_1M_CLK_GPT2</name>
|
|
<description>GPT2 1 MHz clock source select</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VREF_1M_CLK_GPT2_0</name>
|
|
<description>GPT2 ipg_clk_highfreq driven by IPG_PERCLK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VREF_1M_CLK_GPT2_1</name>
|
|
<description>GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR6</name>
|
|
<description>GPR6 General Purpose Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IOMUXC_XBAR_DIR_SEL_2</name>
|
|
<description>IOMUXC XBAR_INOUT2 function direction select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IOMUXC_XBAR_DIR_SEL_2_0</name>
|
|
<description>XBAR_INOUT as input</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMUXC_XBAR_DIR_SEL_2_1</name>
|
|
<description>XBAR_INOUT as output</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IOMUXC_XBAR_DIR_SEL_3</name>
|
|
<description>IOMUXC XBAR_INOUT3 function direction select</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IOMUXC_XBAR_DIR_SEL_3_0</name>
|
|
<description>XBAR_INOUT as input</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IOMUXC_XBAR_DIR_SEL_3_1</name>
|
|
<description>XBAR_INOUT as output</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR7</name>
|
|
<description>GPR7 General Purpose Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPI2C1_STOP_REQ</name>
|
|
<description>LPI2C1 stop request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPI2C1_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPI2C1_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPI2C2_STOP_REQ</name>
|
|
<description>LPI2C2 stop request</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPI2C2_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPI2C2_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSPI1_STOP_REQ</name>
|
|
<description>LPSPI1 stop request</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSPI1_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI1_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSPI2_STOP_REQ</name>
|
|
<description>LPSPI2 stop request</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSPI2_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI2_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART1_STOP_REQ</name>
|
|
<description>LPUART1 stop request</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART1_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART1_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART2_STOP_REQ</name>
|
|
<description>LPUART1 stop request</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART2_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART2_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART3_STOP_REQ</name>
|
|
<description>LPUART3 stop request</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART3_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART3_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART4_STOP_REQ</name>
|
|
<description>LPUART4 stop request</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART4_STOP_REQ_0</name>
|
|
<description>stop request off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART4_STOP_REQ_1</name>
|
|
<description>stop request on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPI2C1_STOP_ACK</name>
|
|
<description>LPI2C1 stop acknowledge</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPI2C1_STOP_ACK_0</name>
|
|
<description>stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPI2C1_STOP_ACK_1</name>
|
|
<description>stop acknowledge is asserted (the module is in Stop mode)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPI2C2_STOP_ACK</name>
|
|
<description>LPI2C2 stop acknowledge</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPI2C2_STOP_ACK_0</name>
|
|
<description>stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPI2C2_STOP_ACK_1</name>
|
|
<description>stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSPI1_STOP_ACK</name>
|
|
<description>LPSPI1 stop acknowledge</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSPI1_STOP_ACK_0</name>
|
|
<description>stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI1_STOP_ACK_1</name>
|
|
<description>stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSPI2_STOP_ACK</name>
|
|
<description>LPSPI2 stop acknowledge</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSPI2_STOP_ACK_0</name>
|
|
<description>stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI2_STOP_ACK_1</name>
|
|
<description>stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART1_STOP_ACK</name>
|
|
<description>LPUART1 stop acknowledge</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART1_STOP_ACK_0</name>
|
|
<description>stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART1_STOP_ACK_1</name>
|
|
<description>stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART2_STOP_ACK</name>
|
|
<description>LPUART1 stop acknowledge</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART2_STOP_ACK_0</name>
|
|
<description>stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART2_STOP_ACK_1</name>
|
|
<description>stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART3_STOP_ACK</name>
|
|
<description>LPUART3 stop acknowledge</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART3_STOP_ACK_0</name>
|
|
<description>stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART3_STOP_ACK_1</name>
|
|
<description>stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART4_STOP_ACK</name>
|
|
<description>LPUART4 stop acknowledge</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART4_STOP_ACK_0</name>
|
|
<description>stop acknowledge is not asserted</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART4_STOP_ACK_1</name>
|
|
<description>stop acknowledge is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR8</name>
|
|
<description>GPR8 General Purpose Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPI2C1_IPG_STOP_MODE</name>
|
|
<description>LPI2C1 stop mode selection, cannot change when ipg_stop is asserted.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPI2C1_IPG_STOP_MODE_0</name>
|
|
<description>the module is functional in Stop mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPI2C1_IPG_STOP_MODE_1</name>
|
|
<description>the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPI2C1_IPG_DOZE</name>
|
|
<description>LPI2C1 ipg_doze mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPI2C1_IPG_DOZE_0</name>
|
|
<description>not in doze mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPI2C1_IPG_DOZE_1</name>
|
|
<description>in doze mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPI2C2_IPG_STOP_MODE</name>
|
|
<description>LPI2C2 stop mode selection, cannot change when ipg_stop is asserted.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPI2C2_IPG_STOP_MODE_0</name>
|
|
<description>the module is functional in Stop mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPI2C2_IPG_STOP_MODE_1</name>
|
|
<description>the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPI2C2_IPG_DOZE</name>
|
|
<description>LPI2C2 ipg_doze mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPI2C2_IPG_DOZE_0</name>
|
|
<description>not in doze mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPI2C2_IPG_DOZE_1</name>
|
|
<description>in doze mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSPI1_IPG_STOP_MODE</name>
|
|
<description>LPSPI1 stop mode selection, cannot change when ipg_stop is asserted.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSPI1_IPG_STOP_MODE_0</name>
|
|
<description>the module is functional in Stop mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI1_IPG_STOP_MODE_1</name>
|
|
<description>the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSPI1_IPG_DOZE</name>
|
|
<description>LPSPI1 ipg_doze mode</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSPI1_IPG_DOZE_0</name>
|
|
<description>not in doze mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI1_IPG_DOZE_1</name>
|
|
<description>in doze mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSPI2_IPG_STOP_MODE</name>
|
|
<description>LPSPI2 stop mode selection, cannot change when ipg_stop is asserted.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSPI2_IPG_STOP_MODE_0</name>
|
|
<description>the module is functional in Stop mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI2_IPG_STOP_MODE_1</name>
|
|
<description>the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSPI2_IPG_DOZE</name>
|
|
<description>LPSPI2 ipg_doze mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSPI2_IPG_DOZE_0</name>
|
|
<description>not in doze mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI2_IPG_DOZE_1</name>
|
|
<description>in doze mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART1_IPG_STOP_MODE</name>
|
|
<description>LPUART1 stop mode selection, cannot change when ipg_stop is asserted.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART1_IPG_STOP_MODE_0</name>
|
|
<description>the module is functional in Stop mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART1_IPG_STOP_MODE_1</name>
|
|
<description>the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART1_IPG_DOZE</name>
|
|
<description>LPUART1 ipg_doze mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART1_IPG_DOZE_0</name>
|
|
<description>not in doze mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART1_IPG_DOZE_1</name>
|
|
<description>in doze mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART2_IPG_STOP_MODE</name>
|
|
<description>LPUART2 stop mode selection, cannot change when ipg_stop is asserted.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART2_IPG_STOP_MODE_0</name>
|
|
<description>the module is functional in Stop mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART2_IPG_STOP_MODE_1</name>
|
|
<description>the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART2_IPG_DOZE</name>
|
|
<description>LPUART2 ipg_doze mode</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART2_IPG_DOZE_0</name>
|
|
<description>not in doze mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART2_IPG_DOZE_1</name>
|
|
<description>in doze mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART3_IPG_STOP_MODE</name>
|
|
<description>LPUART3 stop mode selection, cannot change when ipg_stop is asserted.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART3_IPG_STOP_MODE_0</name>
|
|
<description>the module is functional in Stop mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART3_IPG_STOP_MODE_1</name>
|
|
<description>the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART3_IPG_DOZE</name>
|
|
<description>LPUART3 ipg_doze mode</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART3_IPG_DOZE_0</name>
|
|
<description>not in doze mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART3_IPG_DOZE_1</name>
|
|
<description>in doze mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART4_IPG_STOP_MODE</name>
|
|
<description>LPUART4 stop mode selection, cannot change when ipg_stop is asserted.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART4_IPG_STOP_MODE_0</name>
|
|
<description>the module is functional in Stop mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART4_IPG_STOP_MODE_1</name>
|
|
<description>the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPUART4_IPG_DOZE</name>
|
|
<description>LPUART4 ipg_doze mode</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPUART4_IPG_DOZE_0</name>
|
|
<description>not in doze mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPUART4_IPG_DOZE_1</name>
|
|
<description>in doze mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR9</name>
|
|
<description>GPR9 General Purpose Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR10</name>
|
|
<description>GPR10 General Purpose Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NIDEN</name>
|
|
<description>ARM non-secure (non-invasive) debug enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NIDEN_0</name>
|
|
<description>Debug turned off.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NIDEN_1</name>
|
|
<description>Debug enabled (default).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBG_EN</name>
|
|
<description>ARM invasive debug enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBG_EN_0</name>
|
|
<description>Debug turned off.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBG_EN_1</name>
|
|
<description>Debug enabled (default).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEC_ERR_RESP</name>
|
|
<description>Security error response enable for all security gaskets (on both AHB and AXI buses)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SEC_ERR_RESP_0</name>
|
|
<description>OKEY response</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEC_ERR_RESP_1</name>
|
|
<description>SLVError (default)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCPKEY_OCOTP_OR_KEYMUX</name>
|
|
<description>DCP Key selection bit.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DCPKEY_OCOTP_OR_KEYMUX_0</name>
|
|
<description>Select key from SNVS Master Key.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DCPKEY_OCOTP_OR_KEYMUX_1</name>
|
|
<description>Select key from OCOTP (SW_GP2).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCRAM_TZ_EN</name>
|
|
<description>OCRAM TrustZone (TZ) enable.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OCRAM_TZ_EN_0</name>
|
|
<description>The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OCRAM_TZ_EN_1</name>
|
|
<description>The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCRAM_TZ_ADDR</name>
|
|
<description>OCRAM TrustZone (TZ) start address</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_NIDEN</name>
|
|
<description>Lock NIDEN field for changes</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_NIDEN_0</name>
|
|
<description>Field is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_NIDEN_1</name>
|
|
<description>Field is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_DBG_EN</name>
|
|
<description>Lock DBG_EN field for changes</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_DBG_EN_0</name>
|
|
<description>Field is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_DBG_EN_1</name>
|
|
<description>Field is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_SEC_ERR_RESP</name>
|
|
<description>Lock SEC_ERR_RESP field for changes</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_SEC_ERR_RESP_0</name>
|
|
<description>Field is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_SEC_ERR_RESP_1</name>
|
|
<description>Field is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_DCPKEY_OCOTP_OR_KEYMUX</name>
|
|
<description>Lock DCP Key OCOTP/Key MUX selection bit</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_DCPKEY_OCOTP_OR_KEYMUX_0</name>
|
|
<description>Field is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_DCPKEY_OCOTP_OR_KEYMUX_1</name>
|
|
<description>Field is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_OCRAM_TZ_EN</name>
|
|
<description>Lock OCRAM_TZ_EN field for changes</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_OCRAM_TZ_EN_0</name>
|
|
<description>Field is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_OCRAM_TZ_EN_1</name>
|
|
<description>Field is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_OCRAM_TZ_ADDR</name>
|
|
<description>Lock OCRAM_TZ_ADDR field for changes</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_OCRAM_TZ_ADDR_0</name>
|
|
<description>Field is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_OCRAM_TZ_ADDR_1</name>
|
|
<description>Field is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR11</name>
|
|
<description>GPR11 General Purpose Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M7_APC_AC_R0_CTRL</name>
|
|
<description>Access control of memory region-0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M7_APC_AC_R0_CTRL_0</name>
|
|
<description>No access protection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M7_APC_AC_R0_CTRL_1</name>
|
|
<description>M7 debug protection enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7_APC_AC_R1_CTRL</name>
|
|
<description>Access control of memory region-1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M7_APC_AC_R1_CTRL_0</name>
|
|
<description>No access protection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M7_APC_AC_R1_CTRL_1</name>
|
|
<description>M7 debug protection enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7_APC_AC_R2_CTRL</name>
|
|
<description>Access control of memory region-2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M7_APC_AC_R2_CTRL_0</name>
|
|
<description>No access protection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M7_APC_AC_R2_CTRL_1</name>
|
|
<description>M7 debug protection enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7_APC_AC_R3_CTRL</name>
|
|
<description>Access control of memory region-3</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M7_APC_AC_R3_CTRL_0</name>
|
|
<description>No access protection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M7_APC_AC_R3_CTRL_1</name>
|
|
<description>M7 debug protection enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_M7_APC_AC_R0_CTRL</name>
|
|
<description>Lock M7_APC_AC_R0_CTRL field for changes</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_M7_APC_AC_R1_CTRL</name>
|
|
<description>Lock M7_APC_AC_R1_CTRL field for changes</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_M7_APC_AC_R2_CTRL</name>
|
|
<description>Lock M7_APC_AC_R2_CTRL field for changes</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_M7_APC_AC_R3_CTRL</name>
|
|
<description>Lock M7_APC_AC_R3_CTRL field for changes</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR12</name>
|
|
<description>GPR12 General Purpose Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLEXIO1_IPG_STOP_MODE</name>
|
|
<description>FlexIO1 stop mode selection. Cannot change when ipg_stop is asserted.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_IPG_STOP_MODE_0</name>
|
|
<description>FlexIO1 is functional in Stop mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_IPG_STOP_MODE_1</name>
|
|
<description>When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXIO1_IPG_DOZE</name>
|
|
<description>FLEXIO1 ipg_doze mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_IPG_DOZE_0</name>
|
|
<description>FLEXIO1 is not in doze mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_IPG_DOZE_1</name>
|
|
<description>FLEXIO1 is in doze mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR13</name>
|
|
<description>GPR13 General Purpose Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CACHE_USB</name>
|
|
<description>USB block cacheable attribute value of AXI transactions</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CACHE_USB_0</name>
|
|
<description>Cacheable attribute is off for read/write transactions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CACHE_USB_1</name>
|
|
<description>Cacheable attribute is on for read/write transactions.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR14</name>
|
|
<description>GPR14 General Purpose Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x880000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CM7_CFGITCMSZ</name>
|
|
<description>ITCM total size configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGITCMSZ_0</name>
|
|
<description>0 KB (No ITCM)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGITCMSZ_3</name>
|
|
<description>4 KB</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGITCMSZ_4</name>
|
|
<description>8 KB</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGITCMSZ_5</name>
|
|
<description>16 KB</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGITCMSZ_6</name>
|
|
<description>32 KB</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGITCMSZ_7</name>
|
|
<description>64 KB</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGITCMSZ_8</name>
|
|
<description>128 KB</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CM7_CFGDTCMSZ</name>
|
|
<description>DTCM total size configuration</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGDTCMSZ_0</name>
|
|
<description>0 KB (No DTCM)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGDTCMSZ_3</name>
|
|
<description>4 KB</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGDTCMSZ_4</name>
|
|
<description>8 KB</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGDTCMSZ_5</name>
|
|
<description>16 KB</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGDTCMSZ_6</name>
|
|
<description>32 KB</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGDTCMSZ_7</name>
|
|
<description>64 KB</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM7_CFGDTCMSZ_8</name>
|
|
<description>128 KB</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR15</name>
|
|
<description>GPR15 General Purpose Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR16</name>
|
|
<description>GPR16 General Purpose Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x200003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT_ITCM_EN</name>
|
|
<description>ITCM enable initialization out of reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INIT_ITCM_EN_0</name>
|
|
<description>ITCM is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_ITCM_EN_1</name>
|
|
<description>ITCM is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT_DTCM_EN</name>
|
|
<description>DTCM enable initialization out of reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INIT_DTCM_EN_0</name>
|
|
<description>DTCM is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_DTCM_EN_1</name>
|
|
<description>DTCM is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXRAM_BANK_CFG_SEL</name>
|
|
<description>FlexRAM bank config source select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXRAM_BANK_CFG_SEL_0</name>
|
|
<description>use fuse value to config</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXRAM_BANK_CFG_SEL_1</name>
|
|
<description>use FLEXRAM_BANK_CFG to config</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_VTOR</name>
|
|
<description>Lock CM7_INIT_VTOR field for changes</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_VTOR_0</name>
|
|
<description>CM7_INIT_VTOR field is not locked.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_VTOR_1</name>
|
|
<description>CM7_INIT_VTOR field is locked (read access only).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CM7_INIT_VTOR</name>
|
|
<description>Vector table offset register out of reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>25</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR17</name>
|
|
<description>GPR17 General Purpose Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLEXRAM_BANK_CFG</name>
|
|
<description>FlexRAM bank config value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR18</name>
|
|
<description>GPR18 General Purpose Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK_M7_APC_AC_R0_BOT</name>
|
|
<description>lock M7_APC_AC_R0_BOT field for changes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R0_BOT_0</name>
|
|
<description>Register field [31:1] is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R0_BOT_1</name>
|
|
<description>Register field [31:1] is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7_APC_AC_R0_BOT</name>
|
|
<description>APC end address of memory region-0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR19</name>
|
|
<description>GPR19 General Purpose Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK_M7_APC_AC_R0_TOP</name>
|
|
<description>lock M7_APC_AC_R0_TOP field for changes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R0_TOP_0</name>
|
|
<description>Register field [31:1] is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R0_TOP_1</name>
|
|
<description>Register field [31:1] is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7_APC_AC_R0_TOP</name>
|
|
<description>APC start address of memory region-0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR20</name>
|
|
<description>GPR20 General Purpose Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK_M7_APC_AC_R1_BOT</name>
|
|
<description>lock M7_APC_AC_R1_BOT field for changes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R1_BOT_0</name>
|
|
<description>Register field [31:1] is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R1_BOT_1</name>
|
|
<description>Register field [31:1] is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7_APC_AC_R1_BOT</name>
|
|
<description>APC end address of memory region-1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR21</name>
|
|
<description>GPR21 General Purpose Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK_M7_APC_AC_R1_TOP</name>
|
|
<description>lock M7_APC_AC_R1_TOP field for changes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R1_TOP_0</name>
|
|
<description>Register field [31:1] is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R1_TOP_1</name>
|
|
<description>Register field [31:1] is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7_APC_AC_R1_TOP</name>
|
|
<description>APC start address of memory region-1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR22</name>
|
|
<description>GPR22 General Purpose Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK_M7_APC_AC_R2_BOT</name>
|
|
<description>lock M7_APC_AC_R2_BOT field for changes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R2_BOT_0</name>
|
|
<description>Register field [31:1] is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R2_BOT_1</name>
|
|
<description>Register field [31:1] is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7_APC_AC_R2_BOT</name>
|
|
<description>APC end address of memory region-2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR23</name>
|
|
<description>GPR23 General Purpose Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK_M7_APC_AC_R2_TOP</name>
|
|
<description>lock M7_APC_AC_R2_TOP field for changes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R2_TOP_0</name>
|
|
<description>Register field [31:1] is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R2_TOP_1</name>
|
|
<description>Register field [31:1] is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7_APC_AC_R2_TOP</name>
|
|
<description>APC start address of memory region-2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR24</name>
|
|
<description>GPR24 General Purpose Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK_M7_APC_AC_R3_BOT</name>
|
|
<description>lock M7_APC_AC_R3_BOT field for changes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R3_BOT_0</name>
|
|
<description>Register field [31:1] is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R3_BOT_1</name>
|
|
<description>Register field [31:1] is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7_APC_AC_R3_BOT</name>
|
|
<description>APC end address of memory region-3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR25</name>
|
|
<description>GPR25 General Purpose Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK_M7_APC_AC_R3_TOP</name>
|
|
<description>lock M7_APC_AC_R3_TOP field for changes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R3_TOP_0</name>
|
|
<description>Register field [31:1] is not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_M7_APC_AC_R3_TOP_1</name>
|
|
<description>Register field [31:1] is locked (read access only)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7_APC_AC_R3_TOP</name>
|
|
<description>APC start address of memory region-3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR26</name>
|
|
<description>GPR26 General Purpose Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_SEL</name>
|
|
<description>Select GPIO1 or GPIO2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR27</name>
|
|
<description>GPR27 General Purpose Register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLEXSPI_REMAP_ADDR_START</name>
|
|
<description>Start address of flexspi1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR28</name>
|
|
<description>GPR28 General Purpose Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLEXSPI_REMAP_ADDR_END</name>
|
|
<description>End address of flexspi1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR29</name>
|
|
<description>GPR29 General Purpose Register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLEXSPI_REMAP_ADDR_OFFSET</name>
|
|
<description>Offset address of flexspi1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLEXRAM</name>
|
|
<description>FLEXRAM</description>
|
|
<groupName>FLEXRAM</groupName>
|
|
<baseAddress>0x400B0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FLEXRAM</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TCM_CTRL</name>
|
|
<description>TCM CRTL Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCM_WWAIT_EN</name>
|
|
<description>TCM Write Wait Mode Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TCM_WWAIT_EN_0</name>
|
|
<description>TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCM_WWAIT_EN_1</name>
|
|
<description>TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCM_RWAIT_EN</name>
|
|
<description>TCM Read Wait Mode Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TCM_RWAIT_EN_0</name>
|
|
<description>TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCM_RWAIT_EN_1</name>
|
|
<description>TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_CLK_ON</name>
|
|
<description>Force RAM Clock Always On</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OCRAM_MAGIC_ADDR</name>
|
|
<description>OCRAM Magic Address Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OCRAM_WR_RD_SEL</name>
|
|
<description>OCRAM Write Read Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OCRAM_WR_RD_SEL_0</name>
|
|
<description>When OCRAM read access hits magic address, it will generate interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OCRAM_WR_RD_SEL_1</name>
|
|
<description>When OCRAM write access hits magic address, it will generate interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCRAM_MAGIC_ADDR</name>
|
|
<description>OCRAM Magic Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTCM_MAGIC_ADDR</name>
|
|
<description>DTCM Magic Address Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTCM_WR_RD_SEL</name>
|
|
<description>DTCM Write Read Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DTCM_WR_RD_SEL_0</name>
|
|
<description>When DTCM read access hits magic address, it will generate interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTCM_WR_RD_SEL_1</name>
|
|
<description>When DTCM write access hits magic address, it will generate interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCM_MAGIC_ADDR</name>
|
|
<description>DTCM Magic Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ITCM_MAGIC_ADDR</name>
|
|
<description>ITCM Magic Address Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ITCM_WR_RD_SEL</name>
|
|
<description>ITCM Write Read Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ITCM_WR_RD_SEL_0</name>
|
|
<description>When ITCM read access hits magic address, it will generate interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITCM_WR_RD_SEL_1</name>
|
|
<description>When ITCM write access hits magic address, it will generate interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITCM_MAGIC_ADDR</name>
|
|
<description>ITCM Magic Address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_STATUS</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ITCM_MAM_STATUS</name>
|
|
<description>ITCM Magic Address Match Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ITCM_MAM_STATUS_0</name>
|
|
<description>ITCM did not access magic address.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITCM_MAM_STATUS_1</name>
|
|
<description>ITCM accessed magic address.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCM_MAM_STATUS</name>
|
|
<description>DTCM Magic Address Match Status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DTCM_MAM_STATUS_0</name>
|
|
<description>DTCM did not access magic address.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTCM_MAM_STATUS_1</name>
|
|
<description>DTCM accessed magic address.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCRAM_MAM_STATUS</name>
|
|
<description>OCRAM Magic Address Match Status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OCRAM_MAM_STATUS_0</name>
|
|
<description>OCRAM did not access magic address.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OCRAM_MAM_STATUS_1</name>
|
|
<description>OCRAM accessed magic address.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITCM_ERR_STATUS</name>
|
|
<description>ITCM Access Error Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ITCM_ERR_STATUS_0</name>
|
|
<description>ITCM access error does not happen</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITCM_ERR_STATUS_1</name>
|
|
<description>ITCM access error happens.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCM_ERR_STATUS</name>
|
|
<description>DTCM Access Error Status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DTCM_ERR_STATUS_0</name>
|
|
<description>DTCM access error does not happen</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTCM_ERR_STATUS_1</name>
|
|
<description>DTCM access error happens.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCRAM_ERR_STATUS</name>
|
|
<description>OCRAM Access Error Status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OCRAM_ERR_STATUS_0</name>
|
|
<description>OCRAM access error does not happen</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OCRAM_ERR_STATUS_1</name>
|
|
<description>OCRAM access error happens.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_STAT_EN</name>
|
|
<description>Interrupt Status Enable Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ITCM_MAM_STAT_EN</name>
|
|
<description>ITCM Magic Address Match Status Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ITCM_MAM_STAT_EN_0</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITCM_MAM_STAT_EN_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCM_MAM_STAT_EN</name>
|
|
<description>DTCM Magic Address Match Status Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DTCM_MAM_STAT_EN_0</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTCM_MAM_STAT_EN_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCRAM_MAM_STAT_EN</name>
|
|
<description>OCRAM Magic Address Match Status Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OCRAM_MAM_STAT_EN_0</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OCRAM_MAM_STAT_EN_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITCM_ERR_STAT_EN</name>
|
|
<description>ITCM Access Error Status Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ITCM_ERR_STAT_EN_0</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITCM_ERR_STAT_EN_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCM_ERR_STAT_EN</name>
|
|
<description>DTCM Access Error Status Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DTCM_ERR_STAT_EN_0</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTCM_ERR_STAT_EN_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCRAM_ERR_STAT_EN</name>
|
|
<description>OCRAM Access Error Status Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OCRAM_ERR_STAT_EN_0</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OCRAM_ERR_STAT_EN_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_SIG_EN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ITCM_MAM_SIG_EN</name>
|
|
<description>ITCM Magic Address Match Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ITCM_MAM_SIG_EN_0</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITCM_MAM_SIG_EN_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCM_MAM_SIG_EN</name>
|
|
<description>DTCM Magic Address Match Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DTCM_MAM_SIG_EN_0</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTCM_MAM_SIG_EN_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCRAM_MAM_SIG_EN</name>
|
|
<description>OCRAM Magic Address Match Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OCRAM_MAM_SIG_EN_0</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OCRAM_MAM_SIG_EN_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITCM_ERR_SIG_EN</name>
|
|
<description>ITCM Access Error Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ITCM_ERR_SIG_EN_0</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITCM_ERR_SIG_EN_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTCM_ERR_SIG_EN</name>
|
|
<description>DTCM Access Error Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DTCM_ERR_SIG_EN_0</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTCM_ERR_SIG_EN_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCRAM_ERR_SIG_EN</name>
|
|
<description>OCRAM Access Error Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OCRAM_ERR_SIG_EN_0</name>
|
|
<description>Masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OCRAM_ERR_SIG_EN_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EWM</name>
|
|
<description>EWM</description>
|
|
<groupName>EWM</groupName>
|
|
<baseAddress>0x400B4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EWM</name>
|
|
<value>44</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWMEN</name>
|
|
<description>EWM enable.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-writeOnce</access>
|
|
</field>
|
|
<field>
|
|
<name>ASSIN</name>
|
|
<description>EWM_in's Assertion State Select.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-writeOnce</access>
|
|
</field>
|
|
<field>
|
|
<name>INEN</name>
|
|
<description>Input Enable.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-writeOnce</access>
|
|
</field>
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>Interrupt Enable.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SERV</name>
|
|
<description>Service Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SERVICE</name>
|
|
<description>SERVICE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPL</name>
|
|
<description>Compare Low Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-writeOnce</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPAREL</name>
|
|
<description>COMPAREL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-writeOnce</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPH</name>
|
|
<description>Compare High Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-writeOnce</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPAREH</name>
|
|
<description>COMPAREH</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-writeOnce</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKCTRL</name>
|
|
<description>Clock Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>CLKSEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-writeOnce</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKPRESCALER</name>
|
|
<description>Clock Prescaler Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-writeOnce</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLK_DIV</name>
|
|
<description>CLK_DIV</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-writeOnce</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WDOG1</name>
|
|
<description>WDOG</description>
|
|
<groupName>WDOG</groupName>
|
|
<headerStructName>WDOG</headerStructName>
|
|
<baseAddress>0x400B8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xA</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WDOG1</name>
|
|
<value>74</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>WCR</name>
|
|
<description>Watchdog Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDZST</name>
|
|
<description>WDZST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDZST_0</name>
|
|
<description>Continue timer operation (Default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDZST_1</name>
|
|
<description>Suspend the watchdog timer.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDBG</name>
|
|
<description>WDBG</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDBG_0</name>
|
|
<description>Continue WDOG timer operation (Default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDBG_1</name>
|
|
<description>Suspend the watchdog timer.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDE</name>
|
|
<description>WDE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDE_0</name>
|
|
<description>Disable the Watchdog (Default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDE_1</name>
|
|
<description>Enable the Watchdog.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDT</name>
|
|
<description>WDT</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDT_0</name>
|
|
<description>No effect on WDOG_B (Default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDT_1</name>
|
|
<description>Assert WDOG_B upon a Watchdog Time-out event.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRS</name>
|
|
<description>SRS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRS_0</name>
|
|
<description>Assert system reset signal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRS_1</name>
|
|
<description>No effect on the system (Default).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDA</name>
|
|
<description>WDA</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDA_0</name>
|
|
<description>Assert WDOG_B output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDA_1</name>
|
|
<description>No effect on system (Default).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>software reset extension, an option way to generate software reset</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0</name>
|
|
<description>using original way to generate software reset (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1</name>
|
|
<description>using new way to generate software reset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDW</name>
|
|
<description>WDW</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WDW_0</name>
|
|
<description>Continue WDOG timer operation (Default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDW_1</name>
|
|
<description>Suspend WDOG timer operation.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WT</name>
|
|
<description>WT</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WT_0</name>
|
|
<description>- 0.5 Seconds (Default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WT_1</name>
|
|
<description>- 1.0 Seconds.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WT_2</name>
|
|
<description>- 1.5 Seconds.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WT_3</name>
|
|
<description>- 2.0 Seconds.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WT_255</name>
|
|
<description>- 128 Seconds.</description>
|
|
<value>0xFF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WSR</name>
|
|
<description>Watchdog Service Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WSR</name>
|
|
<description>WSR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WSR_21845</name>
|
|
<description>Write to the Watchdog Service Register (WDOG_WSR).</description>
|
|
<value>0x5555</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WSR_43690</name>
|
|
<description>Write to the Watchdog Service Register (WDOG_WSR).</description>
|
|
<value>0xAAAA</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRSR</name>
|
|
<description>Watchdog Reset Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SFTW</name>
|
|
<description>SFTW</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SFTW_0</name>
|
|
<description>Reset is not the result of a software reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SFTW_1</name>
|
|
<description>Reset is the result of a software reset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOUT</name>
|
|
<description>TOUT</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOUT_0</name>
|
|
<description>Reset is not the result of a WDOG timeout.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOUT_1</name>
|
|
<description>Reset is the result of a WDOG timeout.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POR</name>
|
|
<description>POR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POR_0</name>
|
|
<description>Reset is not the result of a power on reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POR_1</name>
|
|
<description>Reset is the result of a power on reset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WICR</name>
|
|
<description>Watchdog Interrupt Control Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WICT</name>
|
|
<description>WICT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WICT_0</name>
|
|
<description>WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WICT_1</name>
|
|
<description>WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WICT_4</name>
|
|
<description>WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WICT_255</name>
|
|
<description>WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.</description>
|
|
<value>0xFF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WTIS</name>
|
|
<description>WTIS</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WTIS_0</name>
|
|
<description>No interrupt has occurred (Default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WTIS_1</name>
|
|
<description>Interrupt has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WIE</name>
|
|
<description>WIE</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WIE_0</name>
|
|
<description>Disable Interrupt (Default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIE_1</name>
|
|
<description>Enable Interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WMCR</name>
|
|
<description>Watchdog Miscellaneous Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDE</name>
|
|
<description>PDE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PDE_0</name>
|
|
<description>Power Down Counter of WDOG is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDE_1</name>
|
|
<description>Power Down Counter of WDOG is enabled (Default).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="WDOG1">
|
|
<name>WDOG2</name>
|
|
<description>WDOG</description>
|
|
<groupName>WDOG</groupName>
|
|
<baseAddress>0x400D0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xA</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WDOG2</name>
|
|
<value>45</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTWDOG</name>
|
|
<description>WDOG</description>
|
|
<groupName>RTWDOG</groupName>
|
|
<baseAddress>0x400BC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTWDOG</name>
|
|
<value>57</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CS</name>
|
|
<description>Watchdog Control and Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2980</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_0</name>
|
|
<description>Watchdog disabled in chip stop mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_1</name>
|
|
<description>Watchdog enabled in chip stop mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAIT</name>
|
|
<description>Wait Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WAIT_0</name>
|
|
<description>Watchdog disabled in chip wait mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT_1</name>
|
|
<description>Watchdog enabled in chip wait mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBG</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBG_0</name>
|
|
<description>Watchdog disabled in chip debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBG_1</name>
|
|
<description>Watchdog enabled in chip debug mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TST</name>
|
|
<description>Watchdog Test</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TST_0</name>
|
|
<description>Watchdog test mode disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TST_1</name>
|
|
<description>Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TST_2</name>
|
|
<description>Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TST_3</name>
|
|
<description>Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>Allow updates</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UPDATE_0</name>
|
|
<description>Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE_1</name>
|
|
<description>Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT</name>
|
|
<description>Watchdog Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT_0</name>
|
|
<description>Watchdog interrupts are disabled. Watchdog resets are not delayed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT_1</name>
|
|
<description>Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Watchdog Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN_0</name>
|
|
<description>Watchdog disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_1</name>
|
|
<description>Watchdog enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLK</name>
|
|
<description>Watchdog Clock</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLK_0</name>
|
|
<description>Bus clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_1</name>
|
|
<description>LPO clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_2</name>
|
|
<description>INTCLK (internal clock)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_3</name>
|
|
<description>ERCLK (external reference clock)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCS</name>
|
|
<description>Reconfiguration Success</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RCS_0</name>
|
|
<description>Reconfiguring WDOG.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RCS_1</name>
|
|
<description>Reconfiguration is successful.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ULK</name>
|
|
<description>Unlock status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ULK_0</name>
|
|
<description>WDOG is locked.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULK_1</name>
|
|
<description>WDOG is unlocked.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRES</name>
|
|
<description>Watchdog prescaler</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRES_0</name>
|
|
<description>256 prescaler disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRES_1</name>
|
|
<description>256 prescaler enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD32EN</name>
|
|
<description>Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMD32EN_0</name>
|
|
<description>Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMD32EN_1</name>
|
|
<description>Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLG</name>
|
|
<description>Watchdog Interrupt Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLG_0</name>
|
|
<description>No interrupt occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLG_1</name>
|
|
<description>An interrupt occurred.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WIN</name>
|
|
<description>Watchdog Window</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WIN_0</name>
|
|
<description>Window mode disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIN_1</name>
|
|
<description>Window mode enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Watchdog Counter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTLOW</name>
|
|
<description>Low byte of the Watchdog Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNTHIGH</name>
|
|
<description>High byte of the Watchdog Counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOVAL</name>
|
|
<description>Watchdog Timeout Value Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x400</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOVALLOW</name>
|
|
<description>Low byte of the timeout value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TOVALHIGH</name>
|
|
<description>High byte of the timeout value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WIN</name>
|
|
<description>Watchdog Window Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINLOW</name>
|
|
<description>Low byte of Watchdog Window</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WINHIGH</name>
|
|
<description>High byte of Watchdog Window</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC1</name>
|
|
<description>Analog-to-Digital Converter</description>
|
|
<groupName>ADC</groupName>
|
|
<prependToName>ADC1_</prependToName>
|
|
<baseAddress>0x400C4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x5C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC1</name>
|
|
<value>67</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>HC0</name>
|
|
<description>Control register for hardware triggers</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCH</name>
|
|
<description>Input Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCH_16</name>
|
|
<description>External channel selection from ADC_ETC</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCH_25</name>
|
|
<description>VREFSH = internal channel, for ADC self-test, hard connected to VRH internally</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCH_31</name>
|
|
<description>Conversion Disabled. Hardware Triggers will not initiate any conversion.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AIEN</name>
|
|
<description>Conversion Complete Interrupt Enable/Disable Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AIEN_0</name>
|
|
<description>Conversion complete interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIEN_1</name>
|
|
<description>Conversion complete interrupt enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1,2,3,4,5,6,7</dimIndex>
|
|
<name>HC%s</name>
|
|
<description>Control register for hardware triggers</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCH</name>
|
|
<description>Input Channel Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCH_16</name>
|
|
<description>External channel selection from ADC_ETC</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCH_25</name>
|
|
<description>VREFSH = internal channel, for ADC self-test, hard connected to VRH internally</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCH_31</name>
|
|
<description>Conversion Disabled. Hardware Triggers will not initiate any conversion.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AIEN</name>
|
|
<description>Conversion Complete Interrupt Enable/Disable Control</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AIEN_0</name>
|
|
<description>Conversion complete interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AIEN_1</name>
|
|
<description>Conversion complete interrupt enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HS</name>
|
|
<description>Status register for HW triggers</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COCO0</name>
|
|
<description>Conversion Complete Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>R0</name>
|
|
<description>Data result register for HW triggers</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CDATA</name>
|
|
<description>Data (result of an ADC conversion)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1,2,3,4,5,6,7</dimIndex>
|
|
<name>R%s</name>
|
|
<description>Data result register for HW triggers</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CDATA</name>
|
|
<description>Data (result of an ADC conversion)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>Configuration register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADICLK</name>
|
|
<description>Input Clock Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADICLK_0</name>
|
|
<description>IPG clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADICLK_1</name>
|
|
<description>IPG clock divided by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADICLK_2</name>
|
|
<description>Alternate clock (ALTCLK)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADICLK_3</name>
|
|
<description>Asynchronous clock (ADACK)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Conversion Mode Selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MODE_0</name>
|
|
<description>8-bit conversion</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1</name>
|
|
<description>10-bit conversion</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_2</name>
|
|
<description>12-bit conversion</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADLSMP</name>
|
|
<description>Long Sample Time Configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADLSMP_0</name>
|
|
<description>Short sample mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADLSMP_1</name>
|
|
<description>Long sample mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADIV</name>
|
|
<description>Clock Divide Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADIV_0</name>
|
|
<description>Input clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADIV_1</name>
|
|
<description>Input clock / 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADIV_2</name>
|
|
<description>Input clock / 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADIV_3</name>
|
|
<description>Input clock / 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADLPC</name>
|
|
<description>Low-Power Configuration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADLPC_0</name>
|
|
<description>ADC hard block not in low power mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADLPC_1</name>
|
|
<description>ADC hard block in low power mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADSTS</name>
|
|
<description>Defines the sample time duration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADSTS_0</name>
|
|
<description>Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADSTS_1</name>
|
|
<description>Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADSTS_2</name>
|
|
<description>Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADSTS_3</name>
|
|
<description>Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADHSC</name>
|
|
<description>High Speed Configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADHSC_0</name>
|
|
<description>Normal conversion selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADHSC_1</name>
|
|
<description>High speed conversion selected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Voltage Reference Selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFSEL_0</name>
|
|
<description>Selects VREFH/VREFL as reference voltage.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTRG</name>
|
|
<description>Conversion Trigger Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADTRG_0</name>
|
|
<description>Software trigger selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADTRG_1</name>
|
|
<description>Hardware trigger selected</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVGS</name>
|
|
<description>Hardware Average select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AVGS_0</name>
|
|
<description>4 samples averaged</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVGS_1</name>
|
|
<description>8 samples averaged</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVGS_2</name>
|
|
<description>16 samples averaged</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVGS_3</name>
|
|
<description>32 samples averaged</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVWREN</name>
|
|
<description>Data Overwrite Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OVWREN_0</name>
|
|
<description>Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVWREN_1</name>
|
|
<description>Enable the overwriting.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GC</name>
|
|
<description>General control register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADACKEN</name>
|
|
<description>Asynchronous clock output enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADACKEN_0</name>
|
|
<description>Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADACKEN_1</name>
|
|
<description>Asynchronous clock and clock output enabled regardless of the state of the ADC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMAEN_0</name>
|
|
<description>DMA disabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMAEN_1</name>
|
|
<description>DMA enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACREN</name>
|
|
<description>Compare Function Range Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACREN_0</name>
|
|
<description>Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACREN_1</name>
|
|
<description>Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFGT</name>
|
|
<description>Compare Function Greater Than Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACFGT_0</name>
|
|
<description>Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACFGT_1</name>
|
|
<description>Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFE</name>
|
|
<description>Compare Function Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACFE_0</name>
|
|
<description>Compare function disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACFE_1</name>
|
|
<description>Compare function enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVGE</name>
|
|
<description>Hardware average enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AVGE_0</name>
|
|
<description>Hardware average function disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVGE_1</name>
|
|
<description>Hardware average function enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCO</name>
|
|
<description>Continuous Conversion Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADCO_0</name>
|
|
<description>One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCO_1</name>
|
|
<description>Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>Calibration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GS</name>
|
|
<description>General status register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADACT</name>
|
|
<description>Conversion Active</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADACT_0</name>
|
|
<description>Conversion not in progress.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADACT_1</name>
|
|
<description>Conversion in progress.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CALF</name>
|
|
<description>Calibration Failed Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CALF_0</name>
|
|
<description>Calibration completed normally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CALF_1</name>
|
|
<description>Calibration failed. ADC accuracy specifications are not guaranteed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AWKST</name>
|
|
<description>Asynchronous wakeup interrupt status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AWKST_0</name>
|
|
<description>No asynchronous interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AWKST_1</name>
|
|
<description>Asynchronous wake up interrupt occurred in stop mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CV</name>
|
|
<description>Compare value register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CV1</name>
|
|
<description>Compare Value 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CV2</name>
|
|
<description>Compare Value 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFS</name>
|
|
<description>Offset correction value register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFS</name>
|
|
<description>Offset value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SIGN</name>
|
|
<description>Sign bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SIGN_0</name>
|
|
<description>The offset value is added with the raw result</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIGN_1</name>
|
|
<description>The offset value is subtracted from the raw converted value</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAL</name>
|
|
<description>Calibration value register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAL_CODE</name>
|
|
<description>Calibration Result Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TRNG</name>
|
|
<description>TRNG</description>
|
|
<groupName>TRNG</groupName>
|
|
<baseAddress>0x400CC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TRNG</name>
|
|
<value>53</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MCTL</name>
|
|
<description>Miscellaneous Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x12001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SAMP_MODE</name>
|
|
<description>Sample Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAMP_MODE_0</name>
|
|
<description>use Von Neumann data into both Entropy shifter and Statistical Checker</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMP_MODE_1</name>
|
|
<description>use raw data into both Entropy shifter and Statistical Checker</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMP_MODE_2</name>
|
|
<description>use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMP_MODE_3</name>
|
|
<description>undefined/reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_DIV</name>
|
|
<description>Oscillator Divide</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OSC_DIV_0</name>
|
|
<description>use ring oscillator with no divide</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSC_DIV_1</name>
|
|
<description>use ring oscillator divided-by-2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSC_DIV_2</name>
|
|
<description>use ring oscillator divided-by-4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSC_DIV_3</name>
|
|
<description>use ring oscillator divided-by-8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UNUSED4</name>
|
|
<description>This bit is unused. Always reads zero.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UNUSED5</name>
|
|
<description>This bit is unused. Always reads zero.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RST_DEF</name>
|
|
<description>Reset Defaults</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FOR_SCLK</name>
|
|
<description>Force System Clock</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FCT_FAIL</name>
|
|
<description>Read only: Frequency Count Fail</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FCT_VAL</name>
|
|
<description>Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENT_VAL</name>
|
|
<description>Read only: Entropy Valid</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TST_OUT</name>
|
|
<description>Read only: Test point inside ring oscillator.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>Read: Error status</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTOP_OK</name>
|
|
<description>TRNG_OK_TO_STOP</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LRUN_CONT</name>
|
|
<description>Long run count continues between entropy generations</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRGM</name>
|
|
<description>Programming Mode Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCMISC</name>
|
|
<description>Statistical Check Miscellaneous Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10022</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LRUN_MAX</name>
|
|
<description>LONG RUN MAX LIMIT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTY_CT</name>
|
|
<description>RETRY COUNT</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PKRRNG</name>
|
|
<description>Poker Range Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x9A3</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKR_RNG</name>
|
|
<description>Poker Range</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PKRMAX</name>
|
|
<description>Poker Maximum Limit Register</description>
|
|
<alternateGroup>MAX_SQ</alternateGroup>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x6920</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKR_MAX</name>
|
|
<description>Poker Maximum Limit.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PKRSQ</name>
|
|
<description>Poker Square Calculation Result Register</description>
|
|
<alternateGroup>MAX_SQ</alternateGroup>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKR_SQ</name>
|
|
<description>Poker Square Calculation Result.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDCTL</name>
|
|
<description>Seed Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC8009C4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SAMP_SIZE</name>
|
|
<description>Sample Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENT_DLY</name>
|
|
<description>Entropy Delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SBLIM</name>
|
|
<description>Sparse Bit Limit Register</description>
|
|
<alternateGroup>SBLIM_TOTSAM</alternateGroup>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SB_LIM</name>
|
|
<description>Sparse Bit Limit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOTSAM</name>
|
|
<description>Total Samples Register</description>
|
|
<alternateGroup>SBLIM_TOTSAM</alternateGroup>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOT_SAM</name>
|
|
<description>Total Samples</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRQMIN</name>
|
|
<description>Frequency Count Minimum Limit Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x640</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRQ_MIN</name>
|
|
<description>Frequency Count Minimum Limit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>22</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRQCNT</name>
|
|
<description>Frequency Count Register</description>
|
|
<alternateGroup>MAX_CNT</alternateGroup>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRQ_CT</name>
|
|
<description>Frequency Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>22</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRQMAX</name>
|
|
<description>Frequency Count Maximum Limit Register</description>
|
|
<alternateGroup>MAX_CNT</alternateGroup>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x6400</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRQ_MAX</name>
|
|
<description>Frequency Counter Maximum Limit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>22</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCMC</name>
|
|
<description>Statistical Check Monobit Count Register</description>
|
|
<alternateGroup>SCML_MC</alternateGroup>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MONO_CT</name>
|
|
<description>Monobit Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCML</name>
|
|
<description>Statistical Check Monobit Limit Register</description>
|
|
<alternateGroup>SCML_MC</alternateGroup>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10C0568</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MONO_MAX</name>
|
|
<description>Monobit Maximum Limit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MONO_RNG</name>
|
|
<description>Monobit Range</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR1C</name>
|
|
<description>Statistical Check Run Length 1 Count Register</description>
|
|
<alternateGroup>SCR1L_1C</alternateGroup>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R1_0_CT</name>
|
|
<description>Runs of Zero, Length 1 Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>R1_1_CT</name>
|
|
<description>Runs of One, Length 1 Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR1L</name>
|
|
<description>Statistical Check Run Length 1 Limit Register</description>
|
|
<alternateGroup>SCR1L_1C</alternateGroup>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xB20195</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN1_MAX</name>
|
|
<description>Run Length 1 Maximum Limit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RUN1_RNG</name>
|
|
<description>Run Length 1 Range</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR2C</name>
|
|
<description>Statistical Check Run Length 2 Count Register</description>
|
|
<alternateGroup>SCR2L_2C</alternateGroup>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R2_0_CT</name>
|
|
<description>Runs of Zero, Length 2 Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>R2_1_CT</name>
|
|
<description>Runs of One, Length 2 Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR2L</name>
|
|
<description>Statistical Check Run Length 2 Limit Register</description>
|
|
<alternateGroup>SCR2L_2C</alternateGroup>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7A00DC</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN2_MAX</name>
|
|
<description>Run Length 2 Maximum Limit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RUN2_RNG</name>
|
|
<description>Run Length 2 Range</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR3C</name>
|
|
<description>Statistical Check Run Length 3 Count Register</description>
|
|
<alternateGroup>SCR3L_3C</alternateGroup>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R3_0_CT</name>
|
|
<description>Runs of Zeroes, Length 3 Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>R3_1_CT</name>
|
|
<description>Runs of Ones, Length 3 Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR3L</name>
|
|
<description>Statistical Check Run Length 3 Limit Register</description>
|
|
<alternateGroup>SCR3L_3C</alternateGroup>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x58007D</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN3_MAX</name>
|
|
<description>Run Length 3 Maximum Limit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RUN3_RNG</name>
|
|
<description>Run Length 3 Range</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR4C</name>
|
|
<description>Statistical Check Run Length 4 Count Register</description>
|
|
<alternateGroup>SCR4L_4C</alternateGroup>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R4_0_CT</name>
|
|
<description>Runs of Zero, Length 4 Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>R4_1_CT</name>
|
|
<description>Runs of One, Length 4 Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR4L</name>
|
|
<description>Statistical Check Run Length 4 Limit Register</description>
|
|
<alternateGroup>SCR4L_4C</alternateGroup>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40004B</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN4_MAX</name>
|
|
<description>Run Length 4 Maximum Limit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RUN4_RNG</name>
|
|
<description>Run Length 4 Range</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR5C</name>
|
|
<description>Statistical Check Run Length 5 Count Register</description>
|
|
<alternateGroup>SCR5L_5C</alternateGroup>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R5_0_CT</name>
|
|
<description>Runs of Zero, Length 5 Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>R5_1_CT</name>
|
|
<description>Runs of One, Length 5 Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR5L</name>
|
|
<description>Statistical Check Run Length 5 Limit Register</description>
|
|
<alternateGroup>SCR5L_5C</alternateGroup>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2E002F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN5_MAX</name>
|
|
<description>Run Length 5 Maximum Limit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RUN5_RNG</name>
|
|
<description>Run Length 5 Range</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR6PC</name>
|
|
<description>Statistical Check Run Length 6+ Count Register</description>
|
|
<alternateGroup>SCR6PL_PC</alternateGroup>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R6P_0_CT</name>
|
|
<description>Runs of Zero, Length 6+ Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>R6P_1_CT</name>
|
|
<description>Runs of One, Length 6+ Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR6PL</name>
|
|
<description>Statistical Check Run Length 6+ Limit Register</description>
|
|
<alternateGroup>SCR6PL_PC</alternateGroup>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2E002F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN6P_MAX</name>
|
|
<description>Run Length 6+ Maximum Limit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RUN6P_RNG</name>
|
|
<description>Run Length 6+ Range</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TF1BR0</name>
|
|
<description>Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TF1BR1</name>
|
|
<description>Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TF2BR0</name>
|
|
<description>Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TF2BR1</name>
|
|
<description>Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TF3BR0</name>
|
|
<description>Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TF3BR1</name>
|
|
<description>Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TF4BR0</name>
|
|
<description>Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TF4BR1</name>
|
|
<description>Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TF5BR0</name>
|
|
<description>Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TF5BR1</name>
|
|
<description>Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TF6PBR0</name>
|
|
<description>Test Fail, 6 Plus Bit Run, Sampling 0s</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TF6PBR1</name>
|
|
<description>Test Fail, 6 Plus Bit Run, Sampling 1s</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFSB</name>
|
|
<description>Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFLR</name>
|
|
<description>Test Fail, Long Run. If TFLR=1, the Long Run Test has failed.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFP</name>
|
|
<description>Test Fail, Poker. If TFP=1, the Poker Test has failed.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFMB</name>
|
|
<description>Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RETRY_CT</name>
|
|
<description>RETRY COUNT</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>ENT[%s]</name>
|
|
<description>Entropy Read Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENT</name>
|
|
<description>Entropy Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PKRCNT10</name>
|
|
<description>Statistical Check Poker Count 1 and 0 Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKR_0_CT</name>
|
|
<description>Poker 0h Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKR_1_CT</name>
|
|
<description>Poker 1h Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PKRCNT32</name>
|
|
<description>Statistical Check Poker Count 3 and 2 Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKR_2_CT</name>
|
|
<description>Poker 2h Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKR_3_CT</name>
|
|
<description>Poker 3h Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PKRCNT54</name>
|
|
<description>Statistical Check Poker Count 5 and 4 Register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKR_4_CT</name>
|
|
<description>Poker 4h Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKR_5_CT</name>
|
|
<description>Poker 5h Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PKRCNT76</name>
|
|
<description>Statistical Check Poker Count 7 and 6 Register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKR_6_CT</name>
|
|
<description>Poker 6h Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKR_7_CT</name>
|
|
<description>Poker 7h Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PKRCNT98</name>
|
|
<description>Statistical Check Poker Count 9 and 8 Register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKR_8_CT</name>
|
|
<description>Poker 8h Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKR_9_CT</name>
|
|
<description>Poker 9h Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PKRCNTBA</name>
|
|
<description>Statistical Check Poker Count B and A Register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKR_A_CT</name>
|
|
<description>Poker Ah Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKR_B_CT</name>
|
|
<description>Poker Bh Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PKRCNTDC</name>
|
|
<description>Statistical Check Poker Count D and C Register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKR_C_CT</name>
|
|
<description>Poker Ch Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKR_D_CT</name>
|
|
<description>Poker Dh Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PKRCNTFE</name>
|
|
<description>Statistical Check Poker Count F and E Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PKR_E_CT</name>
|
|
<description>Poker Eh Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PKR_F_CT</name>
|
|
<description>Poker Fh Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEC_CFG</name>
|
|
<description>Security Configuration Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UNUSED0</name>
|
|
<description>This bit is unused. Ignore.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NO_PRGM</name>
|
|
<description>If set, the TRNG registers cannot be programmed</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_PRGM_0</name>
|
|
<description>Programability of registers controlled only by the Miscellaneous Control Register's access mode bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_PRGM_1</name>
|
|
<description>Overides Miscellaneous Control Register access mode and prevents TRNG register programming.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UNUSED2</name>
|
|
<description>This bit is unused. Ignore.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_CTRL</name>
|
|
<description>Interrupt Control Register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HW_ERR</name>
|
|
<description>Bit position that can be cleared if corresponding bit of INT_STATUS register has been asserted.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HW_ERR_0</name>
|
|
<description>Corresponding bit of INT_STATUS register cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HW_ERR_1</name>
|
|
<description>Corresponding bit of INT_STATUS register active.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENT_VAL</name>
|
|
<description>Same behavior as bit 0 of this register.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENT_VAL_0</name>
|
|
<description>Same behavior as bit 0 of this register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENT_VAL_1</name>
|
|
<description>Same behavior as bit 0 of this register.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRQ_CT_FAIL</name>
|
|
<description>Same behavior as bit 0 of this register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRQ_CT_FAIL_0</name>
|
|
<description>Same behavior as bit 0 of this register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRQ_CT_FAIL_1</name>
|
|
<description>Same behavior as bit 0 of this register.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_MASK</name>
|
|
<description>Mask Register</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HW_ERR</name>
|
|
<description>Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HW_ERR_0</name>
|
|
<description>Corresponding interrupt of INT_STATUS is masked.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HW_ERR_1</name>
|
|
<description>Corresponding bit of INT_STATUS is active.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENT_VAL</name>
|
|
<description>Same behavior as bit 0 of this register.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENT_VAL_0</name>
|
|
<description>Same behavior as bit 0 of this register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENT_VAL_1</name>
|
|
<description>Same behavior as bit 0 of this register.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRQ_CT_FAIL</name>
|
|
<description>Same behavior as bit 0 of this register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRQ_CT_FAIL_0</name>
|
|
<description>Same behavior as bit 0 of this register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRQ_CT_FAIL_1</name>
|
|
<description>Same behavior as bit 0 of this register.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_STATUS</name>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HW_ERR</name>
|
|
<description>Read: Error status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HW_ERR_0</name>
|
|
<description>no error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HW_ERR_1</name>
|
|
<description>error detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENT_VAL</name>
|
|
<description>Read only: Entropy Valid</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENT_VAL_0</name>
|
|
<description>Busy generation entropy. Any value read is invalid.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENT_VAL_1</name>
|
|
<description>TRNG can be stopped and entropy is valid if read.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRQ_CT_FAIL</name>
|
|
<description>Read only: Frequency Count Fail</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRQ_CT_FAIL_0</name>
|
|
<description>No hardware nor self test frequency errors.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRQ_CT_FAIL_1</name>
|
|
<description>The frequency counter has detected a failure.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VID1</name>
|
|
<description>Version ID Register (MS)</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x300301</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MIN_REV</name>
|
|
<description>Shows the IP's Minor revision of the TRNG.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MIN_REV_0</name>
|
|
<description>Minor revision number for TRNG.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJ_REV</name>
|
|
<description>Shows the IP's Major revision of the TRNG.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJ_REV_1</name>
|
|
<description>Major revision number for TRNG.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IP_ID</name>
|
|
<description>Shows the IP ID.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IP_ID_48</name>
|
|
<description>ID for TRNG.</description>
|
|
<value>0x30</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VID2</name>
|
|
<description>Version ID Register (LS)</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CONFIG_OPT</name>
|
|
<description>Shows the IP's Configuaration options for the TRNG.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONFIG_OPT_0</name>
|
|
<description>TRNG_CONFIG_OPT for TRNG.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECO_REV</name>
|
|
<description>Shows the IP's ECO revision of the TRNG.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECO_REV_0</name>
|
|
<description>TRNG_ECO_REV for TRNG.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTG_OPT</name>
|
|
<description>Shows the integration options for the TRNG.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTG_OPT_0</name>
|
|
<description>INTG_OPT for TRNG.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERA</name>
|
|
<description>Shows the compile options for the TRNG.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERA_0</name>
|
|
<description>COMPILE_OPT for TRNG.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SNVS</name>
|
|
<description>SNVS</description>
|
|
<groupName>SNVS</groupName>
|
|
<baseAddress>0x400D4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SNVS_HP_WRAPPER</name>
|
|
<value>46</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SNVS_HP_WRAPPER_TZ</name>
|
|
<value>47</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SNVS_LP_WRAPPER</name>
|
|
<value>48</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>HPLR</name>
|
|
<description>SNVS_HP Lock Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ZMK_WSL</name>
|
|
<description>Zeroizable Master Key Write Soft Lock When set, prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ZMK_WSL_0</name>
|
|
<description>Write access is allowed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZMK_WSL_1</name>
|
|
<description>Write access is not allowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZMK_RSL</name>
|
|
<description>Zeroizable Master Key Read Soft Lock When set, prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ZMK_RSL_0</name>
|
|
<description>Read access is allowed (only in software Programming mode)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZMK_RSL_1</name>
|
|
<description>Read access is not allowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRTC_SL</name>
|
|
<description>Secure Real Time Counter Soft Lock When set, prevents any writes to the SRTC Registers, SRTC_ENV, and SRTC_INV_EN bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRTC_SL_0</name>
|
|
<description>Write access is allowed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRTC_SL_1</name>
|
|
<description>Write access is not allowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPCALB_SL</name>
|
|
<description>LP Calibration Soft Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPCALB_SL_0</name>
|
|
<description>Write access is allowed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPCALB_SL_1</name>
|
|
<description>Write access is not allowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC_SL</name>
|
|
<description>Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MC_SL_0</name>
|
|
<description>Write access (increment) is allowed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_SL_1</name>
|
|
<description>Write access (increment) is not allowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPR_SL</name>
|
|
<description>General Purpose Register Soft Lock When set, prevents any writes to the GPR</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPR_SL_0</name>
|
|
<description>Write access is allowed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPR_SL_1</name>
|
|
<description>Write access is not allowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSVCR_SL</name>
|
|
<description>LP Security Violation Control Register Soft Lock When set, prevents any writes to the LPSVCR</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSVCR_SL_0</name>
|
|
<description>Write access is allowed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSVCR_SL_1</name>
|
|
<description>Write access is not allowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPTDCR_SL</name>
|
|
<description>LP Tamper Detectors Configuration Register Soft Lock When set, prevents any writes to the LPTDCR</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPTDCR_SL_0</name>
|
|
<description>Write access is allowed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTDCR_SL_1</name>
|
|
<description>Write access is not allowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MKS_SL</name>
|
|
<description>Master Key Select Soft Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LPMKCR</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MKS_SL_0</name>
|
|
<description>Write access is allowed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MKS_SL_1</name>
|
|
<description>Write access is not allowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPSVCR_L</name>
|
|
<description>HP Security Violation Control Register Lock When set, prevents any writes to the HPSVCR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPSVCR_L_0</name>
|
|
<description>Write access is allowed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPSVCR_L_1</name>
|
|
<description>Write access is not allowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPSICR_L</name>
|
|
<description>HP Security Interrupt Control Register Lock When set, prevents any writes to the HPSICR</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPSICR_L_0</name>
|
|
<description>Write access is allowed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPSICR_L_1</name>
|
|
<description>Write access is not allowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HAC_L</name>
|
|
<description>High Assurance Counter Lock When set, prevents any writes to HPHACIVR, HPHACR, and HAC_EN bit of HPCOMR</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HAC_L_0</name>
|
|
<description>Write access is allowed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HAC_L_1</name>
|
|
<description>Write access is not allowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPCOMR</name>
|
|
<description>SNVS_HP Command Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSM_ST</name>
|
|
<description>SSM State Transition Transition state of the system security monitor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM_ST_DIS</name>
|
|
<description>SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSM_ST_DIS_0</name>
|
|
<description>Secure to Trusted State transition is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSM_ST_DIS_1</name>
|
|
<description>Secure to Trusted State transition is disabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSM_SFNS_DIS</name>
|
|
<description>SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSM_SFNS_DIS_0</name>
|
|
<description>Soft Fail to Non-Secure State transition is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSM_SFNS_DIS_1</name>
|
|
<description>Soft Fail to Non-Secure State transition is disabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LP_SWR</name>
|
|
<description>LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LP_SWR_0</name>
|
|
<description>No Action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LP_SWR_1</name>
|
|
<description>Reset LP section</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LP_SWR_DIS</name>
|
|
<description>LP Software Reset Disable When set, disables the LP software reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LP_SWR_DIS_0</name>
|
|
<description>LP software reset is enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LP_SWR_DIS_1</name>
|
|
<description>LP software reset is disabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SW_SV</name>
|
|
<description>Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_FSV</name>
|
|
<description>Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_LPSV</name>
|
|
<description>LP Software Security Violation When set, SNVS_LP treats this bit as a security violation</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROG_ZMK</name>
|
|
<description>Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PROG_ZMK_0</name>
|
|
<description>No Action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PROG_ZMK_1</name>
|
|
<description>Activate hardware key programming mechanism</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MKS_EN</name>
|
|
<description>Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MKS_EN_0</name>
|
|
<description>OTP master key is selected as an SNVS master key</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MKS_EN_1</name>
|
|
<description>SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HAC_EN</name>
|
|
<description>High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HAC_EN_0</name>
|
|
<description>High Assurance Counter is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HAC_EN_1</name>
|
|
<description>High Assurance Counter is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HAC_LOAD</name>
|
|
<description>High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HAC_LOAD_0</name>
|
|
<description>No Action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HAC_LOAD_1</name>
|
|
<description>Load the HAC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HAC_CLEAR</name>
|
|
<description>High Assurance Counter Clear When set, it clears the High Assurance Counter Register</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HAC_CLEAR_0</name>
|
|
<description>No Action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HAC_CLEAR_1</name>
|
|
<description>Clear the HAC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HAC_STOP</name>
|
|
<description>High Assurance Counter Stop This bit can be set only when SSM is in soft fail state</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NPSWA_EN</name>
|
|
<description>Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPCR</name>
|
|
<description>SNVS_HP Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTC_EN</name>
|
|
<description>HP Real Time Counter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_EN_0</name>
|
|
<description>RTC is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_EN_1</name>
|
|
<description>RTC is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPTA_EN</name>
|
|
<description>HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPTA_EN_0</name>
|
|
<description>HP Time Alarm Interrupt is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPTA_EN_1</name>
|
|
<description>HP Time Alarm Interrupt is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIS_PI</name>
|
|
<description>Disable periodic interrupt in the functional interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS_PI_0</name>
|
|
<description>Periodic interrupt will trigger a functional interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_PI_1</name>
|
|
<description>Disable periodic interrupt in the function interrupt</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PI_EN</name>
|
|
<description>HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PI_EN_0</name>
|
|
<description>HP Periodic Interrupt is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_EN_1</name>
|
|
<description>HP Periodic Interrupt is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PI_FREQ</name>
|
|
<description>Periodic Interrupt Frequency Defines frequency of the periodic interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_0</name>
|
|
<description>- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_1</name>
|
|
<description>- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_2</name>
|
|
<description>- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_3</name>
|
|
<description>- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_4</name>
|
|
<description>- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_5</name>
|
|
<description>- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_6</name>
|
|
<description>- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_7</name>
|
|
<description>- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_8</name>
|
|
<description>- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_9</name>
|
|
<description>- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_10</name>
|
|
<description>- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_11</name>
|
|
<description>- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_12</name>
|
|
<description>- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_13</name>
|
|
<description>- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_14</name>
|
|
<description>- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_FREQ_15</name>
|
|
<description>- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPCALB_EN</name>
|
|
<description>HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPCALB_EN_0</name>
|
|
<description>HP Timer calibration disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPCALB_EN_1</name>
|
|
<description>HP Timer calibration enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPCALB_VAL</name>
|
|
<description>HP Calibration Value Defines signed calibration value for the HP Real Time Counter</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPCALB_VAL_0</name>
|
|
<description>+0 counts per each 32768 ticks of the counter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPCALB_VAL_1</name>
|
|
<description>+1 counts per each 32768 ticks of the counter</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPCALB_VAL_2</name>
|
|
<description>+2 counts per each 32768 ticks of the counter</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPCALB_VAL_15</name>
|
|
<description>+15 counts per each 32768 ticks of the counter</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPCALB_VAL_16</name>
|
|
<description>-16 counts per each 32768 ticks of the counter</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPCALB_VAL_17</name>
|
|
<description>-15 counts per each 32768 ticks of the counter</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPCALB_VAL_30</name>
|
|
<description>-2 counts per each 32768 ticks of the counter</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPCALB_VAL_31</name>
|
|
<description>-1 counts per each 32768 ticks of the counter</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HP_TS</name>
|
|
<description>HP Time Synchronize</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HP_TS_0</name>
|
|
<description>No Action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP_TS_1</name>
|
|
<description>Synchronize the HP Time Counter to the LP Time Counter</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BTN_CONFIG</name>
|
|
<description>Button Configuration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BTN_MASK</name>
|
|
<description>Button interrupt mask</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPSICR</name>
|
|
<description>SNVS_HP Security Interrupt Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SV0_EN</name>
|
|
<description>Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV0_EN_0</name>
|
|
<description>Security Violation 0 Interrupt is Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV0_EN_1</name>
|
|
<description>Security Violation 0 Interrupt is Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV1_EN</name>
|
|
<description>Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV1_EN_0</name>
|
|
<description>Security Violation 1 Interrupt is Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV1_EN_1</name>
|
|
<description>Security Violation 1 Interrupt is Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV2_EN</name>
|
|
<description>Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV2_EN_0</name>
|
|
<description>Security Violation 2 Interrupt is Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV2_EN_1</name>
|
|
<description>Security Violation 2 Interrupt is Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV3_EN</name>
|
|
<description>Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV3_EN_0</name>
|
|
<description>Security Violation 3 Interrupt is Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV3_EN_1</name>
|
|
<description>Security Violation 3 Interrupt is Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV4_EN</name>
|
|
<description>Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV4_EN_0</name>
|
|
<description>Security Violation 4 Interrupt is Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV4_EN_1</name>
|
|
<description>Security Violation 4 Interrupt is Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV5_EN</name>
|
|
<description>Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV5_EN_0</name>
|
|
<description>Security Violation 5 Interrupt is Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV5_EN_1</name>
|
|
<description>Security Violation 5 Interrupt is Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSVI_EN</name>
|
|
<description>LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSVI_EN_0</name>
|
|
<description>LP Security Violation Interrupt is Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSVI_EN_1</name>
|
|
<description>LP Security Violation Interrupt is Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPSVCR</name>
|
|
<description>SNVS_HP Security Violation Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SV0_CFG</name>
|
|
<description>Security Violation 0 Security Violation Configuration This field configures the Security Violation 0 Security Violation Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV0_CFG_0</name>
|
|
<description>Security Violation 0 is a non-fatal violation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV0_CFG_1</name>
|
|
<description>Security Violation 0 is a fatal violation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV1_CFG</name>
|
|
<description>Security Violation 1 Security Violation Configuration This field configures the Security Violation 1 Security Violation Input</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV1_CFG_0</name>
|
|
<description>Security Violation 1 is a non-fatal violation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV1_CFG_1</name>
|
|
<description>Security Violation 1 is a fatal violation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV2_CFG</name>
|
|
<description>Security Violation 2 Security Violation Configuration This field configures the Security Violation 2 Security Violation Input</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV2_CFG_0</name>
|
|
<description>Security Violation 2 is a non-fatal violation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV2_CFG_1</name>
|
|
<description>Security Violation 2 is a fatal violation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV3_CFG</name>
|
|
<description>Security Violation 3 Security Violation Configuration This field configures the Security Violation 3 Security Violation Input</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV3_CFG_0</name>
|
|
<description>Security Violation 3 is a non-fatal violation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV3_CFG_1</name>
|
|
<description>Security Violation 3 is a fatal violation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV4_CFG</name>
|
|
<description>Security Violation 4 Security Violation Configuration This field configures the Security Violation 4 Security Violation Input</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV4_CFG_0</name>
|
|
<description>Security Violation 4 is a non-fatal violation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV4_CFG_1</name>
|
|
<description>Security Violation 4 is a fatal violation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV5_CFG</name>
|
|
<description>Security Violation 5 Security Violation Configuration This field configures the Security Violation 5 Security Violation Input</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV5_CFG_0</name>
|
|
<description>Security Violation 5 is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV5_CFG_1</name>
|
|
<description>Security Violation 5 is a non-fatal violation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV5_CFG_2</name>
|
|
<description>Security Violation 5 is a fatal violation</description>
|
|
<value>#1x</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSV_CFG</name>
|
|
<description>LP Security Violation Configuration This field configures the LP security violation source.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSV_CFG_0</name>
|
|
<description>LP security violation is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSV_CFG_1</name>
|
|
<description>LP security violation is a non-fatal violation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSV_CFG_2</name>
|
|
<description>LP security violation is a fatal violation</description>
|
|
<value>#1x</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPSR</name>
|
|
<description>SNVS_HP Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80003000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HPTA</name>
|
|
<description>HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPTA_0</name>
|
|
<description>No time alarm interrupt occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPTA_1</name>
|
|
<description>A time alarm interrupt occurred.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PI</name>
|
|
<description>Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PI_0</name>
|
|
<description>No periodic interrupt occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PI_1</name>
|
|
<description>A periodic interrupt occurred.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPDIS</name>
|
|
<description>Low Power Disable If 1, the low power section has been disabled by means of an input signal to SNVS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BTN</name>
|
|
<description>Button Value of the BTN input</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BI</name>
|
|
<description>Button Interrupt Signal ipi_snvs_btn_int_b was asserted.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>SSM_STATE</name>
|
|
<description>System Security Monitor State This field contains the encoded state of the SSM's state machine</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSM_STATE_0</name>
|
|
<description>Init</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSM_STATE_1</name>
|
|
<description>Hard Fail</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSM_STATE_3</name>
|
|
<description>Soft Fail</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSM_STATE_8</name>
|
|
<description>Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSM_STATE_9</name>
|
|
<description>Check</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSM_STATE_11</name>
|
|
<description>Non-Secure</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSM_STATE_13</name>
|
|
<description>Trusted</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSM_STATE_15</name>
|
|
<description>Secure</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SECURITY_CONFIG</name>
|
|
<description>Security Configuration This field reflects the settings of the sys_secure_boot input and the three security configuration inputs to SNVS</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FAB_CONFIG</name>
|
|
<description>FAB configuration</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_CONFIG</name>
|
|
<description>OPEN configuration</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_CONFIG</name>
|
|
<description>OPEN configuration</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_CONFIG</name>
|
|
<description>OPEN configuration</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FIELD_RETURN_CONFIG</name>
|
|
<description>FIELD RETURN configuration</description>
|
|
<value>#x1xx</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAB_CONFIG</name>
|
|
<description>FAB configuration</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOSED_CONFIG</name>
|
|
<description>CLOSED configuration</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOSED_CONFIG</name>
|
|
<description>CLOSED configuration</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOSED_CONFIG</name>
|
|
<description>CLOSED configuration</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OTPMK_SYNDROME</name>
|
|
<description>One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OTPMK_ZERO</name>
|
|
<description>One Time Programmable Master Key is Equal to Zero</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OTPMK_ZERO_0</name>
|
|
<description>The OTPMK is not zero.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OTPMK_ZERO_1</name>
|
|
<description>The OTPMK is zero.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZMK_ZERO</name>
|
|
<description>Zeroizable Master Key is Equal to Zero</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ZMK_ZERO_0</name>
|
|
<description>The ZMK is not zero.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZMK_ZERO_1</name>
|
|
<description>The ZMK is zero.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPSVSR</name>
|
|
<description>SNVS_HP Security Violation Status Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SV0</name>
|
|
<description>Security Violation 0 security violation was detected.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV0_0</name>
|
|
<description>No Security Violation 0 security violation was detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV0_1</name>
|
|
<description>Security Violation 0 security violation was detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV1</name>
|
|
<description>Security Violation 1 security violation was detected.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV1_0</name>
|
|
<description>No Security Violation 1 security violation was detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV1_1</name>
|
|
<description>Security Violation 1 security violation was detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV2</name>
|
|
<description>Security Violation 2 security violation was detected.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV2_0</name>
|
|
<description>No Security Violation 2 security violation was detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV2_1</name>
|
|
<description>Security Violation 2 security violation was detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV3</name>
|
|
<description>Security Violation 3 security violation was detected.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV3_0</name>
|
|
<description>No Security Violation 3 security violation was detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV3_1</name>
|
|
<description>Security Violation 3 security violation was detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV4</name>
|
|
<description>Security Violation 4 security violation was detected.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV4_0</name>
|
|
<description>No Security Violation 4 security violation was detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV4_1</name>
|
|
<description>Security Violation 4 security violation was detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV5</name>
|
|
<description>Security Violation 5 security violation was detected.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV5_0</name>
|
|
<description>No Security Violation 5 security violation was detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV5_1</name>
|
|
<description>Security Violation 5 security violation was detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SW_SV</name>
|
|
<description>Software Security Violation This bit is a read-only copy of the SW_SV bit in the HP Command Register</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_FSV</name>
|
|
<description>Software Fatal Security Violation This bit is a read-only copy of the SW_FSV bit in the HP Command Register</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_LPSV</name>
|
|
<description>LP Software Security Violation This bit is a read-only copy of the SW_LPSV bit in the HP Command Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ZMK_SYNDROME</name>
|
|
<description>Zeroizable Master Key Syndrome The ZMK syndrome indicates the single-bit error location and parity for the ZMK register</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ZMK_ECC_FAIL</name>
|
|
<description>Zeroizable Master Key Error Correcting Code Check Failure When set, this bit triggers a bad key violation to the SSM and a security violation to the SNVS_LP section, which clears security sensitive data</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ZMK_ECC_FAIL_0</name>
|
|
<description>ZMK ECC Failure was not detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZMK_ECC_FAIL_1</name>
|
|
<description>ZMK ECC Failure was detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LP_SEC_VIO</name>
|
|
<description>LP Security Violation A security volation was detected in the SNVS low power section.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPHACIVR</name>
|
|
<description>SNVS_HP High Assurance Counter IV Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HAC_COUNTER_IV</name>
|
|
<description>High Assurance Counter Initial Value This register is used to set the starting count value to the high assurance counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPHACR</name>
|
|
<description>SNVS_HP High Assurance Counter Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HAC_COUNTER</name>
|
|
<description>High Assurance Counter When the HAC_EN bit is set and the SSM is in the soft fail state, this counter starts to count down with the system clock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPRTCMR</name>
|
|
<description>SNVS_HP Real Time Counter MSB Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTC</name>
|
|
<description>HP Real Time Counter The most-significant 15 bits of the RTC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPRTCLR</name>
|
|
<description>SNVS_HP Real Time Counter LSB Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTC</name>
|
|
<description>HP Real Time Counter least-significant 32 bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPTAMR</name>
|
|
<description>SNVS_HP Time Alarm MSB Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HPTA_MS</name>
|
|
<description>HP Time Alarm, most-significant 15 bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPTALR</name>
|
|
<description>SNVS_HP Time Alarm LSB Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HPTA_LS</name>
|
|
<description>HP Time Alarm, 32 least-significant bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPLR</name>
|
|
<description>SNVS_LP Lock Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ZMK_WHL</name>
|
|
<description>Zeroizable Master Key Write Hard Lock When set, prevents any writes (software and hardware) to the ZMK registers and ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ZMK_WHL_0</name>
|
|
<description>Write access is allowed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZMK_WHL_1</name>
|
|
<description>Write access is not allowed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZMK_RHL</name>
|
|
<description>Zeroizable Master Key Read Hard Lock When set, prevents any software reads to the ZMK registers and ZMK_ECC_VALUE field of the LPMKCR</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ZMK_RHL_0</name>
|
|
<description>Read access is allowed (only in software programming mode).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZMK_RHL_1</name>
|
|
<description>Read access is not allowed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRTC_HL</name>
|
|
<description>Secure Real Time Counter Hard Lock When set, prevents any writes to the SRTC registers, SRTC_ENV, and SRTC_INV_EN bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRTC_HL_0</name>
|
|
<description>Write access is allowed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRTC_HL_1</name>
|
|
<description>Write access is not allowed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPCALB_HL</name>
|
|
<description>LP Calibration Hard Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPCALB_HL_0</name>
|
|
<description>Write access is allowed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPCALB_HL_1</name>
|
|
<description>Write access is not allowed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC_HL</name>
|
|
<description>Monotonic Counter Hard Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MC_HL_0</name>
|
|
<description>Write access (increment) is allowed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_HL_1</name>
|
|
<description>Write access (increment) is not allowed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPR_HL</name>
|
|
<description>General Purpose Register Hard Lock When set, prevents any writes to the GPR</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPR_HL_0</name>
|
|
<description>Write access is allowed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPR_HL_1</name>
|
|
<description>Write access is not allowed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSVCR_HL</name>
|
|
<description>LP Security Violation Control Register Hard Lock When set, prevents any writes to the LPSVCR</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSVCR_HL_0</name>
|
|
<description>Write access is allowed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSVCR_HL_1</name>
|
|
<description>Write access is not allowed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPTDCR_HL</name>
|
|
<description>LP Tamper Detectors Configuration Register Hard Lock When set, prevents any writes to the LPTDCR</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPTDCR_HL_0</name>
|
|
<description>Write access is allowed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTDCR_HL_1</name>
|
|
<description>Write access is not allowed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MKS_HL</name>
|
|
<description>Master Key Select Hard Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LP Master Key Control Register</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MKS_HL_0</name>
|
|
<description>Write access is allowed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MKS_HL_1</name>
|
|
<description>Write access is not allowed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPCR</name>
|
|
<description>SNVS_LP Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRTC_ENV</name>
|
|
<description>Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRTC_ENV_0</name>
|
|
<description>SRTC is disabled or invalid.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRTC_ENV_1</name>
|
|
<description>SRTC is enabled and valid.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPTA_EN</name>
|
|
<description>LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPTA_EN_0</name>
|
|
<description>LP time alarm interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTA_EN_1</name>
|
|
<description>LP time alarm interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MC_ENV</name>
|
|
<description>Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MC_ENV_0</name>
|
|
<description>MC is disabled or invalid.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MC_ENV_1</name>
|
|
<description>MC is enabled and valid.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPWUI_EN</name>
|
|
<description>LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (tamper event, MC rollover, SRTC rollover, or time alarm )</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SRTC_INV_EN</name>
|
|
<description>If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRTC_INV_EN_0</name>
|
|
<description>SRTC stays valid in the case of security violation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRTC_INV_EN_1</name>
|
|
<description>SRTC is invalidated in the case of security violation.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DP_EN</name>
|
|
<description>Dumb PMIC Enabled When set, software can control the system power</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DP_EN_0</name>
|
|
<description>Smart PMIC enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DP_EN_1</name>
|
|
<description>Dumb PMIC enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOP</name>
|
|
<description>Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOP_0</name>
|
|
<description>Leave system power on.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOP_1</name>
|
|
<description>Turn off system power.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWR_GLITCH_EN</name>
|
|
<description>Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LPCALB_EN</name>
|
|
<description>LP Calibration Enable When set, enables the SRTC calibration mechanism</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPCALB_EN_0</name>
|
|
<description>SRTC Time calibration is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPCALB_EN_1</name>
|
|
<description>SRTC Time calibration is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPCALB_VAL</name>
|
|
<description>LP Calibration Value Defines signed calibration value for SRTC</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPCALB_VAL_0</name>
|
|
<description>+0 counts per each 32768 ticks of the counter clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPCALB_VAL_1</name>
|
|
<description>+1 counts per each 32768 ticks of the counter clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPCALB_VAL_2</name>
|
|
<description>+2 counts per each 32768 ticks of the counter clock</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPCALB_VAL_15</name>
|
|
<description>+15 counts per each 32768 ticks of the counter clock</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPCALB_VAL_16</name>
|
|
<description>-16 counts per each 32768 ticks of the counter clock</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPCALB_VAL_17</name>
|
|
<description>-15 counts per each 32768 ticks of the counter clock</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPCALB_VAL_30</name>
|
|
<description>-2 counts per each 32768 ticks of the counter clock</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPCALB_VAL_31</name>
|
|
<description>-1 counts per each 32768 ticks of the counter clock</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BTN_PRESS_TIME</name>
|
|
<description>This field configures the button press time out values for the PMIC Logic</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBOUNCE</name>
|
|
<description>This field configures the amount of debounce time for the BTN input signal</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ON_TIME</name>
|
|
<description>The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK_EN</name>
|
|
<description>PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PK_OVERRIDE</name>
|
|
<description>PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GPR_Z_DIS</name>
|
|
<description>General Purpose Registers Zeroization Disable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPMKCR</name>
|
|
<description>SNVS_LP Master Key Control Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASTER_KEY_SEL</name>
|
|
<description>Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASTER_KEY_SEL_0</name>
|
|
<description>Select one time programmable master key.</description>
|
|
<value>#0x</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTER_KEY_SEL_2</name>
|
|
<description>Select zeroizable master key when MKS_EN bit is set .</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTER_KEY_SEL_3</name>
|
|
<description>Select combined master key when MKS_EN bit is set .</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZMK_HWP</name>
|
|
<description>Zeroizable Master Key hardware Programming mode When set, only the hardware key programming mechanism can set the ZMK and software cannot read it</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ZMK_HWP_0</name>
|
|
<description>ZMK is in the software programming mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZMK_HWP_1</name>
|
|
<description>ZMK is in the hardware programming mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZMK_VAL</name>
|
|
<description>Zeroizable Master Key Valid When set, the ZMK value can be selected by the master key control block for use by cryptographic modules</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ZMK_VAL_0</name>
|
|
<description>ZMK is not valid.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZMK_VAL_1</name>
|
|
<description>ZMK is valid.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZMK_ECC_EN</name>
|
|
<description>Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ZMK_ECC_EN_0</name>
|
|
<description>ZMK ECC check is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ZMK_ECC_EN_1</name>
|
|
<description>ZMK ECC check is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZMK_ECC_VALUE</name>
|
|
<description>Zeroizable Master Key Error Correcting Code Value This field is automatically calculated and set when one is written into ZMK_ECC_EN bit of this register</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSVCR</name>
|
|
<description>SNVS_LP Security Violation Control Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SV0_EN</name>
|
|
<description>Security Violation 0 Enable This bit enables Security Violation 0 Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV0_EN_0</name>
|
|
<description>Security Violation 0 is disabled in the LP domain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV0_EN_1</name>
|
|
<description>Security Violation 0 is enabled in the LP domain.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV1_EN</name>
|
|
<description>Security Violation 1 Enable This bit enables Security Violation 1 Input</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV1_EN_0</name>
|
|
<description>Security Violation 1 is disabled in the LP domain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV1_EN_1</name>
|
|
<description>Security Violation 1 is enabled in the LP domain.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV2_EN</name>
|
|
<description>Security Violation 2 Enable This bit enables Security Violation 2 Input</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV2_EN_0</name>
|
|
<description>Security Violation 2 is disabled in the LP domain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV2_EN_1</name>
|
|
<description>Security Violation 2 is enabled in the LP domain.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV3_EN</name>
|
|
<description>Security Violation 3 Enable This bit enables Security Violation 3 Input</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV3_EN_0</name>
|
|
<description>Security Violation 3 is disabled in the LP domain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV3_EN_1</name>
|
|
<description>Security Violation 3 is enabled in the LP domain.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV4_EN</name>
|
|
<description>Security Violation 4 Enable This bit enables Security Violation 4 Input</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV4_EN_0</name>
|
|
<description>Security Violation 4 is disabled in the LP domain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV4_EN_1</name>
|
|
<description>Security Violation 4 is enabled in the LP domain.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SV5_EN</name>
|
|
<description>Security Violation 5 Enable This bit enables Security Violation 5 Input</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SV5_EN_0</name>
|
|
<description>Security Violation 5 is disabled in the LP domain.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SV5_EN_1</name>
|
|
<description>Security Violation 5 is enabled in the LP domain.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPTDCR</name>
|
|
<description>SNVS_LP Tamper Detectors Configuration Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRTCR_EN</name>
|
|
<description>SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRTCR_EN_0</name>
|
|
<description>SRTC rollover is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRTCR_EN_1</name>
|
|
<description>SRTC rollover is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MCR_EN</name>
|
|
<description>MC Rollover Enable When set, an MC Rollover event generates an LP security violation.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCR_EN_0</name>
|
|
<description>MC rollover is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCR_EN_1</name>
|
|
<description>MC rollover is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ET1_EN</name>
|
|
<description>External Tampering 1 Enable When set, external tampering 1 detection generates an LP security violation</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ET1_EN_0</name>
|
|
<description>External tamper 1 is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ET1_EN_1</name>
|
|
<description>External tamper 1 is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ET1P</name>
|
|
<description>External Tampering 1 Polarity This bit is used to determine the polarity of external tamper 1.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ET1P_0</name>
|
|
<description>External tamper 1 is active low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ET1P_1</name>
|
|
<description>External tamper 1 is active high.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFD_OBSERV</name>
|
|
<description>System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POR_OBSERV</name>
|
|
<description>Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSCB</name>
|
|
<description>Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OSCB_0</name>
|
|
<description>Normal SRTC clock oscillator not bypassed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSCB_1</name>
|
|
<description>Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSR</name>
|
|
<description>SNVS_LP Status Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPTA</name>
|
|
<description>LP Time Alarm</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPTA_0</name>
|
|
<description>No time alarm interrupt occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPTA_1</name>
|
|
<description>A time alarm interrupt occurred.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRTCR</name>
|
|
<description>Secure Real Time Counter Rollover</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRTCR_0</name>
|
|
<description>SRTC has not reached its maximum value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRTCR_1</name>
|
|
<description>SRTC has reached its maximum value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MCR</name>
|
|
<description>Monotonic Counter Rollover</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MCR_0</name>
|
|
<description>MC has not reached its maximum value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCR_1</name>
|
|
<description>MC has reached its maximum value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PGD</name>
|
|
<description>Power Supply Glitch Detected 0 No power supply glitch. 1 Power supply glitch is detected.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>ET1D</name>
|
|
<description>External Tampering 1 Detected</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ET1D_0</name>
|
|
<description>External tampering 1 not detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ET1D_1</name>
|
|
<description>External tampering 1 detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESVD</name>
|
|
<description>External Security Violation Detected Indicates that a security violation is detected on one of the HP security violation ports</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESVD_0</name>
|
|
<description>No external security violation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESVD_1</name>
|
|
<description>External security violation is detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EO</name>
|
|
<description>Emergency Off This bit is set when a power off is requested.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EO_0</name>
|
|
<description>Emergency off was not detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EO_1</name>
|
|
<description>Emergency off was detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPO</name>
|
|
<description>Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPO_0</name>
|
|
<description>Set Power Off was not detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPO_1</name>
|
|
<description>Set Power Off was detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SED</name>
|
|
<description>Scan Exit Detected</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SED_0</name>
|
|
<description>Scan exit was not detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SED_1</name>
|
|
<description>Scan exit was detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPNS</name>
|
|
<description>LP Section is Non-Secured Indicates that LP section was provisioned/programmed in the non-secure state</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPNS_0</name>
|
|
<description>LP section was not programmed in the non-secure state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPNS_1</name>
|
|
<description>LP section was programmed in the non-secure state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPS</name>
|
|
<description>LP Section is Secured Indicates that the LP section is provisioned/programmed in the secure or trusted state</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPS_0</name>
|
|
<description>LP section was not programmed in secure or trusted state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPS_1</name>
|
|
<description>LP section was programmed in secure or trusted state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSRTCMR</name>
|
|
<description>SNVS_LP Secure Real Time Counter MSB Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRTC</name>
|
|
<description>LP Secure Real Time Counter The most-significant 15 bits of the SRTC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSRTCLR</name>
|
|
<description>SNVS_LP Secure Real Time Counter LSB Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRTC</name>
|
|
<description>LP Secure Real Time Counter least-significant 32 bits This register can be programmed only when SRTC is not active and not locked, meaning the SRTC_ENV, SRTC_SL, and SRTC_HL bits are not set</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPTAR</name>
|
|
<description>SNVS_LP Time Alarm Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPTA</name>
|
|
<description>LP Time Alarm This register can be programmed only when the LP time alarm is disabled (LPTA_EN bit is not set)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSMCMR</name>
|
|
<description>SNVS_LP Secure Monotonic Counter MSB Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MON_COUNTER</name>
|
|
<description>Monotonic Counter most-significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR register is detected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MC_ERA_BITS</name>
|
|
<description>Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSMCLR</name>
|
|
<description>SNVS_LP Secure Monotonic Counter LSB Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MON_COUNTER</name>
|
|
<description>Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR Register is detected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPPGDR</name>
|
|
<description>SNVS_LP Power Glitch Detector Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PGD</name>
|
|
<description>Power Glitch Detector Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPGPR0_legacy_alias</name>
|
|
<description>SNVS_LP General Purpose Register 0 (legacy alias)</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPR</name>
|
|
<description>General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>LPZMKR[%s]</name>
|
|
<description>SNVS_LP Zeroizable Master Key Register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ZMK</name>
|
|
<description>Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>LPGPR_alias[%s]</name>
|
|
<description>SNVS_LP General Purpose Registers 0 .. 3</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPR</name>
|
|
<description>General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>LPGPR[%s]</name>
|
|
<description>SNVS_LP General Purpose Registers 0 .. 3</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPR</name>
|
|
<description>General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPVIDR1</name>
|
|
<description>SNVS_HP Version ID Register 1</description>
|
|
<addressOffset>0xBF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x3E0104</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MINOR_REV</name>
|
|
<description>SNVS block minor version number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR_REV</name>
|
|
<description>SNVS block major version number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IP_ID</name>
|
|
<description>SNVS block ID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPVIDR2</name>
|
|
<description>SNVS_HP Version ID Register 2</description>
|
|
<addressOffset>0xBFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x6000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CONFIG_OPT</name>
|
|
<description>SNVS Configuration Options</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ECO_REV</name>
|
|
<description>SNVS ECO Revision</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INTG_OPT</name>
|
|
<description>SNVS Integration Options</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IP_ERA</name>
|
|
<description>IP Era 00h - Era 1 or 2 03h - Era 3 04h - Era 4 05h - Era 5</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CCM_ANALOG</name>
|
|
<description>CCM_ANALOG</description>
|
|
<groupName>CCM_ANALOG</groupName>
|
|
<prependToName>CCM_ANALOG_</prependToName>
|
|
<baseAddress>0x400D8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x180</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PLL_USB1</name>
|
|
<description>Analog USB1 480MHz PLL Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x12000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SELECT</name>
|
|
<description>This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_USB_CLKS</name>
|
|
<description>Powers the 9-phase PLL outputs for USBPHYn</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN_USB_CLKS_0</name>
|
|
<description>PLL outputs for USBPHYn off.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_USB_CLKS_1</name>
|
|
<description>PLL outputs for USBPHYn on.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POWER</name>
|
|
<description>Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable the PLL clock output.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked. 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_USB1_SET</name>
|
|
<description>Analog USB1 480MHz PLL Control Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x12000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SELECT</name>
|
|
<description>This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_USB_CLKS</name>
|
|
<description>Powers the 9-phase PLL outputs for USBPHYn</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN_USB_CLKS_0</name>
|
|
<description>PLL outputs for USBPHYn off.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_USB_CLKS_1</name>
|
|
<description>PLL outputs for USBPHYn on.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POWER</name>
|
|
<description>Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable the PLL clock output.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked. 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_USB1_CLR</name>
|
|
<description>Analog USB1 480MHz PLL Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x12000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SELECT</name>
|
|
<description>This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_USB_CLKS</name>
|
|
<description>Powers the 9-phase PLL outputs for USBPHYn</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN_USB_CLKS_0</name>
|
|
<description>PLL outputs for USBPHYn off.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_USB_CLKS_1</name>
|
|
<description>PLL outputs for USBPHYn on.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POWER</name>
|
|
<description>Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable the PLL clock output.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked. 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_USB1_TOG</name>
|
|
<description>Analog USB1 480MHz PLL Control Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x12000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SELECT</name>
|
|
<description>This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_USB_CLKS</name>
|
|
<description>Powers the 9-phase PLL outputs for USBPHYn</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN_USB_CLKS_0</name>
|
|
<description>PLL outputs for USBPHYn off.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_USB_CLKS_1</name>
|
|
<description>PLL outputs for USBPHYn on.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POWER</name>
|
|
<description>Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable the PLL clock output.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked. 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_SYS</name>
|
|
<description>Analog System PLL Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x13001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SELECT</name>
|
|
<description>This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>Powers down the PLL.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable PLL output</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked; 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_SYS_SET</name>
|
|
<description>Analog System PLL Control Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x13001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SELECT</name>
|
|
<description>This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>Powers down the PLL.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable PLL output</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked; 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_SYS_CLR</name>
|
|
<description>Analog System PLL Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x13001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SELECT</name>
|
|
<description>This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>Powers down the PLL.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable PLL output</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked; 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_SYS_TOG</name>
|
|
<description>Analog System PLL Control Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x13001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SELECT</name>
|
|
<description>This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>Powers down the PLL.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable PLL output</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked; 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_SYS_SS</name>
|
|
<description>528MHz System PLL Spread Spectrum Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STEP</name>
|
|
<description>Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLE_0</name>
|
|
<description>Spread spectrum modulation disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_1</name>
|
|
<description>Soread spectrum modulation enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_SYS_NUM</name>
|
|
<description>Numerator of 528MHz System PLL Fractional Loop Divider Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>A</name>
|
|
<description>30 bit numerator (A) of fractional loop divider (signed integer).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_SYS_DENOM</name>
|
|
<description>Denominator of 528MHz System PLL Fractional Loop Divider Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x12</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>B</name>
|
|
<description>30 bit denominator (B) of fractional loop divider (unsigned integer).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_AUDIO</name>
|
|
<description>Analog Audio PLL control Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x11006</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SELECT</name>
|
|
<description>This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>Powers down the PLL.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable PLL output</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POST_DIV_SELECT</name>
|
|
<description>These bits implement a divider after the PLL, but before the enable and bypass mux.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POST_DIV_SELECT_0</name>
|
|
<description>Divide by 4.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POST_DIV_SELECT_1</name>
|
|
<description>Divide by 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POST_DIV_SELECT_2</name>
|
|
<description>Divide by 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked. 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_AUDIO_SET</name>
|
|
<description>Analog Audio PLL control Register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x11006</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SELECT</name>
|
|
<description>This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>Powers down the PLL.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable PLL output</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POST_DIV_SELECT</name>
|
|
<description>These bits implement a divider after the PLL, but before the enable and bypass mux.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POST_DIV_SELECT_0</name>
|
|
<description>Divide by 4.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POST_DIV_SELECT_1</name>
|
|
<description>Divide by 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POST_DIV_SELECT_2</name>
|
|
<description>Divide by 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked. 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_AUDIO_CLR</name>
|
|
<description>Analog Audio PLL control Register</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x11006</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SELECT</name>
|
|
<description>This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>Powers down the PLL.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable PLL output</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POST_DIV_SELECT</name>
|
|
<description>These bits implement a divider after the PLL, but before the enable and bypass mux.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POST_DIV_SELECT_0</name>
|
|
<description>Divide by 4.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POST_DIV_SELECT_1</name>
|
|
<description>Divide by 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POST_DIV_SELECT_2</name>
|
|
<description>Divide by 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked. 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_AUDIO_TOG</name>
|
|
<description>Analog Audio PLL control Register</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x11006</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SELECT</name>
|
|
<description>This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>Powers down the PLL.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable PLL output</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POST_DIV_SELECT</name>
|
|
<description>These bits implement a divider after the PLL, but before the enable and bypass mux.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POST_DIV_SELECT_0</name>
|
|
<description>Divide by 4.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POST_DIV_SELECT_1</name>
|
|
<description>Divide by 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POST_DIV_SELECT_2</name>
|
|
<description>Divide by 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked. 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_AUDIO_NUM</name>
|
|
<description>Numerator of Audio PLL Fractional Loop Divider Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5F5E100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>A</name>
|
|
<description>30 bit numerator of fractional loop divider.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_AUDIO_DENOM</name>
|
|
<description>Denominator of Audio PLL Fractional Loop Divider Register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2964619C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>B</name>
|
|
<description>30 bit denominator of fractional loop divider.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_ENET</name>
|
|
<description>Analog ENET PLL Control Register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x11001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>Powers down the PLL.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENET_500M_REF_EN</name>
|
|
<description>Enable the PLL providing ENET 500 MHz reference clock</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked; 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_ENET_SET</name>
|
|
<description>Analog ENET PLL Control Register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x11001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>Powers down the PLL.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENET_500M_REF_EN</name>
|
|
<description>Enable the PLL providing ENET 500 MHz reference clock</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked; 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_ENET_CLR</name>
|
|
<description>Analog ENET PLL Control Register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x11001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>Powers down the PLL.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENET_500M_REF_EN</name>
|
|
<description>Enable the PLL providing ENET 500 MHz reference clock</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked; 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL_ENET_TOG</name>
|
|
<description>Analog ENET PLL Control Register</description>
|
|
<addressOffset>0xEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x11001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POWERDOWN</name>
|
|
<description>Powers down the PLL.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS_CLK_SRC</name>
|
|
<description>Determines the bypass source.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_CLK_24M</name>
|
|
<description>Select the 24MHz oscillator as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass the PLL.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENET_500M_REF_EN</name>
|
|
<description>Enable the PLL providing ENET 500 MHz reference clock</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>1 - PLL is currently locked; 0 - PLL is not currently locked.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFD_480</name>
|
|
<description>480MHz Clock (PLL3) Phase Fractional Divider Control Register</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1311100C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD0_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_CLKGATE</name>
|
|
<description>If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFD_480_SET</name>
|
|
<description>480MHz Clock (PLL3) Phase Fractional Divider Control Register</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1311100C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD0_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_CLKGATE</name>
|
|
<description>If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFD_480_CLR</name>
|
|
<description>480MHz Clock (PLL3) Phase Fractional Divider Control Register</description>
|
|
<addressOffset>0xF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1311100C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD0_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_CLKGATE</name>
|
|
<description>If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFD_480_TOG</name>
|
|
<description>480MHz Clock (PLL3) Phase Fractional Divider Control Register</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1311100C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD0_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_CLKGATE</name>
|
|
<description>If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFD_528</name>
|
|
<description>528MHz Clock (PLL2) Phase Fractional Divider Control Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1018101B</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD0_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_CLKGATE</name>
|
|
<description>If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFD_528_SET</name>
|
|
<description>528MHz Clock (PLL2) Phase Fractional Divider Control Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1018101B</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD0_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_CLKGATE</name>
|
|
<description>If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFD_528_CLR</name>
|
|
<description>528MHz Clock (PLL2) Phase Fractional Divider Control Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1018101B</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD0_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_CLKGATE</name>
|
|
<description>If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFD_528_TOG</name>
|
|
<description>528MHz Clock (PLL2) Phase Fractional Divider Control Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1018101B</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD0_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD0_CLKGATE</name>
|
|
<description>If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD1_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD2_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_FRAC</name>
|
|
<description>This field controls the fractional divide value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_STABLE</name>
|
|
<description>This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD3_CLKGATE</name>
|
|
<description>IO Clock Gate</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC0</name>
|
|
<description>Miscellaneous Register 0</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFTOP_PWD</name>
|
|
<description>Control bit to power-down the analog bandgap reference circuitry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_SELFBIASOFF</name>
|
|
<description>Control bit to disable the self-bias circuit in the analog bandgap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_0</name>
|
|
<description>Uses coarse bias currents for startup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_1</name>
|
|
<description>Uses bandgap-based bias currents for best performance.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGADJ</name>
|
|
<description>Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_0</name>
|
|
<description>Nominal VBG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_1</name>
|
|
<description>VBG+0.78%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_2</name>
|
|
<description>VBG+1.56%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_3</name>
|
|
<description>VBG+2.34%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_4</name>
|
|
<description>VBG-0.78%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_5</name>
|
|
<description>VBG-1.56%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_6</name>
|
|
<description>VBG-2.34%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_7</name>
|
|
<description>VBG-3.12%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGUP</name>
|
|
<description>Status bit that signals the analog bandgap voltage is up and stable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_MODE_CONFIG</name>
|
|
<description>Configure the analog behavior in stop mode.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_0</name>
|
|
<description>All analog except RTC powered down on stop mode assertion.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_1</name>
|
|
<description>Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_2</name>
|
|
<description>Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_3</name>
|
|
<description>Beside RTC, low-power bandgap is selected and the rest analog is powered down.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCON_HIGH_SNVS</name>
|
|
<description>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_0</name>
|
|
<description>Turn on the switch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_1</name>
|
|
<description>Turn off the switch</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_I</name>
|
|
<description>This field determines the bias current in the 24MHz oscillator</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOMINAL</name>
|
|
<description>Nominal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_12_5_PERCENT</name>
|
|
<description>Decrease current by 12.5%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_25_PERCENT</name>
|
|
<description>Decrease current by 25.0%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_37_5_PERCENT</name>
|
|
<description>Decrease current by 37.5%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK</name>
|
|
<description>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK_EN</name>
|
|
<description>This bit enables the detector that signals when the 24MHz crystal oscillator is stable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_CTRL</name>
|
|
<description>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALLOW_AUTO_GATE</name>
|
|
<description>Allow the logic to automatically gate the clock when the XTAL is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_AUTO_GATE</name>
|
|
<description>Prevent the logic from ever gating off the clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_DELAY</name>
|
|
<description>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_0</name>
|
|
<description>0.5ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_1</name>
|
|
<description>1.0ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_2</name>
|
|
<description>2.0ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_3</name>
|
|
<description>3.0ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_4</name>
|
|
<description>4.0ms</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_5</name>
|
|
<description>5.0ms</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_6</name>
|
|
<description>6.0ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_7</name>
|
|
<description>7.0ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_XTAL_SOURCE</name>
|
|
<description>This field indicates which chip source is being used for the rtc clock</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_0</name>
|
|
<description>Internal ring oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_1</name>
|
|
<description>RTC_XTAL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_PWD</name>
|
|
<description>This field powers down the 24M crystal oscillator if set true</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC0_SET</name>
|
|
<description>Miscellaneous Register 0</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFTOP_PWD</name>
|
|
<description>Control bit to power-down the analog bandgap reference circuitry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_SELFBIASOFF</name>
|
|
<description>Control bit to disable the self-bias circuit in the analog bandgap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_0</name>
|
|
<description>Uses coarse bias currents for startup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_1</name>
|
|
<description>Uses bandgap-based bias currents for best performance.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGADJ</name>
|
|
<description>Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_0</name>
|
|
<description>Nominal VBG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_1</name>
|
|
<description>VBG+0.78%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_2</name>
|
|
<description>VBG+1.56%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_3</name>
|
|
<description>VBG+2.34%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_4</name>
|
|
<description>VBG-0.78%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_5</name>
|
|
<description>VBG-1.56%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_6</name>
|
|
<description>VBG-2.34%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_7</name>
|
|
<description>VBG-3.12%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGUP</name>
|
|
<description>Status bit that signals the analog bandgap voltage is up and stable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_MODE_CONFIG</name>
|
|
<description>Configure the analog behavior in stop mode.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_0</name>
|
|
<description>All analog except RTC powered down on stop mode assertion.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_1</name>
|
|
<description>Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_2</name>
|
|
<description>Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_3</name>
|
|
<description>Beside RTC, low-power bandgap is selected and the rest analog is powered down.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCON_HIGH_SNVS</name>
|
|
<description>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_0</name>
|
|
<description>Turn on the switch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_1</name>
|
|
<description>Turn off the switch</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_I</name>
|
|
<description>This field determines the bias current in the 24MHz oscillator</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOMINAL</name>
|
|
<description>Nominal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_12_5_PERCENT</name>
|
|
<description>Decrease current by 12.5%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_25_PERCENT</name>
|
|
<description>Decrease current by 25.0%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_37_5_PERCENT</name>
|
|
<description>Decrease current by 37.5%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK</name>
|
|
<description>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK_EN</name>
|
|
<description>This bit enables the detector that signals when the 24MHz crystal oscillator is stable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_CTRL</name>
|
|
<description>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALLOW_AUTO_GATE</name>
|
|
<description>Allow the logic to automatically gate the clock when the XTAL is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_AUTO_GATE</name>
|
|
<description>Prevent the logic from ever gating off the clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_DELAY</name>
|
|
<description>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_0</name>
|
|
<description>0.5ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_1</name>
|
|
<description>1.0ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_2</name>
|
|
<description>2.0ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_3</name>
|
|
<description>3.0ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_4</name>
|
|
<description>4.0ms</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_5</name>
|
|
<description>5.0ms</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_6</name>
|
|
<description>6.0ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_7</name>
|
|
<description>7.0ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_XTAL_SOURCE</name>
|
|
<description>This field indicates which chip source is being used for the rtc clock</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_0</name>
|
|
<description>Internal ring oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_1</name>
|
|
<description>RTC_XTAL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_PWD</name>
|
|
<description>This field powers down the 24M crystal oscillator if set true</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC0_CLR</name>
|
|
<description>Miscellaneous Register 0</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFTOP_PWD</name>
|
|
<description>Control bit to power-down the analog bandgap reference circuitry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_SELFBIASOFF</name>
|
|
<description>Control bit to disable the self-bias circuit in the analog bandgap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_0</name>
|
|
<description>Uses coarse bias currents for startup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_1</name>
|
|
<description>Uses bandgap-based bias currents for best performance.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGADJ</name>
|
|
<description>Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_0</name>
|
|
<description>Nominal VBG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_1</name>
|
|
<description>VBG+0.78%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_2</name>
|
|
<description>VBG+1.56%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_3</name>
|
|
<description>VBG+2.34%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_4</name>
|
|
<description>VBG-0.78%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_5</name>
|
|
<description>VBG-1.56%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_6</name>
|
|
<description>VBG-2.34%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_7</name>
|
|
<description>VBG-3.12%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGUP</name>
|
|
<description>Status bit that signals the analog bandgap voltage is up and stable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_MODE_CONFIG</name>
|
|
<description>Configure the analog behavior in stop mode.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_0</name>
|
|
<description>All analog except RTC powered down on stop mode assertion.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_1</name>
|
|
<description>Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_2</name>
|
|
<description>Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_3</name>
|
|
<description>Beside RTC, low-power bandgap is selected and the rest analog is powered down.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCON_HIGH_SNVS</name>
|
|
<description>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_0</name>
|
|
<description>Turn on the switch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_1</name>
|
|
<description>Turn off the switch</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_I</name>
|
|
<description>This field determines the bias current in the 24MHz oscillator</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOMINAL</name>
|
|
<description>Nominal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_12_5_PERCENT</name>
|
|
<description>Decrease current by 12.5%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_25_PERCENT</name>
|
|
<description>Decrease current by 25.0%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_37_5_PERCENT</name>
|
|
<description>Decrease current by 37.5%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK</name>
|
|
<description>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK_EN</name>
|
|
<description>This bit enables the detector that signals when the 24MHz crystal oscillator is stable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_CTRL</name>
|
|
<description>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALLOW_AUTO_GATE</name>
|
|
<description>Allow the logic to automatically gate the clock when the XTAL is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_AUTO_GATE</name>
|
|
<description>Prevent the logic from ever gating off the clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_DELAY</name>
|
|
<description>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_0</name>
|
|
<description>0.5ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_1</name>
|
|
<description>1.0ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_2</name>
|
|
<description>2.0ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_3</name>
|
|
<description>3.0ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_4</name>
|
|
<description>4.0ms</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_5</name>
|
|
<description>5.0ms</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_6</name>
|
|
<description>6.0ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_7</name>
|
|
<description>7.0ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_XTAL_SOURCE</name>
|
|
<description>This field indicates which chip source is being used for the rtc clock</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_0</name>
|
|
<description>Internal ring oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_1</name>
|
|
<description>RTC_XTAL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_PWD</name>
|
|
<description>This field powers down the 24M crystal oscillator if set true</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC0_TOG</name>
|
|
<description>Miscellaneous Register 0</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFTOP_PWD</name>
|
|
<description>Control bit to power-down the analog bandgap reference circuitry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_SELFBIASOFF</name>
|
|
<description>Control bit to disable the self-bias circuit in the analog bandgap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_0</name>
|
|
<description>Uses coarse bias currents for startup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_1</name>
|
|
<description>Uses bandgap-based bias currents for best performance.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGADJ</name>
|
|
<description>Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_0</name>
|
|
<description>Nominal VBG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_1</name>
|
|
<description>VBG+0.78%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_2</name>
|
|
<description>VBG+1.56%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_3</name>
|
|
<description>VBG+2.34%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_4</name>
|
|
<description>VBG-0.78%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_5</name>
|
|
<description>VBG-1.56%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_6</name>
|
|
<description>VBG-2.34%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_7</name>
|
|
<description>VBG-3.12%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGUP</name>
|
|
<description>Status bit that signals the analog bandgap voltage is up and stable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_MODE_CONFIG</name>
|
|
<description>Configure the analog behavior in stop mode.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_0</name>
|
|
<description>All analog except RTC powered down on stop mode assertion.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_1</name>
|
|
<description>Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_2</name>
|
|
<description>Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_3</name>
|
|
<description>Beside RTC, low-power bandgap is selected and the rest analog is powered down.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCON_HIGH_SNVS</name>
|
|
<description>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_0</name>
|
|
<description>Turn on the switch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_1</name>
|
|
<description>Turn off the switch</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_I</name>
|
|
<description>This field determines the bias current in the 24MHz oscillator</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOMINAL</name>
|
|
<description>Nominal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_12_5_PERCENT</name>
|
|
<description>Decrease current by 12.5%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_25_PERCENT</name>
|
|
<description>Decrease current by 25.0%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_37_5_PERCENT</name>
|
|
<description>Decrease current by 37.5%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK</name>
|
|
<description>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK_EN</name>
|
|
<description>This bit enables the detector that signals when the 24MHz crystal oscillator is stable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_CTRL</name>
|
|
<description>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALLOW_AUTO_GATE</name>
|
|
<description>Allow the logic to automatically gate the clock when the XTAL is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_AUTO_GATE</name>
|
|
<description>Prevent the logic from ever gating off the clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_DELAY</name>
|
|
<description>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_0</name>
|
|
<description>0.5ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_1</name>
|
|
<description>1.0ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_2</name>
|
|
<description>2.0ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_3</name>
|
|
<description>3.0ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_4</name>
|
|
<description>4.0ms</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_5</name>
|
|
<description>5.0ms</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_6</name>
|
|
<description>6.0ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_7</name>
|
|
<description>7.0ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_XTAL_SOURCE</name>
|
|
<description>This field indicates which chip source is being used for the rtc clock</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_0</name>
|
|
<description>Internal ring oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_1</name>
|
|
<description>RTC_XTAL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_PWD</name>
|
|
<description>This field powers down the 24M crystal oscillator if set true</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC1</name>
|
|
<description>Miscellaneous Register 1</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD_480_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD_528_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPPANIC</name>
|
|
<description>This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPLOW</name>
|
|
<description>This status bit is set to one when the temperature sensor low interrupt asserts for low temperature</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPHIGH</name>
|
|
<description>This status bit is set to one when the temperature sensor high interrupt asserts for high temperature</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_ANA_BO</name>
|
|
<description>This status bit is set to one when when any of the analog regulator brownout interrupts assert</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_DIG_BO</name>
|
|
<description>This status bit is set to one when when any of the digital regulator brownout interrupts assert</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC1_SET</name>
|
|
<description>Miscellaneous Register 1</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD_480_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD_528_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPPANIC</name>
|
|
<description>This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPLOW</name>
|
|
<description>This status bit is set to one when the temperature sensor low interrupt asserts for low temperature</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPHIGH</name>
|
|
<description>This status bit is set to one when the temperature sensor high interrupt asserts for high temperature</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_ANA_BO</name>
|
|
<description>This status bit is set to one when when any of the analog regulator brownout interrupts assert</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_DIG_BO</name>
|
|
<description>This status bit is set to one when when any of the digital regulator brownout interrupts assert</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC1_CLR</name>
|
|
<description>Miscellaneous Register 1</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD_480_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD_528_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPPANIC</name>
|
|
<description>This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPLOW</name>
|
|
<description>This status bit is set to one when the temperature sensor low interrupt asserts for low temperature</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPHIGH</name>
|
|
<description>This status bit is set to one when the temperature sensor high interrupt asserts for high temperature</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_ANA_BO</name>
|
|
<description>This status bit is set to one when when any of the analog regulator brownout interrupts assert</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_DIG_BO</name>
|
|
<description>This status bit is set to one when when any of the digital regulator brownout interrupts assert</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC1_TOG</name>
|
|
<description>Miscellaneous Register 1</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD_480_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD_528_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPPANIC</name>
|
|
<description>This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPLOW</name>
|
|
<description>This status bit is set to one when the temperature sensor low interrupt asserts for low temperature</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPHIGH</name>
|
|
<description>This status bit is set to one when the temperature sensor high interrupt asserts for high temperature</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_ANA_BO</name>
|
|
<description>This status bit is set to one when when any of the analog regulator brownout interrupts assert</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_DIG_BO</name>
|
|
<description>This status bit is set to one when when any of the digital regulator brownout interrupts assert</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC2</name>
|
|
<description>Miscellaneous Register 2</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x272727</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG0_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the CORE power domain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_BO_STATUS</name>
|
|
<description>Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG0_OK</name>
|
|
<description>ARM supply Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLL3_DISABLE</name>
|
|
<description>When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLL3_DISABLE_0</name>
|
|
<description>PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL3_DISABLE_1</name>
|
|
<description>PLL3 can be disabled when the SoC is not in any low power mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_STATUS</name>
|
|
<description>Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG1_OK</name>
|
|
<description>GPU supply Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_LSB</name>
|
|
<description>LSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_STATUS</name>
|
|
<description>Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_OK</name>
|
|
<description>Signals that the voltage is above the brownout level for the SOC supply</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_MSB</name>
|
|
<description>MSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC2_SET</name>
|
|
<description>Miscellaneous Register 2</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x272727</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG0_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the CORE power domain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_BO_STATUS</name>
|
|
<description>Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG0_OK</name>
|
|
<description>ARM supply Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLL3_DISABLE</name>
|
|
<description>When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLL3_DISABLE_0</name>
|
|
<description>PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL3_DISABLE_1</name>
|
|
<description>PLL3 can be disabled when the SoC is not in any low power mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_STATUS</name>
|
|
<description>Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG1_OK</name>
|
|
<description>GPU supply Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_LSB</name>
|
|
<description>LSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_STATUS</name>
|
|
<description>Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_OK</name>
|
|
<description>Signals that the voltage is above the brownout level for the SOC supply</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_MSB</name>
|
|
<description>MSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC2_CLR</name>
|
|
<description>Miscellaneous Register 2</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x272727</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG0_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the CORE power domain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_BO_STATUS</name>
|
|
<description>Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG0_OK</name>
|
|
<description>ARM supply Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLL3_DISABLE</name>
|
|
<description>When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLL3_DISABLE_0</name>
|
|
<description>PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL3_DISABLE_1</name>
|
|
<description>PLL3 can be disabled when the SoC is not in any low power mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_STATUS</name>
|
|
<description>Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG1_OK</name>
|
|
<description>GPU supply Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_LSB</name>
|
|
<description>LSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_STATUS</name>
|
|
<description>Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_OK</name>
|
|
<description>Signals that the voltage is above the brownout level for the SOC supply</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_MSB</name>
|
|
<description>MSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC2_TOG</name>
|
|
<description>Miscellaneous Register 2</description>
|
|
<addressOffset>0x17C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x272727</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG0_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the CORE power domain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_BO_STATUS</name>
|
|
<description>Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG0_OK</name>
|
|
<description>ARM supply Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLL3_DISABLE</name>
|
|
<description>When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLL3_DISABLE_0</name>
|
|
<description>PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL3_DISABLE_1</name>
|
|
<description>PLL3 can be disabled when the SoC is not in any low power mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_STATUS</name>
|
|
<description>Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG1_OK</name>
|
|
<description>GPU supply Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_LSB</name>
|
|
<description>LSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_STATUS</name>
|
|
<description>Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_OK</name>
|
|
<description>Signals that the voltage is above the brownout level for the SOC supply</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_MSB</name>
|
|
<description>MSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMU</name>
|
|
<description>PMU</description>
|
|
<alternatePeripheral>CCM_ANALOG</alternatePeripheral>
|
|
<groupName>PMU</groupName>
|
|
<prependToName>PMU_</prependToName>
|
|
<baseAddress>0x400D8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x180</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PMU</name>
|
|
<value>61</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>REG_1P1</name>
|
|
<description>Regulator 1P1 Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1073</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_LINREG</name>
|
|
<description>Control bit to enable the regulator output.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BO</name>
|
|
<description>Control bit to enable the brownout circuitry in the regulator.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_ILIMIT</name>
|
|
<description>Control bit to enable the current-limit circuitry in the regulator.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_PULLDOWN</name>
|
|
<description>Control bit to enable the pull-down circuitry in the regulator</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BO_OFFSET</name>
|
|
<description>Control bits to adjust the regulator brownout offset voltage in 25mV steps</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_TRG</name>
|
|
<description>Control bits to adjust the regulator output voltage</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_4</name>
|
|
<description>0.8V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_16</name>
|
|
<description>1.1V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BO_VDD1P1</name>
|
|
<description>Status bit that signals when a brownout is detected on the regulator output.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OK_VDD1P1</name>
|
|
<description>Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_WEAK_LINREG</name>
|
|
<description>Enables the weak 1p1 regulator</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SELREF_WEAK_LINREG</name>
|
|
<description>Selects the source for the reference voltage of the weak 1p1 regulator.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SELREF_WEAK_LINREG_0</name>
|
|
<description>Weak-linreg output tracks low-power-bandgap voltage</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELREF_WEAK_LINREG_1</name>
|
|
<description>Weak-linreg output tracks VDD_SOC_IN voltage</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_1P1_SET</name>
|
|
<description>Regulator 1P1 Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1073</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_LINREG</name>
|
|
<description>Control bit to enable the regulator output.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BO</name>
|
|
<description>Control bit to enable the brownout circuitry in the regulator.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_ILIMIT</name>
|
|
<description>Control bit to enable the current-limit circuitry in the regulator.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_PULLDOWN</name>
|
|
<description>Control bit to enable the pull-down circuitry in the regulator</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BO_OFFSET</name>
|
|
<description>Control bits to adjust the regulator brownout offset voltage in 25mV steps</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_TRG</name>
|
|
<description>Control bits to adjust the regulator output voltage</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_4</name>
|
|
<description>0.8V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_16</name>
|
|
<description>1.1V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BO_VDD1P1</name>
|
|
<description>Status bit that signals when a brownout is detected on the regulator output.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OK_VDD1P1</name>
|
|
<description>Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_WEAK_LINREG</name>
|
|
<description>Enables the weak 1p1 regulator</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SELREF_WEAK_LINREG</name>
|
|
<description>Selects the source for the reference voltage of the weak 1p1 regulator.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SELREF_WEAK_LINREG_0</name>
|
|
<description>Weak-linreg output tracks low-power-bandgap voltage</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELREF_WEAK_LINREG_1</name>
|
|
<description>Weak-linreg output tracks VDD_SOC_IN voltage</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_1P1_CLR</name>
|
|
<description>Regulator 1P1 Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1073</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_LINREG</name>
|
|
<description>Control bit to enable the regulator output.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BO</name>
|
|
<description>Control bit to enable the brownout circuitry in the regulator.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_ILIMIT</name>
|
|
<description>Control bit to enable the current-limit circuitry in the regulator.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_PULLDOWN</name>
|
|
<description>Control bit to enable the pull-down circuitry in the regulator</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BO_OFFSET</name>
|
|
<description>Control bits to adjust the regulator brownout offset voltage in 25mV steps</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_TRG</name>
|
|
<description>Control bits to adjust the regulator output voltage</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_4</name>
|
|
<description>0.8V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_16</name>
|
|
<description>1.1V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BO_VDD1P1</name>
|
|
<description>Status bit that signals when a brownout is detected on the regulator output.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OK_VDD1P1</name>
|
|
<description>Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_WEAK_LINREG</name>
|
|
<description>Enables the weak 1p1 regulator</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SELREF_WEAK_LINREG</name>
|
|
<description>Selects the source for the reference voltage of the weak 1p1 regulator.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SELREF_WEAK_LINREG_0</name>
|
|
<description>Weak-linreg output tracks low-power-bandgap voltage</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELREF_WEAK_LINREG_1</name>
|
|
<description>Weak-linreg output tracks VDD_SOC_IN voltage</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_1P1_TOG</name>
|
|
<description>Regulator 1P1 Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1073</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_LINREG</name>
|
|
<description>Control bit to enable the regulator output.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BO</name>
|
|
<description>Control bit to enable the brownout circuitry in the regulator.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_ILIMIT</name>
|
|
<description>Control bit to enable the current-limit circuitry in the regulator.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_PULLDOWN</name>
|
|
<description>Control bit to enable the pull-down circuitry in the regulator</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BO_OFFSET</name>
|
|
<description>Control bits to adjust the regulator brownout offset voltage in 25mV steps</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_TRG</name>
|
|
<description>Control bits to adjust the regulator output voltage</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_4</name>
|
|
<description>0.8V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_16</name>
|
|
<description>1.1V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BO_VDD1P1</name>
|
|
<description>Status bit that signals when a brownout is detected on the regulator output.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OK_VDD1P1</name>
|
|
<description>Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_WEAK_LINREG</name>
|
|
<description>Enables the weak 1p1 regulator</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SELREF_WEAK_LINREG</name>
|
|
<description>Selects the source for the reference voltage of the weak 1p1 regulator.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SELREF_WEAK_LINREG_0</name>
|
|
<description>Weak-linreg output tracks low-power-bandgap voltage</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELREF_WEAK_LINREG_1</name>
|
|
<description>Weak-linreg output tracks VDD_SOC_IN voltage</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_3P0</name>
|
|
<description>Regulator 3P0 Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF74</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_LINREG</name>
|
|
<description>Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BO</name>
|
|
<description>Control bit to enable the brownout circuitry in the regulator.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_ILIMIT</name>
|
|
<description>Control bit to enable the current-limit circuitry in the regulator.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BO_OFFSET</name>
|
|
<description>Control bits to adjust the regulator brownout offset voltage in 25mV steps</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VBUS_SEL</name>
|
|
<description>Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_OTG2_VBUS</name>
|
|
<description>Utilize VBUS OTG2 power</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_OTG1_VBUS</name>
|
|
<description>Utilize VBUS OTG1 power</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_TRG</name>
|
|
<description>Control bits to adjust the regulator output voltage</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_0</name>
|
|
<description>2.625V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_15</name>
|
|
<description>3.000V</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_31</name>
|
|
<description>3.400V</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BO_VDD3P0</name>
|
|
<description>Status bit that signals when a brownout is detected on the regulator output.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OK_VDD3P0</name>
|
|
<description>Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_3P0_SET</name>
|
|
<description>Regulator 3P0 Register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF74</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_LINREG</name>
|
|
<description>Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BO</name>
|
|
<description>Control bit to enable the brownout circuitry in the regulator.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_ILIMIT</name>
|
|
<description>Control bit to enable the current-limit circuitry in the regulator.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BO_OFFSET</name>
|
|
<description>Control bits to adjust the regulator brownout offset voltage in 25mV steps</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VBUS_SEL</name>
|
|
<description>Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_OTG2_VBUS</name>
|
|
<description>Utilize VBUS OTG2 power</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_OTG1_VBUS</name>
|
|
<description>Utilize VBUS OTG1 power</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_TRG</name>
|
|
<description>Control bits to adjust the regulator output voltage</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_0</name>
|
|
<description>2.625V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_15</name>
|
|
<description>3.000V</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_31</name>
|
|
<description>3.400V</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BO_VDD3P0</name>
|
|
<description>Status bit that signals when a brownout is detected on the regulator output.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OK_VDD3P0</name>
|
|
<description>Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_3P0_CLR</name>
|
|
<description>Regulator 3P0 Register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF74</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_LINREG</name>
|
|
<description>Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BO</name>
|
|
<description>Control bit to enable the brownout circuitry in the regulator.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_ILIMIT</name>
|
|
<description>Control bit to enable the current-limit circuitry in the regulator.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BO_OFFSET</name>
|
|
<description>Control bits to adjust the regulator brownout offset voltage in 25mV steps</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VBUS_SEL</name>
|
|
<description>Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_OTG2_VBUS</name>
|
|
<description>Utilize VBUS OTG2 power</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_OTG1_VBUS</name>
|
|
<description>Utilize VBUS OTG1 power</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_TRG</name>
|
|
<description>Control bits to adjust the regulator output voltage</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_0</name>
|
|
<description>2.625V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_15</name>
|
|
<description>3.000V</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_31</name>
|
|
<description>3.400V</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BO_VDD3P0</name>
|
|
<description>Status bit that signals when a brownout is detected on the regulator output.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OK_VDD3P0</name>
|
|
<description>Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_3P0_TOG</name>
|
|
<description>Regulator 3P0 Register</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF74</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_LINREG</name>
|
|
<description>Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BO</name>
|
|
<description>Control bit to enable the brownout circuitry in the regulator.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_ILIMIT</name>
|
|
<description>Control bit to enable the current-limit circuitry in the regulator.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BO_OFFSET</name>
|
|
<description>Control bits to adjust the regulator brownout offset voltage in 25mV steps</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VBUS_SEL</name>
|
|
<description>Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USB_OTG2_VBUS</name>
|
|
<description>Utilize VBUS OTG2 power</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USB_OTG1_VBUS</name>
|
|
<description>Utilize VBUS OTG1 power</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_TRG</name>
|
|
<description>Control bits to adjust the regulator output voltage</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_0</name>
|
|
<description>2.625V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_15</name>
|
|
<description>3.000V</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_31</name>
|
|
<description>3.400V</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BO_VDD3P0</name>
|
|
<description>Status bit that signals when a brownout is detected on the regulator output.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OK_VDD3P0</name>
|
|
<description>Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_2P5</name>
|
|
<description>Regulator 2P5 Register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1073</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_LINREG</name>
|
|
<description>Control bit to enable the regulator output.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BO</name>
|
|
<description>Control bit to enable the brownout circuitry in the regulator.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_ILIMIT</name>
|
|
<description>Control bit to enable the current-limit circuitry in the regulator.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_PULLDOWN</name>
|
|
<description>Control bit to enable the pull-down circuitry in the regulator</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BO_OFFSET</name>
|
|
<description>Control bits to adjust the regulator brownout offset voltage in 25mV steps</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_TRG</name>
|
|
<description>Control bits to adjust the regulator output voltage</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_0</name>
|
|
<description>2.10V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_16</name>
|
|
<description>2.50V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_31</name>
|
|
<description>2.875V</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BO_VDD2P5</name>
|
|
<description>Status bit that signals when a brownout is detected on the regulator output.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OK_VDD2P5</name>
|
|
<description>Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_WEAK_LINREG</name>
|
|
<description>Enables the weak 2p5 regulator</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_2P5_SET</name>
|
|
<description>Regulator 2P5 Register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1073</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_LINREG</name>
|
|
<description>Control bit to enable the regulator output.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BO</name>
|
|
<description>Control bit to enable the brownout circuitry in the regulator.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_ILIMIT</name>
|
|
<description>Control bit to enable the current-limit circuitry in the regulator.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_PULLDOWN</name>
|
|
<description>Control bit to enable the pull-down circuitry in the regulator</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BO_OFFSET</name>
|
|
<description>Control bits to adjust the regulator brownout offset voltage in 25mV steps</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_TRG</name>
|
|
<description>Control bits to adjust the regulator output voltage</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_0</name>
|
|
<description>2.10V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_16</name>
|
|
<description>2.50V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_31</name>
|
|
<description>2.875V</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BO_VDD2P5</name>
|
|
<description>Status bit that signals when a brownout is detected on the regulator output.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OK_VDD2P5</name>
|
|
<description>Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_WEAK_LINREG</name>
|
|
<description>Enables the weak 2p5 regulator</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_2P5_CLR</name>
|
|
<description>Regulator 2P5 Register</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1073</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_LINREG</name>
|
|
<description>Control bit to enable the regulator output.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BO</name>
|
|
<description>Control bit to enable the brownout circuitry in the regulator.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_ILIMIT</name>
|
|
<description>Control bit to enable the current-limit circuitry in the regulator.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_PULLDOWN</name>
|
|
<description>Control bit to enable the pull-down circuitry in the regulator</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BO_OFFSET</name>
|
|
<description>Control bits to adjust the regulator brownout offset voltage in 25mV steps</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_TRG</name>
|
|
<description>Control bits to adjust the regulator output voltage</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_0</name>
|
|
<description>2.10V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_16</name>
|
|
<description>2.50V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_31</name>
|
|
<description>2.875V</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BO_VDD2P5</name>
|
|
<description>Status bit that signals when a brownout is detected on the regulator output.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OK_VDD2P5</name>
|
|
<description>Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_WEAK_LINREG</name>
|
|
<description>Enables the weak 2p5 regulator</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_2P5_TOG</name>
|
|
<description>Regulator 2P5 Register</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1073</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_LINREG</name>
|
|
<description>Control bit to enable the regulator output.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BO</name>
|
|
<description>Control bit to enable the brownout circuitry in the regulator.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_ILIMIT</name>
|
|
<description>Control bit to enable the current-limit circuitry in the regulator.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_PULLDOWN</name>
|
|
<description>Control bit to enable the pull-down circuitry in the regulator</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BO_OFFSET</name>
|
|
<description>Control bits to adjust the regulator brownout offset voltage in 25mV steps</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_TRG</name>
|
|
<description>Control bits to adjust the regulator output voltage</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_0</name>
|
|
<description>2.10V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_16</name>
|
|
<description>2.50V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TRG_31</name>
|
|
<description>2.875V</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BO_VDD2P5</name>
|
|
<description>Status bit that signals when a brownout is detected on the regulator output.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OK_VDD2P5</name>
|
|
<description>Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_WEAK_LINREG</name>
|
|
<description>Enables the weak 2p5 regulator</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_CORE</name>
|
|
<description>Digital Regulator Core Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x482012</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG0_TARG</name>
|
|
<description>This field defines the target voltage for the ARM core power domain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_0</name>
|
|
<description>Power gated off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_1</name>
|
|
<description>Target core voltage = 0.725V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_2</name>
|
|
<description>Target core voltage = 0.750V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_3</name>
|
|
<description>Target core voltage = 0.775V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_16</name>
|
|
<description>Target core voltage = 1.100V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_30</name>
|
|
<description>Target core voltage = 1.450V</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_31</name>
|
|
<description>Power FET switched full on. No regulation.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_ADJ</name>
|
|
<description>This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_0</name>
|
|
<description>No adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_1</name>
|
|
<description>+ 0.25%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_2</name>
|
|
<description>+ 0.50%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_3</name>
|
|
<description>+ 0.75%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_4</name>
|
|
<description>+ 1.00%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_5</name>
|
|
<description>+ 1.25%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_6</name>
|
|
<description>+ 1.50%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_7</name>
|
|
<description>+ 1.75%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_8</name>
|
|
<description>- 0.25%</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_9</name>
|
|
<description>- 0.50%</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_10</name>
|
|
<description>- 0.75%</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_11</name>
|
|
<description>- 1.00%</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_12</name>
|
|
<description>- 1.25%</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_13</name>
|
|
<description>- 1.50%</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_14</name>
|
|
<description>- 1.75%</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_15</name>
|
|
<description>- 2.00%</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_TARG</name>
|
|
<description>This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_0</name>
|
|
<description>Power gated off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_1</name>
|
|
<description>Target core voltage = 0.725V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_2</name>
|
|
<description>Target core voltage = 0.750V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_3</name>
|
|
<description>Target core voltage = 0.775V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_16</name>
|
|
<description>Target core voltage = 1.100V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_30</name>
|
|
<description>Target core voltage = 1.450V</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_31</name>
|
|
<description>Power FET switched full on. No regulation.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_ADJ</name>
|
|
<description>This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_0</name>
|
|
<description>No adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_1</name>
|
|
<description>+ 0.25%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_2</name>
|
|
<description>+ 0.50%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_3</name>
|
|
<description>+ 0.75%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_4</name>
|
|
<description>+ 1.00%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_5</name>
|
|
<description>+ 1.25%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_6</name>
|
|
<description>+ 1.50%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_7</name>
|
|
<description>+ 1.75%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_8</name>
|
|
<description>- 0.25%</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_9</name>
|
|
<description>- 0.50%</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_10</name>
|
|
<description>- 0.75%</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_11</name>
|
|
<description>- 1.00%</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_12</name>
|
|
<description>- 1.25%</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_13</name>
|
|
<description>- 1.50%</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_14</name>
|
|
<description>- 1.75%</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_15</name>
|
|
<description>- 2.00%</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_TARG</name>
|
|
<description>This field defines the target voltage for the SOC power domain</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_0</name>
|
|
<description>Power gated off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_1</name>
|
|
<description>Target core voltage = 0.725V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_2</name>
|
|
<description>Target core voltage = 0.750V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_3</name>
|
|
<description>Target core voltage = 0.775V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_16</name>
|
|
<description>Target core voltage = 1.100V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_30</name>
|
|
<description>Target core voltage = 1.450V</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_31</name>
|
|
<description>Power FET switched full on. No regulation.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_ADJ</name>
|
|
<description>This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_0</name>
|
|
<description>No adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_1</name>
|
|
<description>+ 0.25%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_2</name>
|
|
<description>+ 0.50%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_3</name>
|
|
<description>+ 0.75%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_4</name>
|
|
<description>+ 1.00%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_5</name>
|
|
<description>+ 1.25%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_6</name>
|
|
<description>+ 1.50%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_7</name>
|
|
<description>+ 1.75%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_8</name>
|
|
<description>- 0.25%</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_9</name>
|
|
<description>- 0.50%</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_10</name>
|
|
<description>- 0.75%</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_11</name>
|
|
<description>- 1.00%</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_12</name>
|
|
<description>- 1.25%</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_13</name>
|
|
<description>- 1.50%</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_14</name>
|
|
<description>- 1.75%</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_15</name>
|
|
<description>- 2.00%</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAMP_RATE</name>
|
|
<description>Regulator voltage ramp rate.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_0</name>
|
|
<description>Fast</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_1</name>
|
|
<description>Medium Fast</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_2</name>
|
|
<description>Medium Slow</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_3</name>
|
|
<description>Slow</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FET_ODRIVE</name>
|
|
<description>If set, increases the gate drive on power gating FETs to reduce leakage in the off state</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_CORE_SET</name>
|
|
<description>Digital Regulator Core Register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x482012</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG0_TARG</name>
|
|
<description>This field defines the target voltage for the ARM core power domain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_0</name>
|
|
<description>Power gated off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_1</name>
|
|
<description>Target core voltage = 0.725V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_2</name>
|
|
<description>Target core voltage = 0.750V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_3</name>
|
|
<description>Target core voltage = 0.775V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_16</name>
|
|
<description>Target core voltage = 1.100V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_30</name>
|
|
<description>Target core voltage = 1.450V</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_31</name>
|
|
<description>Power FET switched full on. No regulation.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_ADJ</name>
|
|
<description>This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_0</name>
|
|
<description>No adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_1</name>
|
|
<description>+ 0.25%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_2</name>
|
|
<description>+ 0.50%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_3</name>
|
|
<description>+ 0.75%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_4</name>
|
|
<description>+ 1.00%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_5</name>
|
|
<description>+ 1.25%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_6</name>
|
|
<description>+ 1.50%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_7</name>
|
|
<description>+ 1.75%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_8</name>
|
|
<description>- 0.25%</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_9</name>
|
|
<description>- 0.50%</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_10</name>
|
|
<description>- 0.75%</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_11</name>
|
|
<description>- 1.00%</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_12</name>
|
|
<description>- 1.25%</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_13</name>
|
|
<description>- 1.50%</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_14</name>
|
|
<description>- 1.75%</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_15</name>
|
|
<description>- 2.00%</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_TARG</name>
|
|
<description>This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_0</name>
|
|
<description>Power gated off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_1</name>
|
|
<description>Target core voltage = 0.725V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_2</name>
|
|
<description>Target core voltage = 0.750V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_3</name>
|
|
<description>Target core voltage = 0.775V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_16</name>
|
|
<description>Target core voltage = 1.100V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_30</name>
|
|
<description>Target core voltage = 1.450V</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_31</name>
|
|
<description>Power FET switched full on. No regulation.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_ADJ</name>
|
|
<description>This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_0</name>
|
|
<description>No adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_1</name>
|
|
<description>+ 0.25%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_2</name>
|
|
<description>+ 0.50%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_3</name>
|
|
<description>+ 0.75%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_4</name>
|
|
<description>+ 1.00%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_5</name>
|
|
<description>+ 1.25%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_6</name>
|
|
<description>+ 1.50%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_7</name>
|
|
<description>+ 1.75%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_8</name>
|
|
<description>- 0.25%</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_9</name>
|
|
<description>- 0.50%</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_10</name>
|
|
<description>- 0.75%</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_11</name>
|
|
<description>- 1.00%</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_12</name>
|
|
<description>- 1.25%</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_13</name>
|
|
<description>- 1.50%</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_14</name>
|
|
<description>- 1.75%</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_15</name>
|
|
<description>- 2.00%</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_TARG</name>
|
|
<description>This field defines the target voltage for the SOC power domain</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_0</name>
|
|
<description>Power gated off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_1</name>
|
|
<description>Target core voltage = 0.725V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_2</name>
|
|
<description>Target core voltage = 0.750V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_3</name>
|
|
<description>Target core voltage = 0.775V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_16</name>
|
|
<description>Target core voltage = 1.100V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_30</name>
|
|
<description>Target core voltage = 1.450V</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_31</name>
|
|
<description>Power FET switched full on. No regulation.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_ADJ</name>
|
|
<description>This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_0</name>
|
|
<description>No adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_1</name>
|
|
<description>+ 0.25%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_2</name>
|
|
<description>+ 0.50%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_3</name>
|
|
<description>+ 0.75%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_4</name>
|
|
<description>+ 1.00%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_5</name>
|
|
<description>+ 1.25%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_6</name>
|
|
<description>+ 1.50%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_7</name>
|
|
<description>+ 1.75%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_8</name>
|
|
<description>- 0.25%</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_9</name>
|
|
<description>- 0.50%</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_10</name>
|
|
<description>- 0.75%</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_11</name>
|
|
<description>- 1.00%</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_12</name>
|
|
<description>- 1.25%</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_13</name>
|
|
<description>- 1.50%</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_14</name>
|
|
<description>- 1.75%</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_15</name>
|
|
<description>- 2.00%</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAMP_RATE</name>
|
|
<description>Regulator voltage ramp rate.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_0</name>
|
|
<description>Fast</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_1</name>
|
|
<description>Medium Fast</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_2</name>
|
|
<description>Medium Slow</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_3</name>
|
|
<description>Slow</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FET_ODRIVE</name>
|
|
<description>If set, increases the gate drive on power gating FETs to reduce leakage in the off state</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_CORE_CLR</name>
|
|
<description>Digital Regulator Core Register</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x482012</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG0_TARG</name>
|
|
<description>This field defines the target voltage for the ARM core power domain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_0</name>
|
|
<description>Power gated off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_1</name>
|
|
<description>Target core voltage = 0.725V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_2</name>
|
|
<description>Target core voltage = 0.750V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_3</name>
|
|
<description>Target core voltage = 0.775V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_16</name>
|
|
<description>Target core voltage = 1.100V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_30</name>
|
|
<description>Target core voltage = 1.450V</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_31</name>
|
|
<description>Power FET switched full on. No regulation.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_ADJ</name>
|
|
<description>This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_0</name>
|
|
<description>No adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_1</name>
|
|
<description>+ 0.25%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_2</name>
|
|
<description>+ 0.50%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_3</name>
|
|
<description>+ 0.75%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_4</name>
|
|
<description>+ 1.00%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_5</name>
|
|
<description>+ 1.25%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_6</name>
|
|
<description>+ 1.50%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_7</name>
|
|
<description>+ 1.75%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_8</name>
|
|
<description>- 0.25%</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_9</name>
|
|
<description>- 0.50%</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_10</name>
|
|
<description>- 0.75%</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_11</name>
|
|
<description>- 1.00%</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_12</name>
|
|
<description>- 1.25%</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_13</name>
|
|
<description>- 1.50%</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_14</name>
|
|
<description>- 1.75%</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_15</name>
|
|
<description>- 2.00%</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_TARG</name>
|
|
<description>This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_0</name>
|
|
<description>Power gated off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_1</name>
|
|
<description>Target core voltage = 0.725V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_2</name>
|
|
<description>Target core voltage = 0.750V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_3</name>
|
|
<description>Target core voltage = 0.775V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_16</name>
|
|
<description>Target core voltage = 1.100V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_30</name>
|
|
<description>Target core voltage = 1.450V</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_31</name>
|
|
<description>Power FET switched full on. No regulation.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_ADJ</name>
|
|
<description>This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_0</name>
|
|
<description>No adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_1</name>
|
|
<description>+ 0.25%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_2</name>
|
|
<description>+ 0.50%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_3</name>
|
|
<description>+ 0.75%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_4</name>
|
|
<description>+ 1.00%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_5</name>
|
|
<description>+ 1.25%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_6</name>
|
|
<description>+ 1.50%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_7</name>
|
|
<description>+ 1.75%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_8</name>
|
|
<description>- 0.25%</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_9</name>
|
|
<description>- 0.50%</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_10</name>
|
|
<description>- 0.75%</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_11</name>
|
|
<description>- 1.00%</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_12</name>
|
|
<description>- 1.25%</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_13</name>
|
|
<description>- 1.50%</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_14</name>
|
|
<description>- 1.75%</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_15</name>
|
|
<description>- 2.00%</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_TARG</name>
|
|
<description>This field defines the target voltage for the SOC power domain</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_0</name>
|
|
<description>Power gated off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_1</name>
|
|
<description>Target core voltage = 0.725V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_2</name>
|
|
<description>Target core voltage = 0.750V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_3</name>
|
|
<description>Target core voltage = 0.775V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_16</name>
|
|
<description>Target core voltage = 1.100V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_30</name>
|
|
<description>Target core voltage = 1.450V</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_31</name>
|
|
<description>Power FET switched full on. No regulation.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_ADJ</name>
|
|
<description>This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_0</name>
|
|
<description>No adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_1</name>
|
|
<description>+ 0.25%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_2</name>
|
|
<description>+ 0.50%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_3</name>
|
|
<description>+ 0.75%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_4</name>
|
|
<description>+ 1.00%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_5</name>
|
|
<description>+ 1.25%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_6</name>
|
|
<description>+ 1.50%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_7</name>
|
|
<description>+ 1.75%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_8</name>
|
|
<description>- 0.25%</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_9</name>
|
|
<description>- 0.50%</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_10</name>
|
|
<description>- 0.75%</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_11</name>
|
|
<description>- 1.00%</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_12</name>
|
|
<description>- 1.25%</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_13</name>
|
|
<description>- 1.50%</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_14</name>
|
|
<description>- 1.75%</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_15</name>
|
|
<description>- 2.00%</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAMP_RATE</name>
|
|
<description>Regulator voltage ramp rate.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_0</name>
|
|
<description>Fast</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_1</name>
|
|
<description>Medium Fast</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_2</name>
|
|
<description>Medium Slow</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_3</name>
|
|
<description>Slow</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FET_ODRIVE</name>
|
|
<description>If set, increases the gate drive on power gating FETs to reduce leakage in the off state</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REG_CORE_TOG</name>
|
|
<description>Digital Regulator Core Register</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x482012</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG0_TARG</name>
|
|
<description>This field defines the target voltage for the ARM core power domain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_0</name>
|
|
<description>Power gated off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_1</name>
|
|
<description>Target core voltage = 0.725V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_2</name>
|
|
<description>Target core voltage = 0.750V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_3</name>
|
|
<description>Target core voltage = 0.775V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_16</name>
|
|
<description>Target core voltage = 1.100V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_30</name>
|
|
<description>Target core voltage = 1.450V</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_TARG_31</name>
|
|
<description>Power FET switched full on. No regulation.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_ADJ</name>
|
|
<description>This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_0</name>
|
|
<description>No adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_1</name>
|
|
<description>+ 0.25%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_2</name>
|
|
<description>+ 0.50%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_3</name>
|
|
<description>+ 0.75%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_4</name>
|
|
<description>+ 1.00%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_5</name>
|
|
<description>+ 1.25%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_6</name>
|
|
<description>+ 1.50%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_7</name>
|
|
<description>+ 1.75%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_8</name>
|
|
<description>- 0.25%</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_9</name>
|
|
<description>- 0.50%</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_10</name>
|
|
<description>- 0.75%</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_11</name>
|
|
<description>- 1.00%</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_12</name>
|
|
<description>- 1.25%</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_13</name>
|
|
<description>- 1.50%</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_14</name>
|
|
<description>- 1.75%</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_ADJ_15</name>
|
|
<description>- 2.00%</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_TARG</name>
|
|
<description>This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_0</name>
|
|
<description>Power gated off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_1</name>
|
|
<description>Target core voltage = 0.725V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_2</name>
|
|
<description>Target core voltage = 0.750V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_3</name>
|
|
<description>Target core voltage = 0.775V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_16</name>
|
|
<description>Target core voltage = 1.100V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_30</name>
|
|
<description>Target core voltage = 1.450V</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_TARG_31</name>
|
|
<description>Power FET switched full on. No regulation.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_ADJ</name>
|
|
<description>This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_0</name>
|
|
<description>No adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_1</name>
|
|
<description>+ 0.25%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_2</name>
|
|
<description>+ 0.50%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_3</name>
|
|
<description>+ 0.75%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_4</name>
|
|
<description>+ 1.00%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_5</name>
|
|
<description>+ 1.25%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_6</name>
|
|
<description>+ 1.50%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_7</name>
|
|
<description>+ 1.75%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_8</name>
|
|
<description>- 0.25%</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_9</name>
|
|
<description>- 0.50%</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_10</name>
|
|
<description>- 0.75%</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_11</name>
|
|
<description>- 1.00%</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_12</name>
|
|
<description>- 1.25%</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_13</name>
|
|
<description>- 1.50%</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_14</name>
|
|
<description>- 1.75%</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_ADJ_15</name>
|
|
<description>- 2.00%</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_TARG</name>
|
|
<description>This field defines the target voltage for the SOC power domain</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_0</name>
|
|
<description>Power gated off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_1</name>
|
|
<description>Target core voltage = 0.725V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_2</name>
|
|
<description>Target core voltage = 0.750V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_3</name>
|
|
<description>Target core voltage = 0.775V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_16</name>
|
|
<description>Target core voltage = 1.100V</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_30</name>
|
|
<description>Target core voltage = 1.450V</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_TARG_31</name>
|
|
<description>Power FET switched full on. No regulation.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_ADJ</name>
|
|
<description>This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_0</name>
|
|
<description>No adjustment</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_1</name>
|
|
<description>+ 0.25%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_2</name>
|
|
<description>+ 0.50%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_3</name>
|
|
<description>+ 0.75%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_4</name>
|
|
<description>+ 1.00%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_5</name>
|
|
<description>+ 1.25%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_6</name>
|
|
<description>+ 1.50%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_7</name>
|
|
<description>+ 1.75%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_8</name>
|
|
<description>- 0.25%</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_9</name>
|
|
<description>- 0.50%</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_10</name>
|
|
<description>- 0.75%</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_11</name>
|
|
<description>- 1.00%</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_12</name>
|
|
<description>- 1.25%</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_13</name>
|
|
<description>- 1.50%</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_14</name>
|
|
<description>- 1.75%</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_ADJ_15</name>
|
|
<description>- 2.00%</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAMP_RATE</name>
|
|
<description>Regulator voltage ramp rate.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_0</name>
|
|
<description>Fast</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_1</name>
|
|
<description>Medium Fast</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_2</name>
|
|
<description>Medium Slow</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAMP_RATE_3</name>
|
|
<description>Slow</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FET_ODRIVE</name>
|
|
<description>If set, increases the gate drive on power gating FETs to reduce leakage in the off state</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC0</name>
|
|
<description>Miscellaneous Register 0</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFTOP_PWD</name>
|
|
<description>Control bit to power-down the analog bandgap reference circuitry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_PWDVBGUP</name>
|
|
<description>Control bit to power down the VBG-up detection circuitry in the analog bandgap.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_LOWPOWER</name>
|
|
<description>Control bit to enable the low-power mode in the analog bandgap.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_SELFBIASOFF</name>
|
|
<description>Control bit to disable the self-bias circuit in the analog bandgap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_0</name>
|
|
<description>Uses coarse bias currents for startup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_1</name>
|
|
<description>Uses bandgap-based bias currents for best performance.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGADJ</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_0</name>
|
|
<description>Nominal VBG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_1</name>
|
|
<description>VBG+0.78%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_2</name>
|
|
<description>VBG+1.56%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_3</name>
|
|
<description>VBG+2.34%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_4</name>
|
|
<description>VBG-0.78%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_5</name>
|
|
<description>VBG-1.56%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_6</name>
|
|
<description>VBG-2.34%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_7</name>
|
|
<description>VBG-3.12%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGUP</name>
|
|
<description>Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_MODE_CONFIG</name>
|
|
<description>Configure the analog behavior in stop mode.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_0</name>
|
|
<description>SUSPEND (DSM)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STANDBY</name>
|
|
<description>Analog regulators are ON.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_2</name>
|
|
<description>STOP (lower power)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_3</name>
|
|
<description>STOP (very lower power)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCON_HIGH_SNVS</name>
|
|
<description>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_0</name>
|
|
<description>Turn on the switch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_1</name>
|
|
<description>Turn off the switch</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_I</name>
|
|
<description>This field determines the bias current in the 24MHz oscillator</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOMINAL</name>
|
|
<description>Nominal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_12_5_PERCENT</name>
|
|
<description>Decrease current by 12.5%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_25_PERCENT</name>
|
|
<description>Decrease current by 25.0%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_37_5_PERCENT</name>
|
|
<description>Decrease current by 37.5%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK</name>
|
|
<description>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK_EN</name>
|
|
<description>This bit enables the detector that signals when the 24MHz crystal oscillator is stable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_CTRL</name>
|
|
<description>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALLOW_AUTO_GATE</name>
|
|
<description>Allow the logic to automatically gate the clock when the XTAL is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_AUTO_GATE</name>
|
|
<description>Prevent the logic from ever gating off the clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_DELAY</name>
|
|
<description>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_0</name>
|
|
<description>0.5ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_1</name>
|
|
<description>1.0ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_2</name>
|
|
<description>2.0ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_3</name>
|
|
<description>3.0ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_4</name>
|
|
<description>4.0ms</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_5</name>
|
|
<description>5.0ms</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_6</name>
|
|
<description>6.0ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_7</name>
|
|
<description>7.0ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_XTAL_SOURCE</name>
|
|
<description>This field indicates which chip source is being used for the rtc clock.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_0</name>
|
|
<description>Internal ring oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_1</name>
|
|
<description>RTC_XTAL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_PWD</name>
|
|
<description>This field powers down the 24M crystal oscillator if set true.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC0_SET</name>
|
|
<description>Miscellaneous Register 0</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFTOP_PWD</name>
|
|
<description>Control bit to power-down the analog bandgap reference circuitry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_PWDVBGUP</name>
|
|
<description>Control bit to power down the VBG-up detection circuitry in the analog bandgap.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_LOWPOWER</name>
|
|
<description>Control bit to enable the low-power mode in the analog bandgap.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_SELFBIASOFF</name>
|
|
<description>Control bit to disable the self-bias circuit in the analog bandgap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_0</name>
|
|
<description>Uses coarse bias currents for startup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_1</name>
|
|
<description>Uses bandgap-based bias currents for best performance.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGADJ</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_0</name>
|
|
<description>Nominal VBG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_1</name>
|
|
<description>VBG+0.78%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_2</name>
|
|
<description>VBG+1.56%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_3</name>
|
|
<description>VBG+2.34%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_4</name>
|
|
<description>VBG-0.78%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_5</name>
|
|
<description>VBG-1.56%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_6</name>
|
|
<description>VBG-2.34%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_7</name>
|
|
<description>VBG-3.12%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGUP</name>
|
|
<description>Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_MODE_CONFIG</name>
|
|
<description>Configure the analog behavior in stop mode.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_0</name>
|
|
<description>SUSPEND (DSM)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STANDBY</name>
|
|
<description>Analog regulators are ON.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_2</name>
|
|
<description>STOP (lower power)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_3</name>
|
|
<description>STOP (very lower power)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCON_HIGH_SNVS</name>
|
|
<description>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_0</name>
|
|
<description>Turn on the switch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_1</name>
|
|
<description>Turn off the switch</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_I</name>
|
|
<description>This field determines the bias current in the 24MHz oscillator</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOMINAL</name>
|
|
<description>Nominal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_12_5_PERCENT</name>
|
|
<description>Decrease current by 12.5%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_25_PERCENT</name>
|
|
<description>Decrease current by 25.0%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_37_5_PERCENT</name>
|
|
<description>Decrease current by 37.5%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK</name>
|
|
<description>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK_EN</name>
|
|
<description>This bit enables the detector that signals when the 24MHz crystal oscillator is stable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_CTRL</name>
|
|
<description>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALLOW_AUTO_GATE</name>
|
|
<description>Allow the logic to automatically gate the clock when the XTAL is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_AUTO_GATE</name>
|
|
<description>Prevent the logic from ever gating off the clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_DELAY</name>
|
|
<description>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_0</name>
|
|
<description>0.5ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_1</name>
|
|
<description>1.0ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_2</name>
|
|
<description>2.0ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_3</name>
|
|
<description>3.0ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_4</name>
|
|
<description>4.0ms</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_5</name>
|
|
<description>5.0ms</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_6</name>
|
|
<description>6.0ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_7</name>
|
|
<description>7.0ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_XTAL_SOURCE</name>
|
|
<description>This field indicates which chip source is being used for the rtc clock.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_0</name>
|
|
<description>Internal ring oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_1</name>
|
|
<description>RTC_XTAL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_PWD</name>
|
|
<description>This field powers down the 24M crystal oscillator if set true.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC0_CLR</name>
|
|
<description>Miscellaneous Register 0</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFTOP_PWD</name>
|
|
<description>Control bit to power-down the analog bandgap reference circuitry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_PWDVBGUP</name>
|
|
<description>Control bit to power down the VBG-up detection circuitry in the analog bandgap.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_LOWPOWER</name>
|
|
<description>Control bit to enable the low-power mode in the analog bandgap.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_SELFBIASOFF</name>
|
|
<description>Control bit to disable the self-bias circuit in the analog bandgap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_0</name>
|
|
<description>Uses coarse bias currents for startup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_1</name>
|
|
<description>Uses bandgap-based bias currents for best performance.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGADJ</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_0</name>
|
|
<description>Nominal VBG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_1</name>
|
|
<description>VBG+0.78%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_2</name>
|
|
<description>VBG+1.56%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_3</name>
|
|
<description>VBG+2.34%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_4</name>
|
|
<description>VBG-0.78%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_5</name>
|
|
<description>VBG-1.56%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_6</name>
|
|
<description>VBG-2.34%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_7</name>
|
|
<description>VBG-3.12%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGUP</name>
|
|
<description>Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_MODE_CONFIG</name>
|
|
<description>Configure the analog behavior in stop mode.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_0</name>
|
|
<description>SUSPEND (DSM)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STANDBY</name>
|
|
<description>Analog regulators are ON.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_2</name>
|
|
<description>STOP (lower power)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_3</name>
|
|
<description>STOP (very lower power)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCON_HIGH_SNVS</name>
|
|
<description>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_0</name>
|
|
<description>Turn on the switch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_1</name>
|
|
<description>Turn off the switch</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_I</name>
|
|
<description>This field determines the bias current in the 24MHz oscillator</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOMINAL</name>
|
|
<description>Nominal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_12_5_PERCENT</name>
|
|
<description>Decrease current by 12.5%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_25_PERCENT</name>
|
|
<description>Decrease current by 25.0%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_37_5_PERCENT</name>
|
|
<description>Decrease current by 37.5%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK</name>
|
|
<description>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK_EN</name>
|
|
<description>This bit enables the detector that signals when the 24MHz crystal oscillator is stable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_CTRL</name>
|
|
<description>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALLOW_AUTO_GATE</name>
|
|
<description>Allow the logic to automatically gate the clock when the XTAL is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_AUTO_GATE</name>
|
|
<description>Prevent the logic from ever gating off the clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_DELAY</name>
|
|
<description>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_0</name>
|
|
<description>0.5ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_1</name>
|
|
<description>1.0ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_2</name>
|
|
<description>2.0ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_3</name>
|
|
<description>3.0ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_4</name>
|
|
<description>4.0ms</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_5</name>
|
|
<description>5.0ms</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_6</name>
|
|
<description>6.0ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_7</name>
|
|
<description>7.0ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_XTAL_SOURCE</name>
|
|
<description>This field indicates which chip source is being used for the rtc clock.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_0</name>
|
|
<description>Internal ring oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_1</name>
|
|
<description>RTC_XTAL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_PWD</name>
|
|
<description>This field powers down the 24M crystal oscillator if set true.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC0_TOG</name>
|
|
<description>Miscellaneous Register 0</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFTOP_PWD</name>
|
|
<description>Control bit to power-down the analog bandgap reference circuitry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_PWDVBGUP</name>
|
|
<description>Control bit to power down the VBG-up detection circuitry in the analog bandgap.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_LOWPOWER</name>
|
|
<description>Control bit to enable the low-power mode in the analog bandgap.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_SELFBIASOFF</name>
|
|
<description>Control bit to disable the self-bias circuit in the analog bandgap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_0</name>
|
|
<description>Uses coarse bias currents for startup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_1</name>
|
|
<description>Uses bandgap-based bias currents for best performance.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGADJ</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_0</name>
|
|
<description>Nominal VBG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_1</name>
|
|
<description>VBG+0.78%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_2</name>
|
|
<description>VBG+1.56%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_3</name>
|
|
<description>VBG+2.34%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_4</name>
|
|
<description>VBG-0.78%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_5</name>
|
|
<description>VBG-1.56%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_6</name>
|
|
<description>VBG-2.34%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_7</name>
|
|
<description>VBG-3.12%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGUP</name>
|
|
<description>Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_MODE_CONFIG</name>
|
|
<description>Configure the analog behavior in stop mode.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_0</name>
|
|
<description>SUSPEND (DSM)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STANDBY</name>
|
|
<description>Analog regulators are ON.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_2</name>
|
|
<description>STOP (lower power)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_3</name>
|
|
<description>STOP (very lower power)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCON_HIGH_SNVS</name>
|
|
<description>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_0</name>
|
|
<description>Turn on the switch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_1</name>
|
|
<description>Turn off the switch</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_I</name>
|
|
<description>This field determines the bias current in the 24MHz oscillator</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOMINAL</name>
|
|
<description>Nominal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_12_5_PERCENT</name>
|
|
<description>Decrease current by 12.5%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_25_PERCENT</name>
|
|
<description>Decrease current by 25.0%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_37_5_PERCENT</name>
|
|
<description>Decrease current by 37.5%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK</name>
|
|
<description>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK_EN</name>
|
|
<description>This bit enables the detector that signals when the 24MHz crystal oscillator is stable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_CTRL</name>
|
|
<description>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALLOW_AUTO_GATE</name>
|
|
<description>Allow the logic to automatically gate the clock when the XTAL is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_AUTO_GATE</name>
|
|
<description>Prevent the logic from ever gating off the clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_DELAY</name>
|
|
<description>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_0</name>
|
|
<description>0.5ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_1</name>
|
|
<description>1.0ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_2</name>
|
|
<description>2.0ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_3</name>
|
|
<description>3.0ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_4</name>
|
|
<description>4.0ms</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_5</name>
|
|
<description>5.0ms</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_6</name>
|
|
<description>6.0ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_7</name>
|
|
<description>7.0ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_XTAL_SOURCE</name>
|
|
<description>This field indicates which chip source is being used for the rtc clock.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_0</name>
|
|
<description>Internal ring oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_1</name>
|
|
<description>RTC_XTAL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_PWD</name>
|
|
<description>This field powers down the 24M crystal oscillator if set true.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC1</name>
|
|
<description>Miscellaneous Register 1</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD_480_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD_528_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPPANIC</name>
|
|
<description>This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPLOW</name>
|
|
<description>This status bit is set to one when the temperature sensor low interrupt asserts for low temperature</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPHIGH</name>
|
|
<description>This status bit is set to one when the temperature sensor high interrupt asserts for high temperature</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_ANA_BO</name>
|
|
<description>This status bit is set to one when when any of the analog regulator brownout interrupts assert</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_DIG_BO</name>
|
|
<description>This status bit is set to one when when any of the digital regulator brownout interrupts assert</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC1_SET</name>
|
|
<description>Miscellaneous Register 1</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD_480_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD_528_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPPANIC</name>
|
|
<description>This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPLOW</name>
|
|
<description>This status bit is set to one when the temperature sensor low interrupt asserts for low temperature</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPHIGH</name>
|
|
<description>This status bit is set to one when the temperature sensor high interrupt asserts for high temperature</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_ANA_BO</name>
|
|
<description>This status bit is set to one when when any of the analog regulator brownout interrupts assert</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_DIG_BO</name>
|
|
<description>This status bit is set to one when when any of the digital regulator brownout interrupts assert</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC1_CLR</name>
|
|
<description>Miscellaneous Register 1</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD_480_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD_528_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPPANIC</name>
|
|
<description>This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPLOW</name>
|
|
<description>This status bit is set to one when the temperature sensor low interrupt asserts for low temperature</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPHIGH</name>
|
|
<description>This status bit is set to one when the temperature sensor high interrupt asserts for high temperature</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_ANA_BO</name>
|
|
<description>This status bit is set to one when when any of the analog regulator brownout interrupts assert</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_DIG_BO</name>
|
|
<description>This status bit is set to one when when any of the digital regulator brownout interrupts assert</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC1_TOG</name>
|
|
<description>Miscellaneous Register 1</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PFD_480_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PFD_528_AUTOGATE_EN</name>
|
|
<description>This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPPANIC</name>
|
|
<description>This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPLOW</name>
|
|
<description>This status bit is set to one when the temperature sensor low interrupt asserts for low temperature</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_TEMPHIGH</name>
|
|
<description>This status bit is set to one when the temperature sensor high interrupt asserts for high temperature</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_ANA_BO</name>
|
|
<description>This status bit is set to one when when any of the analog regulator brownout interrupts assert</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQ_DIG_BO</name>
|
|
<description>This status bit is set to one when when any of the digital regulator brownout interrupts assert</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC2</name>
|
|
<description>Miscellaneous Control Register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x272727</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG0_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the CORE power domain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_BO_STATUS</name>
|
|
<description>Reg0 brownout status bit.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLL3_disable</name>
|
|
<description>Default value of "0"</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_STATUS</name>
|
|
<description>Reg1 brownout status bit.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_LSB</name>
|
|
<description>LSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_STATUS</name>
|
|
<description>Reg2 brownout status bit.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_OK</name>
|
|
<description>Signals that the voltage is above the brownout level for the SOC supply</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_MSB</name>
|
|
<description>MSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC2_SET</name>
|
|
<description>Miscellaneous Control Register</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x272727</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG0_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the CORE power domain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_BO_STATUS</name>
|
|
<description>Reg0 brownout status bit.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLL3_disable</name>
|
|
<description>Default value of "0"</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_STATUS</name>
|
|
<description>Reg1 brownout status bit.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_LSB</name>
|
|
<description>LSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_STATUS</name>
|
|
<description>Reg2 brownout status bit.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_OK</name>
|
|
<description>Signals that the voltage is above the brownout level for the SOC supply</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_MSB</name>
|
|
<description>MSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC2_CLR</name>
|
|
<description>Miscellaneous Control Register</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x272727</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG0_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the CORE power domain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_BO_STATUS</name>
|
|
<description>Reg0 brownout status bit.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLL3_disable</name>
|
|
<description>Default value of "0"</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_STATUS</name>
|
|
<description>Reg1 brownout status bit.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_LSB</name>
|
|
<description>LSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_STATUS</name>
|
|
<description>Reg2 brownout status bit.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_OK</name>
|
|
<description>Signals that the voltage is above the brownout level for the SOC supply</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_MSB</name>
|
|
<description>MSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC2_TOG</name>
|
|
<description>Miscellaneous Control Register</description>
|
|
<addressOffset>0x17C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x272727</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG0_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the CORE power domain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_BO_STATUS</name>
|
|
<description>Reg0 brownout status bit.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG0_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLL3_disable</name>
|
|
<description>Default value of "0"</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_BO_STATUS</name>
|
|
<description>Reg1 brownout status bit.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG1_BO_STATUS_1</name>
|
|
<description>Brownout, supply is below target minus brownout offset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_LSB</name>
|
|
<description>LSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_LSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_OFFSET</name>
|
|
<description>This field defines the brown out voltage offset for the xPU power domain</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_4</name>
|
|
<description>Brownout offset = 0.100V</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG2_BO_OFFSET_7</name>
|
|
<description>Brownout offset = 0.175V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_BO_STATUS</name>
|
|
<description>Reg2 brownout status bit.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_ENABLE_BO</name>
|
|
<description>Enables the brownout detection.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REG2_OK</name>
|
|
<description>Signals that the voltage is above the brownout level for the SOC supply</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AUDIO_DIV_MSB</name>
|
|
<description>MSB of Post-divider for Audio PLL</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_0</name>
|
|
<description>divide by 1 (Default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUDIO_DIV_MSB_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG0_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG1_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG2_STEP_TIME</name>
|
|
<description>Number of clock periods (24MHz clock).</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>64_CLOCKS</name>
|
|
<description>64</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_CLOCKS</name>
|
|
<description>128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_CLOCKS</name>
|
|
<description>256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>512_CLOCKS</name>
|
|
<description>512</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TEMPMON</name>
|
|
<description>Temperature Monitor</description>
|
|
<alternatePeripheral>CCM_ANALOG</alternatePeripheral>
|
|
<groupName>TEMPMON</groupName>
|
|
<prependToName>TEMPMON_</prependToName>
|
|
<baseAddress>0x400D8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x2A0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TEMP_LOW_HIGH</name>
|
|
<value>63</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TEMP_PANIC</name>
|
|
<value>64</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TEMPSENSE0</name>
|
|
<description>Tempsensor Control Register 0</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POWER_DOWN</name>
|
|
<description>This bit powers down the temperature sensor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POWER_UP</name>
|
|
<description>Enable power to the temperature sensor.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power down the temperature sensor.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEASURE_TEMP</name>
|
|
<description>Starts the measurement process</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Do not start the measurement process.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start the measurement process.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FINISHED</name>
|
|
<description>Indicates that the latest temp is valid</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INVALID</name>
|
|
<description>Last measurement is not ready yet.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALID</name>
|
|
<description>Last measurement is valid.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEMP_CNT</name>
|
|
<description>This bit field contains the last measured temperature count.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALARM_VALUE</name>
|
|
<description>This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEMPSENSE0_SET</name>
|
|
<description>Tempsensor Control Register 0</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POWER_DOWN</name>
|
|
<description>This bit powers down the temperature sensor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POWER_UP</name>
|
|
<description>Enable power to the temperature sensor.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power down the temperature sensor.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEASURE_TEMP</name>
|
|
<description>Starts the measurement process</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Do not start the measurement process.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start the measurement process.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FINISHED</name>
|
|
<description>Indicates that the latest temp is valid</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INVALID</name>
|
|
<description>Last measurement is not ready yet.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALID</name>
|
|
<description>Last measurement is valid.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEMP_CNT</name>
|
|
<description>This bit field contains the last measured temperature count.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALARM_VALUE</name>
|
|
<description>This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEMPSENSE0_CLR</name>
|
|
<description>Tempsensor Control Register 0</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POWER_DOWN</name>
|
|
<description>This bit powers down the temperature sensor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POWER_UP</name>
|
|
<description>Enable power to the temperature sensor.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power down the temperature sensor.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEASURE_TEMP</name>
|
|
<description>Starts the measurement process</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Do not start the measurement process.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start the measurement process.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FINISHED</name>
|
|
<description>Indicates that the latest temp is valid</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INVALID</name>
|
|
<description>Last measurement is not ready yet.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALID</name>
|
|
<description>Last measurement is valid.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEMP_CNT</name>
|
|
<description>This bit field contains the last measured temperature count.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALARM_VALUE</name>
|
|
<description>This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEMPSENSE0_TOG</name>
|
|
<description>Tempsensor Control Register 0</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POWER_DOWN</name>
|
|
<description>This bit powers down the temperature sensor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POWER_UP</name>
|
|
<description>Enable power to the temperature sensor.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power down the temperature sensor.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEASURE_TEMP</name>
|
|
<description>Starts the measurement process</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Do not start the measurement process.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start the measurement process.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FINISHED</name>
|
|
<description>Indicates that the latest temp is valid</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INVALID</name>
|
|
<description>Last measurement is not ready yet.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALID</name>
|
|
<description>Last measurement is valid.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEMP_CNT</name>
|
|
<description>This bit field contains the last measured temperature count.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALARM_VALUE</name>
|
|
<description>This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEMPSENSE1</name>
|
|
<description>Tempsensor Control Register 1</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEASURE_FREQ</name>
|
|
<description>This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEMPSENSE1_SET</name>
|
|
<description>Tempsensor Control Register 1</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEASURE_FREQ</name>
|
|
<description>This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEMPSENSE1_CLR</name>
|
|
<description>Tempsensor Control Register 1</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEASURE_FREQ</name>
|
|
<description>This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEMPSENSE1_TOG</name>
|
|
<description>Tempsensor Control Register 1</description>
|
|
<addressOffset>0x19C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEASURE_FREQ</name>
|
|
<description>This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEMPSENSE2</name>
|
|
<description>Tempsensor Control Register 2</description>
|
|
<addressOffset>0x290</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOW_ALARM_VALUE</name>
|
|
<description>This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PANIC_ALARM_VALUE</name>
|
|
<description>This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEMPSENSE2_SET</name>
|
|
<description>Tempsensor Control Register 2</description>
|
|
<addressOffset>0x294</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOW_ALARM_VALUE</name>
|
|
<description>This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PANIC_ALARM_VALUE</name>
|
|
<description>This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEMPSENSE2_CLR</name>
|
|
<description>Tempsensor Control Register 2</description>
|
|
<addressOffset>0x298</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOW_ALARM_VALUE</name>
|
|
<description>This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PANIC_ALARM_VALUE</name>
|
|
<description>This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEMPSENSE2_TOG</name>
|
|
<description>Tempsensor Control Register 2</description>
|
|
<addressOffset>0x29C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOW_ALARM_VALUE</name>
|
|
<description>This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PANIC_ALARM_VALUE</name>
|
|
<description>This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USB_ANALOG</name>
|
|
<description>USB Analog</description>
|
|
<alternatePeripheral>CCM_ANALOG</alternatePeripheral>
|
|
<groupName>USB_ANALOG</groupName>
|
|
<prependToName>USB_ANALOG_</prependToName>
|
|
<baseAddress>0x400D8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x264</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>USB1_VBUS_DETECT</name>
|
|
<description>USB VBUS Detect Register</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VBUSVALID_THRESH</name>
|
|
<description>Set the threshold for the VBUSVALID comparator</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>4V0</name>
|
|
<description>4.0V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V1</name>
|
|
<description>4.1V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V2</name>
|
|
<description>4.2V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V3</name>
|
|
<description>4.3V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V4</name>
|
|
<description>4.4V (default)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V5</name>
|
|
<description>4.5V</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V6</name>
|
|
<description>4.6V</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V7</name>
|
|
<description>4.7V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VBUSVALID_PWRUP_CMPS</name>
|
|
<description>Powers up comparators for vbus_valid detector.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCHARGE_VBUS</name>
|
|
<description>USB OTG discharge VBUS.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHARGE_VBUS</name>
|
|
<description>USB OTG charge VBUS.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_VBUS_DETECT_SET</name>
|
|
<description>USB VBUS Detect Register</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VBUSVALID_THRESH</name>
|
|
<description>Set the threshold for the VBUSVALID comparator</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>4V0</name>
|
|
<description>4.0V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V1</name>
|
|
<description>4.1V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V2</name>
|
|
<description>4.2V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V3</name>
|
|
<description>4.3V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V4</name>
|
|
<description>4.4V (default)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V5</name>
|
|
<description>4.5V</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V6</name>
|
|
<description>4.6V</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V7</name>
|
|
<description>4.7V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VBUSVALID_PWRUP_CMPS</name>
|
|
<description>Powers up comparators for vbus_valid detector.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCHARGE_VBUS</name>
|
|
<description>USB OTG discharge VBUS.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHARGE_VBUS</name>
|
|
<description>USB OTG charge VBUS.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_VBUS_DETECT_CLR</name>
|
|
<description>USB VBUS Detect Register</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VBUSVALID_THRESH</name>
|
|
<description>Set the threshold for the VBUSVALID comparator</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>4V0</name>
|
|
<description>4.0V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V1</name>
|
|
<description>4.1V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V2</name>
|
|
<description>4.2V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V3</name>
|
|
<description>4.3V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V4</name>
|
|
<description>4.4V (default)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V5</name>
|
|
<description>4.5V</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V6</name>
|
|
<description>4.6V</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V7</name>
|
|
<description>4.7V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VBUSVALID_PWRUP_CMPS</name>
|
|
<description>Powers up comparators for vbus_valid detector.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCHARGE_VBUS</name>
|
|
<description>USB OTG discharge VBUS.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHARGE_VBUS</name>
|
|
<description>USB OTG charge VBUS.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_VBUS_DETECT_TOG</name>
|
|
<description>USB VBUS Detect Register</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x100004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VBUSVALID_THRESH</name>
|
|
<description>Set the threshold for the VBUSVALID comparator</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>4V0</name>
|
|
<description>4.0V</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V1</name>
|
|
<description>4.1V</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V2</name>
|
|
<description>4.2V</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V3</name>
|
|
<description>4.3V</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V4</name>
|
|
<description>4.4V (default)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V5</name>
|
|
<description>4.5V</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V6</name>
|
|
<description>4.6V</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4V7</name>
|
|
<description>4.7V</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VBUSVALID_PWRUP_CMPS</name>
|
|
<description>Powers up comparators for vbus_valid detector.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCHARGE_VBUS</name>
|
|
<description>USB OTG discharge VBUS.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHARGE_VBUS</name>
|
|
<description>USB OTG charge VBUS.</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_CHRG_DETECT</name>
|
|
<description>USB Charger Detect Register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHK_CONTACT</name>
|
|
<description>Check the contact of USB plug</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_CHECK</name>
|
|
<description>Do not check the contact of USB plug.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHECK</name>
|
|
<description>Check whether the USB plug has been in contact with each other</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHK_CHRG_B</name>
|
|
<description>Check the charger connection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CHECK</name>
|
|
<description>Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHECK</name>
|
|
<description>Do not check whether a charger is connected to the USB port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN_B</name>
|
|
<description>Control the charger detector.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable the charger detector.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable the charger detector.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_CHRG_DETECT_SET</name>
|
|
<description>USB Charger Detect Register</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHK_CONTACT</name>
|
|
<description>Check the contact of USB plug</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_CHECK</name>
|
|
<description>Do not check the contact of USB plug.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHECK</name>
|
|
<description>Check whether the USB plug has been in contact with each other</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHK_CHRG_B</name>
|
|
<description>Check the charger connection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CHECK</name>
|
|
<description>Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHECK</name>
|
|
<description>Do not check whether a charger is connected to the USB port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN_B</name>
|
|
<description>Control the charger detector.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable the charger detector.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable the charger detector.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_CHRG_DETECT_CLR</name>
|
|
<description>USB Charger Detect Register</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHK_CONTACT</name>
|
|
<description>Check the contact of USB plug</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_CHECK</name>
|
|
<description>Do not check the contact of USB plug.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHECK</name>
|
|
<description>Check whether the USB plug has been in contact with each other</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHK_CHRG_B</name>
|
|
<description>Check the charger connection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CHECK</name>
|
|
<description>Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHECK</name>
|
|
<description>Do not check whether a charger is connected to the USB port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN_B</name>
|
|
<description>Control the charger detector.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable the charger detector.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable the charger detector.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_CHRG_DETECT_TOG</name>
|
|
<description>USB Charger Detect Register</description>
|
|
<addressOffset>0x1BC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHK_CONTACT</name>
|
|
<description>Check the contact of USB plug</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_CHECK</name>
|
|
<description>Do not check the contact of USB plug.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHECK</name>
|
|
<description>Check whether the USB plug has been in contact with each other</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHK_CHRG_B</name>
|
|
<description>Check the charger connection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CHECK</name>
|
|
<description>Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHECK</name>
|
|
<description>Do not check whether a charger is connected to the USB port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN_B</name>
|
|
<description>Control the charger detector.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable the charger detector.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable the charger detector.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_VBUS_DETECT_STAT</name>
|
|
<description>USB VBUS Detect Status Register</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SESSEND</name>
|
|
<description>Session End for USB OTG</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BVALID</name>
|
|
<description>Indicates VBus is valid for a B-peripheral</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AVALID</name>
|
|
<description>Indicates VBus is valid for a A-peripheral</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VBUS_VALID</name>
|
|
<description>VBus valid for USB OTG</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_CHRG_DETECT_STAT</name>
|
|
<description>USB Charger Detect Status Register</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PLUG_CONTACT</name>
|
|
<description>State of the USB plug contact detector.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NO_CONTACT</name>
|
|
<description>The USB plug has not made contact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GOOD_CONTACT</name>
|
|
<description>The USB plug has made good contact.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHRG_DETECTED</name>
|
|
<description>State of charger detection. This bit is a read only version of the state of the analog signal.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CHARGER_NOT_PRESENT</name>
|
|
<description>The USB port is not connected to a charger.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHARGER_PRESENT</name>
|
|
<description>A charger (either a dedicated charger or a host charger) is connected to the USB port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DM_STATE</name>
|
|
<description>DM line state output of the charger detector.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DP_STATE</name>
|
|
<description>DP line state output of the charger detector.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_LOOPBACK</name>
|
|
<description>USB Loopback Test Register</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UTMI_TESTSTART</name>
|
|
<description>Setting this bit can enable 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_LOOPBACK_SET</name>
|
|
<description>USB Loopback Test Register</description>
|
|
<addressOffset>0x1E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UTMI_TESTSTART</name>
|
|
<description>Setting this bit can enable 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_LOOPBACK_CLR</name>
|
|
<description>USB Loopback Test Register</description>
|
|
<addressOffset>0x1E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UTMI_TESTSTART</name>
|
|
<description>Setting this bit can enable 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_LOOPBACK_TOG</name>
|
|
<description>USB Loopback Test Register</description>
|
|
<addressOffset>0x1EC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UTMI_TESTSTART</name>
|
|
<description>Setting this bit can enable 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_MISC</name>
|
|
<description>USB Misc Register</description>
|
|
<addressOffset>0x1F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HS_USE_EXTERNAL_R</name>
|
|
<description>Use external resistor to generate the current bias for the high speed transmitter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_DEGLITCH</name>
|
|
<description>Enable the deglitching circuit of the USB PLL output.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_CLK_UTMI</name>
|
|
<description>Enables the clk to the UTMI block.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_MISC_SET</name>
|
|
<description>USB Misc Register</description>
|
|
<addressOffset>0x1F4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HS_USE_EXTERNAL_R</name>
|
|
<description>Use external resistor to generate the current bias for the high speed transmitter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_DEGLITCH</name>
|
|
<description>Enable the deglitching circuit of the USB PLL output.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_CLK_UTMI</name>
|
|
<description>Enables the clk to the UTMI block.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_MISC_CLR</name>
|
|
<description>USB Misc Register</description>
|
|
<addressOffset>0x1F8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HS_USE_EXTERNAL_R</name>
|
|
<description>Use external resistor to generate the current bias for the high speed transmitter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_DEGLITCH</name>
|
|
<description>Enable the deglitching circuit of the USB PLL output.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_CLK_UTMI</name>
|
|
<description>Enables the clk to the UTMI block.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1_MISC_TOG</name>
|
|
<description>USB Misc Register</description>
|
|
<addressOffset>0x1FC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HS_USE_EXTERNAL_R</name>
|
|
<description>Use external resistor to generate the current bias for the high speed transmitter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_DEGLITCH</name>
|
|
<description>Enable the deglitching circuit of the USB PLL output.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_CLK_UTMI</name>
|
|
<description>Enables the clk to the UTMI block.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIGPROG</name>
|
|
<description>Chip Silicon Version</description>
|
|
<addressOffset>0x260</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x6D0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SILICON_REVISION</name>
|
|
<description>Chip silicon revision</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SILICON_REVISION_7143424</name>
|
|
<description>Silicon revision 1.0</description>
|
|
<value>0x6D0000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>XTALOSC24M</name>
|
|
<description>XTALOSC24M</description>
|
|
<alternatePeripheral>CCM_ANALOG</alternatePeripheral>
|
|
<groupName>XTALOSC24M</groupName>
|
|
<prependToName>XTALOSC24M_</prependToName>
|
|
<baseAddress>0x400D8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x2D0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MISC0</name>
|
|
<description>Miscellaneous Register 0</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFTOP_PWD</name>
|
|
<description>Control bit to power-down the analog bandgap reference circuitry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_SELFBIASOFF</name>
|
|
<description>Control bit to disable the self-bias circuit in the analog bandgap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_0</name>
|
|
<description>Uses coarse bias currents for startup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_1</name>
|
|
<description>Uses bandgap-based bias currents for best performance.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGADJ</name>
|
|
<description>Not related to oscillator.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_0</name>
|
|
<description>Nominal VBG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_1</name>
|
|
<description>VBG+0.78%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_2</name>
|
|
<description>VBG+1.56%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_3</name>
|
|
<description>VBG+2.34%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_4</name>
|
|
<description>VBG-0.78%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_5</name>
|
|
<description>VBG-1.56%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_6</name>
|
|
<description>VBG-2.34%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_7</name>
|
|
<description>VBG-3.12%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGUP</name>
|
|
<description>Status bit that signals the analog bandgap voltage is up and stable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_MODE_CONFIG</name>
|
|
<description>Configure the analog behavior in stop mode.Not related to oscillator.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_0</name>
|
|
<description>All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_1</name>
|
|
<description>Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_2</name>
|
|
<description>XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_3</name>
|
|
<description>XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCON_HIGH_SNVS</name>
|
|
<description>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_0</name>
|
|
<description>Turn on the switch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_1</name>
|
|
<description>Turn off the switch</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_I</name>
|
|
<description>This field determines the bias current in the 24MHz oscillator</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOMINAL</name>
|
|
<description>Nominal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_12_5_PERCENT</name>
|
|
<description>Decrease current by 12.5%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_25_PERCENT</name>
|
|
<description>Decrease current by 25.0%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_37_5_PERCENT</name>
|
|
<description>Decrease current by 37.5%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK</name>
|
|
<description>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK_EN</name>
|
|
<description>This bit enables the detector that signals when the 24MHz crystal oscillator is stable.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_CTRL</name>
|
|
<description>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALLOW_AUTO_GATE</name>
|
|
<description>Allow the logic to automatically gate the clock when the XTAL is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_AUTO_GATE</name>
|
|
<description>Prevent the logic from ever gating off the clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_DELAY</name>
|
|
<description>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_0</name>
|
|
<description>0.5ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_1</name>
|
|
<description>1.0ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_2</name>
|
|
<description>2.0ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_3</name>
|
|
<description>3.0ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_4</name>
|
|
<description>4.0ms</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_5</name>
|
|
<description>5.0ms</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_6</name>
|
|
<description>6.0ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_7</name>
|
|
<description>7.0ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_XTAL_SOURCE</name>
|
|
<description>This field indicates which chip source is being used for the rtc clock.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_0</name>
|
|
<description>Internal ring oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_1</name>
|
|
<description>RTC_XTAL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_PWD</name>
|
|
<description>This field powers down the 24M crystal oscillator if set true.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VID_PLL_PREDIV</name>
|
|
<description>Predivider for the source clock of the PLL's. Not related to oscillator.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VID_PLL_PREDIV_0</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VID_PLL_PREDIV_1</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC0_SET</name>
|
|
<description>Miscellaneous Register 0</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFTOP_PWD</name>
|
|
<description>Control bit to power-down the analog bandgap reference circuitry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_SELFBIASOFF</name>
|
|
<description>Control bit to disable the self-bias circuit in the analog bandgap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_0</name>
|
|
<description>Uses coarse bias currents for startup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_1</name>
|
|
<description>Uses bandgap-based bias currents for best performance.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGADJ</name>
|
|
<description>Not related to oscillator.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_0</name>
|
|
<description>Nominal VBG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_1</name>
|
|
<description>VBG+0.78%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_2</name>
|
|
<description>VBG+1.56%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_3</name>
|
|
<description>VBG+2.34%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_4</name>
|
|
<description>VBG-0.78%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_5</name>
|
|
<description>VBG-1.56%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_6</name>
|
|
<description>VBG-2.34%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_7</name>
|
|
<description>VBG-3.12%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGUP</name>
|
|
<description>Status bit that signals the analog bandgap voltage is up and stable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_MODE_CONFIG</name>
|
|
<description>Configure the analog behavior in stop mode.Not related to oscillator.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_0</name>
|
|
<description>All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_1</name>
|
|
<description>Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_2</name>
|
|
<description>XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_3</name>
|
|
<description>XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCON_HIGH_SNVS</name>
|
|
<description>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_0</name>
|
|
<description>Turn on the switch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_1</name>
|
|
<description>Turn off the switch</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_I</name>
|
|
<description>This field determines the bias current in the 24MHz oscillator</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOMINAL</name>
|
|
<description>Nominal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_12_5_PERCENT</name>
|
|
<description>Decrease current by 12.5%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_25_PERCENT</name>
|
|
<description>Decrease current by 25.0%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_37_5_PERCENT</name>
|
|
<description>Decrease current by 37.5%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK</name>
|
|
<description>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK_EN</name>
|
|
<description>This bit enables the detector that signals when the 24MHz crystal oscillator is stable.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_CTRL</name>
|
|
<description>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALLOW_AUTO_GATE</name>
|
|
<description>Allow the logic to automatically gate the clock when the XTAL is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_AUTO_GATE</name>
|
|
<description>Prevent the logic from ever gating off the clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_DELAY</name>
|
|
<description>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_0</name>
|
|
<description>0.5ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_1</name>
|
|
<description>1.0ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_2</name>
|
|
<description>2.0ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_3</name>
|
|
<description>3.0ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_4</name>
|
|
<description>4.0ms</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_5</name>
|
|
<description>5.0ms</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_6</name>
|
|
<description>6.0ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_7</name>
|
|
<description>7.0ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_XTAL_SOURCE</name>
|
|
<description>This field indicates which chip source is being used for the rtc clock.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_0</name>
|
|
<description>Internal ring oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_1</name>
|
|
<description>RTC_XTAL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_PWD</name>
|
|
<description>This field powers down the 24M crystal oscillator if set true.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VID_PLL_PREDIV</name>
|
|
<description>Predivider for the source clock of the PLL's. Not related to oscillator.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VID_PLL_PREDIV_0</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VID_PLL_PREDIV_1</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC0_CLR</name>
|
|
<description>Miscellaneous Register 0</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFTOP_PWD</name>
|
|
<description>Control bit to power-down the analog bandgap reference circuitry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_SELFBIASOFF</name>
|
|
<description>Control bit to disable the self-bias circuit in the analog bandgap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_0</name>
|
|
<description>Uses coarse bias currents for startup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_1</name>
|
|
<description>Uses bandgap-based bias currents for best performance.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGADJ</name>
|
|
<description>Not related to oscillator.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_0</name>
|
|
<description>Nominal VBG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_1</name>
|
|
<description>VBG+0.78%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_2</name>
|
|
<description>VBG+1.56%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_3</name>
|
|
<description>VBG+2.34%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_4</name>
|
|
<description>VBG-0.78%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_5</name>
|
|
<description>VBG-1.56%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_6</name>
|
|
<description>VBG-2.34%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_7</name>
|
|
<description>VBG-3.12%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGUP</name>
|
|
<description>Status bit that signals the analog bandgap voltage is up and stable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_MODE_CONFIG</name>
|
|
<description>Configure the analog behavior in stop mode.Not related to oscillator.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_0</name>
|
|
<description>All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_1</name>
|
|
<description>Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_2</name>
|
|
<description>XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_3</name>
|
|
<description>XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCON_HIGH_SNVS</name>
|
|
<description>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_0</name>
|
|
<description>Turn on the switch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_1</name>
|
|
<description>Turn off the switch</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_I</name>
|
|
<description>This field determines the bias current in the 24MHz oscillator</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOMINAL</name>
|
|
<description>Nominal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_12_5_PERCENT</name>
|
|
<description>Decrease current by 12.5%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_25_PERCENT</name>
|
|
<description>Decrease current by 25.0%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_37_5_PERCENT</name>
|
|
<description>Decrease current by 37.5%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK</name>
|
|
<description>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK_EN</name>
|
|
<description>This bit enables the detector that signals when the 24MHz crystal oscillator is stable.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_CTRL</name>
|
|
<description>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALLOW_AUTO_GATE</name>
|
|
<description>Allow the logic to automatically gate the clock when the XTAL is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_AUTO_GATE</name>
|
|
<description>Prevent the logic from ever gating off the clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_DELAY</name>
|
|
<description>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_0</name>
|
|
<description>0.5ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_1</name>
|
|
<description>1.0ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_2</name>
|
|
<description>2.0ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_3</name>
|
|
<description>3.0ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_4</name>
|
|
<description>4.0ms</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_5</name>
|
|
<description>5.0ms</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_6</name>
|
|
<description>6.0ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_7</name>
|
|
<description>7.0ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_XTAL_SOURCE</name>
|
|
<description>This field indicates which chip source is being used for the rtc clock.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_0</name>
|
|
<description>Internal ring oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_1</name>
|
|
<description>RTC_XTAL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_PWD</name>
|
|
<description>This field powers down the 24M crystal oscillator if set true.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VID_PLL_PREDIV</name>
|
|
<description>Predivider for the source clock of the PLL's. Not related to oscillator.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VID_PLL_PREDIV_0</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VID_PLL_PREDIV_1</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC0_TOG</name>
|
|
<description>Miscellaneous Register 0</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFTOP_PWD</name>
|
|
<description>Control bit to power-down the analog bandgap reference circuitry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_SELFBIASOFF</name>
|
|
<description>Control bit to disable the self-bias circuit in the analog bandgap</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_0</name>
|
|
<description>Uses coarse bias currents for startup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_SELFBIASOFF_1</name>
|
|
<description>Uses bandgap-based bias currents for best performance.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGADJ</name>
|
|
<description>Not related to oscillator.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_0</name>
|
|
<description>Nominal VBG</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_1</name>
|
|
<description>VBG+0.78%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_2</name>
|
|
<description>VBG+1.56%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_3</name>
|
|
<description>VBG+2.34%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_4</name>
|
|
<description>VBG-0.78%</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_5</name>
|
|
<description>VBG-1.56%</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_6</name>
|
|
<description>VBG-2.34%</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REFTOP_VBGADJ_7</name>
|
|
<description>VBG-3.12%</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_VBGUP</name>
|
|
<description>Status bit that signals the analog bandgap voltage is up and stable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP_MODE_CONFIG</name>
|
|
<description>Configure the analog behavior in stop mode.Not related to oscillator.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_0</name>
|
|
<description>All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_1</name>
|
|
<description>Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_2</name>
|
|
<description>XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP_MODE_CONFIG_3</name>
|
|
<description>XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCON_HIGH_SNVS</name>
|
|
<description>This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_0</name>
|
|
<description>Turn on the switch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCON_HIGH_SNVS_1</name>
|
|
<description>Turn off the switch</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_I</name>
|
|
<description>This field determines the bias current in the 24MHz oscillator</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOMINAL</name>
|
|
<description>Nominal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_12_5_PERCENT</name>
|
|
<description>Decrease current by 12.5%</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_25_PERCENT</name>
|
|
<description>Decrease current by 25.0%</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MINUS_37_5_PERCENT</name>
|
|
<description>Decrease current by 37.5%</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK</name>
|
|
<description>Status bit that signals that the output of the 24-MHz crystal oscillator is stable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OSC_XTALOK_EN</name>
|
|
<description>This bit enables the detector that signals when the 24MHz crystal oscillator is stable.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_CTRL</name>
|
|
<description>This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALLOW_AUTO_GATE</name>
|
|
<description>Allow the logic to automatically gate the clock when the XTAL is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_AUTO_GATE</name>
|
|
<description>Prevent the logic from ever gating off the clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE_DELAY</name>
|
|
<description>This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_0</name>
|
|
<description>0.5ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_1</name>
|
|
<description>1.0ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_2</name>
|
|
<description>2.0ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_3</name>
|
|
<description>3.0ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_4</name>
|
|
<description>4.0ms</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_5</name>
|
|
<description>5.0ms</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_6</name>
|
|
<description>6.0ms</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKGATE_DELAY_7</name>
|
|
<description>7.0ms</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_XTAL_SOURCE</name>
|
|
<description>This field indicates which chip source is being used for the rtc clock.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_0</name>
|
|
<description>Internal ring oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTC_XTAL_SOURCE_1</name>
|
|
<description>RTC_XTAL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTAL_24M_PWD</name>
|
|
<description>This field powers down the 24M crystal oscillator if set true.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VID_PLL_PREDIV</name>
|
|
<description>Predivider for the source clock of the PLL's. Not related to oscillator.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VID_PLL_PREDIV_0</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VID_PLL_PREDIV_1</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOWPWR_CTRL</name>
|
|
<description>XTAL OSC (LP) Control Register</description>
|
|
<addressOffset>0x270</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RC_OSC_EN</name>
|
|
<description>RC Osc. enable control.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RC_OSC_EN_0</name>
|
|
<description>Use XTAL OSC to source the 24MHz clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RC_OSC_EN_1</name>
|
|
<description>Use RC OSC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_SEL</name>
|
|
<description>Select the source for the 24MHz clock.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OSC_SEL_0</name>
|
|
<description>XTAL OSC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSC_SEL_1</name>
|
|
<description>RC OSC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPBG_SEL</name>
|
|
<description>Bandgap select. Not related to oscillator.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPBG_SEL_0</name>
|
|
<description>Normal power bandgap</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPBG_SEL_1</name>
|
|
<description>Low power bandgap</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPBG_TEST</name>
|
|
<description>Low power bandgap test bit. Not related to oscillator.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_IBIAS_OFF</name>
|
|
<description>Low power reftop ibias disable. Not related to oscillator.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>L1_PWRGATE</name>
|
|
<description>L1 power gate control. Used as software override. Not related to oscillator.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>L2_PWRGATE</name>
|
|
<description>L2 power gate control. Used as software override. Not related to oscillator.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPU_PWRGATE</name>
|
|
<description>CPU power gate control. Used as software override. Test purpose only Not related to oscillator.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISPLAY_PWRGATE</name>
|
|
<description>Display logic power gate control. Used as software override. Not related to oscillator.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RCOSC_CG_OVERRIDE</name>
|
|
<description>For debug purposes only</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XTALOSC_PWRUP_DELAY</name>
|
|
<description>Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_0</name>
|
|
<description>0.25ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_1</name>
|
|
<description>0.5ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_2</name>
|
|
<description>1ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_3</name>
|
|
<description>2ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTALOSC_PWRUP_STAT</name>
|
|
<description>Status of the 24MHz xtal oscillator.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_STAT_0</name>
|
|
<description>Not stable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_STAT_1</name>
|
|
<description>Stable and ready to use</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MIX_PWRGATE</name>
|
|
<description>Display power gate control. Used as software mask. Set to zero to force ungated.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GPU_PWRGATE</name>
|
|
<description>GPU power gate control. Used as software mask. Set to zero to force ungated.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOWPWR_CTRL_SET</name>
|
|
<description>XTAL OSC (LP) Control Register</description>
|
|
<addressOffset>0x274</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RC_OSC_EN</name>
|
|
<description>RC Osc. enable control.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RC_OSC_EN_0</name>
|
|
<description>Use XTAL OSC to source the 24MHz clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RC_OSC_EN_1</name>
|
|
<description>Use RC OSC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_SEL</name>
|
|
<description>Select the source for the 24MHz clock.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OSC_SEL_0</name>
|
|
<description>XTAL OSC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSC_SEL_1</name>
|
|
<description>RC OSC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPBG_SEL</name>
|
|
<description>Bandgap select. Not related to oscillator.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPBG_SEL_0</name>
|
|
<description>Normal power bandgap</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPBG_SEL_1</name>
|
|
<description>Low power bandgap</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPBG_TEST</name>
|
|
<description>Low power bandgap test bit. Not related to oscillator.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_IBIAS_OFF</name>
|
|
<description>Low power reftop ibias disable. Not related to oscillator.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>L1_PWRGATE</name>
|
|
<description>L1 power gate control. Used as software override. Not related to oscillator.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>L2_PWRGATE</name>
|
|
<description>L2 power gate control. Used as software override. Not related to oscillator.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPU_PWRGATE</name>
|
|
<description>CPU power gate control. Used as software override. Test purpose only Not related to oscillator.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISPLAY_PWRGATE</name>
|
|
<description>Display logic power gate control. Used as software override. Not related to oscillator.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RCOSC_CG_OVERRIDE</name>
|
|
<description>For debug purposes only</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XTALOSC_PWRUP_DELAY</name>
|
|
<description>Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_0</name>
|
|
<description>0.25ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_1</name>
|
|
<description>0.5ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_2</name>
|
|
<description>1ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_3</name>
|
|
<description>2ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTALOSC_PWRUP_STAT</name>
|
|
<description>Status of the 24MHz xtal oscillator.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_STAT_0</name>
|
|
<description>Not stable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_STAT_1</name>
|
|
<description>Stable and ready to use</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MIX_PWRGATE</name>
|
|
<description>Display power gate control. Used as software mask. Set to zero to force ungated.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GPU_PWRGATE</name>
|
|
<description>GPU power gate control. Used as software mask. Set to zero to force ungated.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOWPWR_CTRL_CLR</name>
|
|
<description>XTAL OSC (LP) Control Register</description>
|
|
<addressOffset>0x278</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RC_OSC_EN</name>
|
|
<description>RC Osc. enable control.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RC_OSC_EN_0</name>
|
|
<description>Use XTAL OSC to source the 24MHz clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RC_OSC_EN_1</name>
|
|
<description>Use RC OSC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_SEL</name>
|
|
<description>Select the source for the 24MHz clock.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OSC_SEL_0</name>
|
|
<description>XTAL OSC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSC_SEL_1</name>
|
|
<description>RC OSC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPBG_SEL</name>
|
|
<description>Bandgap select. Not related to oscillator.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPBG_SEL_0</name>
|
|
<description>Normal power bandgap</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPBG_SEL_1</name>
|
|
<description>Low power bandgap</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPBG_TEST</name>
|
|
<description>Low power bandgap test bit. Not related to oscillator.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_IBIAS_OFF</name>
|
|
<description>Low power reftop ibias disable. Not related to oscillator.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>L1_PWRGATE</name>
|
|
<description>L1 power gate control. Used as software override. Not related to oscillator.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>L2_PWRGATE</name>
|
|
<description>L2 power gate control. Used as software override. Not related to oscillator.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPU_PWRGATE</name>
|
|
<description>CPU power gate control. Used as software override. Test purpose only Not related to oscillator.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISPLAY_PWRGATE</name>
|
|
<description>Display logic power gate control. Used as software override. Not related to oscillator.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RCOSC_CG_OVERRIDE</name>
|
|
<description>For debug purposes only</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XTALOSC_PWRUP_DELAY</name>
|
|
<description>Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_0</name>
|
|
<description>0.25ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_1</name>
|
|
<description>0.5ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_2</name>
|
|
<description>1ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_3</name>
|
|
<description>2ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTALOSC_PWRUP_STAT</name>
|
|
<description>Status of the 24MHz xtal oscillator.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_STAT_0</name>
|
|
<description>Not stable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_STAT_1</name>
|
|
<description>Stable and ready to use</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MIX_PWRGATE</name>
|
|
<description>Display power gate control. Used as software mask. Set to zero to force ungated.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GPU_PWRGATE</name>
|
|
<description>GPU power gate control. Used as software mask. Set to zero to force ungated.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOWPWR_CTRL_TOG</name>
|
|
<description>XTAL OSC (LP) Control Register</description>
|
|
<addressOffset>0x27C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RC_OSC_EN</name>
|
|
<description>RC Osc. enable control.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RC_OSC_EN_0</name>
|
|
<description>Use XTAL OSC to source the 24MHz clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RC_OSC_EN_1</name>
|
|
<description>Use RC OSC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSC_SEL</name>
|
|
<description>Select the source for the 24MHz clock.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OSC_SEL_0</name>
|
|
<description>XTAL OSC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSC_SEL_1</name>
|
|
<description>RC OSC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPBG_SEL</name>
|
|
<description>Bandgap select. Not related to oscillator.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPBG_SEL_0</name>
|
|
<description>Normal power bandgap</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPBG_SEL_1</name>
|
|
<description>Low power bandgap</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPBG_TEST</name>
|
|
<description>Low power bandgap test bit. Not related to oscillator.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFTOP_IBIAS_OFF</name>
|
|
<description>Low power reftop ibias disable. Not related to oscillator.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>L1_PWRGATE</name>
|
|
<description>L1 power gate control. Used as software override. Not related to oscillator.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>L2_PWRGATE</name>
|
|
<description>L2 power gate control. Used as software override. Not related to oscillator.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPU_PWRGATE</name>
|
|
<description>CPU power gate control. Used as software override. Test purpose only Not related to oscillator.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISPLAY_PWRGATE</name>
|
|
<description>Display logic power gate control. Used as software override. Not related to oscillator.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RCOSC_CG_OVERRIDE</name>
|
|
<description>For debug purposes only</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XTALOSC_PWRUP_DELAY</name>
|
|
<description>Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_0</name>
|
|
<description>0.25ms</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_1</name>
|
|
<description>0.5ms</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_2</name>
|
|
<description>1ms</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_DELAY_3</name>
|
|
<description>2ms</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTALOSC_PWRUP_STAT</name>
|
|
<description>Status of the 24MHz xtal oscillator.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_STAT_0</name>
|
|
<description>Not stable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>XTALOSC_PWRUP_STAT_1</name>
|
|
<description>Stable and ready to use</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MIX_PWRGATE</name>
|
|
<description>Display power gate control. Used as software mask. Set to zero to force ungated.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GPU_PWRGATE</name>
|
|
<description>GPU power gate control. Used as software mask. Set to zero to force ungated.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC_CONFIG0</name>
|
|
<description>XTAL OSC Configuration 0 Register</description>
|
|
<addressOffset>0x2A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1020</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enables the tuning logic to calculate new RC tuning values</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypasses any calculated RC tuning value and uses the programmed register value.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INVERT</name>
|
|
<description>Invert the stepping of the calculated RC tuning value.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RC_OSC_PROG</name>
|
|
<description>RC osc. tuning values.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST_PLUS</name>
|
|
<description>Positive hysteresis value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST_MINUS</name>
|
|
<description>Negative hysteresis value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RC_OSC_PROG_CUR</name>
|
|
<description>The current tuning value in use.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC_CONFIG0_SET</name>
|
|
<description>XTAL OSC Configuration 0 Register</description>
|
|
<addressOffset>0x2A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1020</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enables the tuning logic to calculate new RC tuning values</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypasses any calculated RC tuning value and uses the programmed register value.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INVERT</name>
|
|
<description>Invert the stepping of the calculated RC tuning value.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RC_OSC_PROG</name>
|
|
<description>RC osc. tuning values.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST_PLUS</name>
|
|
<description>Positive hysteresis value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST_MINUS</name>
|
|
<description>Negative hysteresis value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RC_OSC_PROG_CUR</name>
|
|
<description>The current tuning value in use.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC_CONFIG0_CLR</name>
|
|
<description>XTAL OSC Configuration 0 Register</description>
|
|
<addressOffset>0x2A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1020</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enables the tuning logic to calculate new RC tuning values</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypasses any calculated RC tuning value and uses the programmed register value.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INVERT</name>
|
|
<description>Invert the stepping of the calculated RC tuning value.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RC_OSC_PROG</name>
|
|
<description>RC osc. tuning values.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST_PLUS</name>
|
|
<description>Positive hysteresis value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST_MINUS</name>
|
|
<description>Negative hysteresis value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RC_OSC_PROG_CUR</name>
|
|
<description>The current tuning value in use.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC_CONFIG0_TOG</name>
|
|
<description>XTAL OSC Configuration 0 Register</description>
|
|
<addressOffset>0x2AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1020</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enables the tuning logic to calculate new RC tuning values</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypasses any calculated RC tuning value and uses the programmed register value.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INVERT</name>
|
|
<description>Invert the stepping of the calculated RC tuning value.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RC_OSC_PROG</name>
|
|
<description>RC osc. tuning values.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST_PLUS</name>
|
|
<description>Positive hysteresis value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST_MINUS</name>
|
|
<description>Negative hysteresis value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RC_OSC_PROG_CUR</name>
|
|
<description>The current tuning value in use.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC_CONFIG1</name>
|
|
<description>XTAL OSC Configuration 1 Register</description>
|
|
<addressOffset>0x2B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2EE</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT_RC_TRG</name>
|
|
<description>The target count used to tune the RC OSC frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COUNT_RC_CUR</name>
|
|
<description>The current tuning value in use.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC_CONFIG1_SET</name>
|
|
<description>XTAL OSC Configuration 1 Register</description>
|
|
<addressOffset>0x2B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2EE</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT_RC_TRG</name>
|
|
<description>The target count used to tune the RC OSC frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COUNT_RC_CUR</name>
|
|
<description>The current tuning value in use.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC_CONFIG1_CLR</name>
|
|
<description>XTAL OSC Configuration 1 Register</description>
|
|
<addressOffset>0x2B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2EE</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT_RC_TRG</name>
|
|
<description>The target count used to tune the RC OSC frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COUNT_RC_CUR</name>
|
|
<description>The current tuning value in use.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC_CONFIG1_TOG</name>
|
|
<description>XTAL OSC Configuration 1 Register</description>
|
|
<addressOffset>0x2BC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2EE</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT_RC_TRG</name>
|
|
<description>The target count used to tune the RC OSC frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COUNT_RC_CUR</name>
|
|
<description>The current tuning value in use.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC_CONFIG2</name>
|
|
<description>XTAL OSC Configuration 2 Register</description>
|
|
<addressOffset>0x2C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x102E2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT_1M_TRG</name>
|
|
<description>The target count used to tune the 1MHz clock frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_1M</name>
|
|
<description>Enable the 1MHz clock output. 0 - disabled; 1 - enabled.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MUX_1M</name>
|
|
<description>Mux the corrected or uncorrected 1MHz clock to the output</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLK_1M_ERR_FL</name>
|
|
<description>Flag indicates that the count_1m count wasn't reached within 1 32kHz period</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC_CONFIG2_SET</name>
|
|
<description>XTAL OSC Configuration 2 Register</description>
|
|
<addressOffset>0x2C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x102E2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT_1M_TRG</name>
|
|
<description>The target count used to tune the 1MHz clock frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_1M</name>
|
|
<description>Enable the 1MHz clock output. 0 - disabled; 1 - enabled.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MUX_1M</name>
|
|
<description>Mux the corrected or uncorrected 1MHz clock to the output</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLK_1M_ERR_FL</name>
|
|
<description>Flag indicates that the count_1m count wasn't reached within 1 32kHz period</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC_CONFIG2_CLR</name>
|
|
<description>XTAL OSC Configuration 2 Register</description>
|
|
<addressOffset>0x2C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x102E2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT_1M_TRG</name>
|
|
<description>The target count used to tune the 1MHz clock frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_1M</name>
|
|
<description>Enable the 1MHz clock output. 0 - disabled; 1 - enabled.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MUX_1M</name>
|
|
<description>Mux the corrected or uncorrected 1MHz clock to the output</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLK_1M_ERR_FL</name>
|
|
<description>Flag indicates that the count_1m count wasn't reached within 1 32kHz period</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSC_CONFIG2_TOG</name>
|
|
<description>XTAL OSC Configuration 2 Register</description>
|
|
<addressOffset>0x2CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x102E2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT_1M_TRG</name>
|
|
<description>The target count used to tune the 1MHz clock frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_1M</name>
|
|
<description>Enable the 1MHz clock output. 0 - disabled; 1 - enabled.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MUX_1M</name>
|
|
<description>Mux the corrected or uncorrected 1MHz clock to the output</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLK_1M_ERR_FL</name>
|
|
<description>Flag indicates that the count_1m count wasn't reached within 1 32kHz period</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USBPHY</name>
|
|
<description>USBPHY Register Reference Index</description>
|
|
<groupName>USBPHY</groupName>
|
|
<prependToName>USBPHY_</prependToName>
|
|
<baseAddress>0x400D9000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x84</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USB_PHY</name>
|
|
<value>65</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PWD</name>
|
|
<description>USB PHY Power-Down Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1E1C00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPWDFS</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPWDIBIAS</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPWDV2I</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWDENV</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWD1PT1</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWDDIFF</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWDRX</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWD_SET</name>
|
|
<description>USB PHY Power-Down Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1E1C00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPWDFS</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPWDIBIAS</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPWDV2I</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWDENV</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWD1PT1</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWDDIFF</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWDRX</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWD_CLR</name>
|
|
<description>USB PHY Power-Down Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1E1C00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPWDFS</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPWDIBIAS</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPWDV2I</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWDENV</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWD1PT1</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWDDIFF</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWDRX</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWD_TOG</name>
|
|
<description>USB PHY Power-Down Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1E1C00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPWDFS</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPWDIBIAS</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPWDV2I</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWDENV</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWD1PT1</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWDDIFF</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXPWDRX</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX</name>
|
|
<description>USB PHY Transmitter Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10060607</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>D_CAL</name>
|
|
<description>Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved. Note: This bit should remain clear.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCAL45DN</name>
|
|
<description>Decode to select a 45-Ohm resistance to the USB_DN output pin</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved. Note: This bit should remain clear.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCAL45DP</name>
|
|
<description>Decode to select a 45-Ohm resistance to the USB_DP output pin</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USBPHY_TX_EDGECTRL</name>
|
|
<description>Controls the edge-rate of the current sensing transistors used in HS transmit</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD5</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX_SET</name>
|
|
<description>USB PHY Transmitter Control Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10060607</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>D_CAL</name>
|
|
<description>Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved. Note: This bit should remain clear.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCAL45DN</name>
|
|
<description>Decode to select a 45-Ohm resistance to the USB_DN output pin</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved. Note: This bit should remain clear.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCAL45DP</name>
|
|
<description>Decode to select a 45-Ohm resistance to the USB_DP output pin</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USBPHY_TX_EDGECTRL</name>
|
|
<description>Controls the edge-rate of the current sensing transistors used in HS transmit</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD5</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX_CLR</name>
|
|
<description>USB PHY Transmitter Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10060607</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>D_CAL</name>
|
|
<description>Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved. Note: This bit should remain clear.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCAL45DN</name>
|
|
<description>Decode to select a 45-Ohm resistance to the USB_DN output pin</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved. Note: This bit should remain clear.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCAL45DP</name>
|
|
<description>Decode to select a 45-Ohm resistance to the USB_DP output pin</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USBPHY_TX_EDGECTRL</name>
|
|
<description>Controls the edge-rate of the current sensing transistors used in HS transmit</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD5</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX_TOG</name>
|
|
<description>USB PHY Transmitter Control Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10060607</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>D_CAL</name>
|
|
<description>Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved. Note: This bit should remain clear.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCAL45DN</name>
|
|
<description>Decode to select a 45-Ohm resistance to the USB_DN output pin</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved. Note: This bit should remain clear.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCAL45DP</name>
|
|
<description>Decode to select a 45-Ohm resistance to the USB_DP output pin</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USBPHY_TX_EDGECTRL</name>
|
|
<description>Controls the edge-rate of the current sensing transistors used in HS transmit</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD5</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX</name>
|
|
<description>USB PHY Receiver Control Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENVADJ</name>
|
|
<description>The ENVADJ field adjusts the trip point for the envelope detector</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCONADJ</name>
|
|
<description>The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDBYPASS</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX_SET</name>
|
|
<description>USB PHY Receiver Control Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENVADJ</name>
|
|
<description>The ENVADJ field adjusts the trip point for the envelope detector</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCONADJ</name>
|
|
<description>The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDBYPASS</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX_CLR</name>
|
|
<description>USB PHY Receiver Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENVADJ</name>
|
|
<description>The ENVADJ field adjusts the trip point for the envelope detector</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCONADJ</name>
|
|
<description>The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDBYPASS</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX_TOG</name>
|
|
<description>USB PHY Receiver Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENVADJ</name>
|
|
<description>The ENVADJ field adjusts the trip point for the envelope detector</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCONADJ</name>
|
|
<description>The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXDBYPASS</name>
|
|
<description>0 = Normal operation</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>USB PHY General Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0200000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENOTG_ID_CHG_IRQ</name>
|
|
<description>Enable OTG_ID_CHG_IRQ.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENHOSTDISCONDETECT</name>
|
|
<description>For host mode, enables high-speed disconnect detector</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQHOSTDISCON</name>
|
|
<description>Enables interrupt for detection of disconnection to Device when in high-speed host mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOSTDISCONDETECT_IRQ</name>
|
|
<description>Indicates that the device has disconnected in high-speed mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDEVPLUGINDETECT</name>
|
|
<description>For device mode, enables 200-KOhm pullups for detecting connectivity to the host.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVPLUGIN_POLARITY</name>
|
|
<description>For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OTG_ID_CHG_IRQ</name>
|
|
<description>OTG ID change interrupt. Indicates the value of ID pin changed.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENOTGIDDETECT</name>
|
|
<description>Enables circuit to detect resistance of MiniAB ID pin.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESUMEIRQSTICKY</name>
|
|
<description>Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQRESUMEDETECT</name>
|
|
<description>Enables interrupt for detection of a non-J state on the USB line</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESUME_IRQ</name>
|
|
<description>Indicates that the host is sending a wake-up after suspend</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQDEVPLUGIN</name>
|
|
<description>Enables interrupt for the detection of connectivity to the USB line.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVPLUGIN_IRQ</name>
|
|
<description>Indicates that the device is connected</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA_ON_LRADC</name>
|
|
<description>Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUTMILEVEL2</name>
|
|
<description>Enables UTMI+ Level2. This should be enabled if needs to support LS device</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUTMILEVEL3</name>
|
|
<description>Enables UTMI+ Level3</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQWAKEUP</name>
|
|
<description>Enables interrupt for the wakeup events.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP_IRQ</name>
|
|
<description>Indicates that there is a wakeup event</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAUTO_PWRON_PLL</name>
|
|
<description>Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAUTOCLR_CLKGATE</name>
|
|
<description>Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAUTOCLR_PHY_PWD</name>
|
|
<description>Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDPDMCHG_WKUP</name>
|
|
<description>Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIDCHG_WKUP</name>
|
|
<description>Enables the feature to wakeup USB if ID is toggled when USB is suspended.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENVBUSCHG_WKUP</name>
|
|
<description>Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSDLL_RST_EN</name>
|
|
<description>Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OTG_ID_VALUE</name>
|
|
<description>Almost same as OTGID_STATUS in USBPHYx_STATUS Register</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HOST_FORCE_LS_SE0</name>
|
|
<description>Forces the next FS packet that is transmitted to have a EOP with LS timing</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UTMI_SUSPENDM</name>
|
|
<description>Used by the PHY to indicate a powered-down state</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE</name>
|
|
<description>Gate UTMI Clocks</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFTRST</name>
|
|
<description>Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL_SET</name>
|
|
<description>USB PHY General Control Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0200000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENOTG_ID_CHG_IRQ</name>
|
|
<description>Enable OTG_ID_CHG_IRQ.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENHOSTDISCONDETECT</name>
|
|
<description>For host mode, enables high-speed disconnect detector</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQHOSTDISCON</name>
|
|
<description>Enables interrupt for detection of disconnection to Device when in high-speed host mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOSTDISCONDETECT_IRQ</name>
|
|
<description>Indicates that the device has disconnected in high-speed mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDEVPLUGINDETECT</name>
|
|
<description>For device mode, enables 200-KOhm pullups for detecting connectivity to the host.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVPLUGIN_POLARITY</name>
|
|
<description>For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OTG_ID_CHG_IRQ</name>
|
|
<description>OTG ID change interrupt. Indicates the value of ID pin changed.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENOTGIDDETECT</name>
|
|
<description>Enables circuit to detect resistance of MiniAB ID pin.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESUMEIRQSTICKY</name>
|
|
<description>Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQRESUMEDETECT</name>
|
|
<description>Enables interrupt for detection of a non-J state on the USB line</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESUME_IRQ</name>
|
|
<description>Indicates that the host is sending a wake-up after suspend</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQDEVPLUGIN</name>
|
|
<description>Enables interrupt for the detection of connectivity to the USB line.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVPLUGIN_IRQ</name>
|
|
<description>Indicates that the device is connected</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA_ON_LRADC</name>
|
|
<description>Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUTMILEVEL2</name>
|
|
<description>Enables UTMI+ Level2. This should be enabled if needs to support LS device</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUTMILEVEL3</name>
|
|
<description>Enables UTMI+ Level3</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQWAKEUP</name>
|
|
<description>Enables interrupt for the wakeup events.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP_IRQ</name>
|
|
<description>Indicates that there is a wakeup event</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAUTO_PWRON_PLL</name>
|
|
<description>Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAUTOCLR_CLKGATE</name>
|
|
<description>Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAUTOCLR_PHY_PWD</name>
|
|
<description>Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDPDMCHG_WKUP</name>
|
|
<description>Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIDCHG_WKUP</name>
|
|
<description>Enables the feature to wakeup USB if ID is toggled when USB is suspended.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENVBUSCHG_WKUP</name>
|
|
<description>Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSDLL_RST_EN</name>
|
|
<description>Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OTG_ID_VALUE</name>
|
|
<description>Almost same as OTGID_STATUS in USBPHYx_STATUS Register</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HOST_FORCE_LS_SE0</name>
|
|
<description>Forces the next FS packet that is transmitted to have a EOP with LS timing</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UTMI_SUSPENDM</name>
|
|
<description>Used by the PHY to indicate a powered-down state</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE</name>
|
|
<description>Gate UTMI Clocks</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFTRST</name>
|
|
<description>Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL_CLR</name>
|
|
<description>USB PHY General Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0200000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENOTG_ID_CHG_IRQ</name>
|
|
<description>Enable OTG_ID_CHG_IRQ.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENHOSTDISCONDETECT</name>
|
|
<description>For host mode, enables high-speed disconnect detector</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQHOSTDISCON</name>
|
|
<description>Enables interrupt for detection of disconnection to Device when in high-speed host mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOSTDISCONDETECT_IRQ</name>
|
|
<description>Indicates that the device has disconnected in high-speed mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDEVPLUGINDETECT</name>
|
|
<description>For device mode, enables 200-KOhm pullups for detecting connectivity to the host.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVPLUGIN_POLARITY</name>
|
|
<description>For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OTG_ID_CHG_IRQ</name>
|
|
<description>OTG ID change interrupt. Indicates the value of ID pin changed.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENOTGIDDETECT</name>
|
|
<description>Enables circuit to detect resistance of MiniAB ID pin.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESUMEIRQSTICKY</name>
|
|
<description>Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQRESUMEDETECT</name>
|
|
<description>Enables interrupt for detection of a non-J state on the USB line</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESUME_IRQ</name>
|
|
<description>Indicates that the host is sending a wake-up after suspend</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQDEVPLUGIN</name>
|
|
<description>Enables interrupt for the detection of connectivity to the USB line.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVPLUGIN_IRQ</name>
|
|
<description>Indicates that the device is connected</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA_ON_LRADC</name>
|
|
<description>Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUTMILEVEL2</name>
|
|
<description>Enables UTMI+ Level2. This should be enabled if needs to support LS device</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUTMILEVEL3</name>
|
|
<description>Enables UTMI+ Level3</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQWAKEUP</name>
|
|
<description>Enables interrupt for the wakeup events.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP_IRQ</name>
|
|
<description>Indicates that there is a wakeup event</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAUTO_PWRON_PLL</name>
|
|
<description>Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAUTOCLR_CLKGATE</name>
|
|
<description>Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAUTOCLR_PHY_PWD</name>
|
|
<description>Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDPDMCHG_WKUP</name>
|
|
<description>Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIDCHG_WKUP</name>
|
|
<description>Enables the feature to wakeup USB if ID is toggled when USB is suspended.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENVBUSCHG_WKUP</name>
|
|
<description>Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSDLL_RST_EN</name>
|
|
<description>Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OTG_ID_VALUE</name>
|
|
<description>Almost same as OTGID_STATUS in USBPHYx_STATUS Register</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HOST_FORCE_LS_SE0</name>
|
|
<description>Forces the next FS packet that is transmitted to have a EOP with LS timing</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UTMI_SUSPENDM</name>
|
|
<description>Used by the PHY to indicate a powered-down state</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE</name>
|
|
<description>Gate UTMI Clocks</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFTRST</name>
|
|
<description>Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL_TOG</name>
|
|
<description>USB PHY General Control Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0200000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENOTG_ID_CHG_IRQ</name>
|
|
<description>Enable OTG_ID_CHG_IRQ.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENHOSTDISCONDETECT</name>
|
|
<description>For host mode, enables high-speed disconnect detector</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQHOSTDISCON</name>
|
|
<description>Enables interrupt for detection of disconnection to Device when in high-speed host mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOSTDISCONDETECT_IRQ</name>
|
|
<description>Indicates that the device has disconnected in high-speed mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDEVPLUGINDETECT</name>
|
|
<description>For device mode, enables 200-KOhm pullups for detecting connectivity to the host.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVPLUGIN_POLARITY</name>
|
|
<description>For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OTG_ID_CHG_IRQ</name>
|
|
<description>OTG ID change interrupt. Indicates the value of ID pin changed.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENOTGIDDETECT</name>
|
|
<description>Enables circuit to detect resistance of MiniAB ID pin.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESUMEIRQSTICKY</name>
|
|
<description>Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQRESUMEDETECT</name>
|
|
<description>Enables interrupt for detection of a non-J state on the USB line</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESUME_IRQ</name>
|
|
<description>Indicates that the host is sending a wake-up after suspend</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQDEVPLUGIN</name>
|
|
<description>Enables interrupt for the detection of connectivity to the USB line.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVPLUGIN_IRQ</name>
|
|
<description>Indicates that the device is connected</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATA_ON_LRADC</name>
|
|
<description>Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUTMILEVEL2</name>
|
|
<description>Enables UTMI+ Level2. This should be enabled if needs to support LS device</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUTMILEVEL3</name>
|
|
<description>Enables UTMI+ Level3</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIRQWAKEUP</name>
|
|
<description>Enables interrupt for the wakeup events.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP_IRQ</name>
|
|
<description>Indicates that there is a wakeup event</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAUTO_PWRON_PLL</name>
|
|
<description>Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAUTOCLR_CLKGATE</name>
|
|
<description>Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENAUTOCLR_PHY_PWD</name>
|
|
<description>Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDPDMCHG_WKUP</name>
|
|
<description>Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENIDCHG_WKUP</name>
|
|
<description>Enables the feature to wakeup USB if ID is toggled when USB is suspended.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENVBUSCHG_WKUP</name>
|
|
<description>Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSDLL_RST_EN</name>
|
|
<description>Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OTG_ID_VALUE</name>
|
|
<description>Almost same as OTGID_STATUS in USBPHYx_STATUS Register</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HOST_FORCE_LS_SE0</name>
|
|
<description>Forces the next FS packet that is transmitted to have a EOP with LS timing</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UTMI_SUSPENDM</name>
|
|
<description>Used by the PHY to indicate a powered-down state</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE</name>
|
|
<description>Gate UTMI Clocks</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFTRST</name>
|
|
<description>Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>USB PHY Status Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HOSTDISCONDETECT_STATUS</name>
|
|
<description>Indicates that the device has disconnected while in high-speed host mode.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DEVPLUGIN_STATUS</name>
|
|
<description>Indicates that the device has been connected on the USB_DP and USB_DM lines.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OTGID_STATUS</name>
|
|
<description>Indicates the results of ID pin on MiniAB plug</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD3</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RESUME_STATUS</name>
|
|
<description>Indicates that the host is sending a wake-up after suspend and has triggered an interrupt.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD4</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>21</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG</name>
|
|
<description>USB PHY Debug Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7F180000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OTGIDPIOLOCK</name>
|
|
<description>Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBUG_INTERFACE_HOLD</name>
|
|
<description>Use holding registers to assist in timing for external UTMI interface.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSTPULLDOWN</name>
|
|
<description>Set bit 3 to 1 to pull down 15-KOhm on USB_DP line</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENHSTPULLDOWN</name>
|
|
<description>Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX2RXCOUNT</name>
|
|
<description>Delay in between the end of transmit to the beginning of receive</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENTX2RXCOUNT</name>
|
|
<description>Set this bit to allow a countdown to transition in between TX and RX.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SQUELCHRESETCOUNT</name>
|
|
<description>Delay in between the detection of squelch to the reset of high-speed RX.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENSQUELCHRESET</name>
|
|
<description>Set bit to allow squelch to reset high-speed receive.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQUELCHRESETLENGTH</name>
|
|
<description>Duration of RESET in terms of the number of 480-MHz cycles.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOST_RESUME_DEBUG</name>
|
|
<description>Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE</name>
|
|
<description>Gate Test Clocks</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD3</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG_SET</name>
|
|
<description>USB PHY Debug Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7F180000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OTGIDPIOLOCK</name>
|
|
<description>Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBUG_INTERFACE_HOLD</name>
|
|
<description>Use holding registers to assist in timing for external UTMI interface.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSTPULLDOWN</name>
|
|
<description>Set bit 3 to 1 to pull down 15-KOhm on USB_DP line</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENHSTPULLDOWN</name>
|
|
<description>Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX2RXCOUNT</name>
|
|
<description>Delay in between the end of transmit to the beginning of receive</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENTX2RXCOUNT</name>
|
|
<description>Set this bit to allow a countdown to transition in between TX and RX.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SQUELCHRESETCOUNT</name>
|
|
<description>Delay in between the detection of squelch to the reset of high-speed RX.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENSQUELCHRESET</name>
|
|
<description>Set bit to allow squelch to reset high-speed receive.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQUELCHRESETLENGTH</name>
|
|
<description>Duration of RESET in terms of the number of 480-MHz cycles.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOST_RESUME_DEBUG</name>
|
|
<description>Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE</name>
|
|
<description>Gate Test Clocks</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD3</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG_CLR</name>
|
|
<description>USB PHY Debug Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7F180000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OTGIDPIOLOCK</name>
|
|
<description>Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBUG_INTERFACE_HOLD</name>
|
|
<description>Use holding registers to assist in timing for external UTMI interface.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSTPULLDOWN</name>
|
|
<description>Set bit 3 to 1 to pull down 15-KOhm on USB_DP line</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENHSTPULLDOWN</name>
|
|
<description>Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX2RXCOUNT</name>
|
|
<description>Delay in between the end of transmit to the beginning of receive</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENTX2RXCOUNT</name>
|
|
<description>Set this bit to allow a countdown to transition in between TX and RX.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SQUELCHRESETCOUNT</name>
|
|
<description>Delay in between the detection of squelch to the reset of high-speed RX.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENSQUELCHRESET</name>
|
|
<description>Set bit to allow squelch to reset high-speed receive.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQUELCHRESETLENGTH</name>
|
|
<description>Duration of RESET in terms of the number of 480-MHz cycles.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOST_RESUME_DEBUG</name>
|
|
<description>Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE</name>
|
|
<description>Gate Test Clocks</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD3</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG_TOG</name>
|
|
<description>USB PHY Debug Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7F180000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OTGIDPIOLOCK</name>
|
|
<description>Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DEBUG_INTERFACE_HOLD</name>
|
|
<description>Use holding registers to assist in timing for external UTMI interface.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSTPULLDOWN</name>
|
|
<description>Set bit 3 to 1 to pull down 15-KOhm on USB_DP line</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENHSTPULLDOWN</name>
|
|
<description>Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TX2RXCOUNT</name>
|
|
<description>Delay in between the end of transmit to the beginning of receive</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENTX2RXCOUNT</name>
|
|
<description>Set this bit to allow a countdown to transition in between TX and RX.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SQUELCHRESETCOUNT</name>
|
|
<description>Delay in between the detection of squelch to the reset of high-speed RX.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD2</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENSQUELCHRESET</name>
|
|
<description>Set bit to allow squelch to reset high-speed receive.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQUELCHRESETLENGTH</name>
|
|
<description>Duration of RESET in terms of the number of 480-MHz cycles.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HOST_RESUME_DEBUG</name>
|
|
<description>Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE</name>
|
|
<description>Gate Test Clocks</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD3</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG0_STATUS</name>
|
|
<description>UTMI Debug Status Register 0</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOOP_BACK_FAIL_COUNT</name>
|
|
<description>Running count of the failed pseudo-random generator loopback</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UTMI_RXERROR_FAIL_COUNT</name>
|
|
<description>Running count of the UTMI_RXERROR.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SQUELCH_COUNT</name>
|
|
<description>Running count of the squelch reset instead of normal end for HS RX.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG1</name>
|
|
<description>UTMI Debug Status Register 1</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved. Note: This bit should remain clear.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENTAILADJVD</name>
|
|
<description>Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG1_SET</name>
|
|
<description>UTMI Debug Status Register 1</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved. Note: This bit should remain clear.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENTAILADJVD</name>
|
|
<description>Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG1_CLR</name>
|
|
<description>UTMI Debug Status Register 1</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved. Note: This bit should remain clear.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENTAILADJVD</name>
|
|
<description>Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG1_TOG</name>
|
|
<description>UTMI Debug Status Register 1</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSVD0</name>
|
|
<description>Reserved. Note: This bit should remain clear.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENTAILADJVD</name>
|
|
<description>Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSVD1</name>
|
|
<description>Reserved.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VERSION</name>
|
|
<description>UTMI RTL Version</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4030000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STEP</name>
|
|
<description>Fixed read-only value reflecting the stepping of the RTL version.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Fixed read-only value reflecting the MINOR field of the RTL version.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Fixed read-only value reflecting the MAJOR field of the RTL version.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CSU</name>
|
|
<description>CSU registers</description>
|
|
<groupName>CSU</groupName>
|
|
<prependToName>CSU_</prependToName>
|
|
<baseAddress>0x400DC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x35C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CSU</name>
|
|
<value>49</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>32</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31</dimIndex>
|
|
<name>CSL%s</name>
|
|
<description>Config security level register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x330033</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SUR_S2</name>
|
|
<description>Secure user read access control for the second slave</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SUR_S2_0</name>
|
|
<description>The secure user read access is disabled for the second slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUR_S2_1</name>
|
|
<description>The secure user read access is enabled for the second slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSR_S2</name>
|
|
<description>Secure supervisor read access control for the second slave</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSR_S2_0</name>
|
|
<description>The secure supervisor read access is disabled for the second slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSR_S2_1</name>
|
|
<description>The secure supervisor read access is enabled for the second slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NUR_S2</name>
|
|
<description>Non-secure user read access control for the second slave</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NUR_S2_0</name>
|
|
<description>The non-secure user read access is disabled for the second slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NUR_S2_1</name>
|
|
<description>The non-secure user read access is enabled for the second slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSR_S2</name>
|
|
<description>Non-secure supervisor read access control for the second slave</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSR_S2_0</name>
|
|
<description>The non-secure supervisor read access is disabled for the second slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSR_S2_1</name>
|
|
<description>The non-secure supervisor read access is enabled for the second slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUW_S2</name>
|
|
<description>Secure user write access control for the second slave</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SUW_S2_0</name>
|
|
<description>The secure user write access is disabled for the second slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUW_S2_1</name>
|
|
<description>The secure user write access is enabled for the second slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSW_S2</name>
|
|
<description>Secure supervisor write access control for the second slave</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSW_S2_0</name>
|
|
<description>The secure supervisor write access is disabled for the second slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSW_S2_1</name>
|
|
<description>The secure supervisor write access is enabled for the second slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NUW_S2</name>
|
|
<description>Non-secure user write access control for the second slave</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NUW_S2_0</name>
|
|
<description>The non-secure user write access is disabled for the second slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NUW_S2_1</name>
|
|
<description>The non-secure user write access is enabled for the second slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSW_S2</name>
|
|
<description>Non-secure supervisor write access control for the second slave</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSW_S2_0</name>
|
|
<description>The non-secure supervisor write access is disabled for the second slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSW_S2_1</name>
|
|
<description>The non-secure supervisor write access is enabled for the second slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_S2</name>
|
|
<description>The lock bit corresponding to the second slave. It is written by the secure software.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_S2_0</name>
|
|
<description>Not locked. Bits 7-0 can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_S2_1</name>
|
|
<description>Bits 7-0 are locked and cannot be written by the software</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUR_S1</name>
|
|
<description>Secure user read access control for the first slave</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SUR_S1_0</name>
|
|
<description>The secure user read access is disabled for the first slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUR_S1_1</name>
|
|
<description>The secure user read access is enabled for the first slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSR_S1</name>
|
|
<description>Secure supervisor read access control for the first slave</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSR_S1_0</name>
|
|
<description>The secure supervisor read access is disabled for the first slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSR_S1_1</name>
|
|
<description>The secure supervisor read access is enabled for the first slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NUR_S1</name>
|
|
<description>Non-secure user read access control for the first slave</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NUR_S1_0</name>
|
|
<description>The non-secure user read access is disabled for the first slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NUR_S1_1</name>
|
|
<description>The non-secure user read access is enabled for the first slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSR_S1</name>
|
|
<description>Non-secure supervisor read access control for the first slave</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSR_S1_0</name>
|
|
<description>The non-secure supervisor read access is disabled for the first slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSR_S1_1</name>
|
|
<description>The non-secure supervisor read access is enabled for the first slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUW_S1</name>
|
|
<description>Secure user write access control for the first slave</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SUW_S1_0</name>
|
|
<description>The secure user write access is disabled for the first slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SUW_S1_1</name>
|
|
<description>The secure user write access is enabled for the first slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSW_S1</name>
|
|
<description>Secure supervisor write access control for the first slave</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSW_S1_0</name>
|
|
<description>The secure supervisor write access is disabled for the first slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSW_S1_1</name>
|
|
<description>The secure supervisor write access is enabled for the first slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NUW_S1</name>
|
|
<description>Non-secure user write access control for the first slave</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NUW_S1_0</name>
|
|
<description>The non-secure user write access is disabled for the first slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NUW_S1_1</name>
|
|
<description>The non-secure user write access is enabled for the first slave.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSW_S1</name>
|
|
<description>Non-secure supervisor write access control for the first slave</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSW_S1_0</name>
|
|
<description>The non-secure supervisor write access is disabled for the first slave.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSW_S1_1</name>
|
|
<description>The non-secure supervisor write access is enabled for the first slave</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK_S1</name>
|
|
<description>The lock bit corresponding to the first slave. It is written by the secure software.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOCK_S1_0</name>
|
|
<description>Not locked. The bits 16-23 can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK_S1_1</name>
|
|
<description>The bits 16-23 are locked and can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HP0</name>
|
|
<description>HP0 register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HP_DMA</name>
|
|
<description>Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the eDMA</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HP_DMA_0</name>
|
|
<description>The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP_DMA_1</name>
|
|
<description>The HP register bit is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_DMA</name>
|
|
<description>Lock bit set by the TZ software for the eDMA</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_DMA_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_DMA_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HP_LCDIF</name>
|
|
<description>Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the LCDIF</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HP_LCDIF_0</name>
|
|
<description>The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP_LCDIF_1</name>
|
|
<description>The HP register bit is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_LCDIF</name>
|
|
<description>Lock bit set by the TZ software for the LCDIF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_LCDIF_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_LCDIF_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HP_CSI</name>
|
|
<description>Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the CSI</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HP_CSI_0</name>
|
|
<description>The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP_CSI_1</name>
|
|
<description>The HP register bit is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_CSI</name>
|
|
<description>Lock bit set by the TZ software for the CSI</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_CSI_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_CSI_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HP_PXP</name>
|
|
<description>Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the PXP</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HP_PXP_0</name>
|
|
<description>The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP_PXP_1</name>
|
|
<description>The HP register bit is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_PXP</name>
|
|
<description>Lock bit set by the TZ software for the PXP</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_PXP_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_PXP_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HP_DCP</name>
|
|
<description>Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the DCP</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HP_DCP_0</name>
|
|
<description>The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP_DCP_1</name>
|
|
<description>The HP register bit is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_DCP</name>
|
|
<description>Lock bit set by the TZ software for the DCP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_DCP_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_DCP_1</name>
|
|
<description>Lock-the adjacent (next lower) bit cannot be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HP_ENET</name>
|
|
<description>Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the ENET</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HP_ENET_0</name>
|
|
<description>The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP_ENET_1</name>
|
|
<description>The HP register bit is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_ENET</name>
|
|
<description>Lock bit set by the TZ software for the ENET</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_ENET_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_ENET_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HP_USDHC1</name>
|
|
<description>Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HP_USDHC1_0</name>
|
|
<description>The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP_USDHC1_1</name>
|
|
<description>The HP register bit is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_USDHC1</name>
|
|
<description>Lock bit set by the TZ software for the USDHC1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_USDHC1_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_USDHC1_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HP_USDHC2</name>
|
|
<description>Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HP_USDHC2_0</name>
|
|
<description>The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP_USDHC2_1</name>
|
|
<description>The HP register bit is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_USDHC2</name>
|
|
<description>Lock bit set by the TZ software for the USDHC2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_USDHC2_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_USDHC2_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HP_TPSMP</name>
|
|
<description>Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the TPSMP</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HP_TPSMP_0</name>
|
|
<description>The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP_TPSMP_1</name>
|
|
<description>The HP register bit is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_TPSMP</name>
|
|
<description>Lock bit set by the TZ software for the TPSMP</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_TPSMP_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_TPSMP_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HP_USB</name>
|
|
<description>Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USB</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HP_USB_0</name>
|
|
<description>The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HP_USB_1</name>
|
|
<description>The HP register bit is routed to the csu_hprot1 output for the corresponding master.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_USB</name>
|
|
<description>Lock bit set by the TZ software for the USB</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_USB_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_USB_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SA</name>
|
|
<description>Secure access register</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NSA_DMA</name>
|
|
<description>Non-secure access policy indicator bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSA_DMA_0</name>
|
|
<description>Secure access for the corresponding type-1 master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSA_DMA_1</name>
|
|
<description>Non-secure access for the corresponding type-1 master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_DMA</name>
|
|
<description>Lock bit set by the TZ software for the eDMA</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_DMA_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_DMA_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSA_LCDIF</name>
|
|
<description>Non-secure access policy indicator bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSA_LCDIF_0</name>
|
|
<description>Secure access for the corresponding type-1 master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSA_LCDIF_1</name>
|
|
<description>Non-secure access for the corresponding type-1 master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_LCDIF</name>
|
|
<description>Lock bit set by the TZ software for the LCDIF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_LCDIF_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_LCDIF_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSA_CSI</name>
|
|
<description>Non-secure access policy indicator bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSA_CSI_0</name>
|
|
<description>Secure access for the corresponding type-1 master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSA_CSI_1</name>
|
|
<description>Non-secure access for the corresponding type-1 master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_CSI</name>
|
|
<description>Lock bit set by the TZ software for the CSI</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_CSI_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_CSI_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSA_PXP</name>
|
|
<description>Non-Secure Access Policy indicator bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSA_PXP_0</name>
|
|
<description>Secure access for the corresponding type-1 master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSA_PXP_1</name>
|
|
<description>Non-secure access for the corresponding type-1 master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_PXP</name>
|
|
<description>Lock bit set by the TZ software for the PXP</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_PXP_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_PXP_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSA_DCP</name>
|
|
<description>Non-secure access policy indicator bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSA_DCP_0</name>
|
|
<description>Secure access for the corresponding type-1 master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSA_DCP_1</name>
|
|
<description>Non-secure access for the corresponding type-1 master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_DCP</name>
|
|
<description>Lock bit set by the TZ software for the DCP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_DCP_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_DCP_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSA_ENET</name>
|
|
<description>Non-secure access policy indicator bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSA_ENET_0</name>
|
|
<description>Secure access for the corresponding type-1 master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSA_ENET_1</name>
|
|
<description>Non-secure access for the corresponding type-1 master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_ENET</name>
|
|
<description>Lock bit set by the TZ software for the ENET1 and ENET2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_ENET_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_ENET_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSA_USDHC1</name>
|
|
<description>Non-secure access policy indicator bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSA_USDHC1_0</name>
|
|
<description>Secure access for the corresponding type-1 master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSA_USDHC1_1</name>
|
|
<description>Non-secure access for the corresponding type-1 master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_USDHC1</name>
|
|
<description>Lock bit set by the TZ software for the USDHC1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_USDHC1_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_USDHC1_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSA_USDHC2</name>
|
|
<description>Non-secure access policy indicator bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSA_USDHC2_0</name>
|
|
<description>Secure access for the corresponding type-1 master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSA_USDHC2_1</name>
|
|
<description>Non-secure access for the corresponding type-1 master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_USDHC2</name>
|
|
<description>Lock bit set by the TZ software for the USDHC2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_USDHC2_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_USDHC2_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSA_TPSMP</name>
|
|
<description>Non-secure access policy indicator bit</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSA_TPSMP_0</name>
|
|
<description>Secure access for the corresponding type-1 master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSA_TPSMP_1</name>
|
|
<description>Non-secure access for the corresponding type-1 master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_TPSMP</name>
|
|
<description>Lock bit set by the TZ software for the TPSMP</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_TPSMP_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_TPSMP_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSA_USB</name>
|
|
<description>Non-secure access policy indicator bit</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NSA_USB_0</name>
|
|
<description>Secure access for the corresponding type-1 master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NSA_USB_1</name>
|
|
<description>Non-secure access for the corresponding type-1 master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_USB</name>
|
|
<description>Lock bit set by the TZ software for the USB</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_USB_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_USB_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPCONTROL0</name>
|
|
<description>HPCONTROL0 register</description>
|
|
<addressOffset>0x358</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HPC_DMA</name>
|
|
<description>Indicates the privilege/user mode for the eDMA</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPC_DMA_0</name>
|
|
<description>User mode for the corresponding master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPC_DMA_1</name>
|
|
<description>Supervisor mode for the corresponding master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_DMA</name>
|
|
<description>Lock bit set by the TZ software for the eDMA</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_DMA_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_DMA_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPC_LCDIF</name>
|
|
<description>Indicates the privilege/user mode for the LCDIF</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPC_LCDIF_0</name>
|
|
<description>User mode for the corresponding master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPC_LCDIF_1</name>
|
|
<description>Supervisor mode for the corresponding master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_LCDIF</name>
|
|
<description>Lock bit set by the TZ software for the LCDIF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_LCDIF_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_LCDIF_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPC_CSI</name>
|
|
<description>Indicates the privilege/user mode for the CSI</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPC_CSI_0</name>
|
|
<description>User mode for the corresponding master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPC_CSI_1</name>
|
|
<description>Supervisor mode for the corresponding master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_CSI</name>
|
|
<description>Lock bit set by the TZ software for the CSI</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_CSI_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_CSI_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPC_PXP</name>
|
|
<description>Indicates the privilege/user mode for the PXP</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPC_PXP_0</name>
|
|
<description>User mode for the corresponding master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPC_PXP_1</name>
|
|
<description>Supervisor mode for the corresponding master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_PXP</name>
|
|
<description>Lock bit set by the TZ software for the PXP</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_PXP_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_PXP_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPC_DCP</name>
|
|
<description>Indicates the privilege/user mode for the DCP</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPC_DCP_0</name>
|
|
<description>User mode for the corresponding master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPC_DCP_1</name>
|
|
<description>Supervisor mode for the corresponding master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_DCP</name>
|
|
<description>Lock bit set by the TZ software for the DCP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_DCP_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_DCP_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPC_ENET</name>
|
|
<description>Indicates the privilege/user mode for the ENET</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPC_ENET_0</name>
|
|
<description>User mode for the corresponding master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPC_ENET_1</name>
|
|
<description>Supervisor mode for the corresponding master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_ENET</name>
|
|
<description>Lock bit set by the TZ software for the ENET</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_ENET_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_ENET_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPC_USDHC1</name>
|
|
<description>Indicates the privilege/user mode for the USDHC1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPC_USDHC1_0</name>
|
|
<description>User mode for the corresponding master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPC_USDHC1_1</name>
|
|
<description>Supervisor mode for the corresponding master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_USDHC1</name>
|
|
<description>Lock bit set by the TZ software for the USDHC1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_USDHC1_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_USDHC1_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPC_USDHC2</name>
|
|
<description>Indicates the privilege/user mode for the USDHC2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPC_USDHC2_0</name>
|
|
<description>User mode for the corresponding master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPC_USDHC2_1</name>
|
|
<description>Supervisor mode for the corresponding master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_USDHC2</name>
|
|
<description>Lock bit set by the TZ software for the USDHC2.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_USDHC2_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_USDHC2_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPC_TPSMP</name>
|
|
<description>Indicates the privilege/user mode for the TPSMP</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPC_TPSMP_0</name>
|
|
<description>User mode for the corresponding master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPC_TPSMP_1</name>
|
|
<description>Supervisor mode for the corresponding master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_TPSMP</name>
|
|
<description>Lock bit set by the TZ software for the TPSMP.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_TPSMP_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_TPSMP_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HPC_USB</name>
|
|
<description>Indicates the privilege/user mode for the USB</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HPC_USB_0</name>
|
|
<description>User mode for the corresponding master</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HPC_USB_1</name>
|
|
<description>Supervisor mode for the corresponding master</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L_USB</name>
|
|
<description>Lock bit set by the TZ software for the USB.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>L_USB_0</name>
|
|
<description>No lock-the adjacent (next lower) bit can be written by the software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_USB_1</name>
|
|
<description>Lock-the adjacent (next lower) bit can't be written by the software.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USB</name>
|
|
<description>USB</description>
|
|
<groupName>USB</groupName>
|
|
<prependToName>USB_</prependToName>
|
|
<baseAddress>0x400E4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1E0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USB_OTG1</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ID</name>
|
|
<description>Identification register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xE4A1FA05</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Configuration number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NID</name>
|
|
<description>Complement version of ID</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Revision number of the controller core.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWGENERAL</name>
|
|
<description>Hardware General</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x35</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PHYW</name>
|
|
<description>Data width of the transciever connected to the controller core. PHYW bit reset value is</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PHYW_0</name>
|
|
<description>8 bit wide data bus Software non-programmable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHYW_1</name>
|
|
<description>16 bit wide data bus Software non-programmable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHYW_2</name>
|
|
<description>Reset to 8 bit wide data bus Software programmable</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHYW_3</name>
|
|
<description>Reset to 16 bit wide data bus Software programmable</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHYM</name>
|
|
<description>Transciever type</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PHYM_0</name>
|
|
<description>UTMI/UMTI+</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHYM_1</name>
|
|
<description>ULPI DDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHYM_2</name>
|
|
<description>ULPI</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHYM_3</name>
|
|
<description>Serial Only</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHYM_4</name>
|
|
<description>Software programmable - reset to UTMI/UTMI+</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHYM_5</name>
|
|
<description>Software programmable - reset to ULPI DDR</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHYM_6</name>
|
|
<description>Software programmable - reset to ULPI</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHYM_7</name>
|
|
<description>Software programmable - reset to Serial</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM</name>
|
|
<description>Serial interface mode capability</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM_0</name>
|
|
<description>No Serial Engine, always use parallel signalling.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM_1</name>
|
|
<description>Serial Engine present, always use serial signalling for FS/LS.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM_2</name>
|
|
<description>Software programmable - Reset to use parallel signalling for FS/LS</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM_3</name>
|
|
<description>Software programmable - Reset to use serial signalling for FS/LS</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWHOST</name>
|
|
<description>Host Hardware Parameters</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x10020001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HC</name>
|
|
<description>Host Capable. Indicating whether host operation mode is supported or not.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HC_0</name>
|
|
<description>Not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HC_1</name>
|
|
<description>Supported</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NPORT</name>
|
|
<description>The Nmber of downstream ports supported by the host controller is (NPORT+1)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWDEVICE</name>
|
|
<description>Device Hardware Parameters</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x11</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DC</name>
|
|
<description>Device Capable. Indicating whether device operation mode is supported or not.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DC_0</name>
|
|
<description>Not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC_1</name>
|
|
<description>Supported</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEVEP</name>
|
|
<description>Device Endpoint Number</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWTXBUF</name>
|
|
<description>TX Buffer Hardware Parameters</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x80080B08</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXBURST</name>
|
|
<description>Default burst size for memory to TX buffer transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCHANADD</name>
|
|
<description>TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HWRXBUF</name>
|
|
<description>RX Buffer Hardware Parameters</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x808</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXBURST</name>
|
|
<description>Default burst size for memory to RX buffer transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXADD</name>
|
|
<description>Buffer total size for all receive endpoints is (2^RXADD)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPTIMER0LD</name>
|
|
<description>General Purpose Timer #0 Load</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPTLD</name>
|
|
<description>General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPTIMER0CTRL</name>
|
|
<description>General Purpose Timer #0 Controller</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPTCNT</name>
|
|
<description>General Purpose Timer Counter. This field is the count value of the countdown timer.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GPTMODE</name>
|
|
<description>General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPTMODE_0</name>
|
|
<description>One Shot Mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPTMODE_1</name>
|
|
<description>Repeat Mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPTRST</name>
|
|
<description>General Purpose Timer Reset</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPTRST_0</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPTRST_1</name>
|
|
<description>Load counter value from GPTLD bits in n_GPTIMER0LD</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPTRUN</name>
|
|
<description>General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPTRUN_0</name>
|
|
<description>Stop counting</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPTRUN_1</name>
|
|
<description>Run</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPTIMER1LD</name>
|
|
<description>General Purpose Timer #1 Load</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPTLD</name>
|
|
<description>General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPTIMER1CTRL</name>
|
|
<description>General Purpose Timer #1 Controller</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPTCNT</name>
|
|
<description>General Purpose Timer Counter. This field is the count value of the countdown timer.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GPTMODE</name>
|
|
<description>General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPTMODE_0</name>
|
|
<description>One Shot Mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPTMODE_1</name>
|
|
<description>Repeat Mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPTRST</name>
|
|
<description>General Purpose Timer Reset</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPTRST_0</name>
|
|
<description>No action</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPTRST_1</name>
|
|
<description>Load counter value from GPTLD bits in USB_n_GPTIMER0LD</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPTRUN</name>
|
|
<description>General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPTRUN_0</name>
|
|
<description>Stop counting</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPTRUN_1</name>
|
|
<description>Run</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SBUSCFG</name>
|
|
<description>System Bus Config</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AHBBRST</name>
|
|
<description>AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AHBBRST_0</name>
|
|
<description>Incremental burst of unspecified length only</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHBBRST_1</name>
|
|
<description>INCR4 burst, then single transfer</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHBBRST_2</name>
|
|
<description>INCR8 burst, INCR4 burst, then single transfer</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHBBRST_3</name>
|
|
<description>INCR16 burst, INCR8 burst, INCR4 burst, then single transfer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHBBRST_5</name>
|
|
<description>INCR4 burst, then incremental burst of unspecified length</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHBBRST_6</name>
|
|
<description>INCR8 burst, INCR4 burst, then incremental burst of unspecified length</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHBBRST_7</name>
|
|
<description>INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAPLENGTH</name>
|
|
<description>Capability Registers Length</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPLENGTH</name>
|
|
<description>These bits are used as an offset to add to register base to find the beginning of the Operational Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCIVERSION</name>
|
|
<description>Host Controller Interface Version</description>
|
|
<addressOffset>0x102</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x100</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HCIVERSION</name>
|
|
<description>Host Controller Interface Version Number Default value is '10h', which means EHCI rev1.0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCSPARAMS</name>
|
|
<description>Host Controller Structural Parameters</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x10011</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>N_PORTS</name>
|
|
<description>Number of downstream ports</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PPC</name>
|
|
<description>Port Power Control This field indicates whether the host controller implementation includes port power control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>N_PCC</name>
|
|
<description>Number of Ports per Companion Controller This field indicates the number of ports supported per internal Companion Controller</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>N_CC</name>
|
|
<description>Number of Companion Controller (N_CC)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>N_CC_0</name>
|
|
<description>There is no internal Companion Controller and port-ownership hand-off is not supported.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>N_CC_1</name>
|
|
<description>There are internal companion controller(s) and port-ownership hand-offs is supported.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PI</name>
|
|
<description>Port Indicators (P INDICATOR) This bit indicates whether the ports support port indicator control</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>N_PTT</name>
|
|
<description>Number of Ports per Transaction Translator (N_PTT)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>N_TT</name>
|
|
<description>Number of Transaction Translators (N_TT)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCCPARAMS</name>
|
|
<description>Host Controller Capability Parameters</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x6</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC</name>
|
|
<description>64-bit Addressing Capability This bit is set '0b' in all controller core, no 64-bit addressing capability is supported</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PFL</name>
|
|
<description>Programmable Frame List Flag If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ASP</name>
|
|
<description>Asynchronous Schedule Park Capability If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IST</name>
|
|
<description>Isochronous Scheduling Threshold</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EECP</name>
|
|
<description>EHCI Extended Capabilities Pointer</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCIVERSION</name>
|
|
<description>Device Controller Interface Version</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCIVERSION</name>
|
|
<description>Device Controller Interface Version Number Default value is '01h', which means rev0.1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCPARAMS</name>
|
|
<description>Device Controller Capability Parameters</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x188</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEN</name>
|
|
<description>Device Endpoint Number This field indicates the number of endpoints built into the device controller</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DC</name>
|
|
<description>Device Capable When this bit is 1, this controller is capable of operating as a USB 2.0 device.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HC</name>
|
|
<description>Host Capable When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCMD</name>
|
|
<description>USB Command Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Run/Stop (RS) - Read/Write</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Controller Reset (RESET) - Read/Write</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FS_1</name>
|
|
<description>See description at bit 15</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PSE</name>
|
|
<description>Periodic Schedule Enable- Read/Write</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PSE_0</name>
|
|
<description>Do not process the Periodic Schedule</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSE_1</name>
|
|
<description>Use the PERIODICLISTBASE register to access the Periodic Schedule.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASE</name>
|
|
<description>Asynchronous Schedule Enable - Read/Write</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ASE_0</name>
|
|
<description>Do not process the Asynchronous Schedule.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASE_1</name>
|
|
<description>Use the ASYNCLISTADDR register to access the Asynchronous Schedule.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IAA</name>
|
|
<description>Interrupt on Async Advance Doorbell - Read/Write</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ASP</name>
|
|
<description>Asynchronous Schedule Park Mode Count - Read/Write</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ASPE</name>
|
|
<description>Asynchronous Schedule Park Mode Enable - Read/Write</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SUTW</name>
|
|
<description>Setup TripWire - Read/Write</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ATDTW</name>
|
|
<description>Add dTD TripWire - Read/Write</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FS_2</name>
|
|
<description>Frame List Size - (Read/Write or Read Only)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FS_2_0</name>
|
|
<description>1024 elements (4096 bytes) Default value</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FS_2_1</name>
|
|
<description>512 elements (2048 bytes)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITC</name>
|
|
<description>Interrupt Threshold Control -Read/Write</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ITC_0</name>
|
|
<description>Immediate (no threshold)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITC_1</name>
|
|
<description>1 micro-frame</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITC_2</name>
|
|
<description>2 micro-frames</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITC_4</name>
|
|
<description>4 micro-frames</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITC_8</name>
|
|
<description>8 micro-frames</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITC_16</name>
|
|
<description>16 micro-frames</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITC_32</name>
|
|
<description>32 micro-frames</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ITC_64</name>
|
|
<description>64 micro-frames</description>
|
|
<value>0x40</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBSTS</name>
|
|
<description>USB Status Register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UI</name>
|
|
<description>USB Interrupt (USBINT) - R/WC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UEI</name>
|
|
<description>USB Error Interrupt (USBERRINT) - R/WC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCI</name>
|
|
<description>Port Change Detect - R/WC</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRI</name>
|
|
<description>Frame List Rollover - R/WC</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEI</name>
|
|
<description>System Error- R/WC</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AAI</name>
|
|
<description>Interrupt on Async Advance - R/WC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URI</name>
|
|
<description>USB Reset Received - R/WC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SRI</name>
|
|
<description>SOF Received - R/WC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SLI</name>
|
|
<description>DCSuspend - R/WC</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ULPII</name>
|
|
<description>ULPI Interrupt - R/WC</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HCH</name>
|
|
<description>HCHaIted - Read Only</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RCL</name>
|
|
<description>Reclamation - Read Only</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Periodic Schedule Status - Read Only</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AS</name>
|
|
<description>Asynchronous Schedule Status - Read Only</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKI</name>
|
|
<description>NAK Interrupt Bit--RO</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TI0</name>
|
|
<description>General Purpose Timer Interrupt 0(GPTINT0)--R/WC</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TI1</name>
|
|
<description>General Purpose Timer Interrupt 1(GPTINT1)--R/WC</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBINTR</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UE</name>
|
|
<description>USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UEE</name>
|
|
<description>USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCE</name>
|
|
<description>Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRE</name>
|
|
<description>Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEE</name>
|
|
<description>System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AAE</name>
|
|
<description>Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URE</name>
|
|
<description>USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SLE</name>
|
|
<description>Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ULPIE</name>
|
|
<description>ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKE</name>
|
|
<description>NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UAIE</name>
|
|
<description>USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UPIE</name>
|
|
<description>USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIE0</name>
|
|
<description>General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIE1</name>
|
|
<description>General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRINDEX</name>
|
|
<description>USB Frame Index</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRINDEX</name>
|
|
<description>Frame Index</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRINDEX_0</name>
|
|
<description>(1024) 12</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRINDEX_1</name>
|
|
<description>(512) 11</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRINDEX_2</name>
|
|
<description>(256) 10</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRINDEX_3</name>
|
|
<description>(128) 9</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRINDEX_4</name>
|
|
<description>(64) 8</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRINDEX_5</name>
|
|
<description>(32) 7</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRINDEX_6</name>
|
|
<description>(16) 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRINDEX_7</name>
|
|
<description>(8) 5</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICEADDR</name>
|
|
<description>Device Address</description>
|
|
<alternateGroup>DEVICEADDR_PERIODICLISTBASE</alternateGroup>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USBADRA</name>
|
|
<description>Device Address Advance</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>USBADR</name>
|
|
<description>Device Address. These bits correspond to the USB device address</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERIODICLISTBASE</name>
|
|
<description>Frame List Base Address</description>
|
|
<alternateGroup>DEVICEADDR_PERIODICLISTBASE</alternateGroup>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BASEADR</name>
|
|
<description>Base Address (Low)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ASYNCLISTADDR</name>
|
|
<description>Next Asynch. Address</description>
|
|
<alternateGroup>ASYNCLISTADDR_ENDPTLISTADDR</alternateGroup>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASYBASE</name>
|
|
<description>Link Pointer Low (LPL)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>27</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTLISTADDR</name>
|
|
<description>Endpoint List Address</description>
|
|
<alternateGroup>ASYNCLISTADDR_ENDPTLISTADDR</alternateGroup>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPBASE</name>
|
|
<description>Endpoint List Pointer(Low)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>21</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BURSTSIZE</name>
|
|
<description>Programmable Burst Size</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x808</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPBURST</name>
|
|
<description>Programmable RX Burst Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXPBURST</name>
|
|
<description>Programmable TX Burst Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFILLTUNING</name>
|
|
<description>TX FIFO Fill Tuning</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXSCHOH</name>
|
|
<description>Scheduler Overhead</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXSCHHEALTH</name>
|
|
<description>Scheduler Health Counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOTHRES</name>
|
|
<description>FIFO Burst Threshold</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTNAK</name>
|
|
<description>Endpoint NAK</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPRN</name>
|
|
<description>RX Endpoint NAK - R/WC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTN</name>
|
|
<description>TX Endpoint NAK - R/WC</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTNAKEN</name>
|
|
<description>Endpoint NAK Enable</description>
|
|
<addressOffset>0x17C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPRNE</name>
|
|
<description>RX Endpoint NAK Enable - R/W</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTNE</name>
|
|
<description>TX Endpoint NAK Enable - R/W</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIGFLAG</name>
|
|
<description>Configure Flag Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CF</name>
|
|
<description>Configure Flag Host software sets this bit as the last action in its process of configuring the Host Controller</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CF_0</name>
|
|
<description>Port routing control logic default-routes each port to an implementation dependent classic host controller.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CF_1</name>
|
|
<description>Port routing control logic default-routes all ports to this host controller.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PORTSC1</name>
|
|
<description>Port Status & Control</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCS</name>
|
|
<description>Current Connect Status-Read Only</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CSC</name>
|
|
<description>Connect Status Change-R/WC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Port Enabled/Disabled-Read/Write</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PEC</name>
|
|
<description>Port Enable/Disable Change-R/WC</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OCA</name>
|
|
<description>Over-current Active-Read Only</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OCA_0</name>
|
|
<description>This port does not have an over-current condition.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OCA_1</name>
|
|
<description>This port currently has an over-current condition</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCC</name>
|
|
<description>Over-current Change-R/WC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPR</name>
|
|
<description>Force Port Resume -Read/Write</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Suspend - Read/Write or Read Only</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Port Reset - Read/Write or Read Only</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSP</name>
|
|
<description>High-Speed Port - Read Only</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LS</name>
|
|
<description>Line Status-Read Only</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LS_0</name>
|
|
<description>SE0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LS_1</name>
|
|
<description>K-state</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LS_2</name>
|
|
<description>J-state</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LS_3</name>
|
|
<description>Undefined</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PP</name>
|
|
<description>Port Power (PP)-Read/Write or Read Only</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PO</name>
|
|
<description>Port Owner-Read/Write</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PIC</name>
|
|
<description>Port Indicator Control - Read/Write</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PIC_0</name>
|
|
<description>Port indicators are off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIC_1</name>
|
|
<description>Amber</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIC_2</name>
|
|
<description>Green</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PIC_3</name>
|
|
<description>Undefined</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTC</name>
|
|
<description>Port Test Control - Read/Write</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PTC_0</name>
|
|
<description>TEST_MODE_DISABLE</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PTC_1</name>
|
|
<description>J_STATE</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PTC_2</name>
|
|
<description>K_STATE</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PTC_3</name>
|
|
<description>SE0 (host) / NAK (device)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PTC_4</name>
|
|
<description>Packet</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PTC_5</name>
|
|
<description>FORCE_ENABLE_HS</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PTC_6</name>
|
|
<description>FORCE_ENABLE_FS</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PTC_7</name>
|
|
<description>FORCE_ENABLE_LS</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKCN</name>
|
|
<description>Wake on Connect Enable (WKCNNT_E) - Read/Write</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WKDC</name>
|
|
<description>Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WKOC</name>
|
|
<description>Wake on Over-current Enable (WKOC_E) - Read/Write</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PHCD</name>
|
|
<description>PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PHCD_0</name>
|
|
<description>Enable PHY clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PHCD_1</name>
|
|
<description>Disable PHY clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFSC</name>
|
|
<description>Port Force Full Speed Connect - Read/Write</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PFSC_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PFSC_1</name>
|
|
<description>Forced to full speed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTS_2</name>
|
|
<description>See description at bits 31-30</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PSPD</name>
|
|
<description>Port Speed - Read Only. This register field indicates the speed at which the port is operating.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PSPD_0</name>
|
|
<description>Full Speed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSPD_1</name>
|
|
<description>Low Speed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSPD_2</name>
|
|
<description>High Speed</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSPD_3</name>
|
|
<description>Undefined</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTW</name>
|
|
<description>Parallel Transceiver Width This bit has no effect if serial interface engine is used</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PTW_0</name>
|
|
<description>Select the 8-bit UTMI interface [60MHz]</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PTW_1</name>
|
|
<description>Select the 16-bit UTMI interface [30MHz]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STS</name>
|
|
<description>Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PTS_1</name>
|
|
<description>All USB port interface modes are listed in this field description, but not all are supported</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTGSC</name>
|
|
<description>On-The-Go Status & control</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1120</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VD</name>
|
|
<description>VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VC</name>
|
|
<description>VBUS Charge - Read/Write</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OT</name>
|
|
<description>OTG Termination - Read/Write</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DP</name>
|
|
<description>Data Pulsing - Read/Write</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDPU</name>
|
|
<description>ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>USB ID - Read Only. 0 = A device, 1 = B device</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AVV</name>
|
|
<description>A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ASV</name>
|
|
<description>A Session Valid - Read Only. Indicates VBus is above the A session valid threshold.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BSV</name>
|
|
<description>B Session Valid - Read Only. Indicates VBus is above the B session valid threshold.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BSE</name>
|
|
<description>B Session End - Read Only. Indicates VBus is below the B session end threshold.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TOG_1MS</name>
|
|
<description>1 millisecond timer toggle - Read Only. This bit toggles once per millisecond.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DPS</name>
|
|
<description>Data Bus Pulsing Status - Read Only</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IDIS</name>
|
|
<description>USB ID Interrupt Status - Read/Write</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AVVIS</name>
|
|
<description>A VBus Valid Interrupt Status - Read/Write to Clear</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ASVIS</name>
|
|
<description>A Session Valid Interrupt Status - Read/Write to Clear</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BSVIS</name>
|
|
<description>B Session Valid Interrupt Status - Read/Write to Clear</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BSEIS</name>
|
|
<description>B Session End Interrupt Status - Read/Write to Clear</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STATUS_1MS</name>
|
|
<description>1 millisecond timer Interrupt Status - Read/Write to Clear</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIS</name>
|
|
<description>Data Pulse Interrupt Status - Read/Write to Clear</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDIE</name>
|
|
<description>USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AVVIE</name>
|
|
<description>A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ASVIE</name>
|
|
<description>A Session Valid Interrupt Enable - Read/Write</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BSVIE</name>
|
|
<description>B Session Valid Interrupt Enable - Read/Write</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BSEIE</name>
|
|
<description>B Session End Interrupt Enable - Read/Write. Setting this bit enables the B session end interrupt.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN_1MS</name>
|
|
<description>1 millisecond timer Interrupt Enable - Read/Write</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPIE</name>
|
|
<description>Data Pulse Interrupt Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBMODE</name>
|
|
<description>USB Device Mode</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CM</name>
|
|
<description>Controller Mode - R/WO</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CM_0</name>
|
|
<description>Idle [Default for combination host/device]</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_2</name>
|
|
<description>Device Controller [Default for device only controller]</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CM_3</name>
|
|
<description>Host Controller [Default for host only controller]</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ES</name>
|
|
<description>Endian Select - Read/Write</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ES_0</name>
|
|
<description>Little Endian [Default]</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ES_1</name>
|
|
<description>Big Endian</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLOM</name>
|
|
<description>Setup Lockout Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLOM_0</name>
|
|
<description>Setup Lockouts On (default);</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLOM_1</name>
|
|
<description>Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register .</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDIS</name>
|
|
<description>Stream Disable Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTSETUPSTAT</name>
|
|
<description>Endpoint Setup Status</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENDPTSETUPSTAT</name>
|
|
<description>Setup Endpoint Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTPRIME</name>
|
|
<description>Endpoint Prime</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERB</name>
|
|
<description>Prime Endpoint Receive Buffer - R/WS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PETB</name>
|
|
<description>Prime Endpoint Transmit Buffer - R/WS</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTFLUSH</name>
|
|
<description>Endpoint Flush</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FERB</name>
|
|
<description>Flush Endpoint Receive Buffer - R/WS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FETB</name>
|
|
<description>Flush Endpoint Transmit Buffer - R/WS</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTSTAT</name>
|
|
<description>Endpoint Status</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERBR</name>
|
|
<description>Endpoint Receive Buffer Ready -- Read Only</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ETBR</name>
|
|
<description>Endpoint Transmit Buffer Ready -- Read Only</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCOMPLETE</name>
|
|
<description>Endpoint Complete</description>
|
|
<addressOffset>0x1BC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERCE</name>
|
|
<description>Endpoint Receive Complete Event - RW/C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETCE</name>
|
|
<description>Endpoint Transmit Complete Event - R/WC</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCTRL0</name>
|
|
<description>Endpoint Control0</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x800080</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>RX Endpoint Stall - Read/Write 0 End Point OK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>RX Endpoint Enable 1 Enabled Endpoint0 is always enabled.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>TX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXT</name>
|
|
<description>TX Endpoint Type - Read/Write 00 - Control Endpoint0 is fixed as a Control End Point.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TX Endpoint Enable 1 Enabled Endpoint0 is always enabled.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCTRL1</name>
|
|
<description>Endpoint Control 1</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>RX Endpoint Stall - Read/Write 0 End Point OK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXD</name>
|
|
<description>RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXI</name>
|
|
<description>RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXR</name>
|
|
<description>RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXD</name>
|
|
<description>TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXT</name>
|
|
<description>TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXI</name>
|
|
<description>TX Data Toggle Inhibit 0 PID Sequencing Enabled</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXR</name>
|
|
<description>TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCTRL2</name>
|
|
<description>Endpoint Control 2</description>
|
|
<addressOffset>0x1C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>RX Endpoint Stall - Read/Write 0 End Point OK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXD</name>
|
|
<description>RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXI</name>
|
|
<description>RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXR</name>
|
|
<description>RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXD</name>
|
|
<description>TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXT</name>
|
|
<description>TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXI</name>
|
|
<description>TX Data Toggle Inhibit 0 PID Sequencing Enabled</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXR</name>
|
|
<description>TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCTRL3</name>
|
|
<description>Endpoint Control 3</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>RX Endpoint Stall - Read/Write 0 End Point OK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXD</name>
|
|
<description>RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXI</name>
|
|
<description>RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXR</name>
|
|
<description>RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXD</name>
|
|
<description>TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXT</name>
|
|
<description>TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXI</name>
|
|
<description>TX Data Toggle Inhibit 0 PID Sequencing Enabled</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXR</name>
|
|
<description>TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCTRL4</name>
|
|
<description>Endpoint Control 4</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>RX Endpoint Stall - Read/Write 0 End Point OK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXD</name>
|
|
<description>RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXI</name>
|
|
<description>RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXR</name>
|
|
<description>RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXD</name>
|
|
<description>TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXT</name>
|
|
<description>TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXI</name>
|
|
<description>TX Data Toggle Inhibit 0 PID Sequencing Enabled</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXR</name>
|
|
<description>TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCTRL5</name>
|
|
<description>Endpoint Control 5</description>
|
|
<addressOffset>0x1D4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>RX Endpoint Stall - Read/Write 0 End Point OK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXD</name>
|
|
<description>RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXI</name>
|
|
<description>RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXR</name>
|
|
<description>RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXD</name>
|
|
<description>TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXT</name>
|
|
<description>TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXI</name>
|
|
<description>TX Data Toggle Inhibit 0 PID Sequencing Enabled</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXR</name>
|
|
<description>TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCTRL6</name>
|
|
<description>Endpoint Control 6</description>
|
|
<addressOffset>0x1D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>RX Endpoint Stall - Read/Write 0 End Point OK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXD</name>
|
|
<description>RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXI</name>
|
|
<description>RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXR</name>
|
|
<description>RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXD</name>
|
|
<description>TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXT</name>
|
|
<description>TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXI</name>
|
|
<description>TX Data Toggle Inhibit 0 PID Sequencing Enabled</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXR</name>
|
|
<description>TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCTRL7</name>
|
|
<description>Endpoint Control 7</description>
|
|
<addressOffset>0x1DC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>RX Endpoint Stall - Read/Write 0 End Point OK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXD</name>
|
|
<description>RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXI</name>
|
|
<description>RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXR</name>
|
|
<description>RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXD</name>
|
|
<description>TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXT</name>
|
|
<description>TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXI</name>
|
|
<description>TX Data Toggle Inhibit 0 PID Sequencing Enabled</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXR</name>
|
|
<description>TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USBNC</name>
|
|
<description>USB</description>
|
|
<alternatePeripheral>USB</alternatePeripheral>
|
|
<groupName>USBNC</groupName>
|
|
<prependToName>USBNC_</prependToName>
|
|
<baseAddress>0x400E4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x81C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>USB_OTG1_CTRL</name>
|
|
<description>USB OTG1 Control Register</description>
|
|
<addressOffset>0x800</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30001000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OVER_CUR_DIS</name>
|
|
<description>Disable OTG1 Overcurrent Detection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OVER_CUR_DIS_0</name>
|
|
<description>Enables overcurrent detection</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVER_CUR_DIS_1</name>
|
|
<description>Disables overcurrent detection</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OVER_CUR_POL</name>
|
|
<description>OTG1 Polarity of Overcurrent The polarity of OTG1 port overcurrent event</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OVER_CUR_POL_0</name>
|
|
<description>High active (high on this signal represents an overcurrent condition)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OVER_CUR_POL_1</name>
|
|
<description>Low active (low on this signal represents an overcurrent condition)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWR_POL</name>
|
|
<description>OTG1 Power Polarity This bit should be set according to PMIC Power Pin polarity.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWR_POL_0</name>
|
|
<description>PMIC Power Pin is Low active.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWR_POL_1</name>
|
|
<description>PMIC Power Pin is High active.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WIE</name>
|
|
<description>OTG1 Wake-up Interrupt Enable This bit enables or disables the OTG1 wake-up interrupt</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WIE_0</name>
|
|
<description>Interrupt Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIE_1</name>
|
|
<description>Interrupt Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUP_SW_EN</name>
|
|
<description>OTG1 Software Wake-up Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WKUP_SW_EN_0</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WKUP_SW_EN_1</name>
|
|
<description>Enable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUP_SW</name>
|
|
<description>OTG1 Software Wake-up</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WKUP_SW_0</name>
|
|
<description>Inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WKUP_SW_1</name>
|
|
<description>Force wake-up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUP_ID_EN</name>
|
|
<description>OTG1 Wake-up on ID change enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WKUP_ID_EN_0</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WKUP_ID_EN_1</name>
|
|
<description>Enable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUP_VBUS_EN</name>
|
|
<description>OTG1 wake-up on VBUS change enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WKUP_VBUS_EN_0</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WKUP_VBUS_EN_1</name>
|
|
<description>Enable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKUP_DPDM_EN</name>
|
|
<description>Wake-up on DPDM change enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WKUP_DPDM_EN_0</name>
|
|
<description>DPDM changes wake-up to be disabled only when VBUS is 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WKUP_DPDM_EN_1</name>
|
|
<description>(Default) DPDM changes wake-up to be enabled, it is for device only.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WIR</name>
|
|
<description>OTG1 Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTG1 port</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WIR_0</name>
|
|
<description>No wake-up interrupt request received</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIR_1</name>
|
|
<description>Wake-up Interrupt Request received</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB_OTG1_PHY_CTRL_0</name>
|
|
<description>OTG1 UTMI PHY Control 0 Register</description>
|
|
<addressOffset>0x818</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UTMI_CLK_VLD</name>
|
|
<description>Indicating whether OTG1 UTMI PHY clock is valid</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UTMI_CLK_VLD_0</name>
|
|
<description>Invalid</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UTMI_CLK_VLD_1</name>
|
|
<description>Valid</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMA0</name>
|
|
<description>DMA</description>
|
|
<groupName>DMA</groupName>
|
|
<baseAddress>0x400E8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMA0</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA2</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA3</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA4</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA5</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA6</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA7</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA8</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA9</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA10</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA11</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA12</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA13</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA14</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA15</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_ERROR</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x80FFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDBG</name>
|
|
<description>Enable Debug</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDBG_0</name>
|
|
<description>When in debug mode, the DMA continues to operate.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDBG_1</name>
|
|
<description>When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERCA</name>
|
|
<description>Enable Round Robin Channel Arbitration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERCA_0</name>
|
|
<description>Fixed priority arbitration is used for channel selection .</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERCA_1</name>
|
|
<description>Round robin arbitration is used for channel selection .</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HOE</name>
|
|
<description>Halt On Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HOE_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOE_1</name>
|
|
<description>Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT</name>
|
|
<description>Halt DMA Operations</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALT_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT_1</name>
|
|
<description>Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLM</name>
|
|
<description>Continuous Link Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLM_0</name>
|
|
<description>A minor loop channel link made to itself goes through channel arbitration before being activated again.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLM_1</name>
|
|
<description>A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMLM</name>
|
|
<description>Enable Minor Loop Mapping</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EMLM_0</name>
|
|
<description>Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMLM_1</name>
|
|
<description>Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECX</name>
|
|
<description>Error Cancel Transfer</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECX_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECX_1</name>
|
|
<description>Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CX</name>
|
|
<description>Cancel Transfer</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CX_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CX_1</name>
|
|
<description>Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>DMA Active Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_0</name>
|
|
<description>eDMA is idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_1</name>
|
|
<description>eDMA is executing a channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ES</name>
|
|
<description>Error Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBE</name>
|
|
<description>Destination Bus Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBE_0</name>
|
|
<description>No destination bus error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBE_1</name>
|
|
<description>The last recorded error was a bus error on a destination write</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBE</name>
|
|
<description>Source Bus Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SBE_0</name>
|
|
<description>No source bus error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SBE_1</name>
|
|
<description>The last recorded error was a bus error on a source read</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SGE</name>
|
|
<description>Scatter/Gather Configuration Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SGE_0</name>
|
|
<description>No scatter/gather configuration error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGE_1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCE</name>
|
|
<description>NBYTES/CITER Configuration Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NCE_0</name>
|
|
<description>No NBYTES/CITER configuration error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NCE_1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOE</name>
|
|
<description>Destination Offset Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DOE_0</name>
|
|
<description>No destination offset configuration error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOE_1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAE</name>
|
|
<description>Destination Address Error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DAE_0</name>
|
|
<description>No destination address configuration error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DAE_1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOE</name>
|
|
<description>Source Offset Error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SOE_0</name>
|
|
<description>No source offset configuration error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOE_1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAE</name>
|
|
<description>Source Address Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAE_0</name>
|
|
<description>No source address configuration error.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAE_1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERRCHN</name>
|
|
<description>Error Channel Number or Canceled Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPE</name>
|
|
<description>Channel Priority Error</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CPE_0</name>
|
|
<description>No channel priority error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPE_1</name>
|
|
<description>The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECX</name>
|
|
<description>Transfer Canceled</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECX_0</name>
|
|
<description>No canceled transfers</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECX_1</name>
|
|
<description>The last recorded entry was a canceled transfer by the error cancel transfer input</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VLD</name>
|
|
<description>VLD</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VLD_0</name>
|
|
<description>No ERR bits are set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VLD_1</name>
|
|
<description>At least one ERR bit is set indicating a valid error exists that has not been cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERQ</name>
|
|
<description>Enable Request Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERQ0</name>
|
|
<description>Enable DMA Request 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ0_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ0_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ1</name>
|
|
<description>Enable DMA Request 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ1_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ1_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ2</name>
|
|
<description>Enable DMA Request 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ2_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ2_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ3</name>
|
|
<description>Enable DMA Request 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ3_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ3_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ4</name>
|
|
<description>Enable DMA Request 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ4_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ4_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ5</name>
|
|
<description>Enable DMA Request 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ5_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ5_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ6</name>
|
|
<description>Enable DMA Request 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ6_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ6_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ7</name>
|
|
<description>Enable DMA Request 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ7_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ7_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ8</name>
|
|
<description>Enable DMA Request 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ8_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ8_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ9</name>
|
|
<description>Enable DMA Request 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ9_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ9_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ10</name>
|
|
<description>Enable DMA Request 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ10_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ10_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ11</name>
|
|
<description>Enable DMA Request 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ11_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ11_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ12</name>
|
|
<description>Enable DMA Request 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ12_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ12_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ13</name>
|
|
<description>Enable DMA Request 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ13_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ13_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ14</name>
|
|
<description>Enable DMA Request 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ14_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ14_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ15</name>
|
|
<description>Enable DMA Request 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERQ15_0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERQ15_1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEI</name>
|
|
<description>Enable Error Interrupt Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EEI0</name>
|
|
<description>Enable Error Interrupt 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI0_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI0_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI1</name>
|
|
<description>Enable Error Interrupt 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI1_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI1_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI2</name>
|
|
<description>Enable Error Interrupt 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI2_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI2_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI3</name>
|
|
<description>Enable Error Interrupt 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI3_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI3_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI4</name>
|
|
<description>Enable Error Interrupt 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI4_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI4_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI5</name>
|
|
<description>Enable Error Interrupt 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI5_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI5_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI6</name>
|
|
<description>Enable Error Interrupt 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI6_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI6_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI7</name>
|
|
<description>Enable Error Interrupt 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI7_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI7_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI8</name>
|
|
<description>Enable Error Interrupt 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI8_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI8_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI9</name>
|
|
<description>Enable Error Interrupt 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI9_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI9_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI10</name>
|
|
<description>Enable Error Interrupt 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI10_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI10_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI11</name>
|
|
<description>Enable Error Interrupt 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI11_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI11_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI12</name>
|
|
<description>Enable Error Interrupt 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI12_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI12_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI13</name>
|
|
<description>Enable Error Interrupt 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI13_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI13_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI14</name>
|
|
<description>Enable Error Interrupt 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI14_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI14_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI15</name>
|
|
<description>Enable Error Interrupt 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EEI15_0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EEI15_1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CEEI</name>
|
|
<description>Clear Enable Error Interrupt Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEEI</name>
|
|
<description>Clear Enable Error Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAEE</name>
|
|
<description>Clear All Enable Error Interrupts</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAEE_0</name>
|
|
<description>Clear only the EEI bit specified in the CEEI field</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAEE_1</name>
|
|
<description>Clear all bits in EEI</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOP_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOP_1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEEI</name>
|
|
<description>Set Enable Error Interrupt Register</description>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEEI</name>
|
|
<description>Set Enable Error Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAEE</name>
|
|
<description>Sets All Enable Error Interrupts</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAEE_0</name>
|
|
<description>Set only the EEI bit specified in the SEEI field.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAEE_1</name>
|
|
<description>Sets all bits in EEI</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOP_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOP_1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CERQ</name>
|
|
<description>Clear Enable Request Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CERQ</name>
|
|
<description>Clear Enable Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAER</name>
|
|
<description>Clear All Enable Requests</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAER_0</name>
|
|
<description>Clear only the ERQ bit specified in the CERQ field</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAER_1</name>
|
|
<description>Clear all bits in ERQ</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOP_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOP_1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SERQ</name>
|
|
<description>Set Enable Request Register</description>
|
|
<addressOffset>0x1B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SERQ</name>
|
|
<description>Set Enable Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAER</name>
|
|
<description>Set All Enable Requests</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAER_0</name>
|
|
<description>Set only the ERQ bit specified in the SERQ field</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAER_1</name>
|
|
<description>Set all bits in ERQ</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOP_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOP_1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDNE</name>
|
|
<description>Clear DONE Status Bit Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CDNE</name>
|
|
<description>Clear DONE Bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CADN</name>
|
|
<description>Clears All DONE Bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CADN_0</name>
|
|
<description>Clears only the TCDn_CSR[DONE] bit specified in the CDNE field</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CADN_1</name>
|
|
<description>Clears all bits in TCDn_CSR[DONE]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOP_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOP_1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSRT</name>
|
|
<description>Set START Bit Register</description>
|
|
<addressOffset>0x1D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSRT</name>
|
|
<description>Set START Bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SAST</name>
|
|
<description>Set All START Bits (activates all channels)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAST_0</name>
|
|
<description>Set only the TCDn_CSR[START] bit specified in the SSRT field</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAST_1</name>
|
|
<description>Set all bits in TCDn_CSR[START]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOP_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOP_1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CERR</name>
|
|
<description>Clear Error Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CERR</name>
|
|
<description>Clear Error Indicator</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAEI</name>
|
|
<description>Clear All Error Indicators</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAEI_0</name>
|
|
<description>Clear only the ERR bit specified in the CERR field</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAEI_1</name>
|
|
<description>Clear all bits in ERR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOP_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOP_1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CINT</name>
|
|
<description>Clear Interrupt Request Register</description>
|
|
<addressOffset>0x1F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CINT</name>
|
|
<description>Clear Interrupt Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAIR</name>
|
|
<description>Clear All Interrupt Requests</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAIR_0</name>
|
|
<description>Clear only the INT bit specified in the CINT field</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAIR_1</name>
|
|
<description>Clear all bits in INT</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOP_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOP_1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT</name>
|
|
<description>Interrupt Request Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT0</name>
|
|
<description>Interrupt Request 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT0_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT0_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT1</name>
|
|
<description>Interrupt Request 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT1_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT1_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT2</name>
|
|
<description>Interrupt Request 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT2_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT2_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT3</name>
|
|
<description>Interrupt Request 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT3_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT3_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT4</name>
|
|
<description>Interrupt Request 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT4_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT4_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT5</name>
|
|
<description>Interrupt Request 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT5_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT5_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT6</name>
|
|
<description>Interrupt Request 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT6_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT6_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT7</name>
|
|
<description>Interrupt Request 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT7_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT7_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT8</name>
|
|
<description>Interrupt Request 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT8_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT8_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT9</name>
|
|
<description>Interrupt Request 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT9_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT9_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT10</name>
|
|
<description>Interrupt Request 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT10_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT10_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT11</name>
|
|
<description>Interrupt Request 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT11_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT11_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT12</name>
|
|
<description>Interrupt Request 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT12_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT12_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT13</name>
|
|
<description>Interrupt Request 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT13_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT13_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT14</name>
|
|
<description>Interrupt Request 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT14_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT14_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT15</name>
|
|
<description>Interrupt Request 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT15_0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT15_1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERR</name>
|
|
<description>Error Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERR0</name>
|
|
<description>Error In Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR0_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR0_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR1</name>
|
|
<description>Error In Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR1_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR1_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR2</name>
|
|
<description>Error In Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR2_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR2_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR3</name>
|
|
<description>Error In Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR3_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR3_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR4</name>
|
|
<description>Error In Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR4_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR4_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR5</name>
|
|
<description>Error In Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR5_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR5_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR6</name>
|
|
<description>Error In Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR6_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR6_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR7</name>
|
|
<description>Error In Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR7_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR7_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR8</name>
|
|
<description>Error In Channel 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR8_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR8_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR9</name>
|
|
<description>Error In Channel 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR9_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR9_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR10</name>
|
|
<description>Error In Channel 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR10_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR10_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR11</name>
|
|
<description>Error In Channel 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR11_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR11_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR12</name>
|
|
<description>Error In Channel 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR12_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR12_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR13</name>
|
|
<description>Error In Channel 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR13_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR13_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR14</name>
|
|
<description>Error In Channel 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR14_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR14_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR15</name>
|
|
<description>Error In Channel 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ERR15_0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERR15_1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HRS</name>
|
|
<description>Hardware Request Status Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HRS0</name>
|
|
<description>Hardware Request Status Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS0_0</name>
|
|
<description>A hardware service request for channel 0 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS0_1</name>
|
|
<description>A hardware service request for channel 0 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS1</name>
|
|
<description>Hardware Request Status Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS1_0</name>
|
|
<description>A hardware service request for channel 1 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS1_1</name>
|
|
<description>A hardware service request for channel 1 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS2</name>
|
|
<description>Hardware Request Status Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS2_0</name>
|
|
<description>A hardware service request for channel 2 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS2_1</name>
|
|
<description>A hardware service request for channel 2 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS3</name>
|
|
<description>Hardware Request Status Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS3_0</name>
|
|
<description>A hardware service request for channel 3 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS3_1</name>
|
|
<description>A hardware service request for channel 3 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS4</name>
|
|
<description>Hardware Request Status Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS4_0</name>
|
|
<description>A hardware service request for channel 4 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS4_1</name>
|
|
<description>A hardware service request for channel 4 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS5</name>
|
|
<description>Hardware Request Status Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS5_0</name>
|
|
<description>A hardware service request for channel 5 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS5_1</name>
|
|
<description>A hardware service request for channel 5 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS6</name>
|
|
<description>Hardware Request Status Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS6_0</name>
|
|
<description>A hardware service request for channel 6 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS6_1</name>
|
|
<description>A hardware service request for channel 6 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS7</name>
|
|
<description>Hardware Request Status Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS7_0</name>
|
|
<description>A hardware service request for channel 7 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS7_1</name>
|
|
<description>A hardware service request for channel 7 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS8</name>
|
|
<description>Hardware Request Status Channel 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS8_0</name>
|
|
<description>A hardware service request for channel 8 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS8_1</name>
|
|
<description>A hardware service request for channel 8 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS9</name>
|
|
<description>Hardware Request Status Channel 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS9_0</name>
|
|
<description>A hardware service request for channel 9 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS9_1</name>
|
|
<description>A hardware service request for channel 9 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS10</name>
|
|
<description>Hardware Request Status Channel 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS10_0</name>
|
|
<description>A hardware service request for channel 10 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS10_1</name>
|
|
<description>A hardware service request for channel 10 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS11</name>
|
|
<description>Hardware Request Status Channel 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS11_0</name>
|
|
<description>A hardware service request for channel 11 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS11_1</name>
|
|
<description>A hardware service request for channel 11 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS12</name>
|
|
<description>Hardware Request Status Channel 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS12_0</name>
|
|
<description>A hardware service request for channel 12 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS12_1</name>
|
|
<description>A hardware service request for channel 12 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS13</name>
|
|
<description>Hardware Request Status Channel 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS13_0</name>
|
|
<description>A hardware service request for channel 13 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS13_1</name>
|
|
<description>A hardware service request for channel 13 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS14</name>
|
|
<description>Hardware Request Status Channel 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS14_0</name>
|
|
<description>A hardware service request for channel 14 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS14_1</name>
|
|
<description>A hardware service request for channel 14 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS15</name>
|
|
<description>Hardware Request Status Channel 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRS15_0</name>
|
|
<description>A hardware service request for channel 15 is not present</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRS15_1</name>
|
|
<description>A hardware service request for channel 15 is present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EARS</name>
|
|
<description>Enable Asynchronous Request in Stop Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDREQ_0</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_0_0</name>
|
|
<description>Disable asynchronous DMA request for channel 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_0_1</name>
|
|
<description>Enable asynchronous DMA request for channel 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_1</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 1.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_1_0</name>
|
|
<description>Disable asynchronous DMA request for channel 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_1_1</name>
|
|
<description>Enable asynchronous DMA request for channel 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_2</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 2.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_2_0</name>
|
|
<description>Disable asynchronous DMA request for channel 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_2_1</name>
|
|
<description>Enable asynchronous DMA request for channel 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_3</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 3.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_3_0</name>
|
|
<description>Disable asynchronous DMA request for channel 3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_3_1</name>
|
|
<description>Enable asynchronous DMA request for channel 3.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_4</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_4_0</name>
|
|
<description>Disable asynchronous DMA request for channel 4.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_4_1</name>
|
|
<description>Enable asynchronous DMA request for channel 4.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_5</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_5_0</name>
|
|
<description>Disable asynchronous DMA request for channel 5.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_5_1</name>
|
|
<description>Enable asynchronous DMA request for channel 5.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_6</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_6_0</name>
|
|
<description>Disable asynchronous DMA request for channel 6.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_6_1</name>
|
|
<description>Enable asynchronous DMA request for channel 6.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_7</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_7_0</name>
|
|
<description>Disable asynchronous DMA request for channel 7.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_7_1</name>
|
|
<description>Enable asynchronous DMA request for channel 7.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_8</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_8_0</name>
|
|
<description>Disable asynchronous DMA request for channel 8.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_8_1</name>
|
|
<description>Enable asynchronous DMA request for channel 8.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_9</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_9_0</name>
|
|
<description>Disable asynchronous DMA request for channel 9.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_9_1</name>
|
|
<description>Enable asynchronous DMA request for channel 9.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_10</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_10_0</name>
|
|
<description>Disable asynchronous DMA request for channel 10.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_10_1</name>
|
|
<description>Enable asynchronous DMA request for channel 10.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_11</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_11_0</name>
|
|
<description>Disable asynchronous DMA request for channel 11.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_11_1</name>
|
|
<description>Enable asynchronous DMA request for channel 11.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_12</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_12_0</name>
|
|
<description>Disable asynchronous DMA request for channel 12.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_12_1</name>
|
|
<description>Enable asynchronous DMA request for channel 12.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_13</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_13_0</name>
|
|
<description>Disable asynchronous DMA request for channel 13.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_13_1</name>
|
|
<description>Enable asynchronous DMA request for channel 13.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_14</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_14_0</name>
|
|
<description>Disable asynchronous DMA request for channel 14.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_14_1</name>
|
|
<description>Enable asynchronous DMA request for channel 14.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_15</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDREQ_15_0</name>
|
|
<description>Disable asynchronous DMA request for channel 15.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDREQ_15_1</name>
|
|
<description>Enable asynchronous DMA request for channel 15.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI3</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI2</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x101</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI1</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x102</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI0</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x103</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI7</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI6</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x105</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x6</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI5</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x106</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI4</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x107</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI11</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xB</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI10</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x109</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI9</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x10A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x9</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI8</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x10B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI15</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI14</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x10D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xE</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI13</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x10E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xD</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCHPRI12</name>
|
|
<description>Channel Priority Register</description>
|
|
<addressOffset>0x10F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability. This field resets to 0.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DPA_0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DPA_1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption. This field resets to 0.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECP_0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECP_1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x1004</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x1006</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x100C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x1010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x1014</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1016</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1016</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x1018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x101C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x101E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD0_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x101E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x1020</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x1024</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x1026</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1028</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x102C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x1030</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x1034</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1036</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1036</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x1038</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x103C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x103E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD1_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x103E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x1040</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x1044</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x1046</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1048</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x104C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x1050</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x1054</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1056</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1056</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x1058</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x105C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x105E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD2_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x105E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x1060</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x1064</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x1066</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1068</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x106C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x1070</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x1074</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1076</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1076</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x1078</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x107C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x107E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD3_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x107E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x1080</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x1084</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x1086</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1088</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x108C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x1090</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x1094</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1096</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1096</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x1098</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x109C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x109E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD4_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x109E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x10A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x10A4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x10A6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x10A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x10A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x10A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x10AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x10B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x10B4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x10B6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x10B6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x10B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x10BC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x10BE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD5_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x10BE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x10C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x10C4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x10C6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x10C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x10C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x10C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x10CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x10D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x10D4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x10D6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x10D6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x10D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x10DC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x10DE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD6_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x10DE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x10E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x10E4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x10E6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x10E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x10E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x10E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x10EC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x10F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x10F4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x10F6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x10F6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x10F8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x10FC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x10FE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD7_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x10FE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x1100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x1104</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x1106</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x110C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x1110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x1114</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1116</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1116</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x1118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x111C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x111E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD8_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x111E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x1120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x1124</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x1126</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x112C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x1130</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x1134</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1136</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1136</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x1138</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x113C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x113E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD9_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x113E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x1140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x1144</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x1146</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1148</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1148</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1148</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x114C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x1150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x1154</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1156</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1156</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x1158</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x115C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x115E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD10_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x115E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x1160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x1164</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x1166</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1168</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1168</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1168</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x116C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x1170</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x1174</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1176</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1176</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x1178</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x117C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x117E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD11_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x117E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x1180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x1184</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x1186</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1188</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1188</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x1188</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x118C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x1190</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x1194</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1196</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x1196</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x1198</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x119C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x119E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD12_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x119E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x11A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x11A4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x11A6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x11A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x11A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x11A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x11AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x11B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x11B4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x11B6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x11B6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x11B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x11BC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x11BE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD13_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x11BE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x11C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x11C4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x11C6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x11C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x11C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x11C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x11CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x11D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x11D4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x11D6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x11D6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x11D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x11DC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x11DE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD14_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x11DE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x11E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x11E4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x11E6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSIZE_0</name>
|
|
<description>8-bit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_1</name>
|
|
<description>16-bit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_2</name>
|
|
<description>32-bit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_3</name>
|
|
<description>64-bit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSIZE_5</name>
|
|
<description>32-byte burst (4 beats of 64 bits)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_3</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_8</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_9</name>
|
|
<description>This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x11E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x11E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>TCD_NBYTES</alternateGroup>
|
|
<addressOffset>0x11E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMLOE_1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMLOE_0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMLOE_1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x11EC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x11F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x11F4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x11F6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_CITER_ELINK</alternateGroup>
|
|
<addressOffset>0x11F6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x11F8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>DLASTSGA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x11FC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>START_0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTMAJOR_1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTHALF_0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTHALF_1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DREQ_0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DREQ_1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ESG_0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ESG_1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAJORELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BWC_0</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_2</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BWC_3</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x11FE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCD15_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>TCD_BITER_ELINK</alternateGroup>
|
|
<addressOffset>0x11FE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ELINK_0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ELINK_1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMAMUX</name>
|
|
<description>DMAMUX</description>
|
|
<groupName>DMAMUX</groupName>
|
|
<baseAddress>0x400EC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x40</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>CHCFG[%s]</name>
|
|
<description>Channel 0 Configuration Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOURCE</name>
|
|
<description>DMA Channel Source (Slot Number)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>A_ON</name>
|
|
<description>DMA Channel Always Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>A_ON_0</name>
|
|
<description>DMA Channel Always ON function is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>A_ON_1</name>
|
|
<description>DMA Channel Always ON function is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG</name>
|
|
<description>DMA Channel Trigger Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRIG_0</name>
|
|
<description>Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIG_1</name>
|
|
<description>Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENBL</name>
|
|
<description>DMA Mux Channel Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENBL_0</name>
|
|
<description>DMA Mux channel is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENBL_1</name>
|
|
<description>DMA Mux channel is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DCP</name>
|
|
<description>DCP register reference index</description>
|
|
<groupName>DCP</groupName>
|
|
<prependToName>DCP_</prependToName>
|
|
<baseAddress>0x400F0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x434</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DCP</name>
|
|
<value>50</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DCP_VMI</name>
|
|
<value>51</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>DCP control register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF0800000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL_INTERRUPT_ENABLE</name>
|
|
<description>Per-channel interrupt enable bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_CONTEXT_SWITCHING</name>
|
|
<description>Enable automatic context switching for the channels</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_CONTEXT_CACHING</name>
|
|
<description>The software must set this bit to enable the caching of contexts between the operations</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GATHER_RESIDUAL_WRITES</name>
|
|
<description>The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRESENT_SHA</name>
|
|
<description>Indicates whether the SHA1/SHA2 functions are present.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>Absent</name>
|
|
<description>Absent</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Present</name>
|
|
<description>Present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESENT_CRYPTO</name>
|
|
<description>Indicates whether the crypto (cipher/hash) functions are present.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>Absent</name>
|
|
<description>Absent</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Present</name>
|
|
<description>Present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE</name>
|
|
<description>This bit must be set to zero for a normal operation</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFTRST</name>
|
|
<description>Set this bit to zero to enable a normal DCP operation</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL_SET</name>
|
|
<description>DCP control register 0</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF0800000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL_INTERRUPT_ENABLE</name>
|
|
<description>Per-channel interrupt enable bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_CONTEXT_SWITCHING</name>
|
|
<description>Enable automatic context switching for the channels</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_CONTEXT_CACHING</name>
|
|
<description>The software must set this bit to enable the caching of contexts between the operations</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GATHER_RESIDUAL_WRITES</name>
|
|
<description>The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRESENT_SHA</name>
|
|
<description>Indicates whether the SHA1/SHA2 functions are present.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>Absent</name>
|
|
<description>Absent</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Present</name>
|
|
<description>Present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESENT_CRYPTO</name>
|
|
<description>Indicates whether the crypto (cipher/hash) functions are present.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>Absent</name>
|
|
<description>Absent</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Present</name>
|
|
<description>Present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE</name>
|
|
<description>This bit must be set to zero for a normal operation</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFTRST</name>
|
|
<description>Set this bit to zero to enable a normal DCP operation</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL_CLR</name>
|
|
<description>DCP control register 0</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF0800000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL_INTERRUPT_ENABLE</name>
|
|
<description>Per-channel interrupt enable bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_CONTEXT_SWITCHING</name>
|
|
<description>Enable automatic context switching for the channels</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_CONTEXT_CACHING</name>
|
|
<description>The software must set this bit to enable the caching of contexts between the operations</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GATHER_RESIDUAL_WRITES</name>
|
|
<description>The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRESENT_SHA</name>
|
|
<description>Indicates whether the SHA1/SHA2 functions are present.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>Absent</name>
|
|
<description>Absent</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Present</name>
|
|
<description>Present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESENT_CRYPTO</name>
|
|
<description>Indicates whether the crypto (cipher/hash) functions are present.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>Absent</name>
|
|
<description>Absent</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Present</name>
|
|
<description>Present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE</name>
|
|
<description>This bit must be set to zero for a normal operation</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFTRST</name>
|
|
<description>Set this bit to zero to enable a normal DCP operation</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL_TOG</name>
|
|
<description>DCP control register 0</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF0800000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL_INTERRUPT_ENABLE</name>
|
|
<description>Per-channel interrupt enable bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_CONTEXT_SWITCHING</name>
|
|
<description>Enable automatic context switching for the channels</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_CONTEXT_CACHING</name>
|
|
<description>The software must set this bit to enable the caching of contexts between the operations</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GATHER_RESIDUAL_WRITES</name>
|
|
<description>The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRESENT_SHA</name>
|
|
<description>Indicates whether the SHA1/SHA2 functions are present.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>Absent</name>
|
|
<description>Absent</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Present</name>
|
|
<description>Present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESENT_CRYPTO</name>
|
|
<description>Indicates whether the crypto (cipher/hash) functions are present.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>Absent</name>
|
|
<description>Absent</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>Present</name>
|
|
<description>Present</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGATE</name>
|
|
<description>This bit must be set to zero for a normal operation</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFTRST</name>
|
|
<description>Set this bit to zero to enable a normal DCP operation</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>DCP status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ</name>
|
|
<description>Indicates which channels have pending interrupt requests</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>READY_CHANNELS</name>
|
|
<description>Indicates which channels are ready to proceed with a transfer (the active channel is also included)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUR_CHANNEL</name>
|
|
<description>Current (active) channel (encoded)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>None</name>
|
|
<description>None</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OTP_KEY_READY</name>
|
|
<description>When set, it indicates that the OTP key is shifted from the fuse block and is ready for use.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT_SET</name>
|
|
<description>DCP status register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ</name>
|
|
<description>Indicates which channels have pending interrupt requests</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>READY_CHANNELS</name>
|
|
<description>Indicates which channels are ready to proceed with a transfer (the active channel is also included)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUR_CHANNEL</name>
|
|
<description>Current (active) channel (encoded)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>None</name>
|
|
<description>None</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OTP_KEY_READY</name>
|
|
<description>When set, it indicates that the OTP key is shifted from the fuse block and is ready for use.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT_CLR</name>
|
|
<description>DCP status register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ</name>
|
|
<description>Indicates which channels have pending interrupt requests</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>READY_CHANNELS</name>
|
|
<description>Indicates which channels are ready to proceed with a transfer (the active channel is also included)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUR_CHANNEL</name>
|
|
<description>Current (active) channel (encoded)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>None</name>
|
|
<description>None</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OTP_KEY_READY</name>
|
|
<description>When set, it indicates that the OTP key is shifted from the fuse block and is ready for use.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT_TOG</name>
|
|
<description>DCP status register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ</name>
|
|
<description>Indicates which channels have pending interrupt requests</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>READY_CHANNELS</name>
|
|
<description>Indicates which channels are ready to proceed with a transfer (the active channel is also included)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUR_CHANNEL</name>
|
|
<description>Current (active) channel (encoded)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>None</name>
|
|
<description>None</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OTP_KEY_READY</name>
|
|
<description>When set, it indicates that the OTP key is shifted from the fuse block and is ready for use.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHANNELCTRL</name>
|
|
<description>DCP channel control register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_CHANNEL</name>
|
|
<description>Setting a bit in this field enables the DMA channel associated with it</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HIGH_PRIORITY_CHANNEL</name>
|
|
<description>Setting a bit in this field causes the corresponding channel to have high-priority arbitration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0_IRQ_MERGED</name>
|
|
<description>Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHANNELCTRL_SET</name>
|
|
<description>DCP channel control register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_CHANNEL</name>
|
|
<description>Setting a bit in this field enables the DMA channel associated with it</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HIGH_PRIORITY_CHANNEL</name>
|
|
<description>Setting a bit in this field causes the corresponding channel to have high-priority arbitration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0_IRQ_MERGED</name>
|
|
<description>Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHANNELCTRL_CLR</name>
|
|
<description>DCP channel control register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_CHANNEL</name>
|
|
<description>Setting a bit in this field enables the DMA channel associated with it</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HIGH_PRIORITY_CHANNEL</name>
|
|
<description>Setting a bit in this field causes the corresponding channel to have high-priority arbitration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0_IRQ_MERGED</name>
|
|
<description>Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHANNELCTRL_TOG</name>
|
|
<description>DCP channel control register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_CHANNEL</name>
|
|
<description>Setting a bit in this field enables the DMA channel associated with it</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HIGH_PRIORITY_CHANNEL</name>
|
|
<description>Setting a bit in this field causes the corresponding channel to have high-priority arbitration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CH0</name>
|
|
<description>CH0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH1</name>
|
|
<description>CH1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH2</name>
|
|
<description>CH2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CH3</name>
|
|
<description>CH3</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0_IRQ_MERGED</name>
|
|
<description>Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAPABILITY0</name>
|
|
<description>DCP capability 0 register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x404</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUM_KEYS</name>
|
|
<description>Encoded value indicating the number of key-storage locations implemented in the design</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NUM_CHANNELS</name>
|
|
<description>Encoded value indicating the number of channels implemented in the design</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE_UNIQUE_KEY</name>
|
|
<description>Write to a 1 to disable the per-device unique key</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISABLE_DECRYPT</name>
|
|
<description>Write to 1 to disable the decryption</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAPABILITY1</name>
|
|
<description>DCP capability 1 register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x70001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CIPHER_ALGORITHMS</name>
|
|
<description>One-hot field indicating which cipher algorithms are available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AES128</name>
|
|
<description>AES128</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HASH_ALGORITHMS</name>
|
|
<description>One-hot field indicating which hashing features are implemented in the hardware</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SHA1</name>
|
|
<description>SHA1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC32</name>
|
|
<description>CRC32</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHA256</name>
|
|
<description>SHA256</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONTEXT</name>
|
|
<description>DCP context buffer pointer</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Context pointer address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY</name>
|
|
<description>DCP key index</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SUBWORD</name>
|
|
<description>Key subword pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INDEX</name>
|
|
<description>Key index pointer. The valid indices are 0-[number_keys].</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEYDATA</name>
|
|
<description>DCP key data</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Word 0 data for the key. This is the least-significant word.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACKET0</name>
|
|
<description>DCP work packet 0 status register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Next pointer register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACKET1</name>
|
|
<description>DCP work packet 1 status register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTERRUPT</name>
|
|
<description>Reflects whether the channel must issue an interrupt upon the completion of the packet.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DECR_SEMAPHORE</name>
|
|
<description>Reflects whether the channel's semaphore must be decremented at the end of the current operation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Reflects whether the next command pointer register must be loaded into the channel's current descriptor pointer</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN_CONTIGUOUS</name>
|
|
<description>Reflects whether the next packet's address is located following this packet's payload.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_MEMCOPY</name>
|
|
<description>Reflects whether the selected hashing function should be enabled for this operation.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_CIPHER</name>
|
|
<description>Reflects whether the selected cipher function must be enabled for this operation.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_HASH</name>
|
|
<description>Reflects whether the selected hashing function must be enabled for this operation.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BLIT</name>
|
|
<description>Reflects whether the DCP must perform a blit operation</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CIPHER_ENCRYPT</name>
|
|
<description>When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DECRYPT</name>
|
|
<description>DECRYPT</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENCRYPT</name>
|
|
<description>ENCRYPT</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIPHER_INIT</name>
|
|
<description>Reflects whether the cipher block must load the initialization vector from the payload for this operation</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OTP_KEY</name>
|
|
<description>Reflects whether a hardware-based key must be used</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PAYLOAD_KEY</name>
|
|
<description>When set, it indicates the payload contains the key</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HASH_INIT</name>
|
|
<description>Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers must be initialized before the operation</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HASH_TERM</name>
|
|
<description>Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding must be applied by the hardware</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHECK_HASH</name>
|
|
<description>Reflects whether the calculated hash value must be compared to the hash provided in the payload.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HASH_OUTPUT</name>
|
|
<description>When the hashing is enabled, this bit controls whether the input or output data is hashed.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>INPUT</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT</name>
|
|
<description>OUTPUT</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONSTANT_FILL</name>
|
|
<description>When this bit is set (MEMCOPY and BLIT modes only), the DCP simply fills the destination buffer with the value found in the source address field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TEST_SEMA_IRQ</name>
|
|
<description>This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY!</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>KEY_BYTESWAP</name>
|
|
<description>Reflects whether the DCP engine swaps the key bytes (big-endian key).</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>KEY_WORDSWAP</name>
|
|
<description>Reflects whether the DCP engine swaps the key words (big-endian key).</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INPUT_BYTESWAP</name>
|
|
<description>Reflects whether the DCP engine byteswaps the input data (big-endian data).</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INPUT_WORDSWAP</name>
|
|
<description>Reflects whether the DCP engine wordswaps the input data (big-endian data).</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_BYTESWAP</name>
|
|
<description>Reflects whether the DCP engine byteswaps the output data (big-endian data).</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OUTPUT_WORDSWAP</name>
|
|
<description>Reflects whether the DCP engine wordswaps the output data (big-endian data).</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Packet Tag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACKET2</name>
|
|
<description>DCP work packet 2 status register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CIPHER_SELECT</name>
|
|
<description>Cipher selection field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AES128</name>
|
|
<description>AES128</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIPHER_MODE</name>
|
|
<description>Cipher mode selection field. Reflects the mode of operation for the cipher operations.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECB</name>
|
|
<description>ECB</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CBC</name>
|
|
<description>CBC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEY_SELECT</name>
|
|
<description>Key selection field</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KEY0</name>
|
|
<description>KEY0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KEY1</name>
|
|
<description>KEY1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KEY2</name>
|
|
<description>KEY2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KEY3</name>
|
|
<description>KEY3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNIQUE_KEY</name>
|
|
<description>UNIQUE_KEY</description>
|
|
<value>0xFE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OTP_KEY</name>
|
|
<description>OTP_KEY</description>
|
|
<value>0xFF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HASH_SELECT</name>
|
|
<description>Hash Selection Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SHA1</name>
|
|
<description>SHA1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRC32</name>
|
|
<description>CRC32</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHA256</name>
|
|
<description>SHA256</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIPHER_CFG</name>
|
|
<description>Cipher configuration bits. Optional configuration bits are required for the ciphers.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACKET3</name>
|
|
<description>DCP work packet 3 status register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Source buffer address pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACKET4</name>
|
|
<description>DCP work packet 4 status register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Destination buffer address pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACKET5</name>
|
|
<description>DCP work packet 5 status register</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Byte count register. This value is the working value and updates as the operation proceeds.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACKET6</name>
|
|
<description>DCP work packet 6 status register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>This regiser reflects the payload pointer for the current control packet.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0CMDPTR</name>
|
|
<description>DCP channel 0 command pointer address register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Pointer to the descriptor structure to be processed for channel 0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0SEMA</name>
|
|
<description>DCP channel 0 semaphore register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INCREMENT</name>
|
|
<description>The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>This read-only field shows the current (instantaneous) value of the semaphore counter.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0STAT</name>
|
|
<description>DCP channel 0 status register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates the additional error codes for some of the error conditions</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error signalled because the next pointer is 0x00000000</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error signalled because the semaphore is non-zero and neither chain bit is set</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error signalled because an error is reported reading/writing the context buffer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error signalled because an error is reported reading/writing the payload</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0STAT_SET</name>
|
|
<description>DCP channel 0 status register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates the additional error codes for some of the error conditions</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error signalled because the next pointer is 0x00000000</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error signalled because the semaphore is non-zero and neither chain bit is set</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error signalled because an error is reported reading/writing the context buffer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error signalled because an error is reported reading/writing the payload</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0STAT_CLR</name>
|
|
<description>DCP channel 0 status register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates the additional error codes for some of the error conditions</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error signalled because the next pointer is 0x00000000</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error signalled because the semaphore is non-zero and neither chain bit is set</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error signalled because an error is reported reading/writing the context buffer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error signalled because an error is reported reading/writing the payload</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0STAT_TOG</name>
|
|
<description>DCP channel 0 status register</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates the additional error codes for some of the error conditions</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error signalled because the next pointer is 0x00000000</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error signalled because the semaphore is non-zero and neither chain bit is set</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error signalled because an error is reported reading/writing the context buffer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error signalled because an error is reported reading/writing the payload</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0OPTS</name>
|
|
<description>DCP channel 0 options register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0OPTS_SET</name>
|
|
<description>DCP channel 0 options register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0OPTS_CLR</name>
|
|
<description>DCP channel 0 options register</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0OPTS_TOG</name>
|
|
<description>DCP channel 0 options register</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1CMDPTR</name>
|
|
<description>DCP channel 1 command pointer address register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Pointer to the descriptor structure to be processed for channel 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1SEMA</name>
|
|
<description>DCP channel 1 semaphore register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INCREMENT</name>
|
|
<description>The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and the DCP hardware substracts happening on the same clock are protected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>This read-only field shows the current (instantaneous) value of the semaphore counter.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1STAT</name>
|
|
<description>DCP channel 1 status register</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates the additional error codes for some of the error conditions.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error is signalled because the next pointer is 0x00000000.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error is signalled because an error was reported when reading/writing the context buffer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error is signalled because an error was reported when reading/writing the payload.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1STAT_SET</name>
|
|
<description>DCP channel 1 status register</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates the additional error codes for some of the error conditions.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error is signalled because the next pointer is 0x00000000.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error is signalled because an error was reported when reading/writing the context buffer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error is signalled because an error was reported when reading/writing the payload.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1STAT_CLR</name>
|
|
<description>DCP channel 1 status register</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates the additional error codes for some of the error conditions.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error is signalled because the next pointer is 0x00000000.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error is signalled because an error was reported when reading/writing the context buffer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error is signalled because an error was reported when reading/writing the payload.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1STAT_TOG</name>
|
|
<description>DCP channel 1 status register</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates the additional error codes for some of the error conditions.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error is signalled because the next pointer is 0x00000000.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error is signalled because an error was reported when reading/writing the context buffer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error is signalled because an error was reported when reading/writing the payload.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1OPTS</name>
|
|
<description>DCP channel 1 options register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1OPTS_SET</name>
|
|
<description>DCP channel 1 options register</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1OPTS_CLR</name>
|
|
<description>DCP channel 1 options register</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1OPTS_TOG</name>
|
|
<description>DCP channel 1 options register</description>
|
|
<addressOffset>0x17C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2CMDPTR</name>
|
|
<description>DCP channel 2 command pointer address register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Pointer to the descriptor structure to be processed for channel 2.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2SEMA</name>
|
|
<description>DCP channel 2 semaphore register</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INCREMENT</name>
|
|
<description>The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>This read-only field shows the current (instantaneous) value of the semaphore counter.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2STAT</name>
|
|
<description>DCP channel 2 status register</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates additional error codes for some of the error conditions.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error is signalled because the next pointer is 0x00000000.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the context buffer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the payload.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2STAT_SET</name>
|
|
<description>DCP channel 2 status register</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates additional error codes for some of the error conditions.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error is signalled because the next pointer is 0x00000000.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the context buffer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the payload.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2STAT_CLR</name>
|
|
<description>DCP channel 2 status register</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates additional error codes for some of the error conditions.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error is signalled because the next pointer is 0x00000000.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the context buffer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the payload.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2STAT_TOG</name>
|
|
<description>DCP channel 2 status register</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates additional error codes for some of the error conditions.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error is signalled because the next pointer is 0x00000000.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the context buffer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the payload.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2OPTS</name>
|
|
<description>DCP channel 2 options register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2OPTS_SET</name>
|
|
<description>DCP channel 2 options register</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2OPTS_CLR</name>
|
|
<description>DCP channel 2 options register</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2OPTS_TOG</name>
|
|
<description>DCP channel 2 options register</description>
|
|
<addressOffset>0x1BC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3CMDPTR</name>
|
|
<description>DCP channel 3 command pointer address register</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Pointer to the descriptor structure to be processed for channel 3.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3SEMA</name>
|
|
<description>DCP channel 3 semaphore register</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INCREMENT</name>
|
|
<description>The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>This read-only field shows the current (instantaneous) value of the semaphore counter.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3STAT</name>
|
|
<description>DCP channel 3 status register</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates additional error codes for some of the error conditions.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error is signalled because the next pointer is 0x00000000.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the context buffer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the payload.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3STAT_SET</name>
|
|
<description>DCP channel 3 status register</description>
|
|
<addressOffset>0x1E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates additional error codes for some of the error conditions.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error is signalled because the next pointer is 0x00000000.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the context buffer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the payload.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3STAT_CLR</name>
|
|
<description>DCP channel 3 status register</description>
|
|
<addressOffset>0x1E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates additional error codes for some of the error conditions.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error is signalled because the next pointer is 0x00000000.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the context buffer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the payload.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3STAT_TOG</name>
|
|
<description>DCP channel 3 status register</description>
|
|
<addressOffset>0x1EC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HASH_MISMATCH</name>
|
|
<description>This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SETUP</name>
|
|
<description>This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PACKET</name>
|
|
<description>This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_SRC</name>
|
|
<description>This bit indicates that a bus error occurred when reading from the source buffer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_DST</name>
|
|
<description>This bit indicates that a bus error occurred when storing to the destination buffer</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_PAGEFAULT</name>
|
|
<description>This bit indicates that a page fault occurred while converting a virtual address to a physical address</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR_CODE</name>
|
|
<description>Indicates additional error codes for some of the error conditions.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEXT_CHAIN_IS_0</name>
|
|
<description>Error is signalled because the next pointer is 0x00000000.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_CHAIN</name>
|
|
<description>Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTEXT_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the context buffer.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PAYLOAD_ERROR</name>
|
|
<description>Error is signalled because an error was reported while reading/writing the payload.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_MODE</name>
|
|
<description>Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAG</name>
|
|
<description>Indicates the tag from the last completed packet in the command structure.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3OPTS</name>
|
|
<description>DCP channel 3 options register</description>
|
|
<addressOffset>0x1F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3OPTS_SET</name>
|
|
<description>DCP channel 3 options register</description>
|
|
<addressOffset>0x1F4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3OPTS_CLR</name>
|
|
<description>DCP channel 3 options register</description>
|
|
<addressOffset>0x1F8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3OPTS_TOG</name>
|
|
<description>DCP channel 3 options register</description>
|
|
<addressOffset>0x1FC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RECOVERY_TIMER</name>
|
|
<description>This field indicates the recovery time for the channel</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGSELECT</name>
|
|
<description>DCP debug select register</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INDEX</name>
|
|
<description>Selects a value to read via the debug data register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>CONTROL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OTPKEY0</name>
|
|
<description>OTPKEY0</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OTPKEY1</name>
|
|
<description>OTPKEY1</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OTPKEY2</name>
|
|
<description>OTPKEY2</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OTPKEY3</name>
|
|
<description>OTPKEY3</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBGDATA</name>
|
|
<description>DCP debug data register</description>
|
|
<addressOffset>0x410</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Debug data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PAGETABLE</name>
|
|
<description>DCP page table register</description>
|
|
<addressOffset>0x420</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Page table enable control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FLUSH</name>
|
|
<description>Page table flush control. To flush the TLB, write this bit to 1 and then back to 0.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BASE</name>
|
|
<description>Page table base address</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VERSION</name>
|
|
<description>DCP version register</description>
|
|
<addressOffset>0x430</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x2010000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STEP</name>
|
|
<description>Fixed read-only value reflecting the stepping of the version of the design implementation.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Fixed read-only value reflecting the MINOR version of the design implementation.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Fixed read-only value reflecting the MAJOR version of the design implementation.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPC</name>
|
|
<description>GPC</description>
|
|
<groupName>GPC</groupName>
|
|
<prependToName>GPC_</prependToName>
|
|
<baseAddress>0x400F4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x3C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPC</name>
|
|
<value>66</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CNTR</name>
|
|
<description>GPC Interface control register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x520000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEGA_PDN_REQ</name>
|
|
<description>MEGA domain power down request</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MEGA_PDN_REQ_0</name>
|
|
<description>No Request</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEGA_PDN_REQ_1</name>
|
|
<description>Request power down sequence</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEGA_PUP_REQ</name>
|
|
<description>MEGA domain power up request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MEGA_PUP_REQ_0</name>
|
|
<description>No Request</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEGA_PUP_REQ_1</name>
|
|
<description>Request power up sequence</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDRAM0_PGE</name>
|
|
<description>FlexRAM PDRAM0 Power Gate Enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PDRAM0_PGE_0</name>
|
|
<description>FlexRAM PDRAM0 domain will keep power even if the CPU core is powered down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PDRAM0_PGE_1</name>
|
|
<description>FlexRAM PDRAM0 domain will be powered down when the CPU core is powered down..</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR1</name>
|
|
<description>IRQ masking register 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMR1</name>
|
|
<description>IRQ[31:0] masking bits: 1-irq masked, 0-irq is not masked</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR2</name>
|
|
<description>IRQ masking register 2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMR2</name>
|
|
<description>IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR3</name>
|
|
<description>IRQ masking register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMR3</name>
|
|
<description>IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR4</name>
|
|
<description>IRQ masking register 4</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMR4</name>
|
|
<description>IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR1</name>
|
|
<description>IRQ status resister 1</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISR1</name>
|
|
<description>IRQ[31:0] status, read only</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR2</name>
|
|
<description>IRQ status resister 2</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISR2</name>
|
|
<description>IRQ[63:32] status, read only</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR3</name>
|
|
<description>IRQ status resister 3</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISR3</name>
|
|
<description>IRQ[95:64] status, read only</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR4</name>
|
|
<description>IRQ status resister 4</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISR4</name>
|
|
<description>IRQ[127:96] status, read only</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR5</name>
|
|
<description>IRQ masking register 5</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMR5</name>
|
|
<description>IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR5</name>
|
|
<description>IRQ status resister 5</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISR4</name>
|
|
<description>IRQ[159:128] status, read only</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PGC</name>
|
|
<description>PGC</description>
|
|
<alternatePeripheral>GPC</alternatePeripheral>
|
|
<groupName>PGC</groupName>
|
|
<prependToName>PGC_</prependToName>
|
|
<baseAddress>0x400F4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x2B0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MEGA_CTRL</name>
|
|
<description>PGC Mega Control Register</description>
|
|
<addressOffset>0x220</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PCR_0</name>
|
|
<description>Do not switch off power even if pdn_req is asserted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PCR_1</name>
|
|
<description>Switch off power when pdn_req is asserted.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEGA_PUPSCR</name>
|
|
<description>PGC Mega Power Up Sequence Control Register</description>
|
|
<addressOffset>0x224</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW</name>
|
|
<description>After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SW2ISO</name>
|
|
<description>After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEGA_PDNSCR</name>
|
|
<description>PGC Mega Pull Down Sequence Control Register</description>
|
|
<addressOffset>0x228</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x101</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISO</name>
|
|
<description>After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISO2SW</name>
|
|
<description>After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MEGA_SR</name>
|
|
<description>PGC Mega Power Gating Controller Status Register</description>
|
|
<addressOffset>0x22C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSR</name>
|
|
<description>Power status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PSR_0</name>
|
|
<description>The target subsystem was not powered down for the previous power-down request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSR_1</name>
|
|
<description>The target subsystem was powered down for the previous power-down request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPU_CTRL</name>
|
|
<description>PGC CPU Control Register</description>
|
|
<addressOffset>0x2A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCR</name>
|
|
<description>Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PCR_0</name>
|
|
<description>Do not switch off power even if pdn_req is asserted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PCR_1</name>
|
|
<description>Switch off power when pdn_req is asserted.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPU_PUPSCR</name>
|
|
<description>PGC CPU Power Up Sequence Control Register</description>
|
|
<addressOffset>0x2A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW</name>
|
|
<description>There are two different silicon revisions: 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SW2ISO</name>
|
|
<description>There are two different silicon revisions: 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPU_PDNSCR</name>
|
|
<description>PGC CPU Pull Down Sequence Control Register</description>
|
|
<addressOffset>0x2A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x101</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISO</name>
|
|
<description>After a power-down request (pdn_req assertion), the PGC waits a number of 32k clocks equal to the value of ISO before asserting isolation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISO2SW</name>
|
|
<description>After asserting isolation, the PGC waits a number of 32k clocks equal to the value of ISO2SW before negating</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPU_SR</name>
|
|
<description>PGC CPU Power Gating Controller Status Register</description>
|
|
<addressOffset>0x2AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSR</name>
|
|
<description>Power status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PSR_0</name>
|
|
<description>The target subsystem was not powered down for the previous power-down request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSR_1</name>
|
|
<description>The target subsystem was powered down for the previous power-down request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SRC</name>
|
|
<description>SRC</description>
|
|
<groupName>SRC</groupName>
|
|
<prependToName>SRC_</prependToName>
|
|
<baseAddress>0x400F8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x48</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SRC</name>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>SRC Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA0480520</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>lockup_rst</name>
|
|
<description>lockup reset enable bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>lockup_rst_0</name>
|
|
<description>disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>lockup_rst_1</name>
|
|
<description>enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>mask_wdog_rst</name>
|
|
<description>Mask wdog_rst_b source</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>mask_wdog_rst_5</name>
|
|
<description>wdog_rst_b is masked</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>mask_wdog_rst_10</name>
|
|
<description>wdog_rst_b is not masked (default)</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>core0_rst</name>
|
|
<description>Software reset for core0 only</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>core0_rst_0</name>
|
|
<description>do not assert core0 reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>core0_rst_1</name>
|
|
<description>assert core0 reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>core0_dbg_rst</name>
|
|
<description>Software reset for core0 debug only</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>core0_dbg_rst_0</name>
|
|
<description>do not assert core0 debug reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>core0_dbg_rst_1</name>
|
|
<description>assert core0 debug reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>dbg_rst_msk_pg</name>
|
|
<description>Do not assert debug resets after power gating event of core</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>dbg_rst_msk_pg_0</name>
|
|
<description>do not mask core debug resets (debug resets will be asserted after power gating event)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>dbg_rst_msk_pg_1</name>
|
|
<description>mask core debug resets (debug resets won't be asserted after power gating event)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>mask_wdog3_rst</name>
|
|
<description>Mask wdog3_rst_b source</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>mask_wdog3_rst_5</name>
|
|
<description>wdog3_rst_b is masked</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>mask_wdog3_rst_10</name>
|
|
<description>wdog3_rst_b is not masked</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SBMR1</name>
|
|
<description>SRC Boot Mode Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BOOT_CFG1</name>
|
|
<description>Refer to fusemap.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BOOT_CFG2</name>
|
|
<description>Refer to fusemap.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BOOT_CFG3</name>
|
|
<description>Refer to fusemap.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BOOT_CFG4</name>
|
|
<description>Refer to fusemap.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRSR</name>
|
|
<description>SRC Reset Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ipp_reset_b</name>
|
|
<description>Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ipp_reset_b_0</name>
|
|
<description>Reset is not a result of ipp_reset_b pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ipp_reset_b_1</name>
|
|
<description>Reset is a result of ipp_reset_b pin.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>lockup</name>
|
|
<description>Indicates a reset has been caused by CPU lockup.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>lockup_0</name>
|
|
<description>Reset is not a result of the mentioned case.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>lockup_1</name>
|
|
<description>Reset is a result of the mentioned case.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>csu_reset_b</name>
|
|
<description>Indicates whether the reset was the result of the csu_reset_b input.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>csu_reset_b_0</name>
|
|
<description>Reset is not a result of the csu_reset_b event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>csu_reset_b_1</name>
|
|
<description>Reset is a result of the csu_reset_b event.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ipp_user_reset_b</name>
|
|
<description>Indicates whether the reset was the result of the ipp_user_reset_b qualified reset.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ipp_user_reset_b_0</name>
|
|
<description>Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ipp_user_reset_b_1</name>
|
|
<description>Reset is a result of the ipp_user_reset_b qualified as COLD reset event.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>wdog_rst_b</name>
|
|
<description>IC Watchdog Time-out reset</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>wdog_rst_b_0</name>
|
|
<description>Reset is not a result of the watchdog time-out event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>wdog_rst_b_1</name>
|
|
<description>Reset is a result of the watchdog time-out event.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>jtag_rst_b</name>
|
|
<description>HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>jtag_rst_b_0</name>
|
|
<description>Reset is not a result of HIGH-Z reset from JTAG.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>jtag_rst_b_1</name>
|
|
<description>Reset is a result of HIGH-Z reset from JTAG.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>jtag_sw_rst</name>
|
|
<description>JTAG software reset</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>jtag_sw_rst_0</name>
|
|
<description>Reset is not a result of the mentioned case.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>jtag_sw_rst_1</name>
|
|
<description>Reset is not a result of the mentioned case.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>wdog3_rst_b</name>
|
|
<description>IC Watchdog3 Time-out reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>wdog3_rst_b_0</name>
|
|
<description>Reset is not a result of the watchdog3 time-out event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>wdog3_rst_b_1</name>
|
|
<description>Reset is a result of the watchdog3 time-out event.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>tempsense_rst_b</name>
|
|
<description>Temper Sensor software reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>tempsense_rst_b_0</name>
|
|
<description>Reset is not a result of software reset from Temperature Sensor.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>tempsense_rst_b_1</name>
|
|
<description>Reset is a result of software reset from Temperature Sensor.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SBMR2</name>
|
|
<description>SRC Boot Mode Register 2</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEC_CONFIG</name>
|
|
<description>SECONFIG[1] shows the state of the SECONFIG[1] fuse</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR_BT_DIS</name>
|
|
<description>DIR_BT_DIS shows the state of the DIR_BT_DIS fuse</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BT_FUSE_SEL</name>
|
|
<description>BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BMOD</name>
|
|
<description>BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR1</name>
|
|
<description>SRC General Purpose Register 1</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERSISTENT_ENTRY0</name>
|
|
<description>Holds entry function for core0 for waking-up from low power mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR2</name>
|
|
<description>SRC General Purpose Register 2</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERSISTENT_ARG0</name>
|
|
<description>Holds argument of entry function for core0 for waking-up from low power mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPR3</name>
|
|
<description>SRC General Purpose Register 3</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR4</name>
|
|
<description>SRC General Purpose Register 4</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR5</name>
|
|
<description>SRC General Purpose Register 5</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR6</name>
|
|
<description>SRC General Purpose Register 6</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR7</name>
|
|
<description>SRC General Purpose Register 7</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR8</name>
|
|
<description>SRC General Purpose Register 8</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR9</name>
|
|
<description>SRC General Purpose Register 9</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>GPR10</name>
|
|
<description>SRC General Purpose Register 10</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERSIST_REDUNDANT_BOOT</name>
|
|
<description>This field identifies which image must be used - 0/1/2/3</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PERSIST_SECONDARY_BOOT</name>
|
|
<description>This bit identifies which image must be used - primary and secondary</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CCM</name>
|
|
<description>CCM</description>
|
|
<groupName>CCM</groupName>
|
|
<prependToName>CCM_</prependToName>
|
|
<baseAddress>0x400FC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CCM_1</name>
|
|
<value>42</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CCM_2</name>
|
|
<value>43</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>CCM Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x401107F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OSCNT</name>
|
|
<description>Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for the dpll_ip to use and only then the gate in dpll_ip can be opened.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COSC_EN</name>
|
|
<description>On chip oscillator enable bit - this bit value is reflected on the output cosc_en</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COSC_EN_0</name>
|
|
<description>disable on chip oscillator</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COSC_EN_1</name>
|
|
<description>enable on chip oscillator</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REG_BYPASS_COUNT</name>
|
|
<description>Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REG_BYPASS_COUNT_0</name>
|
|
<description>no delay</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG_BYPASS_COUNT_1</name>
|
|
<description>1 CKIL clock period delay</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REG_BYPASS_COUNT_63</name>
|
|
<description>63 CKIL clock periods delay</description>
|
|
<value>0x3F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RBC_EN</name>
|
|
<description>Enable for REG_BYPASS_COUNTER</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RBC_EN_0</name>
|
|
<description>REG_BYPASS_COUNTER disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RBC_EN_1</name>
|
|
<description>REG_BYPASS_COUNTER enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR</name>
|
|
<description>CCM Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REF_EN_B</name>
|
|
<description>Status of the value of CCM_REF_EN_B output of ccm</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_EN_B_0</name>
|
|
<description>value of CCM_REF_EN_B is '0'</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REF_EN_B_1</name>
|
|
<description>value of CCM_REF_EN_B is '1'</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAMP2_READY</name>
|
|
<description>Status indication of CAMP2.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAMP2_READY_0</name>
|
|
<description>CAMP2 is not ready.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAMP2_READY_1</name>
|
|
<description>CAMP2 is ready.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COSC_READY</name>
|
|
<description>Status indication of on board oscillator</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COSC_READY_0</name>
|
|
<description>on board oscillator is not ready.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COSC_READY_1</name>
|
|
<description>on board oscillator is ready.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCSR</name>
|
|
<description>CCM Clock Switcher Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PLL3_SW_CLK_SEL</name>
|
|
<description>Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLL3_SW_CLK_SEL_0</name>
|
|
<description>pll3_main_clk</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL3_SW_CLK_SEL_1</name>
|
|
<description>pll3 bypass clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CBCDR</name>
|
|
<description>CCM Bus Clock Divider Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x28000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IPG_PODF</name>
|
|
<description>Divider for ipg podf.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IPG_PODF_0</name>
|
|
<description>divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IPG_PODF_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IPG_PODF_2</name>
|
|
<description>divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IPG_PODF_3</name>
|
|
<description>divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AHB_PODF</name>
|
|
<description>Divider for AHB PODF</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AHB_PODF_0</name>
|
|
<description>divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_PODF_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_PODF_2</name>
|
|
<description>divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_PODF_3</name>
|
|
<description>divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_PODF_4</name>
|
|
<description>divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_PODF_5</name>
|
|
<description>divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_PODF_6</name>
|
|
<description>divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_PODF_7</name>
|
|
<description>divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PERIPH_CLK_SEL</name>
|
|
<description>Selector for peripheral main clock</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PERIPH_CLK_SEL_0</name>
|
|
<description>derive clock selected by CCM_CBCMR[CORE_CLK_PRE_SEL]</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PERIPH_CLK_SEL_1</name>
|
|
<description>derive clock selected by CCM_CBCMR[PERIPH_CLK2_SEL]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CBCMR</name>
|
|
<description>CCM Bus Clock Multiplexer Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC088020</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPSPI_CLK_SEL</name>
|
|
<description>Selector for lpspi clock multiplexer</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSPI_CLK_SEL_0</name>
|
|
<description>derive clock from PLL3 PFD1 clk</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_CLK_SEL_1</name>
|
|
<description>derive clock from PLL3 PFD0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_CLK_SEL_2</name>
|
|
<description>derive clock from PLL2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_CLK_SEL_3</name>
|
|
<description>derive clock from PLL2 PFD2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PERIPH_CLK2_SEL</name>
|
|
<description>Selector for peripheral clk2 clock multiplexer</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PERIPH_CLK2_SEL_0</name>
|
|
<description>derive clock from pll3_sw_clk</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PERIPH_CLK2_SEL_1</name>
|
|
<description>derive clock from osc_clk</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PERIPH_CLK2_SEL_2</name>
|
|
<description>derive clock from pll2_bypass_clk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRACE_CLK_SEL</name>
|
|
<description>Selector for Trace clock multiplexer</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRACE_CLK_SEL_0</name>
|
|
<description>derive clock from PLL2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_CLK_SEL_1</name>
|
|
<description>derive clock from PLL2 PFD2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_CLK_SEL_2</name>
|
|
<description>derive clock from PLL2 PFD0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_CLK_SEL_3</name>
|
|
<description>derive clock from PLL2 PFD1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRE_PERIPH_CLK_SEL</name>
|
|
<description>Selector for pre_periph clock multiplexer</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRE_PERIPH_CLK_SEL_0</name>
|
|
<description>derive clock from PLL2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRE_PERIPH_CLK_SEL_1</name>
|
|
<description>derive clock from PLL3 PFD3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRE_PERIPH_CLK_SEL_2</name>
|
|
<description>derive clock from PLL2 PFD3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRE_PERIPH_CLK_SEL_3</name>
|
|
<description>derive clock from PLL6</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPSPI_PODF</name>
|
|
<description>Divider for LPSPI. Divider should be updated when output clock is gated.</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_0</name>
|
|
<description>divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_2</name>
|
|
<description>divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_3</name>
|
|
<description>divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_4</name>
|
|
<description>divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_5</name>
|
|
<description>divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_6</name>
|
|
<description>divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_7</name>
|
|
<description>divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_8</name>
|
|
<description>divide by 9</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_9</name>
|
|
<description>divide by 10</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_10</name>
|
|
<description>divide by 11</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_11</name>
|
|
<description>divide by 12</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_12</name>
|
|
<description>divide by 13</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_13</name>
|
|
<description>divide by 14</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_14</name>
|
|
<description>divide by 15</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPSPI_PODF_15</name>
|
|
<description>divide by 16</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSCMR1</name>
|
|
<description>CCM Serial Clock Multiplexer Register 1</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80FC00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERCLK_PODF</name>
|
|
<description>Divider for perclk podf.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_1</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_2</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_3</name>
|
|
<description>Divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_4</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_5</name>
|
|
<description>Divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_6</name>
|
|
<description>Divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_7</name>
|
|
<description>Divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_8</name>
|
|
<description>Divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_9</name>
|
|
<description>Divide by 9</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_10</name>
|
|
<description>Divide by 10</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_11</name>
|
|
<description>Divide by 11</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_12</name>
|
|
<description>Divide by 12</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_13</name>
|
|
<description>Divide by 13</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_14</name>
|
|
<description>Divide by 14</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_15</name>
|
|
<description>Divide by 15</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_16</name>
|
|
<description>Divide by 16</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_17</name>
|
|
<description>Divide by 17</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_18</name>
|
|
<description>Divide by 18</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_19</name>
|
|
<description>Divide by 19</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_20</name>
|
|
<description>Divide by 20</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_21</name>
|
|
<description>Divide by 21</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_22</name>
|
|
<description>Divide by 22</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_23</name>
|
|
<description>Divide by 23</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_24</name>
|
|
<description>Divide by 24</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_25</name>
|
|
<description>Divide by 25</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_26</name>
|
|
<description>Divide by 26</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_27</name>
|
|
<description>Divide by 27</description>
|
|
<value>0x1A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_28</name>
|
|
<description>Divide by 28</description>
|
|
<value>0x1B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_29</name>
|
|
<description>Divide by 29</description>
|
|
<value>0x1C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_30</name>
|
|
<description>Divide by 30</description>
|
|
<value>0x1D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_31</name>
|
|
<description>Divide by 31</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_32</name>
|
|
<description>Divide by 32</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_33</name>
|
|
<description>Divide by 33</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_34</name>
|
|
<description>Divide by 34</description>
|
|
<value>0x21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_35</name>
|
|
<description>Divide by 35</description>
|
|
<value>0x22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_36</name>
|
|
<description>Divide by 36</description>
|
|
<value>0x23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_37</name>
|
|
<description>Divide by 37</description>
|
|
<value>0x24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_38</name>
|
|
<description>Divide by 38</description>
|
|
<value>0x25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_39</name>
|
|
<description>Divide by 39</description>
|
|
<value>0x26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_40</name>
|
|
<description>Divide by 40</description>
|
|
<value>0x27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_41</name>
|
|
<description>Divide by 41</description>
|
|
<value>0x28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_42</name>
|
|
<description>Divide by 42</description>
|
|
<value>0x29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_43</name>
|
|
<description>Divide by 43</description>
|
|
<value>0x2A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_44</name>
|
|
<description>Divide by 44</description>
|
|
<value>0x2B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_45</name>
|
|
<description>Divide by 45</description>
|
|
<value>0x2C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_46</name>
|
|
<description>Divide by 46</description>
|
|
<value>0x2D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_47</name>
|
|
<description>Divide by 47</description>
|
|
<value>0x2E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_48</name>
|
|
<description>Divide by 48</description>
|
|
<value>0x2F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_49</name>
|
|
<description>Divide by 49</description>
|
|
<value>0x30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_50</name>
|
|
<description>Divide by 50</description>
|
|
<value>0x31</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_51</name>
|
|
<description>Divide by 51</description>
|
|
<value>0x32</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_52</name>
|
|
<description>Divide by 52</description>
|
|
<value>0x33</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_53</name>
|
|
<description>Divide by 53</description>
|
|
<value>0x34</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_54</name>
|
|
<description>Divide by 54</description>
|
|
<value>0x35</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_55</name>
|
|
<description>Divide by 55</description>
|
|
<value>0x36</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_56</name>
|
|
<description>Divide by 56</description>
|
|
<value>0x37</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_57</name>
|
|
<description>Divide by 57</description>
|
|
<value>0x38</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_58</name>
|
|
<description>Divide by 58</description>
|
|
<value>0x39</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_59</name>
|
|
<description>Divide by 59</description>
|
|
<value>0x3A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_60</name>
|
|
<description>Divide by 60</description>
|
|
<value>0x3B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_61</name>
|
|
<description>Divide by 61</description>
|
|
<value>0x3C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_62</name>
|
|
<description>Divide by 62</description>
|
|
<value>0x3D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_63</name>
|
|
<description>Divide by 63</description>
|
|
<value>0x3E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_64</name>
|
|
<description>Divide by 64</description>
|
|
<value>0x3F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PERCLK_CLK_SEL</name>
|
|
<description>Selector for the perclk clock multiplexor</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PERCLK_CLK_SEL_0</name>
|
|
<description>derive clock from ipg clk root</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PERCLK_CLK_SEL_1</name>
|
|
<description>derive clock from osc_clk</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI1_CLK_SEL</name>
|
|
<description>Selector for sai1 clock multiplexer</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI1_CLK_SEL_0</name>
|
|
<description>derive clock from PLL3 PFD2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_CLK_SEL_1</name>
|
|
<description>derive from pll3_sw_clk</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_CLK_SEL_2</name>
|
|
<description>derive clock from PLL4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI3_CLK_SEL</name>
|
|
<description>Selector for sai3 clock multiplexer</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI3_CLK_SEL_0</name>
|
|
<description>derive clock from PLL3 PFD2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_CLK_SEL_1</name>
|
|
<description>derive from pll3_sw_clk</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_CLK_SEL_2</name>
|
|
<description>derive clock from PLL4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXSPI_PODF</name>
|
|
<description>Divider for flexspi clock root.</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_PODF_0</name>
|
|
<description>divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_PODF_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_PODF_2</name>
|
|
<description>divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_PODF_3</name>
|
|
<description>divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_PODF_4</name>
|
|
<description>divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_PODF_5</name>
|
|
<description>divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_PODF_6</name>
|
|
<description>divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_PODF_7</name>
|
|
<description>divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXSPI_CLK_SEL</name>
|
|
<description>Selector for flexspi clock multiplexer</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_CLK_SEL_0</name>
|
|
<description>derive clock from PLL2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_CLK_SEL_1</name>
|
|
<description>derive clock from pll3_sw_clk</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_CLK_SEL_2</name>
|
|
<description>derive clock from PLL2 PFD2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_CLK_SEL_3</name>
|
|
<description>derive clock from PLL3 PFD0</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXSPI_CLK_SRC</name>
|
|
<description>Select for source of flexspi_clk_root</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_CLK_SRC_0</name>
|
|
<description>derive clock selected by CCM_CSCMR1[FLEXSPI_CLK_SEL]</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_CLK_SRC_1</name>
|
|
<description>derive clock selected by CCM_CBCMR[PERIPH_CLK2_ SEL]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSCMR2</name>
|
|
<description>CCM Serial Clock Multiplexer Register 2</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x180000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLEXIO1_CLK_SEL</name>
|
|
<description>Selector for flexio1 clock multiplexer</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_CLK_SEL_0</name>
|
|
<description>derive clock from PLL4 divided clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_CLK_SEL_1</name>
|
|
<description>derive clock from PLL3 PFD2 clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_CLK_SEL_2</name>
|
|
<description>derive from PLL2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_CLK_SEL_3</name>
|
|
<description>derive clock from pll3_sw_clk</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACLK_PODF</name>
|
|
<description>Divider for ADC alt_clk, as the list below (other values reserved).</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_ACLK_PODF_7</name>
|
|
<description>pll3_sw_clk / 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_ACLK_PODF_11</name>
|
|
<description>pll3_sw_clk / 12</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_ACLK_PODF_15</name>
|
|
<description>pll3_sw_clk / 16</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACLK_EN</name>
|
|
<description>Enable ADC alt_clk, so that ADC alt_clk can be driven be divided pll3_sw_clk.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_ACLK_EN_0</name>
|
|
<description>ADC alt_clk source is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_ACLK_EN_1</name>
|
|
<description>ADC alt_clk source is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSCDR1</name>
|
|
<description>CCM Serial Clock Divider Register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x6000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UART_CLK_PODF</name>
|
|
<description>Divider for uart clock podf.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_1</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_2</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_3</name>
|
|
<description>Divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_4</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_5</name>
|
|
<description>Divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_6</name>
|
|
<description>Divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_7</name>
|
|
<description>Divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_8</name>
|
|
<description>Divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_9</name>
|
|
<description>Divide by 9</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_10</name>
|
|
<description>Divide by 10</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_11</name>
|
|
<description>Divide by 11</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_12</name>
|
|
<description>Divide by 12</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_13</name>
|
|
<description>Divide by 13</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_14</name>
|
|
<description>Divide by 14</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_15</name>
|
|
<description>Divide by 15</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_16</name>
|
|
<description>Divide by 16</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_17</name>
|
|
<description>Divide by 17</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_18</name>
|
|
<description>Divide by 18</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_19</name>
|
|
<description>Divide by 19</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_20</name>
|
|
<description>Divide by 20</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_21</name>
|
|
<description>Divide by 21</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_22</name>
|
|
<description>Divide by 22</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_23</name>
|
|
<description>Divide by 23</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_24</name>
|
|
<description>Divide by 24</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_25</name>
|
|
<description>Divide by 25</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_26</name>
|
|
<description>Divide by 26</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_27</name>
|
|
<description>Divide by 27</description>
|
|
<value>0x1A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_28</name>
|
|
<description>Divide by 28</description>
|
|
<value>0x1B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_29</name>
|
|
<description>Divide by 29</description>
|
|
<value>0x1C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_30</name>
|
|
<description>Divide by 30</description>
|
|
<value>0x1D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_31</name>
|
|
<description>Divide by 31</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_32</name>
|
|
<description>Divide by 32</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_33</name>
|
|
<description>Divide by 33</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_34</name>
|
|
<description>Divide by 34</description>
|
|
<value>0x21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_35</name>
|
|
<description>Divide by 35</description>
|
|
<value>0x22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_36</name>
|
|
<description>Divide by 36</description>
|
|
<value>0x23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_37</name>
|
|
<description>Divide by 37</description>
|
|
<value>0x24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_38</name>
|
|
<description>Divide by 38</description>
|
|
<value>0x25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_39</name>
|
|
<description>Divide by 39</description>
|
|
<value>0x26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_40</name>
|
|
<description>Divide by 40</description>
|
|
<value>0x27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_41</name>
|
|
<description>Divide by 41</description>
|
|
<value>0x28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_42</name>
|
|
<description>Divide by 42</description>
|
|
<value>0x29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_43</name>
|
|
<description>Divide by 43</description>
|
|
<value>0x2A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_44</name>
|
|
<description>Divide by 44</description>
|
|
<value>0x2B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_45</name>
|
|
<description>Divide by 45</description>
|
|
<value>0x2C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_46</name>
|
|
<description>Divide by 46</description>
|
|
<value>0x2D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_47</name>
|
|
<description>Divide by 47</description>
|
|
<value>0x2E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_48</name>
|
|
<description>Divide by 48</description>
|
|
<value>0x2F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_49</name>
|
|
<description>Divide by 49</description>
|
|
<value>0x30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_50</name>
|
|
<description>Divide by 50</description>
|
|
<value>0x31</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_51</name>
|
|
<description>Divide by 51</description>
|
|
<value>0x32</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_52</name>
|
|
<description>Divide by 52</description>
|
|
<value>0x33</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_53</name>
|
|
<description>Divide by 53</description>
|
|
<value>0x34</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_54</name>
|
|
<description>Divide by 54</description>
|
|
<value>0x35</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_55</name>
|
|
<description>Divide by 55</description>
|
|
<value>0x36</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_56</name>
|
|
<description>Divide by 56</description>
|
|
<value>0x37</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_57</name>
|
|
<description>Divide by 57</description>
|
|
<value>0x38</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_58</name>
|
|
<description>Divide by 58</description>
|
|
<value>0x39</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_59</name>
|
|
<description>Divide by 59</description>
|
|
<value>0x3A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_60</name>
|
|
<description>Divide by 60</description>
|
|
<value>0x3B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_61</name>
|
|
<description>Divide by 61</description>
|
|
<value>0x3C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_62</name>
|
|
<description>Divide by 62</description>
|
|
<value>0x3D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_63</name>
|
|
<description>Divide by 63</description>
|
|
<value>0x3E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_64</name>
|
|
<description>Divide by 64</description>
|
|
<value>0x3F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART_CLK_SEL</name>
|
|
<description>Selector for the UART clock multiplexor</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART_CLK_SEL_0</name>
|
|
<description>derive clock from pll3_80m</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_CLK_SEL_1</name>
|
|
<description>derive clock from osc_clk</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_CLK_SEL_2</name>
|
|
<description>derive clock from per_clk_root</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRACE_PODF</name>
|
|
<description>Divider for trace clock. Divider should be updated when output clock is gated.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_0</name>
|
|
<description>divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_2</name>
|
|
<description>divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_3</name>
|
|
<description>divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_4</name>
|
|
<description>divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_5</name>
|
|
<description>divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_6</name>
|
|
<description>divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_7</name>
|
|
<description>divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_8</name>
|
|
<description>divide by 9</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_9</name>
|
|
<description>divide by 10</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_10</name>
|
|
<description>divide by 11</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_11</name>
|
|
<description>divide by 12</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_12</name>
|
|
<description>divide by 13</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_13</name>
|
|
<description>divide by 14</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_14</name>
|
|
<description>divide by 15</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRACE_PODF_15</name>
|
|
<description>divide by 16</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CS1CDR</name>
|
|
<description>CCM Clock Divider Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xEC102C1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SAI1_CLK_PODF</name>
|
|
<description>Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_1</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_2</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_3</name>
|
|
<description>Divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_4</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_5</name>
|
|
<description>Divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_6</name>
|
|
<description>Divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_7</name>
|
|
<description>Divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_8</name>
|
|
<description>Divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_9</name>
|
|
<description>Divide by 9</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_10</name>
|
|
<description>Divide by 10</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_11</name>
|
|
<description>Divide by 11</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_12</name>
|
|
<description>Divide by 12</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_13</name>
|
|
<description>Divide by 13</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_14</name>
|
|
<description>Divide by 14</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_15</name>
|
|
<description>Divide by 15</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_16</name>
|
|
<description>Divide by 16</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_17</name>
|
|
<description>Divide by 17</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_18</name>
|
|
<description>Divide by 18</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_19</name>
|
|
<description>Divide by 19</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_20</name>
|
|
<description>Divide by 20</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_21</name>
|
|
<description>Divide by 21</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_22</name>
|
|
<description>Divide by 22</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_23</name>
|
|
<description>Divide by 23</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_24</name>
|
|
<description>Divide by 24</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_25</name>
|
|
<description>Divide by 25</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_26</name>
|
|
<description>Divide by 26</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_27</name>
|
|
<description>Divide by 27</description>
|
|
<value>0x1A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_28</name>
|
|
<description>Divide by 28</description>
|
|
<value>0x1B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_29</name>
|
|
<description>Divide by 29</description>
|
|
<value>0x1C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_30</name>
|
|
<description>Divide by 30</description>
|
|
<value>0x1D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_31</name>
|
|
<description>Divide by 31</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_32</name>
|
|
<description>Divide by 32</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_33</name>
|
|
<description>Divide by 33</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_34</name>
|
|
<description>Divide by 34</description>
|
|
<value>0x21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_35</name>
|
|
<description>Divide by 35</description>
|
|
<value>0x22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_36</name>
|
|
<description>Divide by 36</description>
|
|
<value>0x23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_37</name>
|
|
<description>Divide by 37</description>
|
|
<value>0x24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_38</name>
|
|
<description>Divide by 38</description>
|
|
<value>0x25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_39</name>
|
|
<description>Divide by 39</description>
|
|
<value>0x26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_40</name>
|
|
<description>Divide by 40</description>
|
|
<value>0x27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_41</name>
|
|
<description>Divide by 41</description>
|
|
<value>0x28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_42</name>
|
|
<description>Divide by 42</description>
|
|
<value>0x29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_43</name>
|
|
<description>Divide by 43</description>
|
|
<value>0x2A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_44</name>
|
|
<description>Divide by 44</description>
|
|
<value>0x2B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_45</name>
|
|
<description>Divide by 45</description>
|
|
<value>0x2C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_46</name>
|
|
<description>Divide by 46</description>
|
|
<value>0x2D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_47</name>
|
|
<description>Divide by 47</description>
|
|
<value>0x2E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_48</name>
|
|
<description>Divide by 48</description>
|
|
<value>0x2F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_49</name>
|
|
<description>Divide by 49</description>
|
|
<value>0x30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_50</name>
|
|
<description>Divide by 50</description>
|
|
<value>0x31</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_51</name>
|
|
<description>Divide by 51</description>
|
|
<value>0x32</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_52</name>
|
|
<description>Divide by 52</description>
|
|
<value>0x33</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_53</name>
|
|
<description>Divide by 53</description>
|
|
<value>0x34</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_54</name>
|
|
<description>Divide by 54</description>
|
|
<value>0x35</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_55</name>
|
|
<description>Divide by 55</description>
|
|
<value>0x36</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_56</name>
|
|
<description>Divide by 56</description>
|
|
<value>0x37</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_57</name>
|
|
<description>Divide by 57</description>
|
|
<value>0x38</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_58</name>
|
|
<description>Divide by 58</description>
|
|
<value>0x39</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_59</name>
|
|
<description>Divide by 59</description>
|
|
<value>0x3A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_60</name>
|
|
<description>Divide by 60</description>
|
|
<value>0x3B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_61</name>
|
|
<description>Divide by 61</description>
|
|
<value>0x3C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_62</name>
|
|
<description>Divide by 62</description>
|
|
<value>0x3D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_63</name>
|
|
<description>Divide by 63</description>
|
|
<value>0x3E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_64</name>
|
|
<description>Divide by 64</description>
|
|
<value>0x3F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI1_CLK_PRED</name>
|
|
<description>Divider for sai1 clock pred.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI1_CLK_PRED_0</name>
|
|
<description>divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_CLK_PRED_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_CLK_PRED_2</name>
|
|
<description>divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_CLK_PRED_3</name>
|
|
<description>divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_CLK_PRED_4</name>
|
|
<description>divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_CLK_PRED_5</name>
|
|
<description>divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_CLK_PRED_6</name>
|
|
<description>divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI1_CLK_PRED_7</name>
|
|
<description>divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXIO1_CLK_PRED</name>
|
|
<description>Divider for flexio1 clock.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_CLK_PRED_0</name>
|
|
<description>divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_CLK_PRED_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_CLK_PRED_2</name>
|
|
<description>divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_CLK_PRED_3</name>
|
|
<description>divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_CLK_PRED_4</name>
|
|
<description>divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_CLK_PRED_5</name>
|
|
<description>divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_CLK_PRED_6</name>
|
|
<description>divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXIO1_CLK_PRED_7</name>
|
|
<description>divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI3_CLK_PODF</name>
|
|
<description>Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_1</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_2</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_3</name>
|
|
<description>Divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_4</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_5</name>
|
|
<description>Divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_6</name>
|
|
<description>Divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_7</name>
|
|
<description>Divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_8</name>
|
|
<description>Divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_9</name>
|
|
<description>Divide by 9</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_10</name>
|
|
<description>Divide by 10</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_11</name>
|
|
<description>Divide by 11</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_12</name>
|
|
<description>Divide by 12</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_13</name>
|
|
<description>Divide by 13</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_14</name>
|
|
<description>Divide by 14</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_15</name>
|
|
<description>Divide by 15</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_16</name>
|
|
<description>Divide by 16</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_17</name>
|
|
<description>Divide by 17</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_18</name>
|
|
<description>Divide by 18</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_19</name>
|
|
<description>Divide by 19</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_20</name>
|
|
<description>Divide by 20</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_21</name>
|
|
<description>Divide by 21</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_22</name>
|
|
<description>Divide by 22</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_23</name>
|
|
<description>Divide by 23</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_24</name>
|
|
<description>Divide by 24</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_25</name>
|
|
<description>Divide by 25</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_26</name>
|
|
<description>Divide by 26</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_27</name>
|
|
<description>Divide by 27</description>
|
|
<value>0x1A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_28</name>
|
|
<description>Divide by 28</description>
|
|
<value>0x1B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_29</name>
|
|
<description>Divide by 29</description>
|
|
<value>0x1C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_30</name>
|
|
<description>Divide by 30</description>
|
|
<value>0x1D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_31</name>
|
|
<description>Divide by 31</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_32</name>
|
|
<description>Divide by 32</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_33</name>
|
|
<description>Divide by 33</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_34</name>
|
|
<description>Divide by 34</description>
|
|
<value>0x21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_35</name>
|
|
<description>Divide by 35</description>
|
|
<value>0x22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_36</name>
|
|
<description>Divide by 36</description>
|
|
<value>0x23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_37</name>
|
|
<description>Divide by 37</description>
|
|
<value>0x24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_38</name>
|
|
<description>Divide by 38</description>
|
|
<value>0x25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_39</name>
|
|
<description>Divide by 39</description>
|
|
<value>0x26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_40</name>
|
|
<description>Divide by 40</description>
|
|
<value>0x27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_41</name>
|
|
<description>Divide by 41</description>
|
|
<value>0x28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_42</name>
|
|
<description>Divide by 42</description>
|
|
<value>0x29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_43</name>
|
|
<description>Divide by 43</description>
|
|
<value>0x2A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_44</name>
|
|
<description>Divide by 44</description>
|
|
<value>0x2B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_45</name>
|
|
<description>Divide by 45</description>
|
|
<value>0x2C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_46</name>
|
|
<description>Divide by 46</description>
|
|
<value>0x2D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_47</name>
|
|
<description>Divide by 47</description>
|
|
<value>0x2E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_48</name>
|
|
<description>Divide by 48</description>
|
|
<value>0x2F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_49</name>
|
|
<description>Divide by 49</description>
|
|
<value>0x30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_50</name>
|
|
<description>Divide by 50</description>
|
|
<value>0x31</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_51</name>
|
|
<description>Divide by 51</description>
|
|
<value>0x32</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_52</name>
|
|
<description>Divide by 52</description>
|
|
<value>0x33</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_53</name>
|
|
<description>Divide by 53</description>
|
|
<value>0x34</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_54</name>
|
|
<description>Divide by 54</description>
|
|
<value>0x35</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_55</name>
|
|
<description>Divide by 55</description>
|
|
<value>0x36</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_56</name>
|
|
<description>Divide by 56</description>
|
|
<value>0x37</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_57</name>
|
|
<description>Divide by 57</description>
|
|
<value>0x38</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_58</name>
|
|
<description>Divide by 58</description>
|
|
<value>0x39</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_59</name>
|
|
<description>Divide by 59</description>
|
|
<value>0x3A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_60</name>
|
|
<description>Divide by 60</description>
|
|
<value>0x3B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_61</name>
|
|
<description>Divide by 61</description>
|
|
<value>0x3C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_62</name>
|
|
<description>Divide by 62</description>
|
|
<value>0x3D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_63</name>
|
|
<description>Divide by 63</description>
|
|
<value>0x3E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_64</name>
|
|
<description>Divide by 64</description>
|
|
<value>0x3F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAI3_CLK_PRED</name>
|
|
<description>Divider for sai3 clock pred.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAI3_CLK_PRED_0</name>
|
|
<description>divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_CLK_PRED_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_CLK_PRED_2</name>
|
|
<description>divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_CLK_PRED_3</name>
|
|
<description>divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_CLK_PRED_4</name>
|
|
<description>divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_CLK_PRED_5</name>
|
|
<description>divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_CLK_PRED_6</name>
|
|
<description>divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAI3_CLK_PRED_7</name>
|
|
<description>divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXIO1_CLK_PODF</name>
|
|
<description>Divider for flexio1 clock. Divider should be updated when output clock is gated.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_1</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_2</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_3</name>
|
|
<description>Divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_4</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_5</name>
|
|
<description>Divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_6</name>
|
|
<description>Divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_7</name>
|
|
<description>Divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_8</name>
|
|
<description>Divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_9</name>
|
|
<description>Divide by 9</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_10</name>
|
|
<description>Divide by 10</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_11</name>
|
|
<description>Divide by 11</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_12</name>
|
|
<description>Divide by 12</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_13</name>
|
|
<description>Divide by 13</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_14</name>
|
|
<description>Divide by 14</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_15</name>
|
|
<description>Divide by 15</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_16</name>
|
|
<description>Divide by 16</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDCDR</name>
|
|
<description>CCM D1 Clock Divider Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3F00000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPDIF0_CLK_SEL</name>
|
|
<description>Selector for spdif0 clock multiplexer</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPDIF0_CLK_SEL_0</name>
|
|
<description>derive clock from PLL4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPDIF0_CLK_SEL_1</name>
|
|
<description>derive clock from PLL3 PFD2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPDIF0_CLK_SEL_3</name>
|
|
<description>derive clock from pll3_sw_clk</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPDIF0_CLK_PODF</name>
|
|
<description>Divider for spdif0 clock podf. Divider should be updated when output clock is gated.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_1</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_2</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_3</name>
|
|
<description>Divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_4</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_5</name>
|
|
<description>Divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_6</name>
|
|
<description>Divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_7</name>
|
|
<description>Divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_8</name>
|
|
<description>Divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPDIF0_CLK_PRED</name>
|
|
<description>Divider for spdif0 clock pred. Divider should be updated when output clock is gated.</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_1</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_2</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_3</name>
|
|
<description>Divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_4</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_5</name>
|
|
<description>Divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_6</name>
|
|
<description>Divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_7</name>
|
|
<description>Divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_8</name>
|
|
<description>Divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSCDR2</name>
|
|
<description>CCM Serial Clock Divider Register 2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x39000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPI2C_CLK_SEL</name>
|
|
<description>Selector for the LPI2C clock multiplexor</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPI2C_CLK_SEL_0</name>
|
|
<description>derive clock from pll3_60m</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPI2C_CLK_SEL_1</name>
|
|
<description>derive clock from osc_clk</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPI2C_CLK_PODF</name>
|
|
<description>Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_1</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_2</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_3</name>
|
|
<description>Divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_4</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_5</name>
|
|
<description>Divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_6</name>
|
|
<description>Divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_7</name>
|
|
<description>Divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_8</name>
|
|
<description>Divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_9</name>
|
|
<description>Divide by 9</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_10</name>
|
|
<description>Divide by 10</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_11</name>
|
|
<description>Divide by 11</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_12</name>
|
|
<description>Divide by 12</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_13</name>
|
|
<description>Divide by 13</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_14</name>
|
|
<description>Divide by 14</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_15</name>
|
|
<description>Divide by 15</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_16</name>
|
|
<description>Divide by 16</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_17</name>
|
|
<description>Divide by 17</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_18</name>
|
|
<description>Divide by 18</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_19</name>
|
|
<description>Divide by 19</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_20</name>
|
|
<description>Divide by 20</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_21</name>
|
|
<description>Divide by 21</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_22</name>
|
|
<description>Divide by 22</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_23</name>
|
|
<description>Divide by 23</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_24</name>
|
|
<description>Divide by 24</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_25</name>
|
|
<description>Divide by 25</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_26</name>
|
|
<description>Divide by 26</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_27</name>
|
|
<description>Divide by 27</description>
|
|
<value>0x1A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_28</name>
|
|
<description>Divide by 28</description>
|
|
<value>0x1B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_29</name>
|
|
<description>Divide by 29</description>
|
|
<value>0x1C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_30</name>
|
|
<description>Divide by 30</description>
|
|
<value>0x1D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_31</name>
|
|
<description>Divide by 31</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_32</name>
|
|
<description>Divide by 32</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_33</name>
|
|
<description>Divide by 33</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_34</name>
|
|
<description>Divide by 34</description>
|
|
<value>0x21</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_35</name>
|
|
<description>Divide by 35</description>
|
|
<value>0x22</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_36</name>
|
|
<description>Divide by 36</description>
|
|
<value>0x23</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_37</name>
|
|
<description>Divide by 37</description>
|
|
<value>0x24</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_38</name>
|
|
<description>Divide by 38</description>
|
|
<value>0x25</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_39</name>
|
|
<description>Divide by 39</description>
|
|
<value>0x26</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_40</name>
|
|
<description>Divide by 40</description>
|
|
<value>0x27</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_41</name>
|
|
<description>Divide by 41</description>
|
|
<value>0x28</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_42</name>
|
|
<description>Divide by 42</description>
|
|
<value>0x29</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_43</name>
|
|
<description>Divide by 43</description>
|
|
<value>0x2A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_44</name>
|
|
<description>Divide by 44</description>
|
|
<value>0x2B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_45</name>
|
|
<description>Divide by 45</description>
|
|
<value>0x2C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_46</name>
|
|
<description>Divide by 46</description>
|
|
<value>0x2D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_47</name>
|
|
<description>Divide by 47</description>
|
|
<value>0x2E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_48</name>
|
|
<description>Divide by 48</description>
|
|
<value>0x2F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_49</name>
|
|
<description>Divide by 49</description>
|
|
<value>0x30</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_50</name>
|
|
<description>Divide by 50</description>
|
|
<value>0x31</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_51</name>
|
|
<description>Divide by 51</description>
|
|
<value>0x32</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_52</name>
|
|
<description>Divide by 52</description>
|
|
<value>0x33</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_53</name>
|
|
<description>Divide by 53</description>
|
|
<value>0x34</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_54</name>
|
|
<description>Divide by 54</description>
|
|
<value>0x35</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_55</name>
|
|
<description>Divide by 55</description>
|
|
<value>0x36</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_56</name>
|
|
<description>Divide by 56</description>
|
|
<value>0x37</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_57</name>
|
|
<description>Divide by 57</description>
|
|
<value>0x38</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_58</name>
|
|
<description>Divide by 58</description>
|
|
<value>0x39</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_59</name>
|
|
<description>Divide by 59</description>
|
|
<value>0x3A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_60</name>
|
|
<description>Divide by 60</description>
|
|
<value>0x3B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_61</name>
|
|
<description>Divide by 61</description>
|
|
<value>0x3C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_62</name>
|
|
<description>Divide by 62</description>
|
|
<value>0x3D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_63</name>
|
|
<description>Divide by 63</description>
|
|
<value>0x3E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_64</name>
|
|
<description>Divide by 64</description>
|
|
<value>0x3F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDHIPR</name>
|
|
<description>CCM Divider Handshake In-Process Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AHB_PODF_BUSY</name>
|
|
<description>Busy indicator for ahb_podf.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AHB_PODF_BUSY_0</name>
|
|
<description>divider is not busy and its value represents the actual division.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_PODF_BUSY_1</name>
|
|
<description>divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXSPI_PODF_BUSY</name>
|
|
<description>Busy indicator for flexspi_podf.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_PODF_BUSY_0</name>
|
|
<description>divider is not busy and its value represents the actual division.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_PODF_BUSY_1</name>
|
|
<description>divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the flexspi_podf will be applied.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PERCLK_PODF_BUSY</name>
|
|
<description>Busy indicator for perclk_podf.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PERCLK_PODF_BUSY_0</name>
|
|
<description>divider is not busy and its value represents the actual division.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PERCLK_PODF_BUSY_1</name>
|
|
<description>divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the perclk_podf will be applied.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PERIPH_CLK_SEL_BUSY</name>
|
|
<description>Busy indicator for periph_clk_sel mux control.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PERIPH_CLK_SEL_BUSY_0</name>
|
|
<description>mux is not busy and its value represents the actual division.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PERIPH_CLK_SEL_BUSY_1</name>
|
|
<description>mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPCR</name>
|
|
<description>CCM Low Power Control Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x79</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPM</name>
|
|
<description>Setting the low power mode that system will enter on next assertion of dsm_request signal.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LPM_0</name>
|
|
<description>Remain in run mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPM_1</name>
|
|
<description>Transfer to wait mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LPM_2</name>
|
|
<description>Transfer to stop mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARM_CLK_DIS_ON_LPM</name>
|
|
<description>Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARM_CLK_DIS_ON_LPM_0</name>
|
|
<description>ARM clock enabled on wait mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARM_CLK_DIS_ON_LPM_1</name>
|
|
<description>ARM clock disabled on wait mode. .</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBYOS</name>
|
|
<description>Standby clock oscillator bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SBYOS_0</name>
|
|
<description>On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0')</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SBYOS_1</name>
|
|
<description>On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIS_REF_OSC</name>
|
|
<description>dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS_REF_OSC_0</name>
|
|
<description>external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_REF_OSC_1</name>
|
|
<description>external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VSTBY</name>
|
|
<description>Voltage standby request bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VSTBY_0</name>
|
|
<description>Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VSTBY_1</name>
|
|
<description>Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STBY_COUNT</name>
|
|
<description>Standby counter definition</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STBY_COUNT_0</name>
|
|
<description>CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STBY_COUNT_1</name>
|
|
<description>CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STBY_COUNT_2</name>
|
|
<description>CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STBY_COUNT_3</name>
|
|
<description>CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COSC_PWRDOWN</name>
|
|
<description>In run mode, software can manually control powering down of on chip oscillator, i</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COSC_PWRDOWN_0</name>
|
|
<description>On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COSC_PWRDOWN_1</name>
|
|
<description>On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASK_CORE0_WFI</name>
|
|
<description>Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASK_CORE0_WFI_0</name>
|
|
<description>WFI of core0 is not masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK_CORE0_WFI_1</name>
|
|
<description>WFI of core0 is masked</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASK_SCU_IDLE</name>
|
|
<description>Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASK_SCU_IDLE_0</name>
|
|
<description>SCU IDLE is not masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK_SCU_IDLE_1</name>
|
|
<description>SCU IDLE is masked</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASK_L2CC_IDLE</name>
|
|
<description>Mask L2CC IDLE for entering low power mode</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASK_L2CC_IDLE_0</name>
|
|
<description>L2CC IDLE is not masked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK_L2CC_IDLE_1</name>
|
|
<description>L2CC IDLE is masked</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CISR</name>
|
|
<description>CCM Interrupt Status Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LRF_PLL</name>
|
|
<description>CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LRF_PLL_0</name>
|
|
<description>interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LRF_PLL_1</name>
|
|
<description>interrupt generated due to lock ready of all enabled and not bypaseed PLLs</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COSC_READY</name>
|
|
<description>CCM interrupt request 2 generated due to on board oscillator ready, i</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COSC_READY_0</name>
|
|
<description>interrupt is not generated due to on board oscillator ready</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COSC_READY_1</name>
|
|
<description>interrupt generated due to on board oscillator ready</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLEXSPI_PODF_LOADED</name>
|
|
<description>CCM interrupt request 1 generated due to frequency change of flexspi_podf</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_PODF_LOADED_0</name>
|
|
<description>interrupt is not generated due to frequency change of flexspi_podf</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXSPI_PODF_LOADED_1</name>
|
|
<description>interrupt generated due to frequency change of flexspi_podf</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PERCLK_PODF_LOADED</name>
|
|
<description>CCM interrupt request 1 generated due to frequency change of perclk_podf</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PERCLK_PODF_LOADED_0</name>
|
|
<description>interrupt is not generated due to frequency change of perclk_podf</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PERCLK_PODF_LOADED_1</name>
|
|
<description>interrupt generated due to frequency change of perclk_podf</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AHB_PODF_LOADED</name>
|
|
<description>CCM interrupt request 1 generated due to frequency change of ahb_podf</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AHB_PODF_LOADED_0</name>
|
|
<description>interrupt is not generated due to frequency change of ahb_podf</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_PODF_LOADED_1</name>
|
|
<description>interrupt generated due to frequency change of ahb_podf</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PERIPH_CLK_SEL_LOADED</name>
|
|
<description>CCM interrupt request 1 generated due to update of periph_clk_sel.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PERIPH_CLK_SEL_LOADED_0</name>
|
|
<description>interrupt is not generated due to update of periph_clk_sel.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PERIPH_CLK_SEL_LOADED_1</name>
|
|
<description>interrupt generated due to update of periph_clk_sel.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIMR</name>
|
|
<description>CCM Interrupt Mask Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK_LRF_PLL</name>
|
|
<description>mask interrupt generation due to lrf of PLLs</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASK_LRF_PLL_0</name>
|
|
<description>don't mask interrupt due to lrf of PLLs - interrupt will be created</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK_LRF_PLL_1</name>
|
|
<description>mask interrupt due to lrf of PLLs</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASK_COSC_READY</name>
|
|
<description>mask interrupt generation due to on board oscillator ready</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASK_COSC_READY_0</name>
|
|
<description>don't mask interrupt due to on board oscillator ready - interrupt will be created</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK_COSC_READY_1</name>
|
|
<description>mask interrupt due to on board oscillator ready</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASK_FLEXSPI_PODF_LOADED</name>
|
|
<description>mask interrupt generation due to update of flexspi_podf</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASK_FLEXSPI_PODF_LOADED_0</name>
|
|
<description>don't mask interrupt due to update of flexspi_podf</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK_FLEXSPI_PODF_LOADED_1</name>
|
|
<description>mask interrupt due to update of flexspi_podf</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASK_PERCLK_PODF_LOADED</name>
|
|
<description>mask interrupt generation due to update of perclk_podf</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASK_PERCLK_PODF_LOADED_0</name>
|
|
<description>don't mask interrupt due to update of perclk_podf</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK_PERCLK_PODF_LOADED_1</name>
|
|
<description>mask interrupt due to update of perclk_podf</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASK_AHB_PODF_LOADED</name>
|
|
<description>mask interrupt generation due to frequency change of ahb_podf</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASK_AHB_PODF_LOADED_0</name>
|
|
<description>don't mask interrupt due to frequency change of ahb_podf - interrupt will be created</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK_AHB_PODF_LOADED_1</name>
|
|
<description>mask interrupt due to frequency change of ahb_podf</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASK_PERIPH_CLK_SEL_LOADED</name>
|
|
<description>mask interrupt generation due to update of periph_clk_sel.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASK_PERIPH_CLK_SEL_LOADED_0</name>
|
|
<description>don't mask interrupt due to update of periph_clk_sel - interrupt will be created</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK_PERIPH_CLK_SEL_LOADED_1</name>
|
|
<description>mask interrupt due to update of periph_clk_sel</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCOSR</name>
|
|
<description>CCM Clock Output Source Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA0001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKO1_SEL</name>
|
|
<description>Selection of the clock to be generated on CCM_CLKO1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKO1_SEL_0</name>
|
|
<description>pll3_sw_clk (divided by 2)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_SEL_1</name>
|
|
<description>PLL2 (divided by 2)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_SEL_2</name>
|
|
<description>ENET PLL (divided by 2)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_SEL_11</name>
|
|
<description>core_clk_root</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_SEL_12</name>
|
|
<description>ipg_clk_root</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_SEL_13</name>
|
|
<description>perclk_root</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_SEL_15</name>
|
|
<description>pll4_main_clk</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKO1_DIV</name>
|
|
<description>Setting the divider of CCM_CLKO1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKO1_DIV_0</name>
|
|
<description>divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_DIV_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_DIV_2</name>
|
|
<description>divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_DIV_3</name>
|
|
<description>divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_DIV_4</name>
|
|
<description>divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_DIV_5</name>
|
|
<description>divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_DIV_6</name>
|
|
<description>divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_DIV_7</name>
|
|
<description>divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKO1_EN</name>
|
|
<description>Enable of CCM_CLKO1 clock</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKO1_EN_0</name>
|
|
<description>CCM_CLKO1 disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO1_EN_1</name>
|
|
<description>CCM_CLKO1 enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLK_OUT_SEL</name>
|
|
<description>CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLK_OUT_SEL_0</name>
|
|
<description>CCM_CLKO1 output drives CCM_CLKO1 clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_OUT_SEL_1</name>
|
|
<description>CCM_CLKO1 output drives CCM_CLKO2 clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKO2_SEL</name>
|
|
<description>Selection of the clock to be generated on CCM_CLKO2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKO2_SEL_6</name>
|
|
<description>lpi2c_clk_root</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_SEL_14</name>
|
|
<description>osc_clk</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_SEL_16</name>
|
|
<description>lpspi_clk_root</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_SEL_18</name>
|
|
<description>sai1_clk_root</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_SEL_20</name>
|
|
<description>sai3_clk_root</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_SEL_22</name>
|
|
<description>trace_clk_root</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_SEL_27</name>
|
|
<description>flexspi_clk_root</description>
|
|
<value>0x1B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_SEL_28</name>
|
|
<description>uart_clk_root</description>
|
|
<value>0x1C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_SEL_29</name>
|
|
<description>spdif0_clk_root</description>
|
|
<value>0x1D</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKO2_DIV</name>
|
|
<description>Setting the divider of CCM_CLKO2</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKO2_DIV_0</name>
|
|
<description>divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_DIV_1</name>
|
|
<description>divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_DIV_2</name>
|
|
<description>divide by 3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_DIV_3</name>
|
|
<description>divide by 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_DIV_4</name>
|
|
<description>divide by 5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_DIV_5</name>
|
|
<description>divide by 6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_DIV_6</name>
|
|
<description>divide by 7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_DIV_7</name>
|
|
<description>divide by 8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKO2_EN</name>
|
|
<description>Enable of CCM_CLKO2 clock</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKO2_EN_0</name>
|
|
<description>CCM_CLKO2 disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKO2_EN_1</name>
|
|
<description>CCM_CLKO2 enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CGPR</name>
|
|
<description>CCM General Purpose Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMIC_DELAY_SCALER</name>
|
|
<description>Defines clock dividion of clock for stby_count (pmic delay counter)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PMIC_DELAY_SCALER_0</name>
|
|
<description>clock is not divided</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PMIC_DELAY_SCALER_1</name>
|
|
<description>clock is divided /8</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EFUSE_PROG_SUPPLY_GATE</name>
|
|
<description>Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EFUSE_PROG_SUPPLY_GATE_0</name>
|
|
<description>fuse programing supply voltage is gated off to the efuse module</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EFUSE_PROG_SUPPLY_GATE_1</name>
|
|
<description>allow fuse programing.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYS_MEM_DS_CTRL</name>
|
|
<description>System memory DS control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYS_MEM_DS_CTRL_0</name>
|
|
<description>Disable memory DS mode always</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYS_MEM_DS_CTRL_1</name>
|
|
<description>Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYS_MEM_DS_CTRL_2</name>
|
|
<description>enable memory (outside ARM platform) DS mode when system is in STOP mode</description>
|
|
<value>#1x</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FPL</name>
|
|
<description>Fast PLL enable.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FPL_0</name>
|
|
<description>Engage PLL enable default way.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FPL_1</name>
|
|
<description>Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT_MEM_CLK_LPM</name>
|
|
<description>Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INT_MEM_CLK_LPM_0</name>
|
|
<description>Disable the clock to the ARM platform memories when entering Low Power Mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INT_MEM_CLK_LPM_1</name>
|
|
<description>Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCGR0</name>
|
|
<description>CCM Clock Gating Register 0</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CG0</name>
|
|
<description>aips_tz1 clocks (aips_tz1_clk_enable)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG1</name>
|
|
<description>aips_tz2 clocks (aips_tz2_clk_enable)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG2</name>
|
|
<description>mqs clock ( mqs_hmclk_clock_enable)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG3</name>
|
|
<description>flexspi_exsc clock (flexspi_exsc_clk_enable)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG4</name>
|
|
<description>sim_m_clk_r_clk_enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG5</name>
|
|
<description>dcp clock (dcp_clk_enable)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG6</name>
|
|
<description>lpuart3 clock (lpuart3_clk_enable)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG7</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG8</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG9</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG10</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG11</name>
|
|
<description>trace clock (trace_clk_enable)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG12</name>
|
|
<description>gpt2 bus clocks (gpt2_bus_clk_enable)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG13</name>
|
|
<description>gpt2 serial clocks (gpt2_serial_clk_enable)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG14</name>
|
|
<description>lpuart2 clock (lpuart2_clk_enable)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG15</name>
|
|
<description>gpio2_clocks (gpio2_clk_enable)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCGR1</name>
|
|
<description>CCM Clock Gating Register 1</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CG0</name>
|
|
<description>lpspi1 clocks (lpspi1_clk_enable)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG1</name>
|
|
<description>lpspi2 clocks (lpspi2_clk_enable)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG2</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG3</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG4</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG5</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG6</name>
|
|
<description>pit clocks (pit_clk_enable)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG7</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG8</name>
|
|
<description>adc1 clock (adc1_clk_enable)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG9</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG10</name>
|
|
<description>gpt1 bus clock (gpt_clk_enable)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG11</name>
|
|
<description>gpt1 serial clock (gpt_serial_clk_enable)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG12</name>
|
|
<description>lpuart4 clock (lpuart4_clk_enable)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG13</name>
|
|
<description>gpio1 clock (gpio1_clk_enable)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG14</name>
|
|
<description>csu clock (csu_clk_enable)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG15</name>
|
|
<description>gpio5 clock (gpio5_clk_enable)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCGR2</name>
|
|
<description>CCM Clock Gating Register 2</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CG0</name>
|
|
<description>ocram_exsc clock (ocram_exsc_clk_enable)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG1</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG2</name>
|
|
<description>iomuxc_snvs clock (iomuxc_snvs_clk_enable)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG3</name>
|
|
<description>lpi2c1 clock (lpi2c1_clk_enable)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG4</name>
|
|
<description>lpi2c2 clock (lpi2c2_clk_enable)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG5</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG6</name>
|
|
<description>OCOTP_CTRL clock (iim_clk_enable)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG7</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG8</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG9</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG10</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG11</name>
|
|
<description>xbar1 clock (xbar1_clk_enable)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG12</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG13</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG14</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG15</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCGR3</name>
|
|
<description>CCM Clock Gating Register 3</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CG0</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG1</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG2</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG3</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG4</name>
|
|
<description>aoi1 clock (aoi1_clk_enable)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG5</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG6</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG7</name>
|
|
<description>ewm clocks (ewm_clk_enable)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG8</name>
|
|
<description>wdog1 clock (wdog1_clk_enable)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG9</name>
|
|
<description>flexram clock (flexram_clk_enable)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG10</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG11</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG12</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG13</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG14</name>
|
|
<description>The OCRAM clock cannot be turned off when the CM cache is running on this device.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG15</name>
|
|
<description>iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCGR4</name>
|
|
<description>CCM Clock Gating Register 4</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CG0</name>
|
|
<description>sim_m7_clk_r_enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG1</name>
|
|
<description>iomuxc clock (iomuxc_clk_enable)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG2</name>
|
|
<description>iomuxc gpr clock (iomuxc_gpr_clk_enable)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG3</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG4</name>
|
|
<description>sim_m7 clock (sim_m7_clk_enable)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG5</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG6</name>
|
|
<description>sim_m clocks (sim_m_clk_enable)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG7</name>
|
|
<description>sim_ems clocks (sim_ems_clk_enable)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG8</name>
|
|
<description>pwm1 clocks (pwm1_clk_enable)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG9</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG10</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG11</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG12</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG13</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG14</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG15</name>
|
|
<description>dma_ps clocks (dma_ps_clk_enable)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCGR5</name>
|
|
<description>CCM Clock Gating Register 5</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CG0</name>
|
|
<description>rom clock (rom_clk_enable)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG1</name>
|
|
<description>flexio1 clock (flexio1_clk_enable)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG2</name>
|
|
<description>wdog3 clock (wdog3_clk_enable)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG3</name>
|
|
<description>dma clock (dma_clk_enable)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG4</name>
|
|
<description>kpp clock (kpp_clk_enable)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG5</name>
|
|
<description>wdog2 clock (wdog2_clk_enable)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG6</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG7</name>
|
|
<description>spdif clock (spdif_clk_enable)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG8</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG9</name>
|
|
<description>sai1 clock (sai1_clk_enable)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG10</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG11</name>
|
|
<description>sai3 clock (sai3_clk_enable)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG12</name>
|
|
<description>lpuart1 clock (lpuart1_clk_enable)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG13</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG14</name>
|
|
<description>snvs_hp clock (snvs_hp_clk_enable)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG15</name>
|
|
<description>snvs_lp clock (snvs_lp_clk_enable)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCGR6</name>
|
|
<description>CCM Clock Gating Register 6</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CG0</name>
|
|
<description>usboh3 clock (usboh3_clk_enable)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG1</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG2</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG3</name>
|
|
<description>dcdc clocks (dcdc_clk_enable)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG4</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG5</name>
|
|
<description>flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG6</name>
|
|
<description>trng clock (trng_clk_enable)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG7</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG8</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG9</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG10</name>
|
|
<description>sim_per clock (sim_per_clk_enable)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG11</name>
|
|
<description>anadig clocks (anadig_clk_enable)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG12</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG13</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG14</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CG15</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMEOR</name>
|
|
<description>CCM Module Enable Overide Register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD_EN_OV_GPT</name>
|
|
<description>Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk'</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MOD_EN_OV_GPT_0</name>
|
|
<description>don't override module enable signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MOD_EN_OV_GPT_1</name>
|
|
<description>override module enable signal</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MOD_EN_OV_PIT</name>
|
|
<description>Overide clock enable signal from PIT - clock will not be gated based on PIT's signal 'ipg_enable_clk'</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MOD_EN_OV_PIT_0</name>
|
|
<description>don't override module enable signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MOD_EN_OV_PIT_1</name>
|
|
<description>override module enable signal</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MOD_EN_OV_TRNG</name>
|
|
<description>Overide clock enable signal from TRNG</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MOD_EN_OV_TRNG_0</name>
|
|
<description>don't override module enable signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MOD_EN_OV_TRNG_1</name>
|
|
<description>override module enable signal</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ROMC</name>
|
|
<description>ROMC</description>
|
|
<groupName>ROMC</groupName>
|
|
<prependToName>ROMC_</prependToName>
|
|
<baseAddress>0x40180000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x20C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>7,6,5,4,3,2,1,0</dimIndex>
|
|
<name>ROMPATCH%sD</name>
|
|
<description>ROMC Data Registers</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAX</name>
|
|
<description>Data Fix Registers - Stores the data used for 1-word data fix operations</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROMPATCHCNTL</name>
|
|
<description>ROMC Control Register</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8400000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAFIX</name>
|
|
<description>Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for code patch routine</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DATAFIX_0</name>
|
|
<description>Address comparator triggers a opcode patch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATAFIX_1</name>
|
|
<description>Address comparator triggers a data fix</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIS</name>
|
|
<description>ROMC Disable -- This bit, when set, disables all ROMC operations</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIS_0</name>
|
|
<description>Does not affect any ROMC functions (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIS_1</name>
|
|
<description>Disable all ROMC functions: data fixing, and opcode patching</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROMPATCHENH</name>
|
|
<description>ROMC Enable Register High</description>
|
|
<addressOffset>0xF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
</register>
|
|
<register>
|
|
<name>ROMPATCHENL</name>
|
|
<description>ROMC Enable Register Low</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enable Address Comparator - This bit enables the corresponding address comparator to trigger an event</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENABLE_0</name>
|
|
<description>Address comparator disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_1</name>
|
|
<description>Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
|
|
<name>ROMPATCH%sA</name>
|
|
<description>ROMC Address Registers</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>THUMBX</name>
|
|
<description>THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>THUMBX_0</name>
|
|
<description>Arm patch</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THUMBX_1</name>
|
|
<description>THUMB patch (ignore if data fix)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADDRX</name>
|
|
<description>Address Comparator Registers - Indicates the memory address to be watched</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>22</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROMPATCHSR</name>
|
|
<description>ROMC Status Register</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOURCE</name>
|
|
<description>ROMC Source Number - Binary encoding of the number of the address comparator which has an address match in the most recent patch event on ROMC AHB</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SOURCE_0</name>
|
|
<description>Address Comparator 0 matched</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_1</name>
|
|
<description>Address Comparator 1 matched</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_15</name>
|
|
<description>Address Comparator 15 matched</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SW</name>
|
|
<description>ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address comparator matches occurred</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SW_0</name>
|
|
<description>no event or comparator collisions</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SW_1</name>
|
|
<description>a collision has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPUART1</name>
|
|
<description>LPUART</description>
|
|
<groupName>LPUART</groupName>
|
|
<headerStructName>LPUART</headerStructName>
|
|
<baseAddress>0x40184000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPUART1</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4010003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Identification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEATURE_1</name>
|
|
<description>Standard feature set.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEATURE_3</name>
|
|
<description>Standard feature set with MODEM/IrDA support.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x202</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXFIFO</name>
|
|
<description>Transmit FIFO Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO</name>
|
|
<description>Receive FIFO Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GLOBAL</name>
|
|
<description>LPUART Global Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RST_0</name>
|
|
<description>Module is not reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RST_1</name>
|
|
<description>Module is reset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINCFG</name>
|
|
<description>LPUART Pin Configuration Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>Trigger Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRGSEL_0</name>
|
|
<description>Input trigger is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGSEL_1</name>
|
|
<description>Input trigger is used instead of RXD pin input.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGSEL_2</name>
|
|
<description>Input trigger is used instead of CTS_B pin input.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGSEL_3</name>
|
|
<description>Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>LPUART Baud Rate Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF000004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>Baud Rate Modulo Divisor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SBNS</name>
|
|
<description>Stop Bit Number Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SBNS_0</name>
|
|
<description>One stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SBNS_1</name>
|
|
<description>Two stop bits.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RX Input Active Edge Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXEDGIE_0</name>
|
|
<description>Hardware interrupts from STAT[RXEDGIF] are disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXEDGIE_1</name>
|
|
<description>Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LBKDIE_0</name>
|
|
<description>Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LBKDIE_1</name>
|
|
<description>Hardware interrupt requested when STAT[LBKDIF] flag is 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESYNCDIS</name>
|
|
<description>Resynchronization Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RESYNCDIS_0</name>
|
|
<description>Resynchronization during received data word is supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESYNCDIS_1</name>
|
|
<description>Resynchronization during received data word is disabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOTHEDGE</name>
|
|
<description>Both Edge Sampling</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGE_0</name>
|
|
<description>Receiver samples input data using the rising edge of the baud rate clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTHEDGE_1</name>
|
|
<description>Receiver samples input data using the rising and falling edge of the baud rate clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCFG</name>
|
|
<description>Match Configuration</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MATCFG_0</name>
|
|
<description>Address Match Wakeup</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_1</name>
|
|
<description>Idle Match Wakeup</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_2</name>
|
|
<description>Match On and Match Off</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_3</name>
|
|
<description>Enables RWU on Data Match and Match On/Off for transmitter CTS input</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIDMAE</name>
|
|
<description>Receiver Idle DMA Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RIDMAE_0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RIDMAE_1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMAE</name>
|
|
<description>Receiver Full DMA Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDMAE_0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDMAE_1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAE</name>
|
|
<description>Transmitter DMA Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TDMAE_0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TDMAE_1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSR</name>
|
|
<description>Oversampling Ratio</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OSR_0</name>
|
|
<description>Writing 0 to this field will result in an oversampling ratio of 16</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_3</name>
|
|
<description>Oversampling ratio of 4, requires BOTHEDGE to be set.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_4</name>
|
|
<description>Oversampling ratio of 5, requires BOTHEDGE to be set.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_5</name>
|
|
<description>Oversampling ratio of 6, requires BOTHEDGE to be set.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_6</name>
|
|
<description>Oversampling ratio of 7, requires BOTHEDGE to be set.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_7</name>
|
|
<description>Oversampling ratio of 8.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_8</name>
|
|
<description>Oversampling ratio of 9.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_9</name>
|
|
<description>Oversampling ratio of 10.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_10</name>
|
|
<description>Oversampling ratio of 11.</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_11</name>
|
|
<description>Oversampling ratio of 12.</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_12</name>
|
|
<description>Oversampling ratio of 13.</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_13</name>
|
|
<description>Oversampling ratio of 14.</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_14</name>
|
|
<description>Oversampling ratio of 15.</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_15</name>
|
|
<description>Oversampling ratio of 16.</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_16</name>
|
|
<description>Oversampling ratio of 17.</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_17</name>
|
|
<description>Oversampling ratio of 18.</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_18</name>
|
|
<description>Oversampling ratio of 19.</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_19</name>
|
|
<description>Oversampling ratio of 20.</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_20</name>
|
|
<description>Oversampling ratio of 21.</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_21</name>
|
|
<description>Oversampling ratio of 22.</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_22</name>
|
|
<description>Oversampling ratio of 23.</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_23</name>
|
|
<description>Oversampling ratio of 24.</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_24</name>
|
|
<description>Oversampling ratio of 25.</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_25</name>
|
|
<description>Oversampling ratio of 26.</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_26</name>
|
|
<description>Oversampling ratio of 27.</description>
|
|
<value>0x1A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_27</name>
|
|
<description>Oversampling ratio of 28.</description>
|
|
<value>0x1B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_28</name>
|
|
<description>Oversampling ratio of 29.</description>
|
|
<value>0x1C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_29</name>
|
|
<description>Oversampling ratio of 30.</description>
|
|
<value>0x1D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_30</name>
|
|
<description>Oversampling ratio of 31.</description>
|
|
<value>0x1E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OSR_31</name>
|
|
<description>Oversampling ratio of 32.</description>
|
|
<value>0x1F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M10</name>
|
|
<description>10-bit Mode select</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M10_0</name>
|
|
<description>Receiver and transmitter use 7-bit to 9-bit data characters.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M10_1</name>
|
|
<description>Receiver and transmitter use 10-bit data characters.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN2</name>
|
|
<description>Match Address Mode Enable 2</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAEN2_0</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAEN2_1</name>
|
|
<description>Enables automatic address matching or data matching mode for MATCH[MA2].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN1</name>
|
|
<description>Match Address Mode Enable 1</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MAEN1_0</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAEN1_1</name>
|
|
<description>Enables automatic address matching or data matching mode for MATCH[MA1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>LPUART Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC00000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA2F</name>
|
|
<description>Match 2 Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MA2F_0</name>
|
|
<description>Received data is not equal to MA2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MA2F_1</name>
|
|
<description>Received data is equal to MA2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MA1F</name>
|
|
<description>Match 1 Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MA1F_0</name>
|
|
<description>Received data is not equal to MA1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MA1F_1</name>
|
|
<description>Received data is equal to MA1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PF_0</name>
|
|
<description>No parity error.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PF_1</name>
|
|
<description>Parity error.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FE_0</name>
|
|
<description>No framing error detected. This does not guarantee the framing is correct.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FE_1</name>
|
|
<description>Framing error.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NF_0</name>
|
|
<description>No noise detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NF_1</name>
|
|
<description>Noise detected in the received character in the DATA register.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OR_0</name>
|
|
<description>No overrun.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OR_1</name>
|
|
<description>Receive overrun (new LPUART data lost).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLE_0</name>
|
|
<description>No idle line detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLE_1</name>
|
|
<description>Idle line was detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDRF_0</name>
|
|
<description>Receive data buffer empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDRF_1</name>
|
|
<description>Receive data buffer full.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmission Complete Flag</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TC_0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TC_1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TDRE_0</name>
|
|
<description>Transmit data buffer full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TDRE_1</name>
|
|
<description>Transmit data buffer empty.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RAF_0</name>
|
|
<description>LPUART receiver idle waiting for a start bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RAF_1</name>
|
|
<description>LPUART receiver active (RXD input not idle).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LBKDE_0</name>
|
|
<description>LIN break detect is disabled, normal break character can be detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LBKDE_1</name>
|
|
<description>LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Character Generation Length</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BRK13_0</name>
|
|
<description>Break character is transmitted with length of 9 to 13 bit times.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BRK13_1</name>
|
|
<description>Break character is transmitted with length of 12 to 15 bit times.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wake Up Idle Detect</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RWUID_0</name>
|
|
<description>During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RWUID_1</name>
|
|
<description>During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXINV_0</name>
|
|
<description>Receive data not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXINV_1</name>
|
|
<description>Receive data inverted.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>MSB First</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MSBF_0</name>
|
|
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSBF_1</name>
|
|
<description>MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RXD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXEDGIF_0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXEDGIF_1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LBKDIF_0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LBKDIF_1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>LPUART Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PT_0</name>
|
|
<description>Even parity.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PT_1</name>
|
|
<description>Odd parity.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PE_0</name>
|
|
<description>No hardware parity generation or checking.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PE_1</name>
|
|
<description>Parity enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ILT_0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ILT_1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WAKE_0</name>
|
|
<description>Configures RWU for idle-line wakeup.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE_1</name>
|
|
<description>Configures RWU with address-mark wakeup.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-Bit or 8-Bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M_0</name>
|
|
<description>Receiver and transmitter use 8-bit data characters.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M_1</name>
|
|
<description>Receiver and transmitter use 9-bit data characters.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RSRC_0</name>
|
|
<description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RSRC_1</name>
|
|
<description>Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEEN</name>
|
|
<description>Doze Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DOZEEN_0</name>
|
|
<description>LPUART is enabled in Doze mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOZEEN_1</name>
|
|
<description>LPUART is disabled in Doze mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOOPS_0</name>
|
|
<description>Normal operation - RXD and TXD use separate pins.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOOPS_1</name>
|
|
<description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLECFG</name>
|
|
<description>Idle Configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLECFG_0</name>
|
|
<description>1 idle character</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLECFG_1</name>
|
|
<description>2 idle characters</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLECFG_2</name>
|
|
<description>4 idle characters</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLECFG_3</name>
|
|
<description>8 idle characters</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLECFG_4</name>
|
|
<description>16 idle characters</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLECFG_5</name>
|
|
<description>32 idle characters</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLECFG_6</name>
|
|
<description>64 idle characters</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLECFG_7</name>
|
|
<description>128 idle characters</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7</name>
|
|
<description>7-Bit Mode Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>M7_0</name>
|
|
<description>Receiver and transmitter use 8-bit to 10-bit data characters.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>M7_1</name>
|
|
<description>Receiver and transmitter use 7-bit data characters.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MA2IE</name>
|
|
<description>Match 2 Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MA2IE_0</name>
|
|
<description>MA2F interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MA2IE_1</name>
|
|
<description>MA2F interrupt enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MA1IE</name>
|
|
<description>Match 1 Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MA1IE_0</name>
|
|
<description>MA1F interrupt disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MA1IE_1</name>
|
|
<description>MA1F interrupt enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SBK_0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SBK_1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RWU_0</name>
|
|
<description>Normal receiver operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RWU_1</name>
|
|
<description>LPUART receiver in standby waiting for wakeup condition.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RE_0</name>
|
|
<description>Receiver disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RE_1</name>
|
|
<description>Receiver enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TE_0</name>
|
|
<description>Transmitter disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TE_1</name>
|
|
<description>Transmitter enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ILIE_0</name>
|
|
<description>Hardware interrupts from IDLE disabled; use polling.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ILIE_1</name>
|
|
<description>Hardware interrupt requested when IDLE flag is 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Interrupt Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RIE_0</name>
|
|
<description>Hardware interrupts from RDRF disabled; use polling.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RIE_1</name>
|
|
<description>Hardware interrupt requested when RDRF flag is 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable for</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TCIE_0</name>
|
|
<description>Hardware interrupts from TC disabled; use polling.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCIE_1</name>
|
|
<description>Hardware interrupt requested when TC flag is 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIE_0</name>
|
|
<description>Hardware interrupts from TDRE disabled; use polling.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIE_1</name>
|
|
<description>Hardware interrupt requested when TDRE flag is 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PEIE_0</name>
|
|
<description>PF interrupts disabled; use polling).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PEIE_1</name>
|
|
<description>Hardware interrupt requested when PF is set.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEIE_0</name>
|
|
<description>FE interrupts disabled; use polling.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEIE_1</name>
|
|
<description>Hardware interrupt requested when FE is set.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NEIE_0</name>
|
|
<description>NF interrupts disabled; use polling.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEIE_1</name>
|
|
<description>Hardware interrupt requested when NF is set.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Interrupt Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ORIE_0</name>
|
|
<description>OR interrupts disabled; use polling.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ORIE_1</name>
|
|
<description>Hardware interrupt requested when OR is set.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXINV_0</name>
|
|
<description>Transmit data not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXINV_1</name>
|
|
<description>Transmit data inverted.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>TXD Pin Direction in Single-Wire Mode</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXDIR_0</name>
|
|
<description>TXD pin is an input in single-wire mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXDIR_1</name>
|
|
<description>TXD pin is an output in single-wire mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>R9T8</name>
|
|
<description>Receive Bit 9 / Transmit Bit 8</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8T9</name>
|
|
<description>Receive Bit 8 / Transmit Bit 9</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>LPUART Data Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R0T0</name>
|
|
<description>R0T0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R1T1</name>
|
|
<description>R1T1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R2T2</name>
|
|
<description>R2T2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R3T3</name>
|
|
<description>R3T3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R4T4</name>
|
|
<description>R4T4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R5T5</name>
|
|
<description>R5T5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R6T6</name>
|
|
<description>R6T6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R7T7</name>
|
|
<description>R7T7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8T8</name>
|
|
<description>R8T8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R9T9</name>
|
|
<description>R9T9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDLINE</name>
|
|
<description>Idle Line</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IDLINE_0</name>
|
|
<description>Receiver was not idle before receiving this character.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDLINE_1</name>
|
|
<description>Receiver was idle before receiving this character.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer Empty</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXEMPT_0</name>
|
|
<description>Receive buffer contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXEMPT_1</name>
|
|
<description>Receive buffer is empty, data returned on read is not valid.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRETSC</name>
|
|
<description>Frame Error / Transmit Special Character</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRETSC_0</name>
|
|
<description>The dataword was received without a frame error on read, or transmit a normal character on write.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRETSC_1</name>
|
|
<description>The dataword was received with a frame error, or transmit an idle or break character on transmit.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PARITYE</name>
|
|
<description>PARITYE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PARITYE_0</name>
|
|
<description>The dataword was received without a parity error.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PARITYE_1</name>
|
|
<description>The dataword was received with a parity error.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOISY</name>
|
|
<description>NOISY</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOISY_0</name>
|
|
<description>The dataword was received without noise.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOISY_1</name>
|
|
<description>The data was received with noise.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATCH</name>
|
|
<description>LPUART Match Address Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA1</name>
|
|
<description>Match Address 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MA2</name>
|
|
<description>Match Address 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODIR</name>
|
|
<description>LPUART Modem IrDA Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTSE</name>
|
|
<description>Transmitter clear-to-send enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXCTSE_0</name>
|
|
<description>CTS has no effect on the transmitter.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXCTSE_1</name>
|
|
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSE</name>
|
|
<description>Transmitter request-to-send enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXRTSE_0</name>
|
|
<description>The transmitter has no effect on RTS.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXRTSE_1</name>
|
|
<description>When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSPOL</name>
|
|
<description>Transmitter request-to-send polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXRTSPOL_0</name>
|
|
<description>Transmitter RTS is active low.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXRTSPOL_1</name>
|
|
<description>Transmitter RTS is active high.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXRTSE</name>
|
|
<description>Receiver request-to-send enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXRTSE_0</name>
|
|
<description>The receiver has no effect on RTS.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXRTSE_1</name>
|
|
<description>RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCTSC</name>
|
|
<description>Transmit CTS Configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXCTSC_0</name>
|
|
<description>CTS input is sampled at the start of each character.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXCTSC_1</name>
|
|
<description>CTS input is sampled when the transmitter is idle.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCTSSRC</name>
|
|
<description>Transmit CTS Source</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXCTSSRC_0</name>
|
|
<description>CTS input is the CTS_B pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXCTSSRC_1</name>
|
|
<description>CTS input is the inverted Receiver Match result.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSWATER</name>
|
|
<description>Receive RTS Configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TNP</name>
|
|
<description>Transmitter narrow pulse</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TNP_0</name>
|
|
<description>1/OSR.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TNP_1</name>
|
|
<description>2/OSR.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TNP_2</name>
|
|
<description>3/OSR.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TNP_3</name>
|
|
<description>4/OSR.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Infrared enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IREN_0</name>
|
|
<description>IR disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IREN_1</name>
|
|
<description>IR enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO</name>
|
|
<description>LPUART FIFO Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC00011</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFOSIZE</name>
|
|
<description>Receive FIFO Buffer Depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXFIFOSIZE_0</name>
|
|
<description>Receive FIFO/Buffer depth = 1 dataword.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXFIFOSIZE_1</name>
|
|
<description>Receive FIFO/Buffer depth = 4 datawords.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXFIFOSIZE_2</name>
|
|
<description>Receive FIFO/Buffer depth = 8 datawords.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXFIFOSIZE_3</name>
|
|
<description>Receive FIFO/Buffer depth = 16 datawords.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXFIFOSIZE_4</name>
|
|
<description>Receive FIFO/Buffer depth = 32 datawords.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXFIFOSIZE_5</name>
|
|
<description>Receive FIFO/Buffer depth = 64 datawords.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXFIFOSIZE_6</name>
|
|
<description>Receive FIFO/Buffer depth = 128 datawords.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXFIFOSIZE_7</name>
|
|
<description>Receive FIFO/Buffer depth = 256 datawords.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Receive FIFO Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXFE_0</name>
|
|
<description>Receive FIFO is not enabled. Buffer is depth 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXFE_1</name>
|
|
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOSIZE</name>
|
|
<description>Transmit FIFO Buffer Depth</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXFIFOSIZE_0</name>
|
|
<description>Transmit FIFO/Buffer depth = 1 dataword.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXFIFOSIZE_1</name>
|
|
<description>Transmit FIFO/Buffer depth = 4 datawords.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXFIFOSIZE_2</name>
|
|
<description>Transmit FIFO/Buffer depth = 8 datawords.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXFIFOSIZE_3</name>
|
|
<description>Transmit FIFO/Buffer depth = 16 datawords.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXFIFOSIZE_4</name>
|
|
<description>Transmit FIFO/Buffer depth = 32 datawords.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXFIFOSIZE_5</name>
|
|
<description>Transmit FIFO/Buffer depth = 64 datawords.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXFIFOSIZE_6</name>
|
|
<description>Transmit FIFO/Buffer depth = 128 datawords.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXFIFOSIZE_7</name>
|
|
<description>Transmit FIFO/Buffer depth = 256 datawords</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXFE_0</name>
|
|
<description>Transmit FIFO is not enabled. Buffer is depth 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXFE_1</name>
|
|
<description>Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXUFE</name>
|
|
<description>Receive FIFO Underflow Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXUFE_0</name>
|
|
<description>RXUF flag does not generate an interrupt to the host.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXUFE_1</name>
|
|
<description>RXUF flag generates an interrupt to the host.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOFE</name>
|
|
<description>Transmit FIFO Overflow Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXOFE_0</name>
|
|
<description>TXOF flag does not generate an interrupt to the host.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXOFE_1</name>
|
|
<description>TXOF flag generates an interrupt to the host.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIDEN</name>
|
|
<description>Receiver Idle Empty Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXIDEN_0</name>
|
|
<description>Disable RDRF assertion due to partially filled FIFO when receiver is idle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXIDEN_1</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXIDEN_2</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXIDEN_3</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXIDEN_4</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXIDEN_5</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXIDEN_6</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXIDEN_7</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFLUSH</name>
|
|
<description>Receive FIFO/Buffer Flush</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXFLUSH_0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXFLUSH_1</name>
|
|
<description>All data in the receive FIFO/buffer is cleared out.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFLUSH</name>
|
|
<description>Transmit FIFO/Buffer Flush</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXFLUSH_0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXFLUSH_1</name>
|
|
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receiver Buffer Underflow Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXUF_0</name>
|
|
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXUF_1</name>
|
|
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmitter Buffer Overflow Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXOF_0</name>
|
|
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXOF_1</name>
|
|
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer/FIFO Empty</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXEMPT_0</name>
|
|
<description>Receive buffer is not empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXEMPT_1</name>
|
|
<description>Receive buffer is empty.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPT</name>
|
|
<description>Transmit Buffer/FIFO Empty</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXEMPT_0</name>
|
|
<description>Transmit buffer is not empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXEMPT_1</name>
|
|
<description>Transmit buffer is empty.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WATER</name>
|
|
<description>LPUART Watermark Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit Counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive Watermark</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive Counter</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="LPUART1">
|
|
<name>LPUART2</name>
|
|
<description>LPUART</description>
|
|
<groupName>LPUART</groupName>
|
|
<baseAddress>0x40188000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPUART2</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="LPUART1">
|
|
<name>LPUART3</name>
|
|
<description>LPUART</description>
|
|
<groupName>LPUART</groupName>
|
|
<baseAddress>0x4018C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPUART3</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="LPUART1">
|
|
<name>LPUART4</name>
|
|
<description>LPUART</description>
|
|
<groupName>LPUART</groupName>
|
|
<baseAddress>0x40190000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPUART4</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPSPI1</name>
|
|
<description>LPSPI</description>
|
|
<groupName>LPSPI</groupName>
|
|
<headerStructName>LPSPI</headerStructName>
|
|
<baseAddress>0x40194000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x78</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPSPI1</name>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1020004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Module Identification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEATURE_4</name>
|
|
<description>Standard feature set supporting a 32-bit shift register.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x40404</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXFIFO</name>
|
|
<description>Transmit FIFO Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO</name>
|
|
<description>Receive FIFO Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCSNUM</name>
|
|
<description>PCS Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEN</name>
|
|
<description>Module Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MEN_0</name>
|
|
<description>Module is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEN_1</name>
|
|
<description>Module is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RST_0</name>
|
|
<description>Module is not reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RST_1</name>
|
|
<description>Module is reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEN</name>
|
|
<description>Doze Mode Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DOZEN_0</name>
|
|
<description>LPSPI module is enabled in Doze mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOZEN_1</name>
|
|
<description>LPSPI module is disabled in Doze mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBGEN_0</name>
|
|
<description>LPSPI module is disabled in debug mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBGEN_1</name>
|
|
<description>LPSPI module is enabled in debug mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTF</name>
|
|
<description>Reset Transmit FIFO</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTF_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTF_1</name>
|
|
<description>Transmit FIFO is reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRF</name>
|
|
<description>Reset Receive FIFO</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RRF_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RRF_1</name>
|
|
<description>Receive FIFO is reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDF</name>
|
|
<description>Transmit Data Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TDF_0</name>
|
|
<description>Transmit data not requested</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TDF_1</name>
|
|
<description>Transmit data is requested</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive Data Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDF_0</name>
|
|
<description>Receive Data is not ready</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDF_1</name>
|
|
<description>Receive data is ready</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCF</name>
|
|
<description>Word Complete Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCF_0</name>
|
|
<description>Transfer of a received word has not yet completed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WCF_1</name>
|
|
<description>Transfer of a received word has completed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCF</name>
|
|
<description>Frame Complete Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCF_0</name>
|
|
<description>Frame transfer has not completed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCF_1</name>
|
|
<description>Frame transfer has completed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer Complete Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TCF_0</name>
|
|
<description>All transfers have not completed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCF_1</name>
|
|
<description>All transfers have completed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEF</name>
|
|
<description>Transmit Error Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TEF_0</name>
|
|
<description>Transmit FIFO underrun has not occurred</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEF_1</name>
|
|
<description>Transmit FIFO underrun has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REF</name>
|
|
<description>Receive Error Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_0</name>
|
|
<description>Receive FIFO has not overflowed</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REF_1</name>
|
|
<description>Receive FIFO has overflowed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMF</name>
|
|
<description>Data Match Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMF_0</name>
|
|
<description>Have not received matching data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMF_1</name>
|
|
<description>Have received matching data</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBF</name>
|
|
<description>Module Busy Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MBF_0</name>
|
|
<description>LPSPI is idle</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MBF_1</name>
|
|
<description>LPSPI is busy</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDIE</name>
|
|
<description>Transmit Data Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TDIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TDIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDIE</name>
|
|
<description>Receive Data Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCIE</name>
|
|
<description>Word Complete Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WCIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCIE</name>
|
|
<description>Frame Complete Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer Complete Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TCIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transmit Error Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TEIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TEIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REIE</name>
|
|
<description>Receive Error Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMIE</name>
|
|
<description>Data Match Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DER</name>
|
|
<description>DMA Enable Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDDE</name>
|
|
<description>Transmit Data DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TDDE_0</name>
|
|
<description>DMA request is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TDDE_1</name>
|
|
<description>DMA request is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDDE</name>
|
|
<description>Receive Data DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDDE_0</name>
|
|
<description>DMA request is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDDE_1</name>
|
|
<description>DMA request is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR0</name>
|
|
<description>Configuration Register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HREN</name>
|
|
<description>Host Request Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HREN_0</name>
|
|
<description>Host request is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HREN_1</name>
|
|
<description>Host request is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRPOL</name>
|
|
<description>Host Request Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRPOL_0</name>
|
|
<description>Active low</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRPOL_1</name>
|
|
<description>Active high</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRSEL</name>
|
|
<description>Host Request Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRSEL_0</name>
|
|
<description>Host request input is the LPSPI_HREQ pin</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRSEL_1</name>
|
|
<description>Host request input is the input trigger</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIRFIFO</name>
|
|
<description>Circular FIFO Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CIRFIFO_0</name>
|
|
<description>Circular FIFO is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CIRFIFO_1</name>
|
|
<description>Circular FIFO is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMO</name>
|
|
<description>Receive Data Match Only</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDMO_0</name>
|
|
<description>Received data is stored in the receive FIFO as in normal operations</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDMO_1</name>
|
|
<description>Received data is discarded unless the Data Match Flag (DMF) is set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR1</name>
|
|
<description>Configuration Register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASTER</name>
|
|
<description>Master Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASTER_0</name>
|
|
<description>Slave mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTER_1</name>
|
|
<description>Master mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Sample Point</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAMPLE_0</name>
|
|
<description>Input data is sampled on SCK edge</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPLE_1</name>
|
|
<description>Input data is sampled on delayed SCK edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOPCS</name>
|
|
<description>Automatic PCS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUTOPCS_0</name>
|
|
<description>Automatic PCS generation is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTOPCS_1</name>
|
|
<description>Automatic PCS generation is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOSTALL</name>
|
|
<description>No Stall</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOSTALL_0</name>
|
|
<description>Transfers will stall when the transmit FIFO is empty or the receive FIFO is full</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOSTALL_1</name>
|
|
<description>Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSPOL</name>
|
|
<description>Peripheral Chip Select Polarity</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PCSPOL_0</name>
|
|
<description>The Peripheral Chip Select pin PCSx is active low</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PCSPOL_1</name>
|
|
<description>The Peripheral Chip Select pin PCSx is active high</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCFG</name>
|
|
<description>Match Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MATCFG_0</name>
|
|
<description>Match is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_2</name>
|
|
<description>010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_3</name>
|
|
<description>011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_4</name>
|
|
<description>100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)]</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_5</name>
|
|
<description>101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)]</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_6</name>
|
|
<description>110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_7</name>
|
|
<description>111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINCFG</name>
|
|
<description>Pin Configuration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PINCFG_0</name>
|
|
<description>SIN is used for input data and SOUT is used for output data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_1</name>
|
|
<description>SIN is used for both input and output data</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_2</name>
|
|
<description>SOUT is used for both input and output data</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_3</name>
|
|
<description>SOUT is used for input data and SIN is used for output data</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTCFG</name>
|
|
<description>Output Config</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTCFG_0</name>
|
|
<description>Output data retains last value when chip select is negated</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTCFG_1</name>
|
|
<description>Output data is tristated when chip select is negated</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSCFG</name>
|
|
<description>Peripheral Chip Select Configuration</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PCSCFG_0</name>
|
|
<description>PCS[3:2] are enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PCSCFG_1</name>
|
|
<description>PCS[3:2] are disabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMR0</name>
|
|
<description>Data Match Register 0</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH0</name>
|
|
<description>Match 0 Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMR1</name>
|
|
<description>Data Match Register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH1</name>
|
|
<description>Match 1 Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Clock Configuration Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCKDIV</name>
|
|
<description>SCK Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBT</name>
|
|
<description>Delay Between Transfers</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCSSCK</name>
|
|
<description>PCS-to-SCK Delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCKPCS</name>
|
|
<description>SCK-to-PCS Delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>FIFO Control Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit FIFO Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive FIFO Watermark</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSR</name>
|
|
<description>FIFO Status Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit FIFO Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive FIFO Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Command Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAMESZ</name>
|
|
<description>Frame Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WIDTH</name>
|
|
<description>Transfer Width</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WIDTH_0</name>
|
|
<description>1 bit transfer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIDTH_1</name>
|
|
<description>2 bit transfer</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WIDTH_2</name>
|
|
<description>4 bit transfer</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXMSK</name>
|
|
<description>Transmit Data Mask</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXMSK_0</name>
|
|
<description>Normal transfer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXMSK_1</name>
|
|
<description>Mask transmit data</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXMSK</name>
|
|
<description>Receive Data Mask</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXMSK_0</name>
|
|
<description>Normal transfer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXMSK_1</name>
|
|
<description>Receive data is masked</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONTC</name>
|
|
<description>Continuing Command</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONTC_0</name>
|
|
<description>Command word for start of new transfer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTC_1</name>
|
|
<description>Command word for continuing transfer</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous Transfer</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CONT_0</name>
|
|
<description>Continuous transfer is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONT_1</name>
|
|
<description>Continuous transfer is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYSW</name>
|
|
<description>Byte Swap</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BYSW_0</name>
|
|
<description>Byte swap is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BYSW_1</name>
|
|
<description>Byte swap is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSBF</name>
|
|
<description>LSB First</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LSBF_0</name>
|
|
<description>Data is transferred MSB first</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSBF_1</name>
|
|
<description>Data is transferred LSB first</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Chip Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PCS_0</name>
|
|
<description>Transfer using LPSPI_PCS[0]</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PCS_1</name>
|
|
<description>Transfer using LPSPI_PCS[1]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PCS_2</name>
|
|
<description>Transfer using LPSPI_PCS[2]</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PCS_3</name>
|
|
<description>Transfer using LPSPI_PCS[3]</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALE</name>
|
|
<description>Prescaler Value</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_0</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_1</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_2</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_3</name>
|
|
<description>Divide by 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_4</name>
|
|
<description>Divide by 16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_5</name>
|
|
<description>Divide by 32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_6</name>
|
|
<description>Divide by 64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_7</name>
|
|
<description>Divide by 128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CPHA_0</name>
|
|
<description>Data is captured on the leading edge of SCK and changed on the following edge of SCK</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPHA_1</name>
|
|
<description>Data is changed on the leading edge of SCK and captured on the following edge of SCK</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CPOL_0</name>
|
|
<description>The inactive state value of SCK is low</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CPOL_1</name>
|
|
<description>The inactive state value of SCK is high</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDR</name>
|
|
<description>Transmit Data Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSR</name>
|
|
<description>Receive Status Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Start Of Frame</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SOF_0</name>
|
|
<description>Subsequent data word received after LPSPI_PCS assertion</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOF_1</name>
|
|
<description>First data word received after LPSPI_PCS assertion</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPTY</name>
|
|
<description>RX FIFO Empty</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXEMPTY_0</name>
|
|
<description>RX FIFO is not empty</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXEMPTY_1</name>
|
|
<description>RX FIFO is empty</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDR</name>
|
|
<description>Receive Data Register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="LPSPI1">
|
|
<name>LPSPI2</name>
|
|
<description>LPSPI</description>
|
|
<groupName>LPSPI</groupName>
|
|
<baseAddress>0x40198000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x78</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPSPI2</name>
|
|
<value>33</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPI2C1</name>
|
|
<description>LPI2C</description>
|
|
<groupName>LPI2C</groupName>
|
|
<headerStructName>LPI2C</headerStructName>
|
|
<baseAddress>0x401A4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x174</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPI2C1</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1000003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Specification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEATURE_2</name>
|
|
<description>Master only, with standard feature set</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEATURE_3</name>
|
|
<description>Master and slave, with standard feature set</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x202</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTXFIFO</name>
|
|
<description>Master Transmit FIFO Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MRXFIFO</name>
|
|
<description>Master Receive FIFO Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Master Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEN</name>
|
|
<description>Master Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MEN_0</name>
|
|
<description>Master logic is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEN_1</name>
|
|
<description>Master logic is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RST_0</name>
|
|
<description>Master logic is not reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RST_1</name>
|
|
<description>Master logic is reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEN</name>
|
|
<description>Doze mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DOZEN_0</name>
|
|
<description>Master is enabled in Doze mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOZEN_1</name>
|
|
<description>Master is disabled in Doze mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBGEN_0</name>
|
|
<description>Master is disabled in debug mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBGEN_1</name>
|
|
<description>Master is enabled in debug mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTF</name>
|
|
<description>Reset Transmit FIFO</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTF_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTF_1</name>
|
|
<description>Transmit FIFO is reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRF</name>
|
|
<description>Reset Receive FIFO</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RRF_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RRF_1</name>
|
|
<description>Receive FIFO is reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSR</name>
|
|
<description>Master Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDF</name>
|
|
<description>Transmit Data Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TDF_0</name>
|
|
<description>Transmit data is not requested</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TDF_1</name>
|
|
<description>Transmit data is requested</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive Data Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDF_0</name>
|
|
<description>Receive Data is not ready</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDF_1</name>
|
|
<description>Receive data is ready</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPF</name>
|
|
<description>End Packet Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPF_0</name>
|
|
<description>Master has not generated a STOP or Repeated START condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPF_1</name>
|
|
<description>Master has generated a STOP or Repeated START condition</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDF</name>
|
|
<description>STOP Detect Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SDF_0</name>
|
|
<description>Master has not generated a STOP condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SDF_1</name>
|
|
<description>Master has generated a STOP condition</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NDF</name>
|
|
<description>NACK Detect Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NDF_0</name>
|
|
<description>Unexpected NACK was not detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NDF_1</name>
|
|
<description>Unexpected NACK was detected</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALF</name>
|
|
<description>Arbitration Lost Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALF_0</name>
|
|
<description>Master has not lost arbitration</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALF_1</name>
|
|
<description>Master has lost arbitration</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>FIFO Error Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEF_0</name>
|
|
<description>No error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEF_1</name>
|
|
<description>Master sending or receiving data without a START condition</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLTF</name>
|
|
<description>Pin Low Timeout Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLTF_0</name>
|
|
<description>Pin low timeout has not occurred or is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLTF_1</name>
|
|
<description>Pin low timeout has occurred</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMF</name>
|
|
<description>Data Match Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMF_0</name>
|
|
<description>Have not received matching data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMF_1</name>
|
|
<description>Have received matching data</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBF</name>
|
|
<description>Master Busy Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MBF_0</name>
|
|
<description>I2C Master is idle</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MBF_1</name>
|
|
<description>I2C Master is busy</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BBF</name>
|
|
<description>Bus Busy Flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BBF_0</name>
|
|
<description>I2C Bus is idle</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BBF_1</name>
|
|
<description>I2C Bus is busy</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIER</name>
|
|
<description>Master Interrupt Enable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDIE</name>
|
|
<description>Transmit Data Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TDIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TDIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDIE</name>
|
|
<description>Receive Data Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPIE</name>
|
|
<description>End Packet Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EPIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EPIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDIE</name>
|
|
<description>STOP Detect Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SDIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SDIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NDIE</name>
|
|
<description>NACK Detect Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NDIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NDIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALIE</name>
|
|
<description>Arbitration Lost Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>FIFO Error Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEIE_0</name>
|
|
<description>Enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEIE_1</name>
|
|
<description>Disabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLTIE</name>
|
|
<description>Pin Low Timeout Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PLTIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLTIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMIE</name>
|
|
<description>Data Match Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DMIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDER</name>
|
|
<description>Master DMA Enable Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDDE</name>
|
|
<description>Transmit Data DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TDDE_0</name>
|
|
<description>DMA request is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TDDE_1</name>
|
|
<description>DMA request is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDDE</name>
|
|
<description>Receive Data DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDDE_0</name>
|
|
<description>DMA request is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDDE_1</name>
|
|
<description>DMA request is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFGR0</name>
|
|
<description>Master Configuration Register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HREN</name>
|
|
<description>Host Request Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HREN_0</name>
|
|
<description>Host request input is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HREN_1</name>
|
|
<description>Host request input is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRPOL</name>
|
|
<description>Host Request Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRPOL_0</name>
|
|
<description>Active low</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRPOL_1</name>
|
|
<description>Active high</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRSEL</name>
|
|
<description>Host Request Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HRSEL_0</name>
|
|
<description>Host request input is pin HREQ</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HRSEL_1</name>
|
|
<description>Host request input is input trigger</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIRFIFO</name>
|
|
<description>Circular FIFO Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CIRFIFO_0</name>
|
|
<description>Circular FIFO is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CIRFIFO_1</name>
|
|
<description>Circular FIFO is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMO</name>
|
|
<description>Receive Data Match Only</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDMO_0</name>
|
|
<description>Received data is stored in the receive FIFO</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDMO_1</name>
|
|
<description>Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFGR1</name>
|
|
<description>Master Configuration Register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCALE</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_0</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_1</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_2</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_3</name>
|
|
<description>Divide by 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_4</name>
|
|
<description>Divide by 16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_5</name>
|
|
<description>Divide by 32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_6</name>
|
|
<description>Divide by 64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALE_7</name>
|
|
<description>Divide by 128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSTOP</name>
|
|
<description>Automatic STOP Generation</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUTOSTOP_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTOSTOP_1</name>
|
|
<description>STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IGNACK</name>
|
|
<description>IGNACK</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IGNACK_0</name>
|
|
<description>LPI2C Master will receive ACK and NACK normally</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IGNACK_1</name>
|
|
<description>LPI2C Master will treat a received NACK as if it (NACK) was an ACK</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMECFG</name>
|
|
<description>Timeout Configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMECFG_0</name>
|
|
<description>Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMECFG_1</name>
|
|
<description>Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCFG</name>
|
|
<description>Match Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MATCFG_0</name>
|
|
<description>Match is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_2</name>
|
|
<description>Match is enabled (1st data word equals MATCH0 OR MATCH1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_3</name>
|
|
<description>Match is enabled (any data word equals MATCH0 OR MATCH1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_4</name>
|
|
<description>Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_5</name>
|
|
<description>Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_6</name>
|
|
<description>Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCFG_7</name>
|
|
<description>Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINCFG</name>
|
|
<description>Pin Configuration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PINCFG_0</name>
|
|
<description>2-pin open drain mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_1</name>
|
|
<description>2-pin output only mode (ultra-fast mode)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_2</name>
|
|
<description>2-pin push-pull mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_3</name>
|
|
<description>4-pin push-pull mode</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_4</name>
|
|
<description>2-pin open drain mode with separate LPI2C slave</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_5</name>
|
|
<description>2-pin output only mode (ultra-fast mode) with separate LPI2C slave</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_6</name>
|
|
<description>2-pin push-pull mode with separate LPI2C slave</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_7</name>
|
|
<description>4-pin push-pull mode (inverted outputs)</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFGR2</name>
|
|
<description>Master Configuration Register 2</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSIDLE</name>
|
|
<description>Bus Idle Timeout</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTSCL</name>
|
|
<description>Glitch Filter SCL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTSDA</name>
|
|
<description>Glitch Filter SDA</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFGR3</name>
|
|
<description>Master Configuration Register 3</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINLOW</name>
|
|
<description>Pin Low Timeout</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMR</name>
|
|
<description>Master Data Match Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH0</name>
|
|
<description>Match 0 Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MATCH1</name>
|
|
<description>Match 1 Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCCR0</name>
|
|
<description>Master Clock Configuration Register 0</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKLO</name>
|
|
<description>Clock Low Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKHI</name>
|
|
<description>Clock High Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETHOLD</name>
|
|
<description>Setup Hold Delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVD</name>
|
|
<description>Data Valid Delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCCR1</name>
|
|
<description>Master Clock Configuration Register 1</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKLO</name>
|
|
<description>Clock Low Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKHI</name>
|
|
<description>Clock High Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETHOLD</name>
|
|
<description>Setup Hold Delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVD</name>
|
|
<description>Data Valid Delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MFCR</name>
|
|
<description>Master FIFO Control Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit FIFO Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive FIFO Watermark</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MFSR</name>
|
|
<description>Master FIFO Status Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit FIFO Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive FIFO Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MTDR</name>
|
|
<description>Master Transmit Data Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command Data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMD_0</name>
|
|
<description>Transmit DATA[7:0]</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMD_1</name>
|
|
<description>Receive (DATA[7:0] + 1) bytes</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMD_2</name>
|
|
<description>Generate STOP condition</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMD_3</name>
|
|
<description>Receive and discard (DATA[7:0] + 1) bytes</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMD_4</name>
|
|
<description>Generate (repeated) START and transmit address in DATA[7:0]</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMD_5</name>
|
|
<description>Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMD_6</name>
|
|
<description>Generate (repeated) START and transmit address in DATA[7:0] using high speed mode</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMD_7</name>
|
|
<description>Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MRDR</name>
|
|
<description>Master Receive Data Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPTY</name>
|
|
<description>RX Empty</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXEMPTY_0</name>
|
|
<description>Receive FIFO is not empty</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXEMPTY_1</name>
|
|
<description>Receive FIFO is empty</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>Slave Control Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEN</name>
|
|
<description>Slave Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SEN_0</name>
|
|
<description>I2C Slave mode is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEN_1</name>
|
|
<description>I2C Slave mode is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RST_0</name>
|
|
<description>Slave mode logic is not reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RST_1</name>
|
|
<description>Slave mode logic is reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN</name>
|
|
<description>Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FILTEN_0</name>
|
|
<description>Disable digital filter and output delay counter for slave mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTEN_1</name>
|
|
<description>Enable digital filter and output delay counter for slave mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTDZ</name>
|
|
<description>Filter Doze Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FILTDZ_0</name>
|
|
<description>Filter remains enabled in Doze mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FILTDZ_1</name>
|
|
<description>Filter is disabled in Doze mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTF</name>
|
|
<description>Reset Transmit FIFO</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RTF_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RTF_1</name>
|
|
<description>Transmit Data Register is now empty</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRF</name>
|
|
<description>Reset Receive FIFO</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RRF_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RRF_1</name>
|
|
<description>Receive Data Register is now empty</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSR</name>
|
|
<description>Slave Status Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDF</name>
|
|
<description>Transmit Data Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TDF_0</name>
|
|
<description>Transmit data not requested</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TDF_1</name>
|
|
<description>Transmit data is requested</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive Data Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDF_0</name>
|
|
<description>Receive data is not ready</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDF_1</name>
|
|
<description>Receive data is ready</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVF</name>
|
|
<description>Address Valid Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AVF_0</name>
|
|
<description>Address Status Register is not valid</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVF_1</name>
|
|
<description>Address Status Register is valid</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAF</name>
|
|
<description>Transmit ACK Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAF_0</name>
|
|
<description>Transmit ACK/NACK is not required</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAF_1</name>
|
|
<description>Transmit ACK/NACK is required</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSF</name>
|
|
<description>Repeated Start Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RSF_0</name>
|
|
<description>Slave has not detected a Repeated START condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RSF_1</name>
|
|
<description>Slave has detected a Repeated START condition</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDF</name>
|
|
<description>STOP Detect Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SDF_0</name>
|
|
<description>Slave has not detected a STOP condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SDF_1</name>
|
|
<description>Slave has detected a STOP condition</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEF</name>
|
|
<description>Bit Error Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BEF_0</name>
|
|
<description>Slave has not detected a bit error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BEF_1</name>
|
|
<description>Slave has detected a bit error</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>FIFO Error Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEF_0</name>
|
|
<description>FIFO underflow or overflow was not detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEF_1</name>
|
|
<description>FIFO underflow or overflow was detected</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM0F</name>
|
|
<description>Address Match 0 Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AM0F_0</name>
|
|
<description>Have not received an ADDR0 matching address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AM0F_1</name>
|
|
<description>Have received an ADDR0 matching address</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM1F</name>
|
|
<description>Address Match 1 Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AM1F_0</name>
|
|
<description>Have not received an ADDR1 or ADDR0/ADDR1 range matching address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AM1F_1</name>
|
|
<description>Have received an ADDR1 or ADDR0/ADDR1 range matching address</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCF</name>
|
|
<description>General Call Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GCF_0</name>
|
|
<description>Slave has not detected the General Call Address or the General Call Address is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCF_1</name>
|
|
<description>Slave has detected the General Call Address</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SARF</name>
|
|
<description>SMBus Alert Response Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SARF_0</name>
|
|
<description>SMBus Alert Response is disabled or not detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SARF_1</name>
|
|
<description>SMBus Alert Response is enabled and detected</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBF</name>
|
|
<description>Slave Busy Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SBF_0</name>
|
|
<description>I2C Slave is idle</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SBF_1</name>
|
|
<description>I2C Slave is busy</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BBF</name>
|
|
<description>Bus Busy Flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BBF_0</name>
|
|
<description>I2C Bus is idle</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BBF_1</name>
|
|
<description>I2C Bus is busy</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIER</name>
|
|
<description>Slave Interrupt Enable Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDIE</name>
|
|
<description>Transmit Data Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TDIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TDIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDIE</name>
|
|
<description>Receive Data Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVIE</name>
|
|
<description>Address Valid Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AVIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAIE</name>
|
|
<description>Transmit ACK Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TAIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TAIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSIE</name>
|
|
<description>Repeated Start Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RSIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RSIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDIE</name>
|
|
<description>STOP Detect Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SDIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SDIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEIE</name>
|
|
<description>Bit Error Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BEIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BEIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>FIFO Error Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM0IE</name>
|
|
<description>Address Match 0 Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AM0IE_0</name>
|
|
<description>Enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AM0IE_1</name>
|
|
<description>Disabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM1F</name>
|
|
<description>Address Match 1 Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AM1F_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AM1F_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCIE</name>
|
|
<description>General Call Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GCIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SARIE</name>
|
|
<description>SMBus Alert Response Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SARIE_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SARIE_1</name>
|
|
<description>Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDER</name>
|
|
<description>Slave DMA Enable Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDDE</name>
|
|
<description>Transmit Data DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TDDE_0</name>
|
|
<description>DMA request is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TDDE_1</name>
|
|
<description>DMA request is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDDE</name>
|
|
<description>Receive Data DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RDDE_0</name>
|
|
<description>DMA request is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDDE_1</name>
|
|
<description>DMA request is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVDE</name>
|
|
<description>Address Valid DMA Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AVDE_0</name>
|
|
<description>DMA request is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AVDE_1</name>
|
|
<description>DMA request is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCFGR1</name>
|
|
<description>Slave Configuration Register 1</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRSTALL</name>
|
|
<description>Address SCL Stall</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADRSTALL_0</name>
|
|
<description>Clock stretching is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADRSTALL_1</name>
|
|
<description>Clock stretching is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXSTALL</name>
|
|
<description>RX SCL Stall</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXSTALL_0</name>
|
|
<description>Clock stretching is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXSTALL_1</name>
|
|
<description>Clock stretching is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDSTALL</name>
|
|
<description>TX Data SCL Stall</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXDSTALL_0</name>
|
|
<description>Clock stretching is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXDSTALL_1</name>
|
|
<description>Clock stretching is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKSTALL</name>
|
|
<description>ACK SCL Stall</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ACKSTALL_0</name>
|
|
<description>Clock stretching is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACKSTALL_1</name>
|
|
<description>Clock stretching is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCEN</name>
|
|
<description>General Call Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GCEN_0</name>
|
|
<description>General Call address is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GCEN_1</name>
|
|
<description>General Call address is enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAEN</name>
|
|
<description>SMBus Alert Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SAEN_0</name>
|
|
<description>Disables match on SMBus Alert</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAEN_1</name>
|
|
<description>Enables match on SMBus Alert</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCFG</name>
|
|
<description>Transmit Flag Configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXCFG_0</name>
|
|
<description>Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXCFG_1</name>
|
|
<description>Transmit Data Flag will assert whenever the Transmit Data register is empty</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXCFG</name>
|
|
<description>Receive Data Configuration</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXCFG_0</name>
|
|
<description>Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXCFG_1</name>
|
|
<description>Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IGNACK</name>
|
|
<description>Ignore NACK</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IGNACK_0</name>
|
|
<description>Slave will end transfer when NACK is detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IGNACK_1</name>
|
|
<description>Slave will not end transfer when NACK detected</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSMEN</name>
|
|
<description>High Speed Mode Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HSMEN_0</name>
|
|
<description>Disables detection of HS-mode master code</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HSMEN_1</name>
|
|
<description>Enables detection of HS-mode master code</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADDRCFG</name>
|
|
<description>Address Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADDRCFG_0</name>
|
|
<description>Address match 0 (7-bit)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADDRCFG_1</name>
|
|
<description>Address match 0 (10-bit)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADDRCFG_2</name>
|
|
<description>Address match 0 (7-bit) or Address match 1 (7-bit)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADDRCFG_3</name>
|
|
<description>Address match 0 (10-bit) or Address match 1 (10-bit)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADDRCFG_4</name>
|
|
<description>Address match 0 (7-bit) or Address match 1 (10-bit)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADDRCFG_5</name>
|
|
<description>Address match 0 (10-bit) or Address match 1 (7-bit)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADDRCFG_6</name>
|
|
<description>From Address match 0 (7-bit) to Address match 1 (7-bit)</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADDRCFG_7</name>
|
|
<description>From Address match 0 (10-bit) to Address match 1 (10-bit)</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCFGR2</name>
|
|
<description>Slave Configuration Register 2</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKHOLD</name>
|
|
<description>Clock Hold Time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVD</name>
|
|
<description>Data Valid Delay</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTSCL</name>
|
|
<description>Glitch Filter SCL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTSDA</name>
|
|
<description>Glitch Filter SDA</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SAMR</name>
|
|
<description>Slave Address Match Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR0</name>
|
|
<description>Address 0 Value</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR1</name>
|
|
<description>Address 1 Value</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SASR</name>
|
|
<description>Slave Address Status Register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RADDR</name>
|
|
<description>Received Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ANV</name>
|
|
<description>Address Not Valid</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ANV_0</name>
|
|
<description>Received Address (RADDR) is valid</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANV_1</name>
|
|
<description>Received Address (RADDR) is not valid</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAR</name>
|
|
<description>Slave Transmit ACK Register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXNACK</name>
|
|
<description>Transmit NACK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TXNACK_0</name>
|
|
<description>Write a Transmit ACK for each received word</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TXNACK_1</name>
|
|
<description>Write a Transmit NACK for each received word</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STDR</name>
|
|
<description>Slave Transmit Data Register</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRDR</name>
|
|
<description>Slave Receive Data Register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPTY</name>
|
|
<description>RX Empty</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RXEMPTY_0</name>
|
|
<description>The Receive Data Register is not empty</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RXEMPTY_1</name>
|
|
<description>The Receive Data Register is empty</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Start Of Frame</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SOF_0</name>
|
|
<description>Indicates this is not the first data word since a (repeated) START or STOP condition</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOF_1</name>
|
|
<description>Indicates this is the first data word since a (repeated) START or STOP condition</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="LPI2C1">
|
|
<name>LPI2C2</name>
|
|
<description>LPI2C</description>
|
|
<groupName>LPI2C</groupName>
|
|
<baseAddress>0x401A8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x174</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPI2C2</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLEXIO1</name>
|
|
<description>FLEXIO</description>
|
|
<groupName>FLEXIO</groupName>
|
|
<baseAddress>0x401AC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x7A0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FLEXIO1</name>
|
|
<value>68</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1010001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Specification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEATURE_0</name>
|
|
<description>Standard features implemented.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEATURE_1</name>
|
|
<description>Supports state, logic and parallel modes.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x2200808</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTER</name>
|
|
<description>Shifter Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER</name>
|
|
<description>Timer Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PIN</name>
|
|
<description>Pin Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIGGER</name>
|
|
<description>Trigger Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>FlexIO Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLEXEN</name>
|
|
<description>FlexIO Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLEXEN_0</name>
|
|
<description>FlexIO module is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLEXEN_1</name>
|
|
<description>FlexIO module is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SWRST_0</name>
|
|
<description>Software reset is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SWRST_1</name>
|
|
<description>Software reset is enabled, all FlexIO registers except the Control Register are reset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FASTACC</name>
|
|
<description>Fast Access</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FASTACC_0</name>
|
|
<description>Configures for normal register accesses to FlexIO</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FASTACC_1</name>
|
|
<description>Configures for fast register accesses to FlexIO</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGE</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBGE_0</name>
|
|
<description>FlexIO is disabled in debug modes.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBGE_1</name>
|
|
<description>FlexIO is enabled in debug modes</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEN</name>
|
|
<description>Doze Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DOZEN_0</name>
|
|
<description>FlexIO enabled in Doze modes.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOZEN_1</name>
|
|
<description>FlexIO disabled in Doze modes.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIN</name>
|
|
<description>Pin State Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Pin Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTSTAT</name>
|
|
<description>Shifter Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSF</name>
|
|
<description>Shifter Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTERR</name>
|
|
<description>Shifter Error Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEF</name>
|
|
<description>Shifter Error Flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMSTAT</name>
|
|
<description>Timer Status Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSF</name>
|
|
<description>Timer Status Flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTSIEN</name>
|
|
<description>Shifter Status Interrupt Enable</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSIE</name>
|
|
<description>Shifter Status Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTEIEN</name>
|
|
<description>Shifter Error Interrupt Enable</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEIE</name>
|
|
<description>Shifter Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMIEN</name>
|
|
<description>Timer Interrupt Enable Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Timer Status Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTSDEN</name>
|
|
<description>Shifter Status DMA Enable</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSDE</name>
|
|
<description>Shifter Status DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTSTATE</name>
|
|
<description>Shifter State Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATE</name>
|
|
<description>Current State Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>SHIFTCTL[%s]</name>
|
|
<description>Shifter Control N Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Shifter Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SMOD_0</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_1</name>
|
|
<description>Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_2</name>
|
|
<description>Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_4</name>
|
|
<description>Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_5</name>
|
|
<description>Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_6</name>
|
|
<description>State mode. SHIFTBUF contents are used for storing programmable state attributes.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SMOD_7</name>
|
|
<description>Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINPOL</name>
|
|
<description>Shifter Pin Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PINPOL_0</name>
|
|
<description>Pin is active high</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINPOL_1</name>
|
|
<description>Pin is active low</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINSEL</name>
|
|
<description>Shifter Pin Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINCFG</name>
|
|
<description>Shifter Pin Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PINCFG_0</name>
|
|
<description>Shifter pin output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_1</name>
|
|
<description>Shifter pin open drain or bidirectional output enable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_2</name>
|
|
<description>Shifter pin bidirectional output data</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_3</name>
|
|
<description>Shifter pin output</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMPOL</name>
|
|
<description>Timer Polarity</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMPOL_0</name>
|
|
<description>Shift on posedge of Shift clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMPOL_1</name>
|
|
<description>Shift on negedge of Shift clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMSEL</name>
|
|
<description>Timer Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>SHIFTCFG[%s]</name>
|
|
<description>Shifter Configuration N Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSTART</name>
|
|
<description>Shifter Start bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSTART_0</name>
|
|
<description>Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSTART_1</name>
|
|
<description>Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSTART_2</name>
|
|
<description>Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSTART_3</name>
|
|
<description>Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSTOP</name>
|
|
<description>Shifter Stop bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SSTOP_0</name>
|
|
<description>Stop bit disabled for transmitter/receiver/match store</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSTOP_2</name>
|
|
<description>Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSTOP_3</name>
|
|
<description>Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSRC</name>
|
|
<description>Input Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INSRC_0</name>
|
|
<description>Pin</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INSRC_1</name>
|
|
<description>Shifter N+1 Output</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWIDTH</name>
|
|
<description>Parallel Width</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>SHIFTBUF[%s]</name>
|
|
<description>Shifter Buffer N Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTBUF</name>
|
|
<description>Shift Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>SHIFTBUFBIS[%s]</name>
|
|
<description>Shifter Buffer N Bit Swapped Register</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTBUFBIS</name>
|
|
<description>Shift Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>SHIFTBUFBYS[%s]</name>
|
|
<description>Shifter Buffer N Byte Swapped Register</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTBUFBYS</name>
|
|
<description>Shift Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>SHIFTBUFBBS[%s]</name>
|
|
<description>Shifter Buffer N Bit Byte Swapped Register</description>
|
|
<addressOffset>0x380</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTBUFBBS</name>
|
|
<description>Shift Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>TIMCTL[%s]</name>
|
|
<description>Timer Control N Register</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIMOD</name>
|
|
<description>Timer Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMOD_0</name>
|
|
<description>Timer Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMOD_1</name>
|
|
<description>Dual 8-bit counters baud mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMOD_2</name>
|
|
<description>Dual 8-bit counters PWM high mode.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMOD_3</name>
|
|
<description>Single 16-bit counter mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINPOL</name>
|
|
<description>Timer Pin Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PINPOL_0</name>
|
|
<description>Pin is active high</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINPOL_1</name>
|
|
<description>Pin is active low</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINSEL</name>
|
|
<description>Timer Pin Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINCFG</name>
|
|
<description>Timer Pin Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PINCFG_0</name>
|
|
<description>Timer pin output disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_1</name>
|
|
<description>Timer pin open drain or bidirectional output enable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_2</name>
|
|
<description>Timer pin bidirectional output data</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PINCFG_3</name>
|
|
<description>Timer pin output</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGSRC</name>
|
|
<description>Trigger Source</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRGSRC_0</name>
|
|
<description>External trigger selected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGSRC_1</name>
|
|
<description>Internal trigger selected</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGPOL</name>
|
|
<description>Trigger Polarity</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRGPOL_0</name>
|
|
<description>Trigger active high</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGPOL_1</name>
|
|
<description>Trigger active low</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>Trigger Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>TIMCFG[%s]</name>
|
|
<description>Timer Configuration N Register</description>
|
|
<addressOffset>0x480</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSTART</name>
|
|
<description>Timer Start Bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TSTART_0</name>
|
|
<description>Start bit disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TSTART_1</name>
|
|
<description>Start bit enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTOP</name>
|
|
<description>Timer Stop Bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TSTOP_0</name>
|
|
<description>Stop bit disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TSTOP_1</name>
|
|
<description>Stop bit is enabled on timer compare</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TSTOP_2</name>
|
|
<description>Stop bit is enabled on timer disable</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TSTOP_3</name>
|
|
<description>Stop bit is enabled on timer compare and timer disable</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMENA</name>
|
|
<description>Timer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMENA_0</name>
|
|
<description>Timer always enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMENA_1</name>
|
|
<description>Timer enabled on Timer N-1 enable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMENA_2</name>
|
|
<description>Timer enabled on Trigger high</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMENA_3</name>
|
|
<description>Timer enabled on Trigger high and Pin high</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMENA_4</name>
|
|
<description>Timer enabled on Pin rising edge</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMENA_5</name>
|
|
<description>Timer enabled on Pin rising edge and Trigger high</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMENA_6</name>
|
|
<description>Timer enabled on Trigger rising edge</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMENA_7</name>
|
|
<description>Timer enabled on Trigger rising or falling edge</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMDIS</name>
|
|
<description>Timer Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMDIS_0</name>
|
|
<description>Timer never disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMDIS_1</name>
|
|
<description>Timer disabled on Timer N-1 disable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMDIS_2</name>
|
|
<description>Timer disabled on Timer compare (upper 8-bits match and decrement)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMDIS_3</name>
|
|
<description>Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMDIS_4</name>
|
|
<description>Timer disabled on Pin rising or falling edge</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMDIS_5</name>
|
|
<description>Timer disabled on Pin rising or falling edge provided Trigger is high</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMDIS_6</name>
|
|
<description>Timer disabled on Trigger falling edge</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMRST</name>
|
|
<description>Timer Reset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMRST_0</name>
|
|
<description>Timer never reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMRST_2</name>
|
|
<description>Timer reset on Timer Pin equal to Timer Output</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMRST_3</name>
|
|
<description>Timer reset on Timer Trigger equal to Timer Output</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMRST_4</name>
|
|
<description>Timer reset on Timer Pin rising edge</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMRST_6</name>
|
|
<description>Timer reset on Trigger rising edge</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMRST_7</name>
|
|
<description>Timer reset on Trigger rising or falling edge</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMDEC</name>
|
|
<description>Timer Decrement</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMDEC_0</name>
|
|
<description>Decrement counter on FlexIO clock, Shift clock equals Timer output.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMDEC_1</name>
|
|
<description>Decrement counter on Trigger input (both edges), Shift clock equals Timer output.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMDEC_2</name>
|
|
<description>Decrement counter on Pin input (both edges), Shift clock equals Pin input.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMDEC_3</name>
|
|
<description>Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMOUT</name>
|
|
<description>Timer Output</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMOUT_0</name>
|
|
<description>Timer output is logic one when enabled and is not affected by timer reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMOUT_1</name>
|
|
<description>Timer output is logic zero when enabled and is not affected by timer reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMOUT_2</name>
|
|
<description>Timer output is logic one when enabled and on timer reset</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMOUT_3</name>
|
|
<description>Timer output is logic zero when enabled and on timer reset</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>TIMCMP[%s]</name>
|
|
<description>Timer Compare N Register</description>
|
|
<addressOffset>0x500</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMP</name>
|
|
<description>Timer Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>SHIFTBUFNBS[%s]</name>
|
|
<description>Shifter Buffer N Nibble Byte Swapped Register</description>
|
|
<addressOffset>0x680</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTBUFNBS</name>
|
|
<description>Shift Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>SHIFTBUFHWS[%s]</name>
|
|
<description>Shifter Buffer N Half Word Swapped Register</description>
|
|
<addressOffset>0x700</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTBUFHWS</name>
|
|
<description>Shift Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>SHIFTBUFNIS[%s]</name>
|
|
<description>Shifter Buffer N Nibble Swapped Register</description>
|
|
<addressOffset>0x780</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTBUFNIS</name>
|
|
<description>Shift Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIO1</name>
|
|
<description>GPIO</description>
|
|
<groupName>GPIO</groupName>
|
|
<headerStructName>GPIO</headerStructName>
|
|
<baseAddress>0x401B8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x90</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPIO1_Combined_0_15</name>
|
|
<value>70</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>GPIO1_Combined_16_31</name>
|
|
<value>71</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>GPIO data register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>DR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GDIR</name>
|
|
<description>GPIO direction register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GDIR</name>
|
|
<description>GDIR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSR</name>
|
|
<description>GPIO pad status register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSR</name>
|
|
<description>PSR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR1</name>
|
|
<description>GPIO interrupt configuration register1</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICR0</name>
|
|
<description>ICR0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR1</name>
|
|
<description>ICR1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR2</name>
|
|
<description>ICR2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR3</name>
|
|
<description>ICR3</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR4</name>
|
|
<description>ICR4</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR5</name>
|
|
<description>ICR5</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR6</name>
|
|
<description>ICR6</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR7</name>
|
|
<description>ICR7</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR8</name>
|
|
<description>ICR8</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR9</name>
|
|
<description>ICR9</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR10</name>
|
|
<description>ICR10</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR11</name>
|
|
<description>ICR11</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR12</name>
|
|
<description>ICR12</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR13</name>
|
|
<description>ICR13</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR14</name>
|
|
<description>ICR14</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR15</name>
|
|
<description>ICR15</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR2</name>
|
|
<description>GPIO interrupt configuration register2</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICR16</name>
|
|
<description>ICR16</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR17</name>
|
|
<description>ICR17</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR18</name>
|
|
<description>ICR18</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR19</name>
|
|
<description>ICR19</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR20</name>
|
|
<description>ICR20</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR21</name>
|
|
<description>ICR21</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR22</name>
|
|
<description>ICR22</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR23</name>
|
|
<description>ICR23</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR24</name>
|
|
<description>ICR24</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR25</name>
|
|
<description>ICR25</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR26</name>
|
|
<description>ICR26</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR27</name>
|
|
<description>ICR27</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR28</name>
|
|
<description>ICR28</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR29</name>
|
|
<description>ICR29</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR30</name>
|
|
<description>ICR30</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICR31</name>
|
|
<description>ICR31</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOW_LEVEL</name>
|
|
<description>Interrupt n is low-level sensitive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_LEVEL</name>
|
|
<description>Interrupt n is high-level sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Interrupt n is rising-edge sensitive.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Interrupt n is falling-edge sensitive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>GPIO interrupt mask register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMR</name>
|
|
<description>IMR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>GPIO interrupt status register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISR</name>
|
|
<description>ISR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EDGE_SEL</name>
|
|
<description>GPIO edge select register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_EDGE_SEL</name>
|
|
<description>GPIO_EDGE_SEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR_SET</name>
|
|
<description>GPIO data register SET</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DR_SET</name>
|
|
<description>DR_SET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR_CLEAR</name>
|
|
<description>GPIO data register CLEAR</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DR_CLEAR</name>
|
|
<description>DR_CLEAR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR_TOGGLE</name>
|
|
<description>GPIO data register TOGGLE</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DR_TOGGLE</name>
|
|
<description>DR_TOGGLE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIO1">
|
|
<name>GPIO5</name>
|
|
<description>GPIO</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x400C0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x90</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPIO5_Combined_0_15</name>
|
|
<value>73</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIO1">
|
|
<name>GPIO2</name>
|
|
<description>GPIO</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x42000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x90</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPIO2_Combined_0_15</name>
|
|
<value>72</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PWM1</name>
|
|
<description>PWM</description>
|
|
<groupName>PWM</groupName>
|
|
<baseAddress>0x401CC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x196</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PWM1_0</name>
|
|
<value>34</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PWM1_1</name>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PWM1_2</name>
|
|
<value>36</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PWM1_3</name>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PWM1_FAULT</name>
|
|
<value>38</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SM0CNT</name>
|
|
<description>Counter Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Register Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0INIT</name>
|
|
<description>Initial Count Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initial Count Register Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CTRL2</name>
|
|
<description>Control 2 Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLK_SEL_0</name>
|
|
<description>The IPBus clock is used as the clock for the local prescaler and counter.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_SEL_1</name>
|
|
<description>EXT_CLK is used as the clock for the local prescaler and counter.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_SEL_2</name>
|
|
<description>Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RELOAD_SEL</name>
|
|
<description>Reload Source Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RELOAD_SEL_0</name>
|
|
<description>The local RELOAD signal is used to reload registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELOAD_SEL_1</name>
|
|
<description>The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_SEL</name>
|
|
<description>This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_0</name>
|
|
<description>The local force signal, CTRL2[FORCE], from this submodule is used to force updates.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_1</name>
|
|
<description>The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_2</name>
|
|
<description>The local reload signal from this submodule is used to force updates without regard to the state of LDOK.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_3</name>
|
|
<description>The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_4</name>
|
|
<description>The local sync signal from this submodule is used to force updates.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_5</name>
|
|
<description>The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_6</name>
|
|
<description>The external force signal, EXT_FORCE, from outside the PWM module causes updates.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_7</name>
|
|
<description>The external sync signal, EXT_SYNC, from outside the PWM module causes updates.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCE</name>
|
|
<description>Force Initialization</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRCEN</name>
|
|
<description>FRCEN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRCEN_0</name>
|
|
<description>Initialization from a FORCE_OUT is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRCEN_1</name>
|
|
<description>Initialization from a FORCE_OUT is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT_SEL</name>
|
|
<description>Initialization Control Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_0</name>
|
|
<description>Local sync (PWM_X) causes initialization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_1</name>
|
|
<description>Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_2</name>
|
|
<description>Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_3</name>
|
|
<description>EXT_SYNC causes initialization.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMX_INIT</name>
|
|
<description>PWM_X Initial Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM45_INIT</name>
|
|
<description>PWM45 Initial Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM23_INIT</name>
|
|
<description>PWM23 Initial Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INDEP</name>
|
|
<description>Independent or Complementary Pair Operation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INDEP_0</name>
|
|
<description>PWM_A and PWM_B form a complementary PWM pair.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INDEP_1</name>
|
|
<description>PWM_A and PWM_B outputs are independent PWMs.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>WAIT Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x400</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBLEN</name>
|
|
<description>Double Switching Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBLEN_0</name>
|
|
<description>Double switching disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBLEN_1</name>
|
|
<description>Double switching enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLX</name>
|
|
<description>PWMX Double Switching Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBLX_0</name>
|
|
<description>PWMX double pulse disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBLX_1</name>
|
|
<description>PWMX double pulse enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDMOD</name>
|
|
<description>Load Mode Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LDMOD_0</name>
|
|
<description>Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDMOD_1</name>
|
|
<description>Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLIT</name>
|
|
<description>Split the DBLPWM signal to PWMA and PWMB</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPLIT_0</name>
|
|
<description>DBLPWM is not split. PWMA and PWMB each have double pulses.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPLIT_1</name>
|
|
<description>DBLPWM is split to PWMA and PWMB.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSC</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSC_0</name>
|
|
<description>PWM clock frequency = fclk</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_1</name>
|
|
<description>PWM clock frequency = fclk/2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_2</name>
|
|
<description>PWM clock frequency = fclk/4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_3</name>
|
|
<description>PWM clock frequency = fclk/8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_4</name>
|
|
<description>PWM clock frequency = fclk/16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_5</name>
|
|
<description>PWM clock frequency = fclk/32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_6</name>
|
|
<description>PWM clock frequency = fclk/64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_7</name>
|
|
<description>PWM clock frequency = fclk/128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPMODE</name>
|
|
<description>Compare Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPMODE_0</name>
|
|
<description>The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMPMODE_1</name>
|
|
<description>The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Deadtime</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FULL</name>
|
|
<description>Full Cycle Reload</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL_0</name>
|
|
<description>Full-cycle reloads disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL_1</name>
|
|
<description>Full-cycle reloads enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALF</name>
|
|
<description>Half Cycle Reload</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALF_0</name>
|
|
<description>Half-cycle reloads disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF_1</name>
|
|
<description>Half-cycle reloads enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDFQ</name>
|
|
<description>Load Frequency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LDFQ_0</name>
|
|
<description>Every PWM opportunity</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_1</name>
|
|
<description>Every 2 PWM opportunities</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_2</name>
|
|
<description>Every 3 PWM opportunities</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_3</name>
|
|
<description>Every 4 PWM opportunities</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_4</name>
|
|
<description>Every 5 PWM opportunities</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_5</name>
|
|
<description>Every 6 PWM opportunities</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_6</name>
|
|
<description>Every 7 PWM opportunities</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_7</name>
|
|
<description>Every 8 PWM opportunities</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_8</name>
|
|
<description>Every 9 PWM opportunities</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_9</name>
|
|
<description>Every 10 PWM opportunities</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_10</name>
|
|
<description>Every 11 PWM opportunities</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_11</name>
|
|
<description>Every 12 PWM opportunities</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_12</name>
|
|
<description>Every 13 PWM opportunities</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_13</name>
|
|
<description>Every 14 PWM opportunities</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_14</name>
|
|
<description>Every 15 PWM opportunities</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_15</name>
|
|
<description>Every 16 PWM opportunities</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0VAL0</name>
|
|
<description>Value Register 0</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL0</name>
|
|
<description>Value Register 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0FRACVAL1</name>
|
|
<description>Fractional Value Register 1</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL1</name>
|
|
<description>Fractional Value 1 Register</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0VAL1</name>
|
|
<description>Value Register 1</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL1</name>
|
|
<description>Value Register 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0FRACVAL2</name>
|
|
<description>Fractional Value Register 2</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL2</name>
|
|
<description>Fractional Value 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0VAL2</name>
|
|
<description>Value Register 2</description>
|
|
<addressOffset>0x12</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL2</name>
|
|
<description>Value Register 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0FRACVAL3</name>
|
|
<description>Fractional Value Register 3</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL3</name>
|
|
<description>Fractional Value 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0VAL3</name>
|
|
<description>Value Register 3</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL3</name>
|
|
<description>Value Register 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0FRACVAL4</name>
|
|
<description>Fractional Value Register 4</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL4</name>
|
|
<description>Fractional Value 4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0VAL4</name>
|
|
<description>Value Register 4</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL4</name>
|
|
<description>Value Register 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0FRACVAL5</name>
|
|
<description>Fractional Value Register 5</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL5</name>
|
|
<description>Fractional Value 5</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0VAL5</name>
|
|
<description>Value Register 5</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL5</name>
|
|
<description>Value Register 5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0FRCTRL</name>
|
|
<description>Fractional Control Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAC1_EN</name>
|
|
<description>Fractional Cycle PWM Period Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC1_EN_0</name>
|
|
<description>Disable fractional cycle length for the PWM period.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC1_EN_1</name>
|
|
<description>Enable fractional cycle length for the PWM period.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC23_EN</name>
|
|
<description>Fractional Cycle Placement Enable for PWM_A</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC23_EN_0</name>
|
|
<description>Disable fractional cycle placement for PWM_A.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC23_EN_1</name>
|
|
<description>Enable fractional cycle placement for PWM_A.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC45_EN</name>
|
|
<description>Fractional Cycle Placement Enable for PWM_B</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC45_EN_0</name>
|
|
<description>Disable fractional cycle placement for PWM_B.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC45_EN_1</name>
|
|
<description>Enable fractional cycle placement for PWM_B.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC_PU</name>
|
|
<description>Fractional Delay Circuit Power Up</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC_PU_0</name>
|
|
<description>Turn off fractional delay logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC_PU_1</name>
|
|
<description>Power up fractional delay logic.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEST</name>
|
|
<description>Test Status Bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0OCTRL</name>
|
|
<description>Output Control Register</description>
|
|
<addressOffset>0x22</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMXFS</name>
|
|
<description>PWM_X Fault State</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_0</name>
|
|
<description>Output is forced to logic 0 state prior to consideration of output polarity control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_1</name>
|
|
<description>Output is forced to logic 1 state prior to consideration of output polarity control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_2</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_3</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMBFS</name>
|
|
<description>PWM_B Fault State</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_0</name>
|
|
<description>Output is forced to logic 0 state prior to consideration of output polarity control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_1</name>
|
|
<description>Output is forced to logic 1 state prior to consideration of output polarity control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_2</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_3</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMAFS</name>
|
|
<description>PWM_A Fault State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_0</name>
|
|
<description>Output is forced to logic 0 state prior to consideration of output polarity control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_1</name>
|
|
<description>Output is forced to logic 1 state prior to consideration of output polarity control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_2</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_3</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLX</name>
|
|
<description>PWM_X Output Polarity</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POLX_0</name>
|
|
<description>PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POLX_1</name>
|
|
<description>PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLB</name>
|
|
<description>PWM_B Output Polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POLB_0</name>
|
|
<description>PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POLB_1</name>
|
|
<description>PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLA</name>
|
|
<description>PWM_A Output Polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POLA_0</name>
|
|
<description>PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POLA_1</name>
|
|
<description>PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMX_IN</name>
|
|
<description>PWM_X Input</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWMB_IN</name>
|
|
<description>PWM_B Input</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWMA_IN</name>
|
|
<description>PWM_A Input</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0STS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPF</name>
|
|
<description>Compare Flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPF_0</name>
|
|
<description>No compare event has occurred for a particular VALx value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPF_1</name>
|
|
<description>A compare event has occurred for a particular VALx value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFX0</name>
|
|
<description>Capture Flag X0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFX1</name>
|
|
<description>Capture Flag X1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFB0</name>
|
|
<description>Capture Flag B0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFB1</name>
|
|
<description>Capture Flag B1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFA0</name>
|
|
<description>Capture Flag A0</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFA1</name>
|
|
<description>Capture Flag A1</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>RF</name>
|
|
<description>Reload Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RF_0</name>
|
|
<description>No new reload cycle since last STS[RF] clearing</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RF_1</name>
|
|
<description>New reload cycle since last STS[RF] clearing</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REF</name>
|
|
<description>Reload Error Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_0</name>
|
|
<description>No reload error occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REF_1</name>
|
|
<description>Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUF</name>
|
|
<description>Registers Updated Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUF_0</name>
|
|
<description>No register update has occurred since last reload.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUF_1</name>
|
|
<description>At least one of the double buffered registers has been updated since the last reload.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0INTEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x26</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPIE</name>
|
|
<description>Compare Interrupt Enables</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPIE_0</name>
|
|
<description>The corresponding STS[CMPF] bit will not cause an interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPIE_1</name>
|
|
<description>The corresponding STS[CMPF] bit will cause an interrupt request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CX0IE</name>
|
|
<description>Capture X 0 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CX0IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFX0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CX0IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFX0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CX1IE</name>
|
|
<description>Capture X 1 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CX1IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFX1].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CX1IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFX1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CB0IE</name>
|
|
<description>Capture B 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CB0IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFB0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CB0IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFB0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CB1IE</name>
|
|
<description>Capture B 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CB1IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFB1].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CB1IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFB1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CA0IE</name>
|
|
<description>Capture A 0 Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CA0IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFA0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CA0IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFA0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CA1IE</name>
|
|
<description>Capture A 1 Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CA1IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFA1].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CA1IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFA1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Reload Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RIE_0</name>
|
|
<description>STS[RF] CPU interrupt requests disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RIE_1</name>
|
|
<description>STS[RF] CPU interrupt requests enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REIE</name>
|
|
<description>Reload Error Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REIE_0</name>
|
|
<description>STS[REF] CPU interrupt requests disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REIE_1</name>
|
|
<description>STS[REF] CPU interrupt requests enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0DMAEN</name>
|
|
<description>DMA Enable Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CX0DE</name>
|
|
<description>Capture X0 FIFO DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CX1DE</name>
|
|
<description>Capture X1 FIFO DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CB0DE</name>
|
|
<description>Capture B0 FIFO DMA Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CB1DE</name>
|
|
<description>Capture B1 FIFO DMA Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CA0DE</name>
|
|
<description>Capture A0 FIFO DMA Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CA1DE</name>
|
|
<description>Capture A1 FIFO DMA Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAPTDE</name>
|
|
<description>Capture DMA Enable Source Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_0</name>
|
|
<description>Read DMA requests disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_1</name>
|
|
<description>Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_2</name>
|
|
<description>A local sync (VAL1 matches counter) sets the read DMA request.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_3</name>
|
|
<description>A local reload (STS[RF] being set) sets the read DMA request.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAND</name>
|
|
<description>FIFO Watermark AND Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FAND_0</name>
|
|
<description>Selected FIFO watermarks are OR'ed together.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAND_1</name>
|
|
<description>Selected FIFO watermarks are AND'ed together.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VALDE</name>
|
|
<description>Value Registers DMA Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VALDE_0</name>
|
|
<description>DMA write requests disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALDE_1</name>
|
|
<description>DMA write requests for the VALx and FRACVALx registers enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0TCTRL</name>
|
|
<description>Output Trigger Control Register</description>
|
|
<addressOffset>0x2A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUT_TRIG_EN</name>
|
|
<description>Output Trigger Enables</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT_TRIG_EN_0</name>
|
|
<description>PWM_OUT_TRIGx will not set when the counter value matches the VALx value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT_TRIG_EN_1</name>
|
|
<description>PWM_OUT_TRIGx will set when the counter value matches the VALx value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGFRQ</name>
|
|
<description>Trigger frequency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRGFRQ_0</name>
|
|
<description>Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGFRQ_1</name>
|
|
<description>Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWBOT1</name>
|
|
<description>Output Trigger 1 Source Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWBOT1_0</name>
|
|
<description>Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWBOT1_1</name>
|
|
<description>Route the PWMB output to the PWM_OUT_TRIG1 port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWAOT0</name>
|
|
<description>Output Trigger 0 Source Select</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWAOT0_0</name>
|
|
<description>Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWAOT0_1</name>
|
|
<description>Route the PWMA output to the PWM_OUT_TRIG0 port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0DISMAP0</name>
|
|
<description>Fault Disable Mapping Register 0</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIS0A</name>
|
|
<description>PWM_A Fault Disable Mask 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS0B</name>
|
|
<description>PWM_B Fault Disable Mask 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS0X</name>
|
|
<description>PWM_X Fault Disable Mask 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0DISMAP1</name>
|
|
<description>Fault Disable Mapping Register 1</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIS1A</name>
|
|
<description>PWM_A Fault Disable Mask 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS1B</name>
|
|
<description>PWM_B Fault Disable Mask 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS1X</name>
|
|
<description>PWM_X Fault Disable Mask 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0DTCNT0</name>
|
|
<description>Deadtime Count Register 0</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7FF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTCNT0</name>
|
|
<description>DTCNT0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0DTCNT1</name>
|
|
<description>Deadtime Count Register 1</description>
|
|
<addressOffset>0x32</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7FF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTCNT1</name>
|
|
<description>DTCNT1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CAPTCTRLA</name>
|
|
<description>Capture Control A Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARMA</name>
|
|
<description>Arm A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARMA_0</name>
|
|
<description>Input capture operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARMA_1</name>
|
|
<description>Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOTA</name>
|
|
<description>One Shot Mode A</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOTA_0</name>
|
|
<description>Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOTA_1</name>
|
|
<description>One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGA0</name>
|
|
<description>Edge A 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGA0_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA0_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA0_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA0_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGA1</name>
|
|
<description>Edge A 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGA1_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA1_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA1_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA1_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INP_SELA</name>
|
|
<description>Input Select A</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INP_SELA_0</name>
|
|
<description>Raw PWM_A input signal selected as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INP_SELA_1</name>
|
|
<description>Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTA_EN</name>
|
|
<description>Edge Counter A Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGCNTA_EN_0</name>
|
|
<description>Edge counter disabled and held in reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGCNTA_EN_1</name>
|
|
<description>Edge counter enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFAWM</name>
|
|
<description>Capture A FIFOs Water Mark</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CA0CNT</name>
|
|
<description>Capture A0 FIFO Word Count</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CA1CNT</name>
|
|
<description>Capture A1 FIFO Word Count</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CAPTCOMPA</name>
|
|
<description>Capture Compare A Register</description>
|
|
<addressOffset>0x36</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGCMPA</name>
|
|
<description>Edge Compare A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTA</name>
|
|
<description>Edge Counter A</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CAPTCTRLB</name>
|
|
<description>Capture Control B Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARMB</name>
|
|
<description>Arm B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARMB_0</name>
|
|
<description>Input capture operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARMB_1</name>
|
|
<description>Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOTB</name>
|
|
<description>One Shot Mode B</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOTB_0</name>
|
|
<description>Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOTB_1</name>
|
|
<description>One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGB0</name>
|
|
<description>Edge B 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGB0_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB0_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB0_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB0_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGB1</name>
|
|
<description>Edge B 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGB1_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB1_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB1_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB1_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INP_SELB</name>
|
|
<description>Input Select B</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INP_SELB_0</name>
|
|
<description>Raw PWM_B input signal selected as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INP_SELB_1</name>
|
|
<description>Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTB_EN</name>
|
|
<description>Edge Counter B Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGCNTB_EN_0</name>
|
|
<description>Edge counter disabled and held in reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGCNTB_EN_1</name>
|
|
<description>Edge counter enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFBWM</name>
|
|
<description>Capture B FIFOs Water Mark</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CB0CNT</name>
|
|
<description>Capture B0 FIFO Word Count</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CB1CNT</name>
|
|
<description>Capture B1 FIFO Word Count</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CAPTCOMPB</name>
|
|
<description>Capture Compare B Register</description>
|
|
<addressOffset>0x3A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGCMPB</name>
|
|
<description>Edge Compare B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTB</name>
|
|
<description>Edge Counter B</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CAPTCTRLX</name>
|
|
<description>Capture Control X Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARMX</name>
|
|
<description>Arm X</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARMX_0</name>
|
|
<description>Input capture operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARMX_1</name>
|
|
<description>Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOTX</name>
|
|
<description>One Shot Mode Aux</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOTX_0</name>
|
|
<description>Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOTX_1</name>
|
|
<description>One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGX0</name>
|
|
<description>Edge X 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGX0_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX0_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX0_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX0_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGX1</name>
|
|
<description>Edge X 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGX1_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX1_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX1_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX1_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INP_SELX</name>
|
|
<description>Input Select X</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INP_SELX_0</name>
|
|
<description>Raw PWM_X input signal selected as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INP_SELX_1</name>
|
|
<description>Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTX_EN</name>
|
|
<description>Edge Counter X Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGCNTX_EN_0</name>
|
|
<description>Edge counter disabled and held in reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGCNTX_EN_1</name>
|
|
<description>Edge counter enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFXWM</name>
|
|
<description>Capture X FIFOs Water Mark</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CX0CNT</name>
|
|
<description>Capture X0 FIFO Word Count</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CX1CNT</name>
|
|
<description>Capture X1 FIFO Word Count</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CAPTCOMPX</name>
|
|
<description>Capture Compare X Register</description>
|
|
<addressOffset>0x3E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGCMPX</name>
|
|
<description>Edge Compare X</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTX</name>
|
|
<description>Edge Counter X</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CVAL0</name>
|
|
<description>Capture Value 0 Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL0</name>
|
|
<description>CAPTVAL0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CVAL0CYC</name>
|
|
<description>Capture Value 0 Cycle Register</description>
|
|
<addressOffset>0x42</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL0CYC</name>
|
|
<description>CVAL0CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CVAL1</name>
|
|
<description>Capture Value 1 Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL1</name>
|
|
<description>CAPTVAL1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CVAL1CYC</name>
|
|
<description>Capture Value 1 Cycle Register</description>
|
|
<addressOffset>0x46</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL1CYC</name>
|
|
<description>CVAL1CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CVAL2</name>
|
|
<description>Capture Value 2 Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL2</name>
|
|
<description>CAPTVAL2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CVAL2CYC</name>
|
|
<description>Capture Value 2 Cycle Register</description>
|
|
<addressOffset>0x4A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL2CYC</name>
|
|
<description>CVAL2CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CVAL3</name>
|
|
<description>Capture Value 3 Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL3</name>
|
|
<description>CAPTVAL3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CVAL3CYC</name>
|
|
<description>Capture Value 3 Cycle Register</description>
|
|
<addressOffset>0x4E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL3CYC</name>
|
|
<description>CVAL3CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CVAL4</name>
|
|
<description>Capture Value 4 Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL4</name>
|
|
<description>CAPTVAL4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CVAL4CYC</name>
|
|
<description>Capture Value 4 Cycle Register</description>
|
|
<addressOffset>0x52</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL4CYC</name>
|
|
<description>CVAL4CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CVAL5</name>
|
|
<description>Capture Value 5 Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL5</name>
|
|
<description>CAPTVAL5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0CVAL5CYC</name>
|
|
<description>Capture Value 5 Cycle Register</description>
|
|
<addressOffset>0x56</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL5CYC</name>
|
|
<description>CVAL5CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM0PHASEDLY</name>
|
|
<description>Phase Delay Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PHASEDLY</name>
|
|
<description>Initial Count Register Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CNT</name>
|
|
<description>Counter Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Register Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1INIT</name>
|
|
<description>Initial Count Register</description>
|
|
<addressOffset>0x62</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initial Count Register Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CTRL2</name>
|
|
<description>Control 2 Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLK_SEL_0</name>
|
|
<description>The IPBus clock is used as the clock for the local prescaler and counter.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_SEL_1</name>
|
|
<description>EXT_CLK is used as the clock for the local prescaler and counter.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_SEL_2</name>
|
|
<description>Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RELOAD_SEL</name>
|
|
<description>Reload Source Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RELOAD_SEL_0</name>
|
|
<description>The local RELOAD signal is used to reload registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELOAD_SEL_1</name>
|
|
<description>The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_SEL</name>
|
|
<description>This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_0</name>
|
|
<description>The local force signal, CTRL2[FORCE], from this submodule is used to force updates.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_1</name>
|
|
<description>The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_2</name>
|
|
<description>The local reload signal from this submodule is used to force updates without regard to the state of LDOK.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_3</name>
|
|
<description>The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_4</name>
|
|
<description>The local sync signal from this submodule is used to force updates.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_5</name>
|
|
<description>The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_6</name>
|
|
<description>The external force signal, EXT_FORCE, from outside the PWM module causes updates.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_7</name>
|
|
<description>The external sync signal, EXT_SYNC, from outside the PWM module causes updates.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCE</name>
|
|
<description>Force Initialization</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRCEN</name>
|
|
<description>FRCEN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRCEN_0</name>
|
|
<description>Initialization from a FORCE_OUT is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRCEN_1</name>
|
|
<description>Initialization from a FORCE_OUT is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT_SEL</name>
|
|
<description>Initialization Control Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_0</name>
|
|
<description>Local sync (PWM_X) causes initialization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_1</name>
|
|
<description>Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_2</name>
|
|
<description>Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_3</name>
|
|
<description>EXT_SYNC causes initialization.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMX_INIT</name>
|
|
<description>PWM_X Initial Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM45_INIT</name>
|
|
<description>PWM45 Initial Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM23_INIT</name>
|
|
<description>PWM23 Initial Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INDEP</name>
|
|
<description>Independent or Complementary Pair Operation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INDEP_0</name>
|
|
<description>PWM_A and PWM_B form a complementary PWM pair.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INDEP_1</name>
|
|
<description>PWM_A and PWM_B outputs are independent PWMs.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>WAIT Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x66</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x400</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBLEN</name>
|
|
<description>Double Switching Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBLEN_0</name>
|
|
<description>Double switching disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBLEN_1</name>
|
|
<description>Double switching enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLX</name>
|
|
<description>PWMX Double Switching Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBLX_0</name>
|
|
<description>PWMX double pulse disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBLX_1</name>
|
|
<description>PWMX double pulse enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDMOD</name>
|
|
<description>Load Mode Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LDMOD_0</name>
|
|
<description>Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDMOD_1</name>
|
|
<description>Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLIT</name>
|
|
<description>Split the DBLPWM signal to PWMA and PWMB</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPLIT_0</name>
|
|
<description>DBLPWM is not split. PWMA and PWMB each have double pulses.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPLIT_1</name>
|
|
<description>DBLPWM is split to PWMA and PWMB.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSC</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSC_0</name>
|
|
<description>PWM clock frequency = fclk</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_1</name>
|
|
<description>PWM clock frequency = fclk/2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_2</name>
|
|
<description>PWM clock frequency = fclk/4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_3</name>
|
|
<description>PWM clock frequency = fclk/8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_4</name>
|
|
<description>PWM clock frequency = fclk/16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_5</name>
|
|
<description>PWM clock frequency = fclk/32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_6</name>
|
|
<description>PWM clock frequency = fclk/64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_7</name>
|
|
<description>PWM clock frequency = fclk/128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPMODE</name>
|
|
<description>Compare Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPMODE_0</name>
|
|
<description>The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMPMODE_1</name>
|
|
<description>The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Deadtime</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FULL</name>
|
|
<description>Full Cycle Reload</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL_0</name>
|
|
<description>Full-cycle reloads disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL_1</name>
|
|
<description>Full-cycle reloads enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALF</name>
|
|
<description>Half Cycle Reload</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALF_0</name>
|
|
<description>Half-cycle reloads disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF_1</name>
|
|
<description>Half-cycle reloads enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDFQ</name>
|
|
<description>Load Frequency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LDFQ_0</name>
|
|
<description>Every PWM opportunity</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_1</name>
|
|
<description>Every 2 PWM opportunities</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_2</name>
|
|
<description>Every 3 PWM opportunities</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_3</name>
|
|
<description>Every 4 PWM opportunities</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_4</name>
|
|
<description>Every 5 PWM opportunities</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_5</name>
|
|
<description>Every 6 PWM opportunities</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_6</name>
|
|
<description>Every 7 PWM opportunities</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_7</name>
|
|
<description>Every 8 PWM opportunities</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_8</name>
|
|
<description>Every 9 PWM opportunities</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_9</name>
|
|
<description>Every 10 PWM opportunities</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_10</name>
|
|
<description>Every 11 PWM opportunities</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_11</name>
|
|
<description>Every 12 PWM opportunities</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_12</name>
|
|
<description>Every 13 PWM opportunities</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_13</name>
|
|
<description>Every 14 PWM opportunities</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_14</name>
|
|
<description>Every 15 PWM opportunities</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_15</name>
|
|
<description>Every 16 PWM opportunities</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1VAL0</name>
|
|
<description>Value Register 0</description>
|
|
<addressOffset>0x6A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL0</name>
|
|
<description>Value Register 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1FRACVAL1</name>
|
|
<description>Fractional Value Register 1</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL1</name>
|
|
<description>Fractional Value 1 Register</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1VAL1</name>
|
|
<description>Value Register 1</description>
|
|
<addressOffset>0x6E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL1</name>
|
|
<description>Value Register 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1FRACVAL2</name>
|
|
<description>Fractional Value Register 2</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL2</name>
|
|
<description>Fractional Value 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1VAL2</name>
|
|
<description>Value Register 2</description>
|
|
<addressOffset>0x72</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL2</name>
|
|
<description>Value Register 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1FRACVAL3</name>
|
|
<description>Fractional Value Register 3</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL3</name>
|
|
<description>Fractional Value 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1VAL3</name>
|
|
<description>Value Register 3</description>
|
|
<addressOffset>0x76</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL3</name>
|
|
<description>Value Register 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1FRACVAL4</name>
|
|
<description>Fractional Value Register 4</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL4</name>
|
|
<description>Fractional Value 4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1VAL4</name>
|
|
<description>Value Register 4</description>
|
|
<addressOffset>0x7A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL4</name>
|
|
<description>Value Register 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1FRACVAL5</name>
|
|
<description>Fractional Value Register 5</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL5</name>
|
|
<description>Fractional Value 5</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1VAL5</name>
|
|
<description>Value Register 5</description>
|
|
<addressOffset>0x7E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL5</name>
|
|
<description>Value Register 5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1FRCTRL</name>
|
|
<description>Fractional Control Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAC1_EN</name>
|
|
<description>Fractional Cycle PWM Period Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC1_EN_0</name>
|
|
<description>Disable fractional cycle length for the PWM period.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC1_EN_1</name>
|
|
<description>Enable fractional cycle length for the PWM period.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC23_EN</name>
|
|
<description>Fractional Cycle Placement Enable for PWM_A</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC23_EN_0</name>
|
|
<description>Disable fractional cycle placement for PWM_A.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC23_EN_1</name>
|
|
<description>Enable fractional cycle placement for PWM_A.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC45_EN</name>
|
|
<description>Fractional Cycle Placement Enable for PWM_B</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC45_EN_0</name>
|
|
<description>Disable fractional cycle placement for PWM_B.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC45_EN_1</name>
|
|
<description>Enable fractional cycle placement for PWM_B.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC_PU</name>
|
|
<description>Fractional Delay Circuit Power Up</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC_PU_0</name>
|
|
<description>Turn off fractional delay logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC_PU_1</name>
|
|
<description>Power up fractional delay logic.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEST</name>
|
|
<description>Test Status Bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1OCTRL</name>
|
|
<description>Output Control Register</description>
|
|
<addressOffset>0x82</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMXFS</name>
|
|
<description>PWM_X Fault State</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_0</name>
|
|
<description>Output is forced to logic 0 state prior to consideration of output polarity control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_1</name>
|
|
<description>Output is forced to logic 1 state prior to consideration of output polarity control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_2</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_3</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMBFS</name>
|
|
<description>PWM_B Fault State</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_0</name>
|
|
<description>Output is forced to logic 0 state prior to consideration of output polarity control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_1</name>
|
|
<description>Output is forced to logic 1 state prior to consideration of output polarity control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_2</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_3</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMAFS</name>
|
|
<description>PWM_A Fault State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_0</name>
|
|
<description>Output is forced to logic 0 state prior to consideration of output polarity control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_1</name>
|
|
<description>Output is forced to logic 1 state prior to consideration of output polarity control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_2</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_3</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLX</name>
|
|
<description>PWM_X Output Polarity</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POLX_0</name>
|
|
<description>PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POLX_1</name>
|
|
<description>PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLB</name>
|
|
<description>PWM_B Output Polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POLB_0</name>
|
|
<description>PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POLB_1</name>
|
|
<description>PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLA</name>
|
|
<description>PWM_A Output Polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POLA_0</name>
|
|
<description>PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POLA_1</name>
|
|
<description>PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMX_IN</name>
|
|
<description>PWM_X Input</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWMB_IN</name>
|
|
<description>PWM_B Input</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWMA_IN</name>
|
|
<description>PWM_A Input</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1STS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPF</name>
|
|
<description>Compare Flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPF_0</name>
|
|
<description>No compare event has occurred for a particular VALx value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPF_1</name>
|
|
<description>A compare event has occurred for a particular VALx value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFX0</name>
|
|
<description>Capture Flag X0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFX1</name>
|
|
<description>Capture Flag X1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFB0</name>
|
|
<description>Capture Flag B0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFB1</name>
|
|
<description>Capture Flag B1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFA0</name>
|
|
<description>Capture Flag A0</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFA1</name>
|
|
<description>Capture Flag A1</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>RF</name>
|
|
<description>Reload Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RF_0</name>
|
|
<description>No new reload cycle since last STS[RF] clearing</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RF_1</name>
|
|
<description>New reload cycle since last STS[RF] clearing</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REF</name>
|
|
<description>Reload Error Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_0</name>
|
|
<description>No reload error occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REF_1</name>
|
|
<description>Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUF</name>
|
|
<description>Registers Updated Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUF_0</name>
|
|
<description>No register update has occurred since last reload.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUF_1</name>
|
|
<description>At least one of the double buffered registers has been updated since the last reload.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1INTEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x86</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPIE</name>
|
|
<description>Compare Interrupt Enables</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPIE_0</name>
|
|
<description>The corresponding STS[CMPF] bit will not cause an interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPIE_1</name>
|
|
<description>The corresponding STS[CMPF] bit will cause an interrupt request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CX0IE</name>
|
|
<description>Capture X 0 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CX0IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFX0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CX0IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFX0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CX1IE</name>
|
|
<description>Capture X 1 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CX1IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFX1].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CX1IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFX1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CB0IE</name>
|
|
<description>Capture B 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CB0IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFB0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CB0IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFB0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CB1IE</name>
|
|
<description>Capture B 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CB1IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFB1].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CB1IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFB1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CA0IE</name>
|
|
<description>Capture A 0 Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CA0IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFA0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CA0IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFA0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CA1IE</name>
|
|
<description>Capture A 1 Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CA1IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFA1].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CA1IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFA1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Reload Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RIE_0</name>
|
|
<description>STS[RF] CPU interrupt requests disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RIE_1</name>
|
|
<description>STS[RF] CPU interrupt requests enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REIE</name>
|
|
<description>Reload Error Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REIE_0</name>
|
|
<description>STS[REF] CPU interrupt requests disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REIE_1</name>
|
|
<description>STS[REF] CPU interrupt requests enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1DMAEN</name>
|
|
<description>DMA Enable Register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CX0DE</name>
|
|
<description>Capture X0 FIFO DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CX1DE</name>
|
|
<description>Capture X1 FIFO DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CB0DE</name>
|
|
<description>Capture B0 FIFO DMA Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CB1DE</name>
|
|
<description>Capture B1 FIFO DMA Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CA0DE</name>
|
|
<description>Capture A0 FIFO DMA Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CA1DE</name>
|
|
<description>Capture A1 FIFO DMA Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAPTDE</name>
|
|
<description>Capture DMA Enable Source Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_0</name>
|
|
<description>Read DMA requests disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_1</name>
|
|
<description>Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_2</name>
|
|
<description>A local sync (VAL1 matches counter) sets the read DMA request.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_3</name>
|
|
<description>A local reload (STS[RF] being set) sets the read DMA request.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAND</name>
|
|
<description>FIFO Watermark AND Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FAND_0</name>
|
|
<description>Selected FIFO watermarks are OR'ed together.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAND_1</name>
|
|
<description>Selected FIFO watermarks are AND'ed together.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VALDE</name>
|
|
<description>Value Registers DMA Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VALDE_0</name>
|
|
<description>DMA write requests disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALDE_1</name>
|
|
<description>DMA write requests for the VALx and FRACVALx registers enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1TCTRL</name>
|
|
<description>Output Trigger Control Register</description>
|
|
<addressOffset>0x8A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUT_TRIG_EN</name>
|
|
<description>Output Trigger Enables</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT_TRIG_EN_0</name>
|
|
<description>PWM_OUT_TRIGx will not set when the counter value matches the VALx value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT_TRIG_EN_1</name>
|
|
<description>PWM_OUT_TRIGx will set when the counter value matches the VALx value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGFRQ</name>
|
|
<description>Trigger frequency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRGFRQ_0</name>
|
|
<description>Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGFRQ_1</name>
|
|
<description>Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWBOT1</name>
|
|
<description>Output Trigger 1 Source Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWBOT1_0</name>
|
|
<description>Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWBOT1_1</name>
|
|
<description>Route the PWMB output to the PWM_OUT_TRIG1 port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWAOT0</name>
|
|
<description>Output Trigger 0 Source Select</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWAOT0_0</name>
|
|
<description>Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWAOT0_1</name>
|
|
<description>Route the PWMA output to the PWM_OUT_TRIG0 port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1DISMAP0</name>
|
|
<description>Fault Disable Mapping Register 0</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIS0A</name>
|
|
<description>PWM_A Fault Disable Mask 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS0B</name>
|
|
<description>PWM_B Fault Disable Mask 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS0X</name>
|
|
<description>PWM_X Fault Disable Mask 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1DISMAP1</name>
|
|
<description>Fault Disable Mapping Register 1</description>
|
|
<addressOffset>0x8E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIS1A</name>
|
|
<description>PWM_A Fault Disable Mask 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS1B</name>
|
|
<description>PWM_B Fault Disable Mask 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS1X</name>
|
|
<description>PWM_X Fault Disable Mask 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1DTCNT0</name>
|
|
<description>Deadtime Count Register 0</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7FF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTCNT0</name>
|
|
<description>DTCNT0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1DTCNT1</name>
|
|
<description>Deadtime Count Register 1</description>
|
|
<addressOffset>0x92</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7FF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTCNT1</name>
|
|
<description>DTCNT1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CAPTCTRLA</name>
|
|
<description>Capture Control A Register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARMA</name>
|
|
<description>Arm A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARMA_0</name>
|
|
<description>Input capture operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARMA_1</name>
|
|
<description>Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOTA</name>
|
|
<description>One Shot Mode A</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOTA_0</name>
|
|
<description>Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOTA_1</name>
|
|
<description>One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGA0</name>
|
|
<description>Edge A 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGA0_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA0_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA0_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA0_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGA1</name>
|
|
<description>Edge A 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGA1_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA1_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA1_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA1_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INP_SELA</name>
|
|
<description>Input Select A</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INP_SELA_0</name>
|
|
<description>Raw PWM_A input signal selected as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INP_SELA_1</name>
|
|
<description>Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTA_EN</name>
|
|
<description>Edge Counter A Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGCNTA_EN_0</name>
|
|
<description>Edge counter disabled and held in reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGCNTA_EN_1</name>
|
|
<description>Edge counter enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFAWM</name>
|
|
<description>Capture A FIFOs Water Mark</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CA0CNT</name>
|
|
<description>Capture A0 FIFO Word Count</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CA1CNT</name>
|
|
<description>Capture A1 FIFO Word Count</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CAPTCOMPA</name>
|
|
<description>Capture Compare A Register</description>
|
|
<addressOffset>0x96</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGCMPA</name>
|
|
<description>Edge Compare A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTA</name>
|
|
<description>Edge Counter A</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CAPTCTRLB</name>
|
|
<description>Capture Control B Register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARMB</name>
|
|
<description>Arm B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARMB_0</name>
|
|
<description>Input capture operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARMB_1</name>
|
|
<description>Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOTB</name>
|
|
<description>One Shot Mode B</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOTB_0</name>
|
|
<description>Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOTB_1</name>
|
|
<description>One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGB0</name>
|
|
<description>Edge B 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGB0_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB0_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB0_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB0_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGB1</name>
|
|
<description>Edge B 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGB1_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB1_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB1_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB1_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INP_SELB</name>
|
|
<description>Input Select B</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INP_SELB_0</name>
|
|
<description>Raw PWM_B input signal selected as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INP_SELB_1</name>
|
|
<description>Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTB_EN</name>
|
|
<description>Edge Counter B Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGCNTB_EN_0</name>
|
|
<description>Edge counter disabled and held in reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGCNTB_EN_1</name>
|
|
<description>Edge counter enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFBWM</name>
|
|
<description>Capture B FIFOs Water Mark</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CB0CNT</name>
|
|
<description>Capture B0 FIFO Word Count</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CB1CNT</name>
|
|
<description>Capture B1 FIFO Word Count</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CAPTCOMPB</name>
|
|
<description>Capture Compare B Register</description>
|
|
<addressOffset>0x9A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGCMPB</name>
|
|
<description>Edge Compare B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTB</name>
|
|
<description>Edge Counter B</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CAPTCTRLX</name>
|
|
<description>Capture Control X Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARMX</name>
|
|
<description>Arm X</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARMX_0</name>
|
|
<description>Input capture operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARMX_1</name>
|
|
<description>Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOTX</name>
|
|
<description>One Shot Mode Aux</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOTX_0</name>
|
|
<description>Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOTX_1</name>
|
|
<description>One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGX0</name>
|
|
<description>Edge X 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGX0_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX0_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX0_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX0_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGX1</name>
|
|
<description>Edge X 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGX1_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX1_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX1_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX1_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INP_SELX</name>
|
|
<description>Input Select X</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INP_SELX_0</name>
|
|
<description>Raw PWM_X input signal selected as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INP_SELX_1</name>
|
|
<description>Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTX_EN</name>
|
|
<description>Edge Counter X Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGCNTX_EN_0</name>
|
|
<description>Edge counter disabled and held in reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGCNTX_EN_1</name>
|
|
<description>Edge counter enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFXWM</name>
|
|
<description>Capture X FIFOs Water Mark</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CX0CNT</name>
|
|
<description>Capture X0 FIFO Word Count</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CX1CNT</name>
|
|
<description>Capture X1 FIFO Word Count</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CAPTCOMPX</name>
|
|
<description>Capture Compare X Register</description>
|
|
<addressOffset>0x9E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGCMPX</name>
|
|
<description>Edge Compare X</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTX</name>
|
|
<description>Edge Counter X</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CVAL0</name>
|
|
<description>Capture Value 0 Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL0</name>
|
|
<description>CAPTVAL0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CVAL0CYC</name>
|
|
<description>Capture Value 0 Cycle Register</description>
|
|
<addressOffset>0xA2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL0CYC</name>
|
|
<description>CVAL0CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CVAL1</name>
|
|
<description>Capture Value 1 Register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL1</name>
|
|
<description>CAPTVAL1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CVAL1CYC</name>
|
|
<description>Capture Value 1 Cycle Register</description>
|
|
<addressOffset>0xA6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL1CYC</name>
|
|
<description>CVAL1CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CVAL2</name>
|
|
<description>Capture Value 2 Register</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL2</name>
|
|
<description>CAPTVAL2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CVAL2CYC</name>
|
|
<description>Capture Value 2 Cycle Register</description>
|
|
<addressOffset>0xAA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL2CYC</name>
|
|
<description>CVAL2CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CVAL3</name>
|
|
<description>Capture Value 3 Register</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL3</name>
|
|
<description>CAPTVAL3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CVAL3CYC</name>
|
|
<description>Capture Value 3 Cycle Register</description>
|
|
<addressOffset>0xAE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL3CYC</name>
|
|
<description>CVAL3CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CVAL4</name>
|
|
<description>Capture Value 4 Register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL4</name>
|
|
<description>CAPTVAL4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CVAL4CYC</name>
|
|
<description>Capture Value 4 Cycle Register</description>
|
|
<addressOffset>0xB2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL4CYC</name>
|
|
<description>CVAL4CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CVAL5</name>
|
|
<description>Capture Value 5 Register</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL5</name>
|
|
<description>CAPTVAL5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1CVAL5CYC</name>
|
|
<description>Capture Value 5 Cycle Register</description>
|
|
<addressOffset>0xB6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL5CYC</name>
|
|
<description>CVAL5CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM1PHASEDLY</name>
|
|
<description>Phase Delay Register</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PHASEDLY</name>
|
|
<description>Initial Count Register Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CNT</name>
|
|
<description>Counter Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Register Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2INIT</name>
|
|
<description>Initial Count Register</description>
|
|
<addressOffset>0xC2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initial Count Register Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CTRL2</name>
|
|
<description>Control 2 Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLK_SEL_0</name>
|
|
<description>The IPBus clock is used as the clock for the local prescaler and counter.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_SEL_1</name>
|
|
<description>EXT_CLK is used as the clock for the local prescaler and counter.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_SEL_2</name>
|
|
<description>Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RELOAD_SEL</name>
|
|
<description>Reload Source Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RELOAD_SEL_0</name>
|
|
<description>The local RELOAD signal is used to reload registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELOAD_SEL_1</name>
|
|
<description>The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_SEL</name>
|
|
<description>This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_0</name>
|
|
<description>The local force signal, CTRL2[FORCE], from this submodule is used to force updates.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_1</name>
|
|
<description>The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_2</name>
|
|
<description>The local reload signal from this submodule is used to force updates without regard to the state of LDOK.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_3</name>
|
|
<description>The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_4</name>
|
|
<description>The local sync signal from this submodule is used to force updates.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_5</name>
|
|
<description>The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_6</name>
|
|
<description>The external force signal, EXT_FORCE, from outside the PWM module causes updates.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_7</name>
|
|
<description>The external sync signal, EXT_SYNC, from outside the PWM module causes updates.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCE</name>
|
|
<description>Force Initialization</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRCEN</name>
|
|
<description>FRCEN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRCEN_0</name>
|
|
<description>Initialization from a FORCE_OUT is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRCEN_1</name>
|
|
<description>Initialization from a FORCE_OUT is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT_SEL</name>
|
|
<description>Initialization Control Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_0</name>
|
|
<description>Local sync (PWM_X) causes initialization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_1</name>
|
|
<description>Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_2</name>
|
|
<description>Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_3</name>
|
|
<description>EXT_SYNC causes initialization.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMX_INIT</name>
|
|
<description>PWM_X Initial Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM45_INIT</name>
|
|
<description>PWM45 Initial Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM23_INIT</name>
|
|
<description>PWM23 Initial Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INDEP</name>
|
|
<description>Independent or Complementary Pair Operation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INDEP_0</name>
|
|
<description>PWM_A and PWM_B form a complementary PWM pair.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INDEP_1</name>
|
|
<description>PWM_A and PWM_B outputs are independent PWMs.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>WAIT Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0xC6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x400</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBLEN</name>
|
|
<description>Double Switching Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBLEN_0</name>
|
|
<description>Double switching disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBLEN_1</name>
|
|
<description>Double switching enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLX</name>
|
|
<description>PWMX Double Switching Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBLX_0</name>
|
|
<description>PWMX double pulse disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBLX_1</name>
|
|
<description>PWMX double pulse enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDMOD</name>
|
|
<description>Load Mode Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LDMOD_0</name>
|
|
<description>Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDMOD_1</name>
|
|
<description>Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLIT</name>
|
|
<description>Split the DBLPWM signal to PWMA and PWMB</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPLIT_0</name>
|
|
<description>DBLPWM is not split. PWMA and PWMB each have double pulses.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPLIT_1</name>
|
|
<description>DBLPWM is split to PWMA and PWMB.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSC</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSC_0</name>
|
|
<description>PWM clock frequency = fclk</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_1</name>
|
|
<description>PWM clock frequency = fclk/2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_2</name>
|
|
<description>PWM clock frequency = fclk/4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_3</name>
|
|
<description>PWM clock frequency = fclk/8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_4</name>
|
|
<description>PWM clock frequency = fclk/16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_5</name>
|
|
<description>PWM clock frequency = fclk/32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_6</name>
|
|
<description>PWM clock frequency = fclk/64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_7</name>
|
|
<description>PWM clock frequency = fclk/128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPMODE</name>
|
|
<description>Compare Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPMODE_0</name>
|
|
<description>The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMPMODE_1</name>
|
|
<description>The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Deadtime</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FULL</name>
|
|
<description>Full Cycle Reload</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL_0</name>
|
|
<description>Full-cycle reloads disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL_1</name>
|
|
<description>Full-cycle reloads enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALF</name>
|
|
<description>Half Cycle Reload</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALF_0</name>
|
|
<description>Half-cycle reloads disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF_1</name>
|
|
<description>Half-cycle reloads enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDFQ</name>
|
|
<description>Load Frequency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LDFQ_0</name>
|
|
<description>Every PWM opportunity</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_1</name>
|
|
<description>Every 2 PWM opportunities</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_2</name>
|
|
<description>Every 3 PWM opportunities</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_3</name>
|
|
<description>Every 4 PWM opportunities</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_4</name>
|
|
<description>Every 5 PWM opportunities</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_5</name>
|
|
<description>Every 6 PWM opportunities</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_6</name>
|
|
<description>Every 7 PWM opportunities</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_7</name>
|
|
<description>Every 8 PWM opportunities</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_8</name>
|
|
<description>Every 9 PWM opportunities</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_9</name>
|
|
<description>Every 10 PWM opportunities</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_10</name>
|
|
<description>Every 11 PWM opportunities</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_11</name>
|
|
<description>Every 12 PWM opportunities</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_12</name>
|
|
<description>Every 13 PWM opportunities</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_13</name>
|
|
<description>Every 14 PWM opportunities</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_14</name>
|
|
<description>Every 15 PWM opportunities</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_15</name>
|
|
<description>Every 16 PWM opportunities</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2VAL0</name>
|
|
<description>Value Register 0</description>
|
|
<addressOffset>0xCA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL0</name>
|
|
<description>Value Register 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2FRACVAL1</name>
|
|
<description>Fractional Value Register 1</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL1</name>
|
|
<description>Fractional Value 1 Register</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2VAL1</name>
|
|
<description>Value Register 1</description>
|
|
<addressOffset>0xCE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL1</name>
|
|
<description>Value Register 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2FRACVAL2</name>
|
|
<description>Fractional Value Register 2</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL2</name>
|
|
<description>Fractional Value 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2VAL2</name>
|
|
<description>Value Register 2</description>
|
|
<addressOffset>0xD2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL2</name>
|
|
<description>Value Register 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2FRACVAL3</name>
|
|
<description>Fractional Value Register 3</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL3</name>
|
|
<description>Fractional Value 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2VAL3</name>
|
|
<description>Value Register 3</description>
|
|
<addressOffset>0xD6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL3</name>
|
|
<description>Value Register 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2FRACVAL4</name>
|
|
<description>Fractional Value Register 4</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL4</name>
|
|
<description>Fractional Value 4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2VAL4</name>
|
|
<description>Value Register 4</description>
|
|
<addressOffset>0xDA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL4</name>
|
|
<description>Value Register 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2FRACVAL5</name>
|
|
<description>Fractional Value Register 5</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL5</name>
|
|
<description>Fractional Value 5</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2VAL5</name>
|
|
<description>Value Register 5</description>
|
|
<addressOffset>0xDE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL5</name>
|
|
<description>Value Register 5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2FRCTRL</name>
|
|
<description>Fractional Control Register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAC1_EN</name>
|
|
<description>Fractional Cycle PWM Period Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC1_EN_0</name>
|
|
<description>Disable fractional cycle length for the PWM period.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC1_EN_1</name>
|
|
<description>Enable fractional cycle length for the PWM period.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC23_EN</name>
|
|
<description>Fractional Cycle Placement Enable for PWM_A</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC23_EN_0</name>
|
|
<description>Disable fractional cycle placement for PWM_A.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC23_EN_1</name>
|
|
<description>Enable fractional cycle placement for PWM_A.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC45_EN</name>
|
|
<description>Fractional Cycle Placement Enable for PWM_B</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC45_EN_0</name>
|
|
<description>Disable fractional cycle placement for PWM_B.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC45_EN_1</name>
|
|
<description>Enable fractional cycle placement for PWM_B.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC_PU</name>
|
|
<description>Fractional Delay Circuit Power Up</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC_PU_0</name>
|
|
<description>Turn off fractional delay logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC_PU_1</name>
|
|
<description>Power up fractional delay logic.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEST</name>
|
|
<description>Test Status Bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2OCTRL</name>
|
|
<description>Output Control Register</description>
|
|
<addressOffset>0xE2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMXFS</name>
|
|
<description>PWM_X Fault State</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_0</name>
|
|
<description>Output is forced to logic 0 state prior to consideration of output polarity control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_1</name>
|
|
<description>Output is forced to logic 1 state prior to consideration of output polarity control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_2</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_3</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMBFS</name>
|
|
<description>PWM_B Fault State</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_0</name>
|
|
<description>Output is forced to logic 0 state prior to consideration of output polarity control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_1</name>
|
|
<description>Output is forced to logic 1 state prior to consideration of output polarity control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_2</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_3</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMAFS</name>
|
|
<description>PWM_A Fault State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_0</name>
|
|
<description>Output is forced to logic 0 state prior to consideration of output polarity control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_1</name>
|
|
<description>Output is forced to logic 1 state prior to consideration of output polarity control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_2</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_3</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLX</name>
|
|
<description>PWM_X Output Polarity</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POLX_0</name>
|
|
<description>PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POLX_1</name>
|
|
<description>PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLB</name>
|
|
<description>PWM_B Output Polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POLB_0</name>
|
|
<description>PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POLB_1</name>
|
|
<description>PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLA</name>
|
|
<description>PWM_A Output Polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POLA_0</name>
|
|
<description>PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POLA_1</name>
|
|
<description>PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMX_IN</name>
|
|
<description>PWM_X Input</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWMB_IN</name>
|
|
<description>PWM_B Input</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWMA_IN</name>
|
|
<description>PWM_A Input</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2STS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPF</name>
|
|
<description>Compare Flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPF_0</name>
|
|
<description>No compare event has occurred for a particular VALx value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPF_1</name>
|
|
<description>A compare event has occurred for a particular VALx value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFX0</name>
|
|
<description>Capture Flag X0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFX1</name>
|
|
<description>Capture Flag X1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFB0</name>
|
|
<description>Capture Flag B0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFB1</name>
|
|
<description>Capture Flag B1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFA0</name>
|
|
<description>Capture Flag A0</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFA1</name>
|
|
<description>Capture Flag A1</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>RF</name>
|
|
<description>Reload Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RF_0</name>
|
|
<description>No new reload cycle since last STS[RF] clearing</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RF_1</name>
|
|
<description>New reload cycle since last STS[RF] clearing</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REF</name>
|
|
<description>Reload Error Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_0</name>
|
|
<description>No reload error occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REF_1</name>
|
|
<description>Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUF</name>
|
|
<description>Registers Updated Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUF_0</name>
|
|
<description>No register update has occurred since last reload.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUF_1</name>
|
|
<description>At least one of the double buffered registers has been updated since the last reload.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2INTEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0xE6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPIE</name>
|
|
<description>Compare Interrupt Enables</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPIE_0</name>
|
|
<description>The corresponding STS[CMPF] bit will not cause an interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPIE_1</name>
|
|
<description>The corresponding STS[CMPF] bit will cause an interrupt request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CX0IE</name>
|
|
<description>Capture X 0 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CX0IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFX0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CX0IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFX0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CX1IE</name>
|
|
<description>Capture X 1 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CX1IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFX1].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CX1IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFX1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CB0IE</name>
|
|
<description>Capture B 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CB0IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFB0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CB0IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFB0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CB1IE</name>
|
|
<description>Capture B 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CB1IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFB1].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CB1IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFB1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CA0IE</name>
|
|
<description>Capture A 0 Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CA0IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFA0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CA0IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFA0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CA1IE</name>
|
|
<description>Capture A 1 Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CA1IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFA1].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CA1IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFA1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Reload Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RIE_0</name>
|
|
<description>STS[RF] CPU interrupt requests disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RIE_1</name>
|
|
<description>STS[RF] CPU interrupt requests enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REIE</name>
|
|
<description>Reload Error Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REIE_0</name>
|
|
<description>STS[REF] CPU interrupt requests disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REIE_1</name>
|
|
<description>STS[REF] CPU interrupt requests enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2DMAEN</name>
|
|
<description>DMA Enable Register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CX0DE</name>
|
|
<description>Capture X0 FIFO DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CX1DE</name>
|
|
<description>Capture X1 FIFO DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CB0DE</name>
|
|
<description>Capture B0 FIFO DMA Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CB1DE</name>
|
|
<description>Capture B1 FIFO DMA Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CA0DE</name>
|
|
<description>Capture A0 FIFO DMA Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CA1DE</name>
|
|
<description>Capture A1 FIFO DMA Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAPTDE</name>
|
|
<description>Capture DMA Enable Source Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_0</name>
|
|
<description>Read DMA requests disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_1</name>
|
|
<description>Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_2</name>
|
|
<description>A local sync (VAL1 matches counter) sets the read DMA request.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_3</name>
|
|
<description>A local reload (STS[RF] being set) sets the read DMA request.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAND</name>
|
|
<description>FIFO Watermark AND Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FAND_0</name>
|
|
<description>Selected FIFO watermarks are OR'ed together.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAND_1</name>
|
|
<description>Selected FIFO watermarks are AND'ed together.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VALDE</name>
|
|
<description>Value Registers DMA Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VALDE_0</name>
|
|
<description>DMA write requests disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALDE_1</name>
|
|
<description>DMA write requests for the VALx and FRACVALx registers enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2TCTRL</name>
|
|
<description>Output Trigger Control Register</description>
|
|
<addressOffset>0xEA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUT_TRIG_EN</name>
|
|
<description>Output Trigger Enables</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT_TRIG_EN_0</name>
|
|
<description>PWM_OUT_TRIGx will not set when the counter value matches the VALx value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT_TRIG_EN_1</name>
|
|
<description>PWM_OUT_TRIGx will set when the counter value matches the VALx value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGFRQ</name>
|
|
<description>Trigger frequency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRGFRQ_0</name>
|
|
<description>Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGFRQ_1</name>
|
|
<description>Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWBOT1</name>
|
|
<description>Output Trigger 1 Source Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWBOT1_0</name>
|
|
<description>Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWBOT1_1</name>
|
|
<description>Route the PWMB output to the PWM_OUT_TRIG1 port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWAOT0</name>
|
|
<description>Output Trigger 0 Source Select</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWAOT0_0</name>
|
|
<description>Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWAOT0_1</name>
|
|
<description>Route the PWMA output to the PWM_OUT_TRIG0 port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2DISMAP0</name>
|
|
<description>Fault Disable Mapping Register 0</description>
|
|
<addressOffset>0xEC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIS0A</name>
|
|
<description>PWM_A Fault Disable Mask 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS0B</name>
|
|
<description>PWM_B Fault Disable Mask 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS0X</name>
|
|
<description>PWM_X Fault Disable Mask 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2DISMAP1</name>
|
|
<description>Fault Disable Mapping Register 1</description>
|
|
<addressOffset>0xEE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIS1A</name>
|
|
<description>PWM_A Fault Disable Mask 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS1B</name>
|
|
<description>PWM_B Fault Disable Mask 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS1X</name>
|
|
<description>PWM_X Fault Disable Mask 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2DTCNT0</name>
|
|
<description>Deadtime Count Register 0</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7FF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTCNT0</name>
|
|
<description>DTCNT0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2DTCNT1</name>
|
|
<description>Deadtime Count Register 1</description>
|
|
<addressOffset>0xF2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7FF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTCNT1</name>
|
|
<description>DTCNT1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CAPTCTRLA</name>
|
|
<description>Capture Control A Register</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARMA</name>
|
|
<description>Arm A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARMA_0</name>
|
|
<description>Input capture operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARMA_1</name>
|
|
<description>Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOTA</name>
|
|
<description>One Shot Mode A</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOTA_0</name>
|
|
<description>Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOTA_1</name>
|
|
<description>One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGA0</name>
|
|
<description>Edge A 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGA0_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA0_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA0_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA0_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGA1</name>
|
|
<description>Edge A 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGA1_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA1_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA1_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA1_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INP_SELA</name>
|
|
<description>Input Select A</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INP_SELA_0</name>
|
|
<description>Raw PWM_A input signal selected as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INP_SELA_1</name>
|
|
<description>Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTA_EN</name>
|
|
<description>Edge Counter A Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGCNTA_EN_0</name>
|
|
<description>Edge counter disabled and held in reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGCNTA_EN_1</name>
|
|
<description>Edge counter enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFAWM</name>
|
|
<description>Capture A FIFOs Water Mark</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CA0CNT</name>
|
|
<description>Capture A0 FIFO Word Count</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CA1CNT</name>
|
|
<description>Capture A1 FIFO Word Count</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CAPTCOMPA</name>
|
|
<description>Capture Compare A Register</description>
|
|
<addressOffset>0xF6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGCMPA</name>
|
|
<description>Edge Compare A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTA</name>
|
|
<description>Edge Counter A</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CAPTCTRLB</name>
|
|
<description>Capture Control B Register</description>
|
|
<addressOffset>0xF8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARMB</name>
|
|
<description>Arm B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARMB_0</name>
|
|
<description>Input capture operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARMB_1</name>
|
|
<description>Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOTB</name>
|
|
<description>One Shot Mode B</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOTB_0</name>
|
|
<description>Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOTB_1</name>
|
|
<description>One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGB0</name>
|
|
<description>Edge B 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGB0_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB0_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB0_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB0_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGB1</name>
|
|
<description>Edge B 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGB1_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB1_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB1_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB1_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INP_SELB</name>
|
|
<description>Input Select B</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INP_SELB_0</name>
|
|
<description>Raw PWM_B input signal selected as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INP_SELB_1</name>
|
|
<description>Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTB_EN</name>
|
|
<description>Edge Counter B Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGCNTB_EN_0</name>
|
|
<description>Edge counter disabled and held in reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGCNTB_EN_1</name>
|
|
<description>Edge counter enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFBWM</name>
|
|
<description>Capture B FIFOs Water Mark</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CB0CNT</name>
|
|
<description>Capture B0 FIFO Word Count</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CB1CNT</name>
|
|
<description>Capture B1 FIFO Word Count</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CAPTCOMPB</name>
|
|
<description>Capture Compare B Register</description>
|
|
<addressOffset>0xFA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGCMPB</name>
|
|
<description>Edge Compare B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTB</name>
|
|
<description>Edge Counter B</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CAPTCTRLX</name>
|
|
<description>Capture Control X Register</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARMX</name>
|
|
<description>Arm X</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARMX_0</name>
|
|
<description>Input capture operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARMX_1</name>
|
|
<description>Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOTX</name>
|
|
<description>One Shot Mode Aux</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOTX_0</name>
|
|
<description>Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOTX_1</name>
|
|
<description>One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGX0</name>
|
|
<description>Edge X 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGX0_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX0_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX0_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX0_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGX1</name>
|
|
<description>Edge X 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGX1_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX1_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX1_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX1_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INP_SELX</name>
|
|
<description>Input Select X</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INP_SELX_0</name>
|
|
<description>Raw PWM_X input signal selected as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INP_SELX_1</name>
|
|
<description>Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTX_EN</name>
|
|
<description>Edge Counter X Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGCNTX_EN_0</name>
|
|
<description>Edge counter disabled and held in reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGCNTX_EN_1</name>
|
|
<description>Edge counter enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFXWM</name>
|
|
<description>Capture X FIFOs Water Mark</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CX0CNT</name>
|
|
<description>Capture X0 FIFO Word Count</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CX1CNT</name>
|
|
<description>Capture X1 FIFO Word Count</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CAPTCOMPX</name>
|
|
<description>Capture Compare X Register</description>
|
|
<addressOffset>0xFE</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGCMPX</name>
|
|
<description>Edge Compare X</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTX</name>
|
|
<description>Edge Counter X</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CVAL0</name>
|
|
<description>Capture Value 0 Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL0</name>
|
|
<description>CAPTVAL0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CVAL0CYC</name>
|
|
<description>Capture Value 0 Cycle Register</description>
|
|
<addressOffset>0x102</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL0CYC</name>
|
|
<description>CVAL0CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CVAL1</name>
|
|
<description>Capture Value 1 Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL1</name>
|
|
<description>CAPTVAL1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CVAL1CYC</name>
|
|
<description>Capture Value 1 Cycle Register</description>
|
|
<addressOffset>0x106</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL1CYC</name>
|
|
<description>CVAL1CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CVAL2</name>
|
|
<description>Capture Value 2 Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL2</name>
|
|
<description>CAPTVAL2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CVAL2CYC</name>
|
|
<description>Capture Value 2 Cycle Register</description>
|
|
<addressOffset>0x10A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL2CYC</name>
|
|
<description>CVAL2CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CVAL3</name>
|
|
<description>Capture Value 3 Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL3</name>
|
|
<description>CAPTVAL3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CVAL3CYC</name>
|
|
<description>Capture Value 3 Cycle Register</description>
|
|
<addressOffset>0x10E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL3CYC</name>
|
|
<description>CVAL3CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CVAL4</name>
|
|
<description>Capture Value 4 Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL4</name>
|
|
<description>CAPTVAL4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CVAL4CYC</name>
|
|
<description>Capture Value 4 Cycle Register</description>
|
|
<addressOffset>0x112</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL4CYC</name>
|
|
<description>CVAL4CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CVAL5</name>
|
|
<description>Capture Value 5 Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL5</name>
|
|
<description>CAPTVAL5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2CVAL5CYC</name>
|
|
<description>Capture Value 5 Cycle Register</description>
|
|
<addressOffset>0x116</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL5CYC</name>
|
|
<description>CVAL5CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM2PHASEDLY</name>
|
|
<description>Phase Delay Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PHASEDLY</name>
|
|
<description>Initial Count Register Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CNT</name>
|
|
<description>Counter Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter Register Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3INIT</name>
|
|
<description>Initial Count Register</description>
|
|
<addressOffset>0x122</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initial Count Register Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CTRL2</name>
|
|
<description>Control 2 Register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLK_SEL_0</name>
|
|
<description>The IPBus clock is used as the clock for the local prescaler and counter.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_SEL_1</name>
|
|
<description>EXT_CLK is used as the clock for the local prescaler and counter.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_SEL_2</name>
|
|
<description>Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RELOAD_SEL</name>
|
|
<description>Reload Source Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RELOAD_SEL_0</name>
|
|
<description>The local RELOAD signal is used to reload registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RELOAD_SEL_1</name>
|
|
<description>The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_SEL</name>
|
|
<description>This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_0</name>
|
|
<description>The local force signal, CTRL2[FORCE], from this submodule is used to force updates.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_1</name>
|
|
<description>The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_2</name>
|
|
<description>The local reload signal from this submodule is used to force updates without regard to the state of LDOK.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_3</name>
|
|
<description>The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_4</name>
|
|
<description>The local sync signal from this submodule is used to force updates.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_5</name>
|
|
<description>The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_6</name>
|
|
<description>The external force signal, EXT_FORCE, from outside the PWM module causes updates.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_SEL_7</name>
|
|
<description>The external sync signal, EXT_SYNC, from outside the PWM module causes updates.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCE</name>
|
|
<description>Force Initialization</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRCEN</name>
|
|
<description>FRCEN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRCEN_0</name>
|
|
<description>Initialization from a FORCE_OUT is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRCEN_1</name>
|
|
<description>Initialization from a FORCE_OUT is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT_SEL</name>
|
|
<description>Initialization Control Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_0</name>
|
|
<description>Local sync (PWM_X) causes initialization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_1</name>
|
|
<description>Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_2</name>
|
|
<description>Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INIT_SEL_3</name>
|
|
<description>EXT_SYNC causes initialization.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMX_INIT</name>
|
|
<description>PWM_X Initial Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM45_INIT</name>
|
|
<description>PWM45 Initial Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWM23_INIT</name>
|
|
<description>PWM23 Initial Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INDEP</name>
|
|
<description>Independent or Complementary Pair Operation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INDEP_0</name>
|
|
<description>PWM_A and PWM_B form a complementary PWM pair.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INDEP_1</name>
|
|
<description>PWM_A and PWM_B outputs are independent PWMs.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>WAIT Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x126</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x400</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBLEN</name>
|
|
<description>Double Switching Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBLEN_0</name>
|
|
<description>Double switching disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBLEN_1</name>
|
|
<description>Double switching enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLX</name>
|
|
<description>PWMX Double Switching Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBLX_0</name>
|
|
<description>PWMX double pulse disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBLX_1</name>
|
|
<description>PWMX double pulse enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDMOD</name>
|
|
<description>Load Mode Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LDMOD_0</name>
|
|
<description>Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDMOD_1</name>
|
|
<description>Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPLIT</name>
|
|
<description>Split the DBLPWM signal to PWMA and PWMB</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPLIT_0</name>
|
|
<description>DBLPWM is not split. PWMA and PWMB each have double pulses.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPLIT_1</name>
|
|
<description>DBLPWM is split to PWMA and PWMB.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRSC</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRSC_0</name>
|
|
<description>PWM clock frequency = fclk</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_1</name>
|
|
<description>PWM clock frequency = fclk/2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_2</name>
|
|
<description>PWM clock frequency = fclk/4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_3</name>
|
|
<description>PWM clock frequency = fclk/8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_4</name>
|
|
<description>PWM clock frequency = fclk/16</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_5</name>
|
|
<description>PWM clock frequency = fclk/32</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_6</name>
|
|
<description>PWM clock frequency = fclk/64</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRSC_7</name>
|
|
<description>PWM clock frequency = fclk/128</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMPMODE</name>
|
|
<description>Compare Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMPMODE_0</name>
|
|
<description>The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMPMODE_1</name>
|
|
<description>The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Deadtime</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FULL</name>
|
|
<description>Full Cycle Reload</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FULL_0</name>
|
|
<description>Full-cycle reloads disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULL_1</name>
|
|
<description>Full-cycle reloads enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALF</name>
|
|
<description>Half Cycle Reload</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALF_0</name>
|
|
<description>Half-cycle reloads disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF_1</name>
|
|
<description>Half-cycle reloads enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDFQ</name>
|
|
<description>Load Frequency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LDFQ_0</name>
|
|
<description>Every PWM opportunity</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_1</name>
|
|
<description>Every 2 PWM opportunities</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_2</name>
|
|
<description>Every 3 PWM opportunities</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_3</name>
|
|
<description>Every 4 PWM opportunities</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_4</name>
|
|
<description>Every 5 PWM opportunities</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_5</name>
|
|
<description>Every 6 PWM opportunities</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_6</name>
|
|
<description>Every 7 PWM opportunities</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_7</name>
|
|
<description>Every 8 PWM opportunities</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_8</name>
|
|
<description>Every 9 PWM opportunities</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_9</name>
|
|
<description>Every 10 PWM opportunities</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_10</name>
|
|
<description>Every 11 PWM opportunities</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_11</name>
|
|
<description>Every 12 PWM opportunities</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_12</name>
|
|
<description>Every 13 PWM opportunities</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_13</name>
|
|
<description>Every 14 PWM opportunities</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_14</name>
|
|
<description>Every 15 PWM opportunities</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDFQ_15</name>
|
|
<description>Every 16 PWM opportunities</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3VAL0</name>
|
|
<description>Value Register 0</description>
|
|
<addressOffset>0x12A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL0</name>
|
|
<description>Value Register 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3FRACVAL1</name>
|
|
<description>Fractional Value Register 1</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL1</name>
|
|
<description>Fractional Value 1 Register</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3VAL1</name>
|
|
<description>Value Register 1</description>
|
|
<addressOffset>0x12E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL1</name>
|
|
<description>Value Register 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3FRACVAL2</name>
|
|
<description>Fractional Value Register 2</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL2</name>
|
|
<description>Fractional Value 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3VAL2</name>
|
|
<description>Value Register 2</description>
|
|
<addressOffset>0x132</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL2</name>
|
|
<description>Value Register 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3FRACVAL3</name>
|
|
<description>Fractional Value Register 3</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL3</name>
|
|
<description>Fractional Value 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3VAL3</name>
|
|
<description>Value Register 3</description>
|
|
<addressOffset>0x136</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL3</name>
|
|
<description>Value Register 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3FRACVAL4</name>
|
|
<description>Fractional Value Register 4</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL4</name>
|
|
<description>Fractional Value 4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3VAL4</name>
|
|
<description>Value Register 4</description>
|
|
<addressOffset>0x13A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL4</name>
|
|
<description>Value Register 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3FRACVAL5</name>
|
|
<description>Fractional Value Register 5</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL5</name>
|
|
<description>Fractional Value 5</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3VAL5</name>
|
|
<description>Value Register 5</description>
|
|
<addressOffset>0x13E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL5</name>
|
|
<description>Value Register 5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3FRCTRL</name>
|
|
<description>Fractional Control Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAC1_EN</name>
|
|
<description>Fractional Cycle PWM Period Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC1_EN_0</name>
|
|
<description>Disable fractional cycle length for the PWM period.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC1_EN_1</name>
|
|
<description>Enable fractional cycle length for the PWM period.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC23_EN</name>
|
|
<description>Fractional Cycle Placement Enable for PWM_A</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC23_EN_0</name>
|
|
<description>Disable fractional cycle placement for PWM_A.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC23_EN_1</name>
|
|
<description>Enable fractional cycle placement for PWM_A.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC45_EN</name>
|
|
<description>Fractional Cycle Placement Enable for PWM_B</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC45_EN_0</name>
|
|
<description>Disable fractional cycle placement for PWM_B.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC45_EN_1</name>
|
|
<description>Enable fractional cycle placement for PWM_B.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC_PU</name>
|
|
<description>Fractional Delay Circuit Power Up</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRAC_PU_0</name>
|
|
<description>Turn off fractional delay logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRAC_PU_1</name>
|
|
<description>Power up fractional delay logic.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEST</name>
|
|
<description>Test Status Bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3OCTRL</name>
|
|
<description>Output Control Register</description>
|
|
<addressOffset>0x142</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMXFS</name>
|
|
<description>PWM_X Fault State</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_0</name>
|
|
<description>Output is forced to logic 0 state prior to consideration of output polarity control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_1</name>
|
|
<description>Output is forced to logic 1 state prior to consideration of output polarity control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_2</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMXFS_3</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMBFS</name>
|
|
<description>PWM_B Fault State</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_0</name>
|
|
<description>Output is forced to logic 0 state prior to consideration of output polarity control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_1</name>
|
|
<description>Output is forced to logic 1 state prior to consideration of output polarity control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_2</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMBFS_3</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMAFS</name>
|
|
<description>PWM_A Fault State</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_0</name>
|
|
<description>Output is forced to logic 0 state prior to consideration of output polarity control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_1</name>
|
|
<description>Output is forced to logic 1 state prior to consideration of output polarity control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_2</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMAFS_3</name>
|
|
<description>Output is tristated.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLX</name>
|
|
<description>PWM_X Output Polarity</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POLX_0</name>
|
|
<description>PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POLX_1</name>
|
|
<description>PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLB</name>
|
|
<description>PWM_B Output Polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POLB_0</name>
|
|
<description>PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POLB_1</name>
|
|
<description>PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLA</name>
|
|
<description>PWM_A Output Polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>POLA_0</name>
|
|
<description>PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POLA_1</name>
|
|
<description>PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMX_IN</name>
|
|
<description>PWM_X Input</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWMB_IN</name>
|
|
<description>PWM_B Input</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PWMA_IN</name>
|
|
<description>PWM_A Input</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3STS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPF</name>
|
|
<description>Compare Flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPF_0</name>
|
|
<description>No compare event has occurred for a particular VALx value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPF_1</name>
|
|
<description>A compare event has occurred for a particular VALx value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFX0</name>
|
|
<description>Capture Flag X0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFX1</name>
|
|
<description>Capture Flag X1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFB0</name>
|
|
<description>Capture Flag B0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFB1</name>
|
|
<description>Capture Flag B1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFA0</name>
|
|
<description>Capture Flag A0</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>CFA1</name>
|
|
<description>Capture Flag A1</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>RF</name>
|
|
<description>Reload Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RF_0</name>
|
|
<description>No new reload cycle since last STS[RF] clearing</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RF_1</name>
|
|
<description>New reload cycle since last STS[RF] clearing</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REF</name>
|
|
<description>Reload Error Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REF_0</name>
|
|
<description>No reload error occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REF_1</name>
|
|
<description>Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUF</name>
|
|
<description>Registers Updated Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUF_0</name>
|
|
<description>No register update has occurred since last reload.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUF_1</name>
|
|
<description>At least one of the double buffered registers has been updated since the last reload.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3INTEN</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x146</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMPIE</name>
|
|
<description>Compare Interrupt Enables</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPIE_0</name>
|
|
<description>The corresponding STS[CMPF] bit will not cause an interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPIE_1</name>
|
|
<description>The corresponding STS[CMPF] bit will cause an interrupt request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CX0IE</name>
|
|
<description>Capture X 0 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CX0IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFX0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CX0IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFX0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CX1IE</name>
|
|
<description>Capture X 1 Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CX1IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFX1].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CX1IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFX1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CB0IE</name>
|
|
<description>Capture B 0 Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CB0IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFB0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CB0IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFB0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CB1IE</name>
|
|
<description>Capture B 1 Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CB1IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFB1].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CB1IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFB1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CA0IE</name>
|
|
<description>Capture A 0 Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CA0IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFA0].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CA0IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFA0].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CA1IE</name>
|
|
<description>Capture A 1 Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CA1IE_0</name>
|
|
<description>Interrupt request disabled for STS[CFA1].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CA1IE_1</name>
|
|
<description>Interrupt request enabled for STS[CFA1].</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Reload Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RIE_0</name>
|
|
<description>STS[RF] CPU interrupt requests disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RIE_1</name>
|
|
<description>STS[RF] CPU interrupt requests enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REIE</name>
|
|
<description>Reload Error Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REIE_0</name>
|
|
<description>STS[REF] CPU interrupt requests disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REIE_1</name>
|
|
<description>STS[REF] CPU interrupt requests enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3DMAEN</name>
|
|
<description>DMA Enable Register</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CX0DE</name>
|
|
<description>Capture X0 FIFO DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CX1DE</name>
|
|
<description>Capture X1 FIFO DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CB0DE</name>
|
|
<description>Capture B0 FIFO DMA Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CB1DE</name>
|
|
<description>Capture B1 FIFO DMA Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CA0DE</name>
|
|
<description>Capture A0 FIFO DMA Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CA1DE</name>
|
|
<description>Capture A1 FIFO DMA Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAPTDE</name>
|
|
<description>Capture DMA Enable Source Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_0</name>
|
|
<description>Read DMA requests disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_1</name>
|
|
<description>Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_2</name>
|
|
<description>A local sync (VAL1 matches counter) sets the read DMA request.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAPTDE_3</name>
|
|
<description>A local reload (STS[RF] being set) sets the read DMA request.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAND</name>
|
|
<description>FIFO Watermark AND Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FAND_0</name>
|
|
<description>Selected FIFO watermarks are OR'ed together.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAND_1</name>
|
|
<description>Selected FIFO watermarks are AND'ed together.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VALDE</name>
|
|
<description>Value Registers DMA Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VALDE_0</name>
|
|
<description>DMA write requests disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALDE_1</name>
|
|
<description>DMA write requests for the VALx and FRACVALx registers enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3TCTRL</name>
|
|
<description>Output Trigger Control Register</description>
|
|
<addressOffset>0x14A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUT_TRIG_EN</name>
|
|
<description>Output Trigger Enables</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUT_TRIG_EN_0</name>
|
|
<description>PWM_OUT_TRIGx will not set when the counter value matches the VALx value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUT_TRIG_EN_1</name>
|
|
<description>PWM_OUT_TRIGx will set when the counter value matches the VALx value.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGFRQ</name>
|
|
<description>Trigger frequency</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRGFRQ_0</name>
|
|
<description>Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRGFRQ_1</name>
|
|
<description>Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWBOT1</name>
|
|
<description>Output Trigger 1 Source Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWBOT1_0</name>
|
|
<description>Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWBOT1_1</name>
|
|
<description>Route the PWMB output to the PWM_OUT_TRIG1 port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWAOT0</name>
|
|
<description>Output Trigger 0 Source Select</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWAOT0_0</name>
|
|
<description>Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWAOT0_1</name>
|
|
<description>Route the PWMA output to the PWM_OUT_TRIG0 port.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3DISMAP0</name>
|
|
<description>Fault Disable Mapping Register 0</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIS0A</name>
|
|
<description>PWM_A Fault Disable Mask 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS0B</name>
|
|
<description>PWM_B Fault Disable Mask 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS0X</name>
|
|
<description>PWM_X Fault Disable Mask 0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3DISMAP1</name>
|
|
<description>Fault Disable Mapping Register 1</description>
|
|
<addressOffset>0x14E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIS1A</name>
|
|
<description>PWM_A Fault Disable Mask 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS1B</name>
|
|
<description>PWM_B Fault Disable Mask 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIS1X</name>
|
|
<description>PWM_X Fault Disable Mask 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3DTCNT0</name>
|
|
<description>Deadtime Count Register 0</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7FF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTCNT0</name>
|
|
<description>DTCNT0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3DTCNT1</name>
|
|
<description>Deadtime Count Register 1</description>
|
|
<addressOffset>0x152</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7FF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTCNT1</name>
|
|
<description>DTCNT1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CAPTCTRLA</name>
|
|
<description>Capture Control A Register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARMA</name>
|
|
<description>Arm A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARMA_0</name>
|
|
<description>Input capture operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARMA_1</name>
|
|
<description>Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOTA</name>
|
|
<description>One Shot Mode A</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOTA_0</name>
|
|
<description>Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOTA_1</name>
|
|
<description>One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGA0</name>
|
|
<description>Edge A 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGA0_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA0_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA0_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA0_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGA1</name>
|
|
<description>Edge A 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGA1_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA1_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA1_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGA1_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INP_SELA</name>
|
|
<description>Input Select A</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INP_SELA_0</name>
|
|
<description>Raw PWM_A input signal selected as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INP_SELA_1</name>
|
|
<description>Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTA_EN</name>
|
|
<description>Edge Counter A Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGCNTA_EN_0</name>
|
|
<description>Edge counter disabled and held in reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGCNTA_EN_1</name>
|
|
<description>Edge counter enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFAWM</name>
|
|
<description>Capture A FIFOs Water Mark</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CA0CNT</name>
|
|
<description>Capture A0 FIFO Word Count</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CA1CNT</name>
|
|
<description>Capture A1 FIFO Word Count</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CAPTCOMPA</name>
|
|
<description>Capture Compare A Register</description>
|
|
<addressOffset>0x156</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGCMPA</name>
|
|
<description>Edge Compare A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTA</name>
|
|
<description>Edge Counter A</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CAPTCTRLB</name>
|
|
<description>Capture Control B Register</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARMB</name>
|
|
<description>Arm B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARMB_0</name>
|
|
<description>Input capture operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARMB_1</name>
|
|
<description>Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOTB</name>
|
|
<description>One Shot Mode B</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOTB_0</name>
|
|
<description>Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOTB_1</name>
|
|
<description>One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGB0</name>
|
|
<description>Edge B 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGB0_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB0_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB0_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB0_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGB1</name>
|
|
<description>Edge B 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGB1_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB1_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB1_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGB1_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INP_SELB</name>
|
|
<description>Input Select B</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INP_SELB_0</name>
|
|
<description>Raw PWM_B input signal selected as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INP_SELB_1</name>
|
|
<description>Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTB_EN</name>
|
|
<description>Edge Counter B Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGCNTB_EN_0</name>
|
|
<description>Edge counter disabled and held in reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGCNTB_EN_1</name>
|
|
<description>Edge counter enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFBWM</name>
|
|
<description>Capture B FIFOs Water Mark</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CB0CNT</name>
|
|
<description>Capture B0 FIFO Word Count</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CB1CNT</name>
|
|
<description>Capture B1 FIFO Word Count</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CAPTCOMPB</name>
|
|
<description>Capture Compare B Register</description>
|
|
<addressOffset>0x15A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGCMPB</name>
|
|
<description>Edge Compare B</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTB</name>
|
|
<description>Edge Counter B</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CAPTCTRLX</name>
|
|
<description>Capture Control X Register</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARMX</name>
|
|
<description>Arm X</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ARMX_0</name>
|
|
<description>Input capture operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARMX_1</name>
|
|
<description>Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONESHOTX</name>
|
|
<description>One Shot Mode Aux</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONESHOTX_0</name>
|
|
<description>Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONESHOTX_1</name>
|
|
<description>One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGX0</name>
|
|
<description>Edge X 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGX0_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX0_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX0_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX0_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGX1</name>
|
|
<description>Edge X 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGX1_0</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX1_1</name>
|
|
<description>Capture falling edges</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX1_2</name>
|
|
<description>Capture rising edges</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGX1_3</name>
|
|
<description>Capture any edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INP_SELX</name>
|
|
<description>Input Select X</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INP_SELX_0</name>
|
|
<description>Raw PWM_X input signal selected as source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INP_SELX_1</name>
|
|
<description>Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTX_EN</name>
|
|
<description>Edge Counter X Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EDGCNTX_EN_0</name>
|
|
<description>Edge counter disabled and held in reset</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGCNTX_EN_1</name>
|
|
<description>Edge counter enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFXWM</name>
|
|
<description>Capture X FIFOs Water Mark</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CX0CNT</name>
|
|
<description>Capture X0 FIFO Word Count</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CX1CNT</name>
|
|
<description>Capture X1 FIFO Word Count</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CAPTCOMPX</name>
|
|
<description>Capture Compare X Register</description>
|
|
<addressOffset>0x15E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDGCMPX</name>
|
|
<description>Edge Compare X</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EDGCNTX</name>
|
|
<description>Edge Counter X</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CVAL0</name>
|
|
<description>Capture Value 0 Register</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL0</name>
|
|
<description>CAPTVAL0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CVAL0CYC</name>
|
|
<description>Capture Value 0 Cycle Register</description>
|
|
<addressOffset>0x162</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL0CYC</name>
|
|
<description>CVAL0CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CVAL1</name>
|
|
<description>Capture Value 1 Register</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL1</name>
|
|
<description>CAPTVAL1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CVAL1CYC</name>
|
|
<description>Capture Value 1 Cycle Register</description>
|
|
<addressOffset>0x166</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL1CYC</name>
|
|
<description>CVAL1CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CVAL2</name>
|
|
<description>Capture Value 2 Register</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL2</name>
|
|
<description>CAPTVAL2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CVAL2CYC</name>
|
|
<description>Capture Value 2 Cycle Register</description>
|
|
<addressOffset>0x16A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL2CYC</name>
|
|
<description>CVAL2CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CVAL3</name>
|
|
<description>Capture Value 3 Register</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL3</name>
|
|
<description>CAPTVAL3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CVAL3CYC</name>
|
|
<description>Capture Value 3 Cycle Register</description>
|
|
<addressOffset>0x16E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL3CYC</name>
|
|
<description>CVAL3CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CVAL4</name>
|
|
<description>Capture Value 4 Register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL4</name>
|
|
<description>CAPTVAL4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CVAL4CYC</name>
|
|
<description>Capture Value 4 Cycle Register</description>
|
|
<addressOffset>0x172</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL4CYC</name>
|
|
<description>CVAL4CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CVAL5</name>
|
|
<description>Capture Value 5 Register</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPTVAL5</name>
|
|
<description>CAPTVAL5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3CVAL5CYC</name>
|
|
<description>Capture Value 5 Cycle Register</description>
|
|
<addressOffset>0x176</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL5CYC</name>
|
|
<description>CVAL5CYC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SM3PHASEDLY</name>
|
|
<description>Phase Delay Register</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PHASEDLY</name>
|
|
<description>Initial Count Register Bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTEN</name>
|
|
<description>Output Enable Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMX_EN</name>
|
|
<description>PWM_X Output Enables</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMX_EN_0</name>
|
|
<description>PWM_X output disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMX_EN_1</name>
|
|
<description>PWM_X output enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMB_EN</name>
|
|
<description>PWM_B Output Enables</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMB_EN_0</name>
|
|
<description>PWM_B output disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMB_EN_1</name>
|
|
<description>PWM_B output enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMA_EN</name>
|
|
<description>PWM_A Output Enables</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWMA_EN_0</name>
|
|
<description>PWM_A output disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWMA_EN_1</name>
|
|
<description>PWM_A output enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK</name>
|
|
<description>Mask Register</description>
|
|
<addressOffset>0x182</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASKX</name>
|
|
<description>PWM_X Masks</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASKX_0</name>
|
|
<description>PWM_X output normal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASKX_1</name>
|
|
<description>PWM_X output masked.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASKB</name>
|
|
<description>PWM_B Masks</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASKB_0</name>
|
|
<description>PWM_B output normal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASKB_1</name>
|
|
<description>PWM_B output masked.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASKA</name>
|
|
<description>PWM_A Masks</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MASKA_0</name>
|
|
<description>PWM_A output normal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASKA_1</name>
|
|
<description>PWM_A output masked.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UPDATE_MASK</name>
|
|
<description>Update Mask Bits Immediately</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UPDATE_MASK_0</name>
|
|
<description>Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE_MASK_1</name>
|
|
<description>Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWCOUT</name>
|
|
<description>Software Controlled Output Register</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SM0OUT45</name>
|
|
<description>Submodule 0 Software Controlled Output 45</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM0OUT45_0</name>
|
|
<description>A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM0OUT45_1</name>
|
|
<description>A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM0OUT23</name>
|
|
<description>Submodule 0 Software Controlled Output 23</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM0OUT23_0</name>
|
|
<description>A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM0OUT23_1</name>
|
|
<description>A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM1OUT45</name>
|
|
<description>Submodule 1 Software Controlled Output 45</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM1OUT45_0</name>
|
|
<description>A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM1OUT45_1</name>
|
|
<description>A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM1OUT23</name>
|
|
<description>Submodule 1 Software Controlled Output 23</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM1OUT23_0</name>
|
|
<description>A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM1OUT23_1</name>
|
|
<description>A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM2OUT45</name>
|
|
<description>Submodule 2 Software Controlled Output 45</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM2OUT45_0</name>
|
|
<description>A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM2OUT45_1</name>
|
|
<description>A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM2OUT23</name>
|
|
<description>Submodule 2 Software Controlled Output 23</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM2OUT23_0</name>
|
|
<description>A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM2OUT23_1</name>
|
|
<description>A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM3OUT45</name>
|
|
<description>Submodule 3 Software Controlled Output 45</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM3OUT45_0</name>
|
|
<description>A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM3OUT45_1</name>
|
|
<description>A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM3OUT23</name>
|
|
<description>Submodule 3 Software Controlled Output 23</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM3OUT23_0</name>
|
|
<description>A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM3OUT23_1</name>
|
|
<description>A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTSRCSEL</name>
|
|
<description>PWM Source Select Register</description>
|
|
<addressOffset>0x186</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SM0SEL45</name>
|
|
<description>Submodule 0 PWM45 Control Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM0SEL45_0</name>
|
|
<description>Generated SM0PWM45 signal is used by the deadtime logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM0SEL45_1</name>
|
|
<description>Inverted generated SM0PWM45 signal is used by the deadtime logic.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM0SEL45_2</name>
|
|
<description>SWCOUT[SM0OUT45] is used by the deadtime logic.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM0SEL45_3</name>
|
|
<description>PWM0_EXTB signal is used by the deadtime logic.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM0SEL23</name>
|
|
<description>Submodule 0 PWM23 Control Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM0SEL23_0</name>
|
|
<description>Generated SM0PWM23 signal is used by the deadtime logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM0SEL23_1</name>
|
|
<description>Inverted generated SM0PWM23 signal is used by the deadtime logic.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM0SEL23_2</name>
|
|
<description>SWCOUT[SM0OUT23] is used by the deadtime logic.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM0SEL23_3</name>
|
|
<description>PWM0_EXTA signal is used by the deadtime logic.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM1SEL45</name>
|
|
<description>Submodule 1 PWM45 Control Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM1SEL45_0</name>
|
|
<description>Generated SM1PWM45 signal is used by the deadtime logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM1SEL45_1</name>
|
|
<description>Inverted generated SM1PWM45 signal is used by the deadtime logic.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM1SEL45_2</name>
|
|
<description>SWCOUT[SM1OUT45] is used by the deadtime logic.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM1SEL45_3</name>
|
|
<description>PWM1_EXTB signal is used by the deadtime logic.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM1SEL23</name>
|
|
<description>Submodule 1 PWM23 Control Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM1SEL23_0</name>
|
|
<description>Generated SM1PWM23 signal is used by the deadtime logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM1SEL23_1</name>
|
|
<description>Inverted generated SM1PWM23 signal is used by the deadtime logic.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM1SEL23_2</name>
|
|
<description>SWCOUT[SM1OUT23] is used by the deadtime logic.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM1SEL23_3</name>
|
|
<description>PWM1_EXTA signal is used by the deadtime logic.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM2SEL45</name>
|
|
<description>Submodule 2 PWM45 Control Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM2SEL45_0</name>
|
|
<description>Generated SM2PWM45 signal is used by the deadtime logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM2SEL45_1</name>
|
|
<description>Inverted generated SM2PWM45 signal is used by the deadtime logic.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM2SEL45_2</name>
|
|
<description>SWCOUT[SM2OUT45] is used by the deadtime logic.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM2SEL45_3</name>
|
|
<description>PWM2_EXTB signal is used by the deadtime logic.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM2SEL23</name>
|
|
<description>Submodule 2 PWM23 Control Select</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM2SEL23_0</name>
|
|
<description>Generated SM2PWM23 signal is used by the deadtime logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM2SEL23_1</name>
|
|
<description>Inverted generated SM2PWM23 signal is used by the deadtime logic.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM2SEL23_2</name>
|
|
<description>SWCOUT[SM2OUT23] is used by the deadtime logic.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM2SEL23_3</name>
|
|
<description>PWM2_EXTA signal is used by the deadtime logic.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM3SEL45</name>
|
|
<description>Submodule 3 PWM45 Control Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM3SEL45_0</name>
|
|
<description>Generated SM3PWM45 signal is used by the deadtime logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM3SEL45_1</name>
|
|
<description>Inverted generated SM3PWM45 signal is used by the deadtime logic.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM3SEL45_2</name>
|
|
<description>SWCOUT[SM3OUT45] is used by the deadtime logic.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM3SEL45_3</name>
|
|
<description>PWM3_EXTB signal is used by the deadtime logic.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SM3SEL23</name>
|
|
<description>Submodule 3 PWM23 Control Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SM3SEL23_0</name>
|
|
<description>Generated SM3PWM23 signal is used by the deadtime logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM3SEL23_1</name>
|
|
<description>Inverted generated SM3PWM23 signal is used by the deadtime logic.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM3SEL23_2</name>
|
|
<description>SWCOUT[SM3OUT23] is used by the deadtime logic.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SM3SEL23_3</name>
|
|
<description>PWM3_EXTA signal is used by the deadtime logic.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCTRL</name>
|
|
<description>Master Control Register</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LDOK</name>
|
|
<description>Load Okay</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LDOK_0</name>
|
|
<description>Do not load new values.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LDOK_1</name>
|
|
<description>Load prescaler, modulus, and PWM values of the corresponding submodule.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLDOK</name>
|
|
<description>Clear Load Okay</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RUN_0</name>
|
|
<description>PWM generator is disabled in the corresponding submodule.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN_1</name>
|
|
<description>PWM generator is enabled in the corresponding submodule.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IPOL</name>
|
|
<description>Current Polarity</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IPOL_0</name>
|
|
<description>PWM23 is used to generate complementary PWM pair in the corresponding submodule.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IPOL_1</name>
|
|
<description>PWM45 is used to generate complementary PWM pair in the corresponding submodule.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCTRL2</name>
|
|
<description>Master Control 2 Register</description>
|
|
<addressOffset>0x18A</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MONPLL</name>
|
|
<description>Monitor PLL State</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MONPLL_0</name>
|
|
<description>Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MONPLL_1</name>
|
|
<description>Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MONPLL_2</name>
|
|
<description>Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MONPLL_3</name>
|
|
<description>Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCTRL0</name>
|
|
<description>Fault Control Register</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIE</name>
|
|
<description>Fault Interrupt Enables</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FIE_0</name>
|
|
<description>FAULTx CPU interrupt requests disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FIE_1</name>
|
|
<description>FAULTx CPU interrupt requests enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSAFE</name>
|
|
<description>Fault Safety Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FSAFE_0</name>
|
|
<description>Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is setm then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FSAFE_1</name>
|
|
<description>Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAUTO</name>
|
|
<description>Automatic Fault Clearing</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FAUTO_0</name>
|
|
<description>Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the states of FSTS[FHALF] and FSTS[FFULL]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL[FSAFE].</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAUTO_1</name>
|
|
<description>Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLVL</name>
|
|
<description>Fault Level</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FLVL_0</name>
|
|
<description>A logic 0 on the fault input indicates a fault condition.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FLVL_1</name>
|
|
<description>A logic 1 on the fault input indicates a fault condition.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSTS0</name>
|
|
<description>Fault Status Register</description>
|
|
<addressOffset>0x18E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FFLAG</name>
|
|
<description>Fault Flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FFLAG_0</name>
|
|
<description>No fault on the FAULTx pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FFLAG_1</name>
|
|
<description>Fault on the FAULTx pin.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFULL</name>
|
|
<description>Full Cycle</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FFULL_0</name>
|
|
<description>PWM outputs are not re-enabled at the start of a full cycle</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FFULL_1</name>
|
|
<description>PWM outputs are re-enabled at the start of a full cycle</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFPIN</name>
|
|
<description>Filtered Fault Pins</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FHALF</name>
|
|
<description>Half Cycle Fault Recovery</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FHALF_0</name>
|
|
<description>PWM outputs are not re-enabled at the start of a half cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FHALF_1</name>
|
|
<description>PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FFILT0</name>
|
|
<description>Fault Filter Register</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT_PER</name>
|
|
<description>Fault Filter Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILT_CNT</name>
|
|
<description>Fault Filter Count</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GSTR</name>
|
|
<description>Fault Glitch Stretch Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GSTR_0</name>
|
|
<description>Fault input glitch stretching is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GSTR_1</name>
|
|
<description>Input fault signals will be stretched to at least 2 IPBus clock cycles.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTST0</name>
|
|
<description>Fault Test Register</description>
|
|
<addressOffset>0x192</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTEST</name>
|
|
<description>Fault Test</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FTEST_0</name>
|
|
<description>No fault</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FTEST_1</name>
|
|
<description>Cause a simulated fault</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCTRL20</name>
|
|
<description>Fault Control 2 Register</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NOCOMB</name>
|
|
<description>No Combinational Path From Fault Input To PWM Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOCOMB_0</name>
|
|
<description>There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOCOMB_1</name>
|
|
<description>The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPDIF</name>
|
|
<description>SPDIF</description>
|
|
<groupName>SPDIF</groupName>
|
|
<prependToName>SPDIF_</prependToName>
|
|
<baseAddress>0x401DC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x54</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPDIF</name>
|
|
<value>60</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>SPDIF Configuration Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x400</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USrc_Sel</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USrc_Sel_0</name>
|
|
<description>No embedded U channel</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USrc_Sel_1</name>
|
|
<description>U channel from SPDIF receive block (CD mode)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USrc_Sel_3</name>
|
|
<description>U channel from on chip transmitter</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TxSel</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TxSel_0</name>
|
|
<description>Off and output 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxSel_1</name>
|
|
<description>Feed-through SPDIFIN</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxSel_5</name>
|
|
<description>Tx Normal operation</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ValCtrl</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ValCtrl_0</name>
|
|
<description>Outgoing Validity always set</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ValCtrl_1</name>
|
|
<description>Outgoing Validity always clear</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMA_TX_En</name>
|
|
<description>DMA Transmit Request Enable (Tx FIFO empty)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMA_Rx_En</name>
|
|
<description>DMA Receive Request Enable (RX FIFO full)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TxFIFO_Ctrl</name>
|
|
<description>no description available</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TxFIFO_Ctrl_0</name>
|
|
<description>Send out digital zero on SPDIF Tx</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxFIFO_Ctrl_1</name>
|
|
<description>Tx Normal operation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxFIFO_Ctrl_2</name>
|
|
<description>Reset to 1 sample remaining</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>soft_reset</name>
|
|
<description>When write 1 to this bit, it will cause SPDIF software reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOW_POWER</name>
|
|
<description>When write 1 to this bit, it will cause SPDIF enter low-power mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TxFIFOEmpty_Sel</name>
|
|
<description>no description available</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TxFIFOEmpty_Sel_0</name>
|
|
<description>Empty interrupt if 0 sample in Tx left and right FIFOs</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxFIFOEmpty_Sel_1</name>
|
|
<description>Empty interrupt if at most 4 sample in Tx left and right FIFOs</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxFIFOEmpty_Sel_2</name>
|
|
<description>Empty interrupt if at most 8 sample in Tx left and right FIFOs</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxFIFOEmpty_Sel_3</name>
|
|
<description>Empty interrupt if at most 12 sample in Tx left and right FIFOs</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TxAutoSync</name>
|
|
<description>no description available</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TxAutoSync_0</name>
|
|
<description>Tx FIFO auto sync off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxAutoSync_1</name>
|
|
<description>Tx FIFO auto sync on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RxAutoSync</name>
|
|
<description>no description available</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RxAutoSync_0</name>
|
|
<description>Rx FIFO auto sync off</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RxAutoSync_1</name>
|
|
<description>RxFIFO auto sync on</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RxFIFOFull_Sel</name>
|
|
<description>no description available</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RxFIFOFull_Sel_0</name>
|
|
<description>Full interrupt if at least 1 sample in Rx left and right FIFOs</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RxFIFOFull_Sel_1</name>
|
|
<description>Full interrupt if at least 4 sample in Rx left and right FIFOs</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RxFIFOFull_Sel_2</name>
|
|
<description>Full interrupt if at least 8 sample in Rx left and right FIFOs</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RxFIFOFull_Sel_3</name>
|
|
<description>Full interrupt if at least 16 sample in Rx left and right FIFO</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RxFIFO_Rst</name>
|
|
<description>no description available</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RxFIFO_Rst_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RxFIFO_Rst_1</name>
|
|
<description>Reset register to 1 sample remaining</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RxFIFO_Off_On</name>
|
|
<description>no description available</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RxFIFO_Off_On_0</name>
|
|
<description>SPDIF Rx FIFO is on</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RxFIFO_Off_On_1</name>
|
|
<description>SPDIF Rx FIFO is off. Does not accept data from interface</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RxFIFO_Ctrl</name>
|
|
<description>no description available</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RxFIFO_Ctrl_0</name>
|
|
<description>Normal operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RxFIFO_Ctrl_1</name>
|
|
<description>Always read zero from Rx data register</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCD</name>
|
|
<description>CDText Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USyncMode</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USyncMode_0</name>
|
|
<description>Non-CD data</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USyncMode_1</name>
|
|
<description>CD user channel subcode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRPC</name>
|
|
<description>PhaseConfig Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GainSel</name>
|
|
<description>Gain selection:</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GainSel_0</name>
|
|
<description>24*(2**10)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GainSel_1</name>
|
|
<description>16*(2**10)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GainSel_2</name>
|
|
<description>12*(2**10)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GainSel_3</name>
|
|
<description>8*(2**10)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GainSel_4</name>
|
|
<description>6*(2**10)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GainSel_5</name>
|
|
<description>4*(2**10)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GainSel_6</name>
|
|
<description>3*(2**10)</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK bit to show that the internal DPLL is locked, read only</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ClkSrc_Sel</name>
|
|
<description>Clock source selection, all other settings not shown are reserved:</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ClkSrc_Sel_0</name>
|
|
<description>if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ClkSrc_Sel_1</name>
|
|
<description>if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ClkSrc_Sel_3</name>
|
|
<description>if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ClkSrc_Sel_5</name>
|
|
<description>REF_CLK_32K (XTALOSC)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ClkSrc_Sel_6</name>
|
|
<description>tx_clk (SPDIF0_CLK_ROOT)</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ClkSrc_Sel_8</name>
|
|
<description>SPDIF_EXT_CLK</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIE</name>
|
|
<description>InterruptEn Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RxFIFOFul</name>
|
|
<description>SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TxEm</name>
|
|
<description>SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LockLoss</name>
|
|
<description>SPDIF receiver loss of lock</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RxFIFOResyn</name>
|
|
<description>Rx FIFO resync</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RxFIFOUnOv</name>
|
|
<description>Rx FIFO underrun/overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UQErr</name>
|
|
<description>U/Q Channel framing error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UQSync</name>
|
|
<description>U/Q Channel sync found</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>QRxOv</name>
|
|
<description>Q Channel receive register overrun</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>QRxFul</name>
|
|
<description>Q Channel receive register full, can't be cleared with reg</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URxOv</name>
|
|
<description>U Channel receive register overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URxFul</name>
|
|
<description>U Channel receive register full, can't be cleared with reg</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BitErr</name>
|
|
<description>SPDIF receiver found parity bit error</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SymErr</name>
|
|
<description>SPDIF receiver found illegal symbol</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ValNoGood</name>
|
|
<description>SPDIF validity flag no good</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNew</name>
|
|
<description>SPDIF receive change in value of control channel</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TxResyn</name>
|
|
<description>SPDIF Tx FIFO resync</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TxUnOv</name>
|
|
<description>SPDIF Tx FIFO under/overrun</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>Lock</name>
|
|
<description>SPDIF receiver's DPLL is locked</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIC</name>
|
|
<description>InterruptClear Register</description>
|
|
<alternateGroup>SIC_SIS</alternateGroup>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LockLoss</name>
|
|
<description>SPDIF receiver loss of lock</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RxFIFOResyn</name>
|
|
<description>Rx FIFO resync</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RxFIFOUnOv</name>
|
|
<description>Rx FIFO underrun/overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UQErr</name>
|
|
<description>U/Q Channel framing error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UQSync</name>
|
|
<description>U/Q Channel sync found</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>QRxOv</name>
|
|
<description>Q Channel receive register overrun</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>URxOv</name>
|
|
<description>U Channel receive register overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BitErr</name>
|
|
<description>SPDIF receiver found parity bit error</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SymErr</name>
|
|
<description>SPDIF receiver found illegal symbol</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ValNoGood</name>
|
|
<description>SPDIF validity flag no good</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNew</name>
|
|
<description>SPDIF receive change in value of control channel</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TxResyn</name>
|
|
<description>SPDIF Tx FIFO resync</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TxUnOv</name>
|
|
<description>SPDIF Tx FIFO under/overrun</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>Lock</name>
|
|
<description>SPDIF receiver's DPLL is locked</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIS</name>
|
|
<description>InterruptStat Register</description>
|
|
<alternateGroup>SIC_SIS</alternateGroup>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RxFIFOFul</name>
|
|
<description>SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TxEm</name>
|
|
<description>SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LockLoss</name>
|
|
<description>SPDIF receiver loss of lock</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RxFIFOResyn</name>
|
|
<description>Rx FIFO resync</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RxFIFOUnOv</name>
|
|
<description>Rx FIFO underrun/overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UQErr</name>
|
|
<description>U/Q Channel framing error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UQSync</name>
|
|
<description>U/Q Channel sync found</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>QRxOv</name>
|
|
<description>Q Channel receive register overrun</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>QRxFul</name>
|
|
<description>Q Channel receive register full, can't be cleared with reg</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>URxOv</name>
|
|
<description>U Channel receive register overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>URxFul</name>
|
|
<description>U Channel receive register full, can't be cleared with reg</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BitErr</name>
|
|
<description>SPDIF receiver found parity bit error</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SymErr</name>
|
|
<description>SPDIF receiver found illegal symbol</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ValNoGood</name>
|
|
<description>SPDIF validity flag no good</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNew</name>
|
|
<description>SPDIF receive change in value of control channel</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TxResyn</name>
|
|
<description>SPDIF Tx FIFO resync</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TxUnOv</name>
|
|
<description>SPDIF Tx FIFO under/overrun</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>Lock</name>
|
|
<description>SPDIF receiver's DPLL is locked</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRL</name>
|
|
<description>SPDIFRxLeft Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RxDataLeft</name>
|
|
<description>Processor receive SPDIF data left</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRR</name>
|
|
<description>SPDIFRxRight Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RxDataRight</name>
|
|
<description>Processor receive SPDIF data right</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCSH</name>
|
|
<description>SPDIFRxCChannel_h Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RxCChannel_h</name>
|
|
<description>SPDIF receive C channel register, contains first 24 bits of C channel without interpretation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCSL</name>
|
|
<description>SPDIFRxCChannel_l Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RxCChannel_l</name>
|
|
<description>SPDIF receive C channel register, contains next 24 bits of C channel without interpretation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRU</name>
|
|
<description>UchannelRx Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RxUChannel</name>
|
|
<description>SPDIF receive U channel register, contains next 3 U channel bytes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRQ</name>
|
|
<description>QchannelRx Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RxQChannel</name>
|
|
<description>SPDIF receive Q channel register, contains next 3 Q channel bytes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STL</name>
|
|
<description>SPDIFTxLeft Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TxDataLeft</name>
|
|
<description>SPDIF transmit left channel data. It is write-only, and always returns zeros when read</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STR</name>
|
|
<description>SPDIFTxRight Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TxDataRight</name>
|
|
<description>SPDIF transmit right channel data. It is write-only, and always returns zeros when read</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STCSCH</name>
|
|
<description>SPDIFTxCChannelCons_h Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TxCChannelCons_h</name>
|
|
<description>SPDIF transmit Cons</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STCSCL</name>
|
|
<description>SPDIFTxCChannelCons_l Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TxCChannelCons_l</name>
|
|
<description>SPDIF transmit Cons</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRFM</name>
|
|
<description>FreqMeas Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FreqMeas</name>
|
|
<description>Frequency measurement data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STC</name>
|
|
<description>SPDIFTxClk Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20F00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TxClk_DF</name>
|
|
<description>Divider factor (1-128)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TxClk_DF_0</name>
|
|
<description>divider factor is 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxClk_DF_1</name>
|
|
<description>divider factor is 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxClk_DF_127</name>
|
|
<description>divider factor is 128</description>
|
|
<value>0x7F</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>tx_all_clk_en</name>
|
|
<description>Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>tx_all_clk_en_0</name>
|
|
<description>disable transfer clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>tx_all_clk_en_1</name>
|
|
<description>enable transfer clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TxClk_Source</name>
|
|
<description>no description available</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TxClk_Source_0</name>
|
|
<description>XTALOSC input (XTALOSC clock)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxClk_Source_1</name>
|
|
<description>tx_clk input (from SPDIF0_CLK_ROOT. See CCM.)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxClk_Source_2</name>
|
|
<description>tx_clk1 (from SAI1)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxClk_Source_3</name>
|
|
<description>tx_clk2 SPDIF_EXT_CLK, from pads</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxClk_Source_4</name>
|
|
<description>tx_clk3 (from SAI2)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxClk_Source_5</name>
|
|
<description>ipg_clk input (frequency divided)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TxClk_Source_6</name>
|
|
<description>tx_clk4 (from SAI3)</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCLK_DF</name>
|
|
<description>system clock divider factor, 2~512.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCLK_DF_0</name>
|
|
<description>no clock signal</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCLK_DF_1</name>
|
|
<description>divider factor is 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCLK_DF_511</name>
|
|
<description>divider factor is 512</description>
|
|
<value>0x1FF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SAI1</name>
|
|
<description>I2S</description>
|
|
<groupName>I2S</groupName>
|
|
<headerStructName>I2S</headerStructName>
|
|
<baseAddress>0x401E0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xE4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SAI1</name>
|
|
<value>56</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x3000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Specification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEATURE_0</name>
|
|
<description>Standard feature set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x50502</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATALINE</name>
|
|
<description>Number of Datalines</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FIFO</name>
|
|
<description>FIFO Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRAME</name>
|
|
<description>Frame Size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCSR</name>
|
|
<description>SAI Transmit Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRDE</name>
|
|
<description>FIFO Request DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRDE_0</name>
|
|
<description>Disables the DMA request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRDE_1</name>
|
|
<description>Enables the DMA request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FWDE</name>
|
|
<description>FIFO Warning DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FWDE_0</name>
|
|
<description>Disables the DMA request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FWDE_1</name>
|
|
<description>Enables the DMA request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRIE</name>
|
|
<description>FIFO Request Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRIE_0</name>
|
|
<description>Disables the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRIE_1</name>
|
|
<description>Enables the interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FWIE</name>
|
|
<description>FIFO Warning Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FWIE_0</name>
|
|
<description>Disables the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FWIE_1</name>
|
|
<description>Enables the interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>FIFO Error Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEIE_0</name>
|
|
<description>Disables the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEIE_1</name>
|
|
<description>Enables the interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEIE</name>
|
|
<description>Sync Error Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SEIE_0</name>
|
|
<description>Disables interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEIE_1</name>
|
|
<description>Enables interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WSIE</name>
|
|
<description>Word Start Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WSIE_0</name>
|
|
<description>Disables interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WSIE_1</name>
|
|
<description>Enables interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRF</name>
|
|
<description>FIFO Request Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRF_0</name>
|
|
<description>Transmit FIFO watermark has not been reached.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRF_1</name>
|
|
<description>Transmit FIFO watermark has been reached.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FWF</name>
|
|
<description>FIFO Warning Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FWF_0</name>
|
|
<description>No enabled transmit FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FWF_1</name>
|
|
<description>Enabled transmit FIFO is empty.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>FIFO Error Flag</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEF_0</name>
|
|
<description>Transmit underrun not detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEF_1</name>
|
|
<description>Transmit underrun detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEF</name>
|
|
<description>Sync Error Flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SEF_0</name>
|
|
<description>Sync error not detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEF_1</name>
|
|
<description>Frame sync error detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WSF</name>
|
|
<description>Word Start Flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WSF_0</name>
|
|
<description>Start of word not detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WSF_1</name>
|
|
<description>Start of word detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SR</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_0</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SR_1</name>
|
|
<description>Software reset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FR</name>
|
|
<description>FIFO Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FR_0</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FR_1</name>
|
|
<description>FIFO reset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCE</name>
|
|
<description>Bit Clock Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BCE_0</name>
|
|
<description>Transmit bit clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BCE_1</name>
|
|
<description>Transmit bit clock is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGE</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBGE_0</name>
|
|
<description>Transmitter is disabled in Debug mode, after completing the current frame.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBGE_1</name>
|
|
<description>Transmitter is enabled in Debug mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPE</name>
|
|
<description>Stop Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOPE_0</name>
|
|
<description>Transmitter disabled in Stop mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOPE_1</name>
|
|
<description>Transmitter enabled in Stop mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TE_0</name>
|
|
<description>Transmitter is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TE_1</name>
|
|
<description>Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR1</name>
|
|
<description>SAI Transmit Configuration 1 Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFW</name>
|
|
<description>Transmit FIFO Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR2</name>
|
|
<description>SAI Transmit Configuration 2 Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Bit Clock Divide</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BCD</name>
|
|
<description>Bit Clock Direction</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BCD_0</name>
|
|
<description>Bit clock is generated externally in Slave mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BCD_1</name>
|
|
<description>Bit clock is generated internally in Master mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCP</name>
|
|
<description>Bit Clock Polarity</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BCP_0</name>
|
|
<description>Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BCP_1</name>
|
|
<description>Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>MCLK Select</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MSEL_0</name>
|
|
<description>Bus Clock selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSEL_1</name>
|
|
<description>Master Clock (MCLK) 1 option selected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSEL_2</name>
|
|
<description>Master Clock (MCLK) 2 option selected.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSEL_3</name>
|
|
<description>Master Clock (MCLK) 3 option selected.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCI</name>
|
|
<description>Bit Clock Input</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BCI_0</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BCI_1</name>
|
|
<description>Internal logic is clocked as if bit clock was externally generated.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCS</name>
|
|
<description>Bit Clock Swap</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BCS_0</name>
|
|
<description>Use the normal bit clock source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BCS_1</name>
|
|
<description>Swap the bit clock source.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Synchronous Mode</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYNC_0</name>
|
|
<description>Asynchronous mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNC_1</name>
|
|
<description>Synchronous with receiver.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR3</name>
|
|
<description>SAI Transmit Configuration 3 Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDFL</name>
|
|
<description>Word Flag Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCE</name>
|
|
<description>Transmit Channel Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CFR</name>
|
|
<description>Channel FIFO Reset</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR4</name>
|
|
<description>SAI Transmit Configuration 4 Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FSD</name>
|
|
<description>Frame Sync Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FSD_0</name>
|
|
<description>Frame sync is generated externally in Slave mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FSD_1</name>
|
|
<description>Frame sync is generated internally in Master mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSP</name>
|
|
<description>Frame Sync Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FSP_0</name>
|
|
<description>Frame sync is active high.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FSP_1</name>
|
|
<description>Frame sync is active low.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONDEM</name>
|
|
<description>On Demand Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONDEM_0</name>
|
|
<description>Internal frame sync is generated continuously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONDEM_1</name>
|
|
<description>Internal frame sync is generated when the FIFO warning flag is clear.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSE</name>
|
|
<description>Frame Sync Early</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FSE_0</name>
|
|
<description>Frame sync asserts with the first bit of the frame.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FSE_1</name>
|
|
<description>Frame sync asserts one bit before the first bit of the frame.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MF</name>
|
|
<description>MSB First</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MF_0</name>
|
|
<description>LSB is transmitted first.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MF_1</name>
|
|
<description>MSB is transmitted first.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHMOD</name>
|
|
<description>Channel Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CHMOD_0</name>
|
|
<description>TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHMOD_1</name>
|
|
<description>Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYWD</name>
|
|
<description>Sync Width</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRSZ</name>
|
|
<description>Frame size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPACK</name>
|
|
<description>FIFO Packing Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FPACK_0</name>
|
|
<description>FIFO packing is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FPACK_2</name>
|
|
<description>8-bit FIFO packing is enabled</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FPACK_3</name>
|
|
<description>16-bit FIFO packing is enabled</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCOMB</name>
|
|
<description>FIFO Combine Mode</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCOMB_0</name>
|
|
<description>FIFO combine mode disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCOMB_1</name>
|
|
<description>FIFO combine mode enabled on FIFO reads (from transmit shift registers).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCOMB_2</name>
|
|
<description>FIFO combine mode enabled on FIFO writes (by software).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCOMB_3</name>
|
|
<description>FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCONT</name>
|
|
<description>FIFO Continue on Error</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCONT_0</name>
|
|
<description>On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCONT_1</name>
|
|
<description>On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR5</name>
|
|
<description>SAI Transmit Configuration 5 Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FBT</name>
|
|
<description>First Bit Shifted</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>W0W</name>
|
|
<description>Word 0 Width</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WNW</name>
|
|
<description>Word N Width</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>TDR[%s]</name>
|
|
<description>SAI Transmit Data Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDR</name>
|
|
<description>Transmit Data Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>TFR[%s]</name>
|
|
<description>SAI Transmit FIFO Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFP</name>
|
|
<description>Read FIFO Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WFP</name>
|
|
<description>Write FIFO Pointer</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WCP</name>
|
|
<description>Write Channel Pointer</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WCP_0</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WCP_1</name>
|
|
<description>FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMR</name>
|
|
<description>SAI Transmit Mask Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TWM</name>
|
|
<description>Transmit Word Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TWM_0</name>
|
|
<description>Word N is enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWM_1</name>
|
|
<description>Word N is masked. The transmit data pins are tri-stated or drive zero when masked.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCSR</name>
|
|
<description>SAI Receive Control Register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRDE</name>
|
|
<description>FIFO Request DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRDE_0</name>
|
|
<description>Disables the DMA request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRDE_1</name>
|
|
<description>Enables the DMA request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FWDE</name>
|
|
<description>FIFO Warning DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FWDE_0</name>
|
|
<description>Disables the DMA request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FWDE_1</name>
|
|
<description>Enables the DMA request.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRIE</name>
|
|
<description>FIFO Request Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRIE_0</name>
|
|
<description>Disables the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRIE_1</name>
|
|
<description>Enables the interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FWIE</name>
|
|
<description>FIFO Warning Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FWIE_0</name>
|
|
<description>Disables the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FWIE_1</name>
|
|
<description>Enables the interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>FIFO Error Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEIE_0</name>
|
|
<description>Disables the interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEIE_1</name>
|
|
<description>Enables the interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEIE</name>
|
|
<description>Sync Error Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SEIE_0</name>
|
|
<description>Disables interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEIE_1</name>
|
|
<description>Enables interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WSIE</name>
|
|
<description>Word Start Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WSIE_0</name>
|
|
<description>Disables interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WSIE_1</name>
|
|
<description>Enables interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRF</name>
|
|
<description>FIFO Request Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRF_0</name>
|
|
<description>Receive FIFO watermark not reached.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRF_1</name>
|
|
<description>Receive FIFO watermark has been reached.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FWF</name>
|
|
<description>FIFO Warning Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FWF_0</name>
|
|
<description>No enabled receive FIFO is full.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FWF_1</name>
|
|
<description>Enabled receive FIFO is full.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>FIFO Error Flag</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FEF_0</name>
|
|
<description>Receive overflow not detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEF_1</name>
|
|
<description>Receive overflow detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEF</name>
|
|
<description>Sync Error Flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SEF_0</name>
|
|
<description>Sync error not detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEF_1</name>
|
|
<description>Frame sync error detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WSF</name>
|
|
<description>Word Start Flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WSF_0</name>
|
|
<description>Start of word not detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WSF_1</name>
|
|
<description>Start of word detected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SR</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SR_0</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SR_1</name>
|
|
<description>Software reset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FR</name>
|
|
<description>FIFO Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FR_0</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FR_1</name>
|
|
<description>FIFO reset.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCE</name>
|
|
<description>Bit Clock Enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BCE_0</name>
|
|
<description>Receive bit clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BCE_1</name>
|
|
<description>Receive bit clock is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGE</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBGE_0</name>
|
|
<description>Receiver is disabled in Debug mode, after completing the current frame.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBGE_1</name>
|
|
<description>Receiver is enabled in Debug mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPE</name>
|
|
<description>Stop Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOPE_0</name>
|
|
<description>Receiver disabled in Stop mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOPE_1</name>
|
|
<description>Receiver enabled in Stop mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RE_0</name>
|
|
<description>Receiver is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RE_1</name>
|
|
<description>Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR1</name>
|
|
<description>SAI Receive Configuration 1 Register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFW</name>
|
|
<description>Receive FIFO Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR2</name>
|
|
<description>SAI Receive Configuration 2 Register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Bit Clock Divide</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BCD</name>
|
|
<description>Bit Clock Direction</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BCD_0</name>
|
|
<description>Bit clock is generated externally in Slave mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BCD_1</name>
|
|
<description>Bit clock is generated internally in Master mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCP</name>
|
|
<description>Bit Clock Polarity</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BCP_0</name>
|
|
<description>Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BCP_1</name>
|
|
<description>Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>MCLK Select</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MSEL_0</name>
|
|
<description>Bus Clock selected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSEL_1</name>
|
|
<description>Master Clock (MCLK) 1 option selected.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSEL_2</name>
|
|
<description>Master Clock (MCLK) 2 option selected.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSEL_3</name>
|
|
<description>Master Clock (MCLK) 3 option selected.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCI</name>
|
|
<description>Bit Clock Input</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BCI_0</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BCI_1</name>
|
|
<description>Internal logic is clocked as if bit clock was externally generated.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BCS</name>
|
|
<description>Bit Clock Swap</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BCS_0</name>
|
|
<description>Use the normal bit clock source.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BCS_1</name>
|
|
<description>Swap the bit clock source.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Synchronous Mode</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYNC_0</name>
|
|
<description>Asynchronous mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYNC_1</name>
|
|
<description>Synchronous with transmitter.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR3</name>
|
|
<description>SAI Receive Configuration 3 Register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDFL</name>
|
|
<description>Word Flag Configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RCE</name>
|
|
<description>Receive Channel Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CFR</name>
|
|
<description>Channel FIFO Reset</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR4</name>
|
|
<description>SAI Receive Configuration 4 Register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FSD</name>
|
|
<description>Frame Sync Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FSD_0</name>
|
|
<description>Frame Sync is generated externally in Slave mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FSD_1</name>
|
|
<description>Frame Sync is generated internally in Master mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSP</name>
|
|
<description>Frame Sync Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FSP_0</name>
|
|
<description>Frame sync is active high.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FSP_1</name>
|
|
<description>Frame sync is active low.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ONDEM</name>
|
|
<description>On Demand Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ONDEM_0</name>
|
|
<description>Internal frame sync is generated continuously.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONDEM_1</name>
|
|
<description>Internal frame sync is generated when the FIFO warning flag is clear.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSE</name>
|
|
<description>Frame Sync Early</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FSE_0</name>
|
|
<description>Frame sync asserts with the first bit of the frame.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FSE_1</name>
|
|
<description>Frame sync asserts one bit before the first bit of the frame.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MF</name>
|
|
<description>MSB First</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MF_0</name>
|
|
<description>LSB is received first.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MF_1</name>
|
|
<description>MSB is received first.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYWD</name>
|
|
<description>Sync Width</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRSZ</name>
|
|
<description>Frame Size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FPACK</name>
|
|
<description>FIFO Packing Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FPACK_0</name>
|
|
<description>FIFO packing is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FPACK_2</name>
|
|
<description>8-bit FIFO packing is enabled</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FPACK_3</name>
|
|
<description>16-bit FIFO packing is enabled</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCOMB</name>
|
|
<description>FIFO Combine Mode</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCOMB_0</name>
|
|
<description>FIFO combine mode disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCOMB_1</name>
|
|
<description>FIFO combine mode enabled on FIFO writes (from receive shift registers).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCOMB_2</name>
|
|
<description>FIFO combine mode enabled on FIFO reads (by software).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCOMB_3</name>
|
|
<description>FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCONT</name>
|
|
<description>FIFO Continue on Error</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FCONT_0</name>
|
|
<description>On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FCONT_1</name>
|
|
<description>On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR5</name>
|
|
<description>SAI Receive Configuration 5 Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FBT</name>
|
|
<description>First Bit Shifted</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>W0W</name>
|
|
<description>Word 0 Width</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WNW</name>
|
|
<description>Word N Width</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>RDR[%s]</name>
|
|
<description>SAI Receive Data Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>Receive Data Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<name>RFR[%s]</name>
|
|
<description>SAI Receive FIFO Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RFP</name>
|
|
<description>Read FIFO Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RCP</name>
|
|
<description>Receive Channel Pointer</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RCP_0</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RCP_1</name>
|
|
<description>FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WFP</name>
|
|
<description>Write FIFO Pointer</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RMR</name>
|
|
<description>SAI Receive Mask Register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RWM</name>
|
|
<description>Receive Word Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RWM_0</name>
|
|
<description>Word N is enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RWM_1</name>
|
|
<description>Word N is masked.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SAI1">
|
|
<name>SAI3</name>
|
|
<description>I2S</description>
|
|
<groupName>I2S</groupName>
|
|
<baseAddress>0x401E8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xE4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SAI3_RX</name>
|
|
<value>58</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SAI3_TX</name>
|
|
<value>59</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPT1</name>
|
|
<description>GPT</description>
|
|
<groupName>GPT</groupName>
|
|
<prependToName>GPT1_</prependToName>
|
|
<headerStructName>GPT</headerStructName>
|
|
<baseAddress>0x401EC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPT1</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>GPT Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>GPT Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN_0</name>
|
|
<description>GPT is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_1</name>
|
|
<description>GPT is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENMOD</name>
|
|
<description>GPT Enable mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENMOD_0</name>
|
|
<description>GPT counter will retain its value when it is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENMOD_1</name>
|
|
<description>GPT counter value is reset to 0 when it is disabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>GPT debug mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DBGEN_0</name>
|
|
<description>GPT is disabled in debug mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DBGEN_1</name>
|
|
<description>GPT is enabled in debug mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>GPT Wait Mode enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WAITEN_0</name>
|
|
<description>GPT is disabled in wait mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAITEN_1</name>
|
|
<description>GPT is enabled in wait mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEEN</name>
|
|
<description>GPT Doze Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DOZEEN_0</name>
|
|
<description>GPT is disabled in doze mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOZEEN_1</name>
|
|
<description>GPT is enabled in doze mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPEN</name>
|
|
<description>GPT Stop Mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STOPEN_0</name>
|
|
<description>GPT is disabled in Stop mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOPEN_1</name>
|
|
<description>GPT is enabled in Stop mode.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSRC</name>
|
|
<description>Clock Source select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CLKSRC_0</name>
|
|
<description>No clock</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKSRC_1</name>
|
|
<description>Peripheral Clock (ipg_clk)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKSRC_2</name>
|
|
<description>High Frequency Reference Clock (ipg_clk_highfreq)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKSRC_3</name>
|
|
<description>External Clock</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKSRC_4</name>
|
|
<description>Low Frequency Reference Clock (ipg_clk_32k)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLKSRC_5</name>
|
|
<description>Crystal oscillator as Reference Clock (ipg_clk_24M)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRR</name>
|
|
<description>Free-Run or Restart mode</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FRR_0</name>
|
|
<description>Restart mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FRR_1</name>
|
|
<description>Free-Run mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN_24M</name>
|
|
<description>Enable 24 MHz clock input from crystal</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN_24M_0</name>
|
|
<description>24M clock disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_24M_1</name>
|
|
<description>24M clock enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWR</name>
|
|
<description>Software reset</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SWR_0</name>
|
|
<description>GPT is not in reset state</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SWR_1</name>
|
|
<description>GPT is in reset state</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IM1</name>
|
|
<description>See IM2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IM2</name>
|
|
<description>IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IM2_0</name>
|
|
<description>capture disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IM2_1</name>
|
|
<description>capture on rising edge only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IM2_2</name>
|
|
<description>capture on falling edge only</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IM2_3</name>
|
|
<description>capture on both edges</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OM1</name>
|
|
<description>See OM3</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OM2</name>
|
|
<description>See OM3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OM3</name>
|
|
<description>OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OM3_0</name>
|
|
<description>Output disconnected. No response on pin.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OM3_1</name>
|
|
<description>Toggle output pin</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OM3_2</name>
|
|
<description>Clear output pin</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OM3_3</name>
|
|
<description>Set output pin</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OM3_4</name>
|
|
<description>Generate an active low pulse (that is one input clock wide) on the output pin.</description>
|
|
<value>#1xx</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FO1</name>
|
|
<description>See F03</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FO2</name>
|
|
<description>See F03</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FO3</name>
|
|
<description>FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FO3_0</name>
|
|
<description>Writing a 0 has no effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FO3_1</name>
|
|
<description>Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<description>GPT Prescaler Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRESCALER_0</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALER_1</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALER_4095</name>
|
|
<description>Divide by 4096</description>
|
|
<value>0xFFF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER24M</name>
|
|
<description>Prescaler bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRESCALER24M_0</name>
|
|
<description>Divide by 1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALER24M_1</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRESCALER24M_15</name>
|
|
<description>Divide by 16</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>GPT Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF1</name>
|
|
<description>See OF3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>OF2</name>
|
|
<description>See OF3</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>OF3</name>
|
|
<description>OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OF3_0</name>
|
|
<description>Compare event has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OF3_1</name>
|
|
<description>Compare event has occurred.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IF1</name>
|
|
<description>See IF2</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>IF2</name>
|
|
<description>IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IF2_0</name>
|
|
<description>Capture event has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF2_1</name>
|
|
<description>Capture event has occurred.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROV</name>
|
|
<description>Rollover Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ROV_0</name>
|
|
<description>Rollover has not occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ROV_1</name>
|
|
<description>Rollover has occurred.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>GPT Interrupt Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OF1IE</name>
|
|
<description>See OF3IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OF2IE</name>
|
|
<description>See OF3IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OF3IE</name>
|
|
<description>OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OF3IE_0</name>
|
|
<description>Output Compare Channel n interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OF3IE_1</name>
|
|
<description>Output Compare Channel n interrupt is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IF1IE</name>
|
|
<description>See IF2IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IF2IE</name>
|
|
<description>IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IF2IE_0</name>
|
|
<description>IF2IE Input Capture n Interrupt Enable is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF2IE_1</name>
|
|
<description>IF2IE Input Capture n Interrupt Enable is enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROVIE</name>
|
|
<description>Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ROVIE_0</name>
|
|
<description>Rollover interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ROVIE_1</name>
|
|
<description>Rollover interrupt enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OCR1</name>
|
|
<description>GPT Output Compare Register 1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OCR2</name>
|
|
<description>GPT Output Compare Register 2</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OCR3</name>
|
|
<description>GPT Output Compare Register 3</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR1</name>
|
|
<description>GPT Input Capture Register 1</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPT</name>
|
|
<description>Capture Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR2</name>
|
|
<description>GPT Input Capture Register 2</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPT</name>
|
|
<description>Capture Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>GPT Counter Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value. The COUNT bits show the current count value of the GPT counter.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPT1">
|
|
<name>GPT2</name>
|
|
<description>GPT</description>
|
|
<groupName>GPT</groupName>
|
|
<prependToName>GPT2_</prependToName>
|
|
<baseAddress>0x401F0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPT2</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OCOTP</name>
|
|
<description>no description available</description>
|
|
<groupName>OCOTP</groupName>
|
|
<baseAddress>0x401F4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x6F4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>HW_OCOTP_CTRL</name>
|
|
<description>OTP Controller Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>OTP write and read access address register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>OTP controller status bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Set by the controller when an access to a locked region(OTP or shadow register) is requested</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RELOAD_SHADOWS</name>
|
|
<description>Set to force re-loading the shadow registers (HW/SW capability and LOCK)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WR_UNLOCK</name>
|
|
<description>Write 0x3E77 to enable OTP write accesses</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_CTRL_SET</name>
|
|
<description>OTP Controller Control Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>OTP write and read access address register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToSet</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>OTP controller status bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<modifiedWriteValues>oneToSet</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Set by the controller when an access to a locked region(OTP or shadow register) is requested</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToSet</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>RELOAD_SHADOWS</name>
|
|
<description>Set to force re-loading the shadow registers (HW/SW capability and LOCK)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToSet</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>WR_UNLOCK</name>
|
|
<description>Write 0x3E77 to enable OTP write accesses</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToSet</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_CTRL_CLR</name>
|
|
<description>OTP Controller Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>OTP write and read access address register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>OTP controller status bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Set by the controller when an access to a locked region(OTP or shadow register) is requested</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>RELOAD_SHADOWS</name>
|
|
<description>Set to force re-loading the shadow registers (HW/SW capability and LOCK)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>WR_UNLOCK</name>
|
|
<description>Write 0x3E77 to enable OTP write accesses</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_CTRL_TOG</name>
|
|
<description>OTP Controller Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>OTP write and read access address register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToToggle</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>OTP controller status bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<modifiedWriteValues>oneToToggle</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>ERROR</name>
|
|
<description>Set by the controller when an access to a locked region(OTP or shadow register) is requested</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToToggle</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>RELOAD_SHADOWS</name>
|
|
<description>Set to force re-loading the shadow registers (HW/SW capability and LOCK)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToToggle</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>WR_UNLOCK</name>
|
|
<description>Write 0x3E77 to enable OTP write accesses</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToToggle</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_TIMING</name>
|
|
<description>OTP Controller Timing Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x60D9755</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STROBE_PROG</name>
|
|
<description>This count value specifies the strobe period in one time write OTP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RELAX</name>
|
|
<description>This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STROBE_READ</name>
|
|
<description>This count value specifies the strobe period in one time read OTP</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAIT</name>
|
|
<description>This count value specifies time interval between auto read and write access in one time program</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_DATA</name>
|
|
<description>OTP Controller Write Data Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Used to initiate a write to OTP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_READ_CTRL</name>
|
|
<description>OTP Controller Write Data Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>READ_FUSE</name>
|
|
<description>Used to initiate a read to OTP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_READ_FUSE_DATA</name>
|
|
<description>OTP Controller Read Data Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>The data read from OTP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SW_STICKY</name>
|
|
<description>Sticky bit Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRK_REVOKE_LOCK</name>
|
|
<description>Shadow register write and OTP write lock for SRK_REVOKE region</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FIELD_RETURN_LOCK</name>
|
|
<description>Shadow register write and OTP write lock for FIELD_RETURN region</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SCS</name>
|
|
<description>Software Controllable Signals Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HAB_JDE</name>
|
|
<description>HAB JTAG Debug Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SPARE</name>
|
|
<description>Unallocated read/write bits for implementation specific software use.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>When set, all of the bits in this register are locked and can not be changed through SW programming</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SCS_SET</name>
|
|
<description>Software Controllable Signals Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HAB_JDE</name>
|
|
<description>HAB JTAG Debug Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToSet</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>SPARE</name>
|
|
<description>Unallocated read/write bits for implementation specific software use.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToSet</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>When set, all of the bits in this register are locked and can not be changed through SW programming</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToSet</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SCS_CLR</name>
|
|
<description>Software Controllable Signals Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HAB_JDE</name>
|
|
<description>HAB JTAG Debug Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>SPARE</name>
|
|
<description>Unallocated read/write bits for implementation specific software use.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>When set, all of the bits in this register are locked and can not be changed through SW programming</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SCS_TOG</name>
|
|
<description>Software Controllable Signals Register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HAB_JDE</name>
|
|
<description>HAB JTAG Debug Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToToggle</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>SPARE</name>
|
|
<description>Unallocated read/write bits for implementation specific software use.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToToggle</modifiedWriteValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>When set, all of the bits in this register are locked and can not be changed through SW programming</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToToggle</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_VERSION</name>
|
|
<description>OTP Controller Version Register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x6000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STEP</name>
|
|
<description>Fixed read-only value reflecting the stepping of the RTL version.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Fixed read-only value reflecting the MINOR field of the RTL version.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Fixed read-only value reflecting the MAJOR field of the RTL version.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_TIMING2</name>
|
|
<description>OTP Controller Timing Register 2</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1C30092</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RELAX_PROG</name>
|
|
<description>This count value specifies the strobe period in one time write OTP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RELAX_READ</name>
|
|
<description>This count value specifies the strobe period in one time read OTP</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RELAX1</name>
|
|
<description>This count value specifies time interval between auto read and write access in one time program</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_LOCK</name>
|
|
<description>Value of OTP Bank0 Word0 (Lock controls)</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TESTER</name>
|
|
<description>Status of shadow register and OTP write lock for tester region</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BOOT_CFG</name>
|
|
<description>Status of shadow register and OTP write lock for boot_cfg region</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MEM_TRIM</name>
|
|
<description>Status of shadow register and OTP write lock for mem_trim region</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SJC_RESP</name>
|
|
<description>Status of shadow register read and write, OTP read and write lock for sjc_resp region</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAC_ADDR</name>
|
|
<description>Status of shadow register and OTP write lock for mac_addr region</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GP1</name>
|
|
<description>Status of shadow register and OTP write lock for gp1 region</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GP2</name>
|
|
<description>Status of shadow register and OTP write lock for gp2 region</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OTPMK_MSB</name>
|
|
<description>Status of shadow register read and write, OTP read and write lock for otpmk region (MSB)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_GP1</name>
|
|
<description>Status of shadow register and OTP write lock for sw_gp1 region</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OTPMK_LSB</name>
|
|
<description>Status of shadow register read and write, OTP read and write lock for otpmk region (LSB)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ANALOG</name>
|
|
<description>Status of shadow register and OTP write lock for analog region</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OTPMK_CRC</name>
|
|
<description>Status of shadow register and OTP write lock for otpmk_crc region</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_GP2_LOCK</name>
|
|
<description>Status of shadow register and OTP write lock for sw_gp2 region</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MISC_CONF</name>
|
|
<description>Status of shadow register and OTP write lock for misc_conf region</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SW_GP2_RLOCK</name>
|
|
<description>Status of shadow register and OTP read lock for sw_gp2 region</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GP3</name>
|
|
<description>Status of shadow register and OTP write lock for gp3 region</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FIELD_RETURN</name>
|
|
<description>Reserved</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_CFG0</name>
|
|
<description>Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)</description>
|
|
<addressOffset>0x410</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>This register contains 32 bits of the Unique ID and SJC_CHALLENGE field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_CFG1</name>
|
|
<description>Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.)</description>
|
|
<addressOffset>0x420</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>This register contains 32 bits of the Unique ID and SJC_CHALLENGE field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_CFG2</name>
|
|
<description>Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.)</description>
|
|
<addressOffset>0x430</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 0, word 3 (ADDR = 0x03)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_CFG3</name>
|
|
<description>Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.)</description>
|
|
<addressOffset>0x440</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 0, word 4 (ADDR = 0x04)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_CFG4</name>
|
|
<description>Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.)</description>
|
|
<addressOffset>0x450</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 0, word 5 (ADDR = 0x05)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_CFG5</name>
|
|
<description>Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.)</description>
|
|
<addressOffset>0x460</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 0, word 6 (ADDR = 0x06)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_CFG6</name>
|
|
<description>Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.)</description>
|
|
<addressOffset>0x470</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 0, word 7 (ADDR = 0x07)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_MEM0</name>
|
|
<description>Value of OTP Bank1 Word0 (Memory Related Info.)</description>
|
|
<addressOffset>0x480</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP bank 1, word 0 (ADDR = 0x08)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_MEM1</name>
|
|
<description>Value of OTP Bank1 Word1 (Memory Related Info.)</description>
|
|
<addressOffset>0x490</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP bank 1, word 1 (ADDR = 0x09)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_MEM2</name>
|
|
<description>Value of OTP Bank1 Word2 (Memory Related Info.)</description>
|
|
<addressOffset>0x4A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP bank 1, word 2 (ADDR = 0x0A)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_MEM3</name>
|
|
<description>Value of OTP Bank1 Word3 (Memory Related Info.)</description>
|
|
<addressOffset>0x4B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP bank 1, word 3 (ADDR = 0x0B)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_MEM4</name>
|
|
<description>Value of OTP Bank1 Word4 (Memory Related Info.)</description>
|
|
<addressOffset>0x4C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP bank 1, word 4 (ADDR = 0x0C)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_ANA0</name>
|
|
<description>Value of OTP Bank1 Word5 (Analog Info.)</description>
|
|
<addressOffset>0x4D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP bank 1, word 5 (ADDR = 0x0D)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_ANA1</name>
|
|
<description>Value of OTP Bank1 Word6 (Analog Info.)</description>
|
|
<addressOffset>0x4E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP bank 1, word 6 (ADDR = 0x0E)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_ANA2</name>
|
|
<description>Value of OTP Bank1 Word7 (Analog Info.)</description>
|
|
<addressOffset>0x4F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP bank 1, word 7 (ADDR = 0x0F)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SRK0</name>
|
|
<description>Shadow Register for OTP Bank3 Word0 (SRK Hash)</description>
|
|
<addressOffset>0x580</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 3, word 0 (ADDR = 0x1C))</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SRK1</name>
|
|
<description>Shadow Register for OTP Bank3 Word1 (SRK Hash)</description>
|
|
<addressOffset>0x590</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 3, word 1 (ADDR = 0x1D))</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SRK2</name>
|
|
<description>Shadow Register for OTP Bank3 Word2 (SRK Hash)</description>
|
|
<addressOffset>0x5A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 3, word 2 (ADDR = 0x1E))</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SRK3</name>
|
|
<description>Shadow Register for OTP Bank3 Word3 (SRK Hash)</description>
|
|
<addressOffset>0x5B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 3, word 3 (ADDR = 0x1F))</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SRK4</name>
|
|
<description>Shadow Register for OTP Bank3 Word4 (SRK Hash)</description>
|
|
<addressOffset>0x5C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 3, word 4 (ADDR = 0x20))</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SRK5</name>
|
|
<description>Shadow Register for OTP Bank3 Word5 (SRK Hash)</description>
|
|
<addressOffset>0x5D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 3, word 5 (ADDR = 0x21))</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SRK6</name>
|
|
<description>Shadow Register for OTP Bank3 Word6 (SRK Hash)</description>
|
|
<addressOffset>0x5E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 3, word 6 (ADDR = 0x22))</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SRK7</name>
|
|
<description>Shadow Register for OTP Bank3 Word7 (SRK Hash)</description>
|
|
<addressOffset>0x5F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 3, word 7 (ADDR = 0x23))</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SJC_RESP0</name>
|
|
<description>Value of OTP Bank4 Word0 (Secure JTAG Response Field)</description>
|
|
<addressOffset>0x600</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 4, word 0 (ADDR = 0x20))</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SJC_RESP1</name>
|
|
<description>Value of OTP Bank4 Word1 (Secure JTAG Response Field)</description>
|
|
<addressOffset>0x610</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 4, word 1 (ADDR = 0x21))</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_MAC0</name>
|
|
<description>Value of OTP Bank4 Word2 (MAC Address)</description>
|
|
<addressOffset>0x620</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 4, word 2 (ADDR = 0x22).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_MAC1</name>
|
|
<description>Value of OTP Bank4 Word3 (MAC Address)</description>
|
|
<addressOffset>0x630</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 4, word 3 (ADDR = 0x23).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_GP3</name>
|
|
<description>Value of OTP Bank4 Word4 (MAC Address)</description>
|
|
<addressOffset>0x640</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 4, word 4 (ADDR = 0x24).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_GP1</name>
|
|
<description>Value of OTP Bank4 Word6 (General Purpose Customer Defined Info)</description>
|
|
<addressOffset>0x660</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 4, word 6 (ADDR = 0x26).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_GP2</name>
|
|
<description>Value of OTP Bank4 Word7 (General Purpose Customer Defined Info)</description>
|
|
<addressOffset>0x670</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 4, word 7 (ADDR = 0x27).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SW_GP1</name>
|
|
<description>Value of OTP Bank5 Word0 (SW GP1)</description>
|
|
<addressOffset>0x680</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 5, word 0 (ADDR = 0x28).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SW_GP20</name>
|
|
<description>Value of OTP Bank5 Word1 (SW GP2)</description>
|
|
<addressOffset>0x690</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 5, word 1 (ADDR = 0x29).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SW_GP21</name>
|
|
<description>Value of OTP Bank5 Word2 (SW GP2)</description>
|
|
<addressOffset>0x6A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 5, word 2 (ADDR = 0x2a).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SW_GP22</name>
|
|
<description>Value of OTP Bank5 Word3 (SW GP2)</description>
|
|
<addressOffset>0x6B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 5, word 3 (ADDR = 0x2b).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SW_GP23</name>
|
|
<description>Value of OTP Bank5 Word4 (SW GP2)</description>
|
|
<addressOffset>0x6C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 5, word 4 (ADDR = 0x2c).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_MISC_CONF0</name>
|
|
<description>Value of OTP Bank5 Word5 (Misc Conf)</description>
|
|
<addressOffset>0x6D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 5, word 5 (ADDR = 0x2d).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_MISC_CONF1</name>
|
|
<description>Value of OTP Bank5 Word6 (Misc Conf)</description>
|
|
<addressOffset>0x6E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 5, word 6 (ADDR = 0x2e).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HW_OCOTP_SRK_REVOKE</name>
|
|
<description>Value of OTP Bank5 Word7 (SRK Revoke)</description>
|
|
<addressOffset>0x6F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>Reflects value of OTP Bank 5, word 7 (ADDR = 0x2f).</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IOMUXC</name>
|
|
<description>IOMUXC</description>
|
|
<groupName>IOMUXC</groupName>
|
|
<prependToName>IOMUXC_</prependToName>
|
|
<baseAddress>0x401F8000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x224</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_14</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_14 SW MUX Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPI2C1_SCL of instance: LPI2C1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPUART3_CTS_B of instance: LPUART3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: KPP_COL00 of instance: KPP</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPUART4_CTS_B of instance: LPUART4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO26 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO28 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: REF_CLK_24M of instance: XTAL OSC</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: XBAR1_INOUT02 of instance: XBAR1</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_14</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_13</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_13 SW MUX Control Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPI2C1_SDA of instance: LPI2C1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPUART3_RTS_B of instance: LPUART3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: KPP_ROW00 of instance: KPP</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPUART4_RTS_B of instance: LPUART4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO25 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO27 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: NMI_GLUE_NMI of instance: NMI_GLUE</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: JTAG_TMS of instance: JTAG</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_13</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_12</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_12 SW MUX Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPSPI2_SCK of instance: LPSPI2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: FLEXPWM1_PWM0_X of instance: FLEXPWM1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: KPP_COL01 of instance: KPP</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: PIT_TRIGGER01 of instance: PIT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO24 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO26 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: USB_OTG1_PWR of instance: USB</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: JTAG_TCK of instance: JTAG</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_12</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_11</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_11 SW MUX Control Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPSPI2_PCS0 of instance: LPSPI2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: FLEXPWM1_PWM1_X of instance: FLEXPWM1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: KPP_ROW01 of instance: KPP</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: PIT_TRIGGER02 of instance: PIT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO23 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO25 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: WDOG1_B of instance: WDOG1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: JTAG_MOD of instance: JTAG</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_11</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_10</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_10 SW MUX Control Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPSPI2_SDO of instance: LPSPI2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: FLEXPWM1_PWM2_X of instance: FLEXPWM1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: KPP_COL02 of instance: KPP</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: PIT_TRIGGER03 of instance: PIT</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO22 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO24 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: OTG1_ID of instance: anatop</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: JTAG_TDI of instance: JTAG</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_10</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_09</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_09 SW MUX Control Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPSPI2_SDI of instance: LPSPI2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: FLEXPWM1_PWM3_X of instance: FLEXPWM1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: KPP_ROW02 of instance: KPP</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: ARM_TRACE_SWO of instance: cm7_mxrt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO21 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO23 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: REF_32K_OUT of instance: anatop</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: JTAG_TDO of instance: JTAG</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_09</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_08</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_08 SW MUX Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPI2C2_SCL of instance: LPI2C2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPUART3_TXD of instance: LPUART3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: ARM_CM7_TXEV of instance: cm7_mxrt</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPUART2_CTS_B of instance: LPUART2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: GPT2_COMPARE3 of instance: GPT2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO22 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: EWM_OUT_B of instance: EWM</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: JTAG_TRSTB of instance: JTAG</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_08</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_07</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_07 SW MUX Control Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPI2C2_SDA of instance: LPI2C2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPUART3_RXD of instance: LPUART3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: ARM_CM7_RXEV of instance: cm7_mxrt</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPUART2_RTS_B of instance: LPUART2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: GPT2_CAPTURE2 of instance: GPT2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO21 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: OCOTP_FUSE_LATCHED of instance: OCOTP</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: XBAR1_INOUT03 of instance: XBAR1</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_07</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_06</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_06 SW MUX Control Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPSPI1_SCK of instance: LPSPI1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: PIT_TRIGGER00 of instance: PIT</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_A of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: KPP_COL01 of instance: KPP</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: GPT2_COMPARE2 of instance: GPT2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO20 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: LPI2C1_HREQ of instance: LPI2C1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_06</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_05</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_05 SW MUX Control Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPSPI1_PCS0 of instance: LPSPI1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: PIT_TRIGGER01 of instance: PIT</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_B of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: KPP_ROW01 of instance: KPP</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: GPT2_CAPTURE1 of instance: GPT2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO19 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_05</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_04</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_04 SW MUX Control Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPSPI1_SDO of instance: LPSPI1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: PIT_TRIGGER02 of instance: PIT</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM2_A of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: KPP_COL02 of instance: KPP</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: GPT2_COMPARE1 of instance: GPT2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO18 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SNVS_HP_VIO_5_CTL of instance: snvs_hp</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_04</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_03</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_03 SW MUX Control Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPSPI1_SDI of instance: LPSPI1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: PIT_TRIGGER03 of instance: PIT</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM2_B of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: KPP_ROW02 of instance: KPP</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: GPT2_CLK of instance: GPT2</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO17 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SNVS_HP_VIO_5_B of instance: snvs_hp</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: JTAG_DE_B of instance: JTAG</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_03</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_02</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_02 SW MUX Control Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPUART4_TXD of instance: LPUART4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPSPI1_PCS1 of instance: LPSPI1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: WDOG2_B of instance: WDOG2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: LPI2C2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: MQS_RIGHT of instance: MQS</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO16 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: ARM_CM7_TRACE_CLK of instance: cm7_mxrt</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_02</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_01</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_01 SW MUX Control Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPUART4_RXD of instance: LPUART4</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPSPI2_PCS1 of instance: LPSPI2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: WDOG1_ANY of instance: WDOG1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: LPI2C2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: MQS_LEFT of instance: MQS</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO15 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: USB_OTG1_OC of instance: USB</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: ARM_CM7_TRACE_SWO of instance: cm7_mxrt</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_01</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_AD_00</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_AD_00 SW MUX Control Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPUART2_TXD of instance: LPUART2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPSPI1_PCS2 of instance: LPSPI1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: KPP_COL03 of instance: KPP</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: USB_OTG1_PWR of instance: USB</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO20 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO14 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: NMI_GLUE_NMI of instance: NMI_GLUE</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: ARM_CM7_TRACE00 of instance: cm7_mxrt</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_AD_00</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_14</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_14 SW MUX Control Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_A_DQS of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: FLEXSPI_B_DQS of instance: FLEXSPI</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_14</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_13</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_13 SW MUX Control Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_B_SCLK of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: SAI3_RX_BCLK of instance: SAI3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: ARM_CM7_TXEV of instance: cm7_mxrt</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: CCM_PMIC_RDY of instance: CCM</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO19 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO13 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SRC_BT_CFG03 of instance: SRC</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_13</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_12</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_12 SW MUX Control Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_A_DQS of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPSPI2_PCS0 of instance: LPSPI2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: LPUART1_TXD of instance: LPUART1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO18 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO12 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: WDOG2_RST_B_DEB of instance: WDOG2</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_12</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_11</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_11 SW MUX Control Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_A_DATA3 of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPSPI2_SCK of instance: LPSPI2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: LPUART1_RXD of instance: LPUART1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO17 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO11 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: WDOG1_RST_B_DEB of instance: WDOG1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_11</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_10</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_10 SW MUX Control Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_A_SCLK of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPSPI2_SDO of instance: LPSPI2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: LPUART2_TXD of instance: LPUART2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO16 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO10 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_10</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_09</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_09 SW MUX Control Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_A_DATA0 of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPSPI2_SDI of instance: LPSPI2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: LPUART2_RXD of instance: LPUART2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO15 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_09</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_08</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_08 SW MUX Control Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_A_DATA2 of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPI2C2_SCL of instance: LPI2C2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: LPSPI1_SCK of instance: LPSPI1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO14 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_08</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_07</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_07 SW MUX Control Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_A_DATA1 of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPI2C2_SDA of instance: LPI2C2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: LPSPI1_PCS0 of instance: LPSPI1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO13 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_07</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_06</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_06 SW MUX Control Register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_A_SS0_B of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPI2C1_SCL of instance: LPI2C1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: LPSPI1_SDO of instance: LPSPI1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO12 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_06</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_05</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_05 SW MUX Control Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_A_SS1_B of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPI2C1_SDA of instance: LPI2C1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: LPSPI1_SDI of instance: LPSPI1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO11 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_05</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_04</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_04 SW MUX Control Register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x6</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_B_DATA03 of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: SAI3_RX_SYNC of instance: SAI3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_A of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: CCM_WAIT of instance: CCM</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO10 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SRC_BOOT_MODE00 of instance: SRC</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_04</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_03</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_03 SW MUX Control Register</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x6</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_B_DATA00 of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: SAI3_RX_DATA of instance: SAI3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_B of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: CCM_REF_EN_B of instance: CCM</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO09 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO03 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SRC_BOOT_MODE01 of instance: SRC</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_03</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_02</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_02 SW MUX Control Register</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_B_DATA02 of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: SAI3_TX_DATA of instance: SAI3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM0_A of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: CCM_CLKO1 of instance: CCM</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO08 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO02 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: SRC</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_02</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_01</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_01 SW MUX Control Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_B_DATA01 of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: SAI3_TX_BCLK of instance: SAI3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM0_B of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: CCM_CLKO2 of instance: CCM</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO07 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO01 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: SRC</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_01</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_SD_00</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_SD_00 SW MUX Control Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_B_SS0_B of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: SAI3_TX_SYNC of instance: SAI3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: ARM_CM7_RXEV of instance: cm7_mxrt</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: CCM_STOP of instance: CCM</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO06 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIO2_IO00 of instance: GPIO2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SRC_BT_CFG02 of instance: SRC</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_SD_00</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_13</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_13 SW MUX Control Register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPUART2_RXD of instance: LPUART2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPSPI2_PCS2 of instance: LPSPI2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: KPP_ROW03 of instance: KPP</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: OTG1_ID of instance: anatop</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO05 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO13 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SPDIF_LOCK of instance: SPDIF</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: ARM_CM7_TRACE01 of instance: cm7_mxrt</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_13</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_12</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_12 SW MUX Control Register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPUART3_TXD of instance: LPUART3</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPI2C1_SCL of instance: LPI2C1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: KPP_COL00 of instance: KPP</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: USB_OTG1_OC of instance: USB</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO04 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO12 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SPDIF_EXT_CLK of instance: SPDIF</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: ARM_CM7_TRACE02 of instance: cm7_mxrt</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_12</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_11</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_11 SW MUX Control Register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPUART3_RXD of instance: LPUART3</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPI2C1_SDA of instance: LPI2C1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: KPP_ROW00 of instance: KPP</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: FLEXSPI_B_SS1_B of instance: FLEXSPI</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO03 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO11 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SPDIF_OUT of instance: SPDIF</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT7</name>
|
|
<description>Select mux mode: ALT7 mux port: ARM_CM7_TRACE03 of instance: cm7_mxrt</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_11</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_10</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_10 SW MUX Control Register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPUART1_TXD of instance: LPUART1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: LPI2C1_HREQ of instance: LPI2C1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: EWM_OUT_B of instance: EWM</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: LPI2C2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO02 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO10 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SPDIF_IN of instance: SPDIF</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_10</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_09</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_09 SW MUX Control Register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: LPUART1_RXD of instance: LPUART1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: WDOG1_B of instance: WDOG1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXSPI_A_SS1_B of instance: FLEXSPI</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: LPI2C2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO01 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO09 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: SPDIF_SR_CLK of instance: SPDIF</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_09</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_08</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_08 SW MUX Control Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: SAI1_MCLK of instance: SAI1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: GPT1_CLK of instance: GPT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_A of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPUART3_TXD of instance: LPUART3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: FLEXIO1_IO00 of instance: FLEXIO1</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO08 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: LPUART1_CTS_B of instance: LPUART1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_08</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_07</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_07 SW MUX Control Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: SAI1_TX_SYNC of instance: SAI1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: GPT1_COMPARE1 of instance: GPT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_B of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPUART3_RXD of instance: LPUART3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: SPDIF_LOCK of instance: SPDIF</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO07 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT6</name>
|
|
<description>Select mux mode: ALT6 mux port: LPUART1_RTS_B of instance: LPUART1</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_07</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_06</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_06 SW MUX Control Register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: SAI1_TX_BCLK of instance: SAI1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: GPT1_CAPTURE1 of instance: GPT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM2_A of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPUART4_TXD of instance: LPUART4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: SPDIF_EXT_CLK of instance: SPDIF</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO06 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_06</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_05</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_05 SW MUX Control Register</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: SAI1_TX_DATA01 of instance: SAI1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: GPT1_COMPARE2 of instance: GPT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM2_B of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPUART4_RXD of instance: LPUART4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: SPDIF_OUT of instance: SPDIF</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO05 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_05</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_04</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_04 SW MUX Control Register</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: SAI1_TX_DATA00 of instance: SAI1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: GPT1_CAPTURE2 of instance: GPT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_A of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: SPDIF_IN of instance: SPDIF</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO04 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_04</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_03</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_03 SW MUX Control Register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: SAI1_RX_DATA00 of instance: SAI1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: GPT1_COMPARE3 of instance: GPT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_B of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: SPDIF_SR_CLK of instance: SPDIF</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO03 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_03</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_02</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_02 SW MUX Control Register</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: SAI1_RX_SYNC of instance: SAI1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: WDOG2_B of instance: WDOG2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM0_A of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPI2C1_SCL of instance: LPI2C1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: KPP_COL03 of instance: KPP</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO02 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_02</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_01</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_01 SW MUX Control Register</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: SAI1_RX_BCLK of instance: SAI1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: WDOG1_ANY of instance: WDOG1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: FLEXPWM1_PWM0_B of instance: FLEXPWM1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPI2C1_SDA of instance: LPI2C1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: KPP_ROW03 of instance: KPP</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO01 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_01</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_MUX_CTL_PAD_GPIO_00</name>
|
|
<description>SW_MUX_CTL_PAD_GPIO_00 SW MUX Control Register</description>
|
|
<addressOffset>0xBC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MUX_MODE</name>
|
|
<description>MUX Mode Select Field.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ALT0</name>
|
|
<description>Select mux mode: ALT0 mux port: FLEXSPI_B_DQS of instance: FLEXSPI</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT1</name>
|
|
<description>Select mux mode: ALT1 mux port: SAI3_MCLK of instance: SAI3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT2</name>
|
|
<description>Select mux mode: ALT2 mux port: LPSPI2_PCS3 of instance: LPSPI2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT3</name>
|
|
<description>Select mux mode: ALT3 mux port: LPSPI1_PCS3 of instance: LPSPI1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT4</name>
|
|
<description>Select mux mode: ALT4 mux port: PIT_TRIGGER00 of instance: PIT</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALT5</name>
|
|
<description>Select mux mode: ALT5 mux port: GPIOMUX_IO00 of instance: GPIOMUX</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SION</name>
|
|
<description>Software Input On Field.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Input Path is determined by functionality</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Force input path of pad GPIO_00</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_14</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_14 SW PAD Control Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_13</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_13 SW PAD Control Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x70A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_12</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_12 SW PAD Control Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_11</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_11 SW PAD Control Register</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_10</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_10 SW PAD Control Register</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x70A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_09</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_09 SW PAD Control Register</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x90B1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_08</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_08 SW PAD Control Register</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x70A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_07</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_07 SW PAD Control Register</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_06</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_06 SW PAD Control Register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_05</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_05 SW PAD Control Register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_04</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_04 SW PAD Control Register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_03</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_03 SW PAD Control Register</description>
|
|
<addressOffset>0xEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_02</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_02 SW PAD Control Register</description>
|
|
<addressOffset>0xF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_01</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_01 SW PAD Control Register</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_AD_00</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_AD_00 SW PAD Control Register</description>
|
|
<addressOffset>0xF8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_14</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_14 SW PAD Control Register</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_13</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_13 SW PAD Control Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_12</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_12 SW PAD Control Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_11</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_11 SW PAD Control Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_10</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_10 SW PAD Control Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_09</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_09 SW PAD Control Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_08</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_08 SW PAD Control Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_07</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_07 SW PAD Control Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_06</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_06 SW PAD Control Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_05</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_05 SW PAD Control Register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_04</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_04 SW PAD Control Register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_03</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_03 SW PAD Control Register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_02</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_02 SW PAD Control Register</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_01</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_01 SW PAD Control Register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_SD_00</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_SD_00 SW PAD Control Register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_13</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_13 SW PAD Control Register</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_12</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_12 SW PAD Control Register</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_11</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_11 SW PAD Control Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_10</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_10 SW PAD Control Register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_09</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_09 SW PAD Control Register</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_08</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_08 SW PAD Control Register</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_07</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_07 SW PAD Control Register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_06</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_06 SW PAD Control Register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_05</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_05 SW PAD Control Register</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_04</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_04 SW PAD Control Register</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_03</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_03 SW PAD Control Register</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_02</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_02 SW PAD Control Register</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_01</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_01 SW PAD Control Register</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_PAD_CTL_PAD_GPIO_00</name>
|
|
<description>SW_PAD_CTL_PAD_GPIO_00 SW PAD Control Register</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10A0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SRE_0_Slow_Slew_Rate</name>
|
|
<description>Slow Slew Rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SRE_1_Fast_Slew_Rate</name>
|
|
<description>Fast Slew Rate</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Field</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DSE_0_output_driver_disabled_</name>
|
|
<description>output driver disabled;</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_</name>
|
|
<description>R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_2_R0_2</name>
|
|
<description>R0/2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_3_R0_3</name>
|
|
<description>R0/3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_4_R0_4</name>
|
|
<description>R0/4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_5_R0_5</name>
|
|
<description>R0/5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_6_R0_6</name>
|
|
<description>R0/6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DSE_7_R0_7</name>
|
|
<description>R0/7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPEED</name>
|
|
<description>Speed Field</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SPEED_0_low_50MHz</name>
|
|
<description>low(50MHz)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_1_medium_100MHz</name>
|
|
<description>medium(100MHz)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_2_fast_150MHz</name>
|
|
<description>fast(150MHz)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPEED_3_max_200MHz</name>
|
|
<description>max(200MHz)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable Field</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ODE_0_Open_Drain_Disabled</name>
|
|
<description>Open Drain Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ODE_1_Open_Drain_Enabled</name>
|
|
<description>Open Drain Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PKE</name>
|
|
<description>Pull / Keep Enable Field</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PKE_0_Pull_Keeper_Disabled</name>
|
|
<description>Pull/Keeper Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PKE_1_Pull_Keeper_Enabled</name>
|
|
<description>Pull/Keeper Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUE</name>
|
|
<description>Pull / Keep Select Field</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUE_0_Keeper</name>
|
|
<description>Keeper</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUE_1_Pull</name>
|
|
<description>Pull</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PUS</name>
|
|
<description>Pull Up / Down Config. Field</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PUS_0_100K_Ohm_Pull_Down</name>
|
|
<description>100K Ohm Pull Down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_1_47K_Ohm_Pull_Up</name>
|
|
<description>47K Ohm Pull Up</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_2_100K_Ohm_Pull_Up</name>
|
|
<description>100K Ohm Pull Up</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PUS_3_22K_Ohm_Pull_Up</name>
|
|
<description>22K Ohm Pull Up</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hyst. Enable Field</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HYS_0_Hysteresis_Disabled</name>
|
|
<description>Hysteresis Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HYS_1_Hysteresis_Enabled</name>
|
|
<description>Hysteresis Enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB_OTG_ID_SELECT_INPUT</name>
|
|
<description>USB_OTG_ID_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_10_ALT6</name>
|
|
<description>Selecting Pad: GPIO_AD_10 for Mode: ALT6</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_13_ALT3</name>
|
|
<description>Selecting Pad: GPIO_13 for Mode: ALT3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLEXPWM1_PWMA_SELECT_INPUT_0</name>
|
|
<description>FLEXPWM1_PWMA_SELECT_INPUT_0 DAISY Register</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_02_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_02 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_02_ALT2</name>
|
|
<description>Selecting Pad: GPIO_02 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLEXPWM1_PWMA_SELECT_INPUT_1</name>
|
|
<description>FLEXPWM1_PWMA_SELECT_INPUT_1 DAISY Register</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_04_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_04 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_04_ALT2</name>
|
|
<description>Selecting Pad: GPIO_04 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLEXPWM1_PWMA_SELECT_INPUT_2</name>
|
|
<description>FLEXPWM1_PWMA_SELECT_INPUT_2 DAISY Register</description>
|
|
<addressOffset>0x17C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_04_ALT2</name>
|
|
<description>Selecting Pad: GPIO_AD_04 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_06_ALT2</name>
|
|
<description>Selecting Pad: GPIO_06 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLEXPWM1_PWMA_SELECT_INPUT_3</name>
|
|
<description>FLEXPWM1_PWMA_SELECT_INPUT_3 DAISY Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_06_ALT2</name>
|
|
<description>Selecting Pad: GPIO_AD_06 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_08_ALT2</name>
|
|
<description>Selecting Pad: GPIO_08 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLEXPWM1_PWMB_SELECT_INPUT_0</name>
|
|
<description>FLEXPWM1_PWMB_SELECT_INPUT_0 DAISY Register</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_01_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_01 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_01_ALT2</name>
|
|
<description>Selecting Pad: GPIO_01 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLEXPWM1_PWMB_SELECT_INPUT_1</name>
|
|
<description>FLEXPWM1_PWMB_SELECT_INPUT_1 DAISY Register</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_03_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_03 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_03_ALT2</name>
|
|
<description>Selecting Pad: GPIO_03 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLEXPWM1_PWMB_SELECT_INPUT_2</name>
|
|
<description>FLEXPWM1_PWMB_SELECT_INPUT_2 DAISY Register</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_03_ALT2</name>
|
|
<description>Selecting Pad: GPIO_AD_03 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_05_ALT2</name>
|
|
<description>Selecting Pad: GPIO_05 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLEXPWM1_PWMB_SELECT_INPUT_3</name>
|
|
<description>FLEXPWM1_PWMB_SELECT_INPUT_3 DAISY Register</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_05_ALT2</name>
|
|
<description>Selecting Pad: GPIO_AD_05 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_07_ALT2</name>
|
|
<description>Selecting Pad: GPIO_07 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLEXSPI_DQS_FA_SELECT_INPUT</name>
|
|
<description>FLEXSPI_DQS_FA_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_14_ALT0</name>
|
|
<description>Selecting Pad: GPIO_SD_14 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_12_ALT0</name>
|
|
<description>Selecting Pad: GPIO_SD_12 for Mode: ALT0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLEXSPI_DQS_FB_SELECT_INPUT</name>
|
|
<description>FLEXSPI_DQS_FB_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_14_ALT1</name>
|
|
<description>Selecting Pad: GPIO_SD_14 for Mode: ALT1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_00_ALT0</name>
|
|
<description>Selecting Pad: GPIO_00 for Mode: ALT0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KPP_COL_SELECT_INPUT_0</name>
|
|
<description>KPP_COL_SELECT_INPUT_0 DAISY Register</description>
|
|
<addressOffset>0x19C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_14_ALT2</name>
|
|
<description>Selecting Pad: GPIO_AD_14 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_12_ALT2</name>
|
|
<description>Selecting Pad: GPIO_12 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KPP_COL_SELECT_INPUT_1</name>
|
|
<description>KPP_COL_SELECT_INPUT_1 DAISY Register</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_12_ALT2</name>
|
|
<description>Selecting Pad: GPIO_AD_12 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_06_ALT3</name>
|
|
<description>Selecting Pad: GPIO_AD_06 for Mode: ALT3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KPP_COL_SELECT_INPUT_2</name>
|
|
<description>KPP_COL_SELECT_INPUT_2 DAISY Register</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_10_ALT2</name>
|
|
<description>Selecting Pad: GPIO_AD_10 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_04_ALT3</name>
|
|
<description>Selecting Pad: GPIO_AD_04 for Mode: ALT3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KPP_COL_SELECT_INPUT_3</name>
|
|
<description>KPP_COL_SELECT_INPUT_3 DAISY Register</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_00_ALT2</name>
|
|
<description>Selecting Pad: GPIO_AD_00 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_02_ALT4</name>
|
|
<description>Selecting Pad: GPIO_02 for Mode: ALT4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KPP_ROW_SELECT_INPUT_0</name>
|
|
<description>KPP_ROW_SELECT_INPUT_0 DAISY Register</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_13_ALT2</name>
|
|
<description>Selecting Pad: GPIO_AD_13 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_11_ALT2</name>
|
|
<description>Selecting Pad: GPIO_11 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KPP_ROW_SELECT_INPUT_1</name>
|
|
<description>KPP_ROW_SELECT_INPUT_1 DAISY Register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_11_ALT2</name>
|
|
<description>Selecting Pad: GPIO_AD_11 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_05_ALT3</name>
|
|
<description>Selecting Pad: GPIO_AD_05 for Mode: ALT3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KPP_ROW_SELECT_INPUT_2</name>
|
|
<description>KPP_ROW_SELECT_INPUT_2 DAISY Register</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_09_ALT2</name>
|
|
<description>Selecting Pad: GPIO_AD_09 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_03_ALT3</name>
|
|
<description>Selecting Pad: GPIO_AD_03 for Mode: ALT3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KPP_ROW_SELECT_INPUT_3</name>
|
|
<description>KPP_ROW_SELECT_INPUT_3 DAISY Register</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_13_ALT2</name>
|
|
<description>Selecting Pad: GPIO_13 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_01_ALT4</name>
|
|
<description>Selecting Pad: GPIO_01 for Mode: ALT4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPI2C1_HREQ_SELECT_INPUT</name>
|
|
<description>LPI2C1_HREQ_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1BC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_06_ALT6</name>
|
|
<description>Selecting Pad: GPIO_AD_06 for Mode: ALT6</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_10_ALT1</name>
|
|
<description>Selecting Pad: GPIO_10 for Mode: ALT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPI2C1_SCL_SELECT_INPUT</name>
|
|
<description>LPI2C1_SCL_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_14_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_14 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_06_ALT1</name>
|
|
<description>Selecting Pad: GPIO_SD_06 for Mode: ALT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_12_ALT1</name>
|
|
<description>Selecting Pad: GPIO_12 for Mode: ALT1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_02_ALT3</name>
|
|
<description>Selecting Pad: GPIO_02 for Mode: ALT3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPI2C1_SDA_SELECT_INPUT</name>
|
|
<description>LPI2C1_SDA_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_13_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_13 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_05_ALT1</name>
|
|
<description>Selecting Pad: GPIO_SD_05 for Mode: ALT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_11_ALT1</name>
|
|
<description>Selecting Pad: GPIO_11 for Mode: ALT1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_01_ALT3</name>
|
|
<description>Selecting Pad: GPIO_01 for Mode: ALT3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPI2C2_SCL_SELECT_INPUT</name>
|
|
<description>LPI2C2_SCL_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1C8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_08_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_08 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_02_ALT3</name>
|
|
<description>Selecting Pad: GPIO_AD_02 for Mode: ALT3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_08_ALT1</name>
|
|
<description>Selecting Pad: GPIO_SD_08 for Mode: ALT1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_10_ALT3</name>
|
|
<description>Selecting Pad: GPIO_10 for Mode: ALT3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPI2C2_SDA_SELECT_INPUT</name>
|
|
<description>LPI2C2_SDA_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_07_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_07 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_01_ALT3</name>
|
|
<description>Selecting Pad: GPIO_AD_01 for Mode: ALT3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_07_ALT1</name>
|
|
<description>Selecting Pad: GPIO_SD_07 for Mode: ALT1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_09_ALT3</name>
|
|
<description>Selecting Pad: GPIO_09 for Mode: ALT3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSPI1_PCS_SELECT_INPUT_0</name>
|
|
<description>LPSPI1_PCS_SELECT_INPUT_0 DAISY Register</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_05_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_05 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_07_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_07 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSPI1_SCK_SELECT_INPUT</name>
|
|
<description>LPSPI1_SCK_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1D4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_06_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_06 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_08_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_08 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSPI1_SDI_SELECT_INPUT</name>
|
|
<description>LPSPI1_SDI_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1D8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_03_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_03 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_05_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_05 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSPI1_SDO_SELECT_INPUT</name>
|
|
<description>LPSPI1_SDO_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1DC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_04_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_04 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_06_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_06 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSPI2_PCS_SELECT_INPUT_0</name>
|
|
<description>LPSPI2_PCS_SELECT_INPUT_0 DAISY Register</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_11_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_11 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_12_ALT1</name>
|
|
<description>Selecting Pad: GPIO_SD_12 for Mode: ALT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSPI2_SCK_SELECT_INPUT</name>
|
|
<description>LPSPI2_SCK_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1E4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_12_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_12 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_11_ALT1</name>
|
|
<description>Selecting Pad: GPIO_SD_11 for Mode: ALT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSPI2_SDI_SELECT_INPUT</name>
|
|
<description>LPSPI2_SDI_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1E8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_09_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_09 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_09_ALT1</name>
|
|
<description>Selecting Pad: GPIO_SD_09 for Mode: ALT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPSPI2_SDO_SELECT_INPUT</name>
|
|
<description>LPSPI2_SDO_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1EC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_10_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_10 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_10_ALT1</name>
|
|
<description>Selecting Pad: GPIO_SD_10 for Mode: ALT1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPUART1_RXD_SELECT_INPUT</name>
|
|
<description>LPUART1_RXD_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1F0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_11_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_11 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_09_ALT0</name>
|
|
<description>Selecting Pad: GPIO_09 for Mode: ALT0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPUART1_TXD_SELECT_INPUT</name>
|
|
<description>LPUART1_TXD_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1F4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_12_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_12 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_10_ALT0</name>
|
|
<description>Selecting Pad: GPIO_10 for Mode: ALT0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPUART2_RXD_SELECT_INPUT</name>
|
|
<description>LPUART2_RXD_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1F8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_09_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_09 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_13_ALT0</name>
|
|
<description>Selecting Pad: GPIO_13 for Mode: ALT0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPUART2_TXD_SELECT_INPUT</name>
|
|
<description>LPUART2_TXD_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x1FC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_00_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_00 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_10_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_10 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPUART3_RXD_SELECT_INPUT</name>
|
|
<description>LPUART3_RXD_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_07_ALT1</name>
|
|
<description>Selecting Pad: GPIO_AD_07 for Mode: ALT1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_11_ALT0</name>
|
|
<description>Selecting Pad: GPIO_11 for Mode: ALT0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_07_ALT3</name>
|
|
<description>Selecting Pad: GPIO_07 for Mode: ALT3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPUART3_TXD_SELECT_INPUT</name>
|
|
<description>LPUART3_TXD_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_08_ALT1</name>
|
|
<description>Selecting Pad: GPIO_AD_08 for Mode: ALT1</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_12_ALT0</name>
|
|
<description>Selecting Pad: GPIO_12 for Mode: ALT0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_08_ALT3</name>
|
|
<description>Selecting Pad: GPIO_08 for Mode: ALT3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPUART4_RXD_SELECT_INPUT</name>
|
|
<description>LPUART4_RXD_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_01_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_01 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_05_ALT3</name>
|
|
<description>Selecting Pad: GPIO_05 for Mode: ALT3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPUART4_TXD_SELECT_INPUT</name>
|
|
<description>LPUART4_TXD_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_02_ALT0</name>
|
|
<description>Selecting Pad: GPIO_AD_02 for Mode: ALT0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_06_ALT3</name>
|
|
<description>Selecting Pad: GPIO_06 for Mode: ALT3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMI_GLUE_NMI_SELECT_INPUT</name>
|
|
<description>NMI_GLUE_NMI_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_13_ALT6</name>
|
|
<description>Selecting Pad: GPIO_AD_13 for Mode: ALT6</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_00_ALT6</name>
|
|
<description>Selecting Pad: GPIO_AD_00 for Mode: ALT6</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPDIF_IN1_SELECT_INPUT</name>
|
|
<description>SPDIF_IN1_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_10_ALT6</name>
|
|
<description>Selecting Pad: GPIO_10 for Mode: ALT6</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_04_ALT4</name>
|
|
<description>Selecting Pad: GPIO_04 for Mode: ALT4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SPDIF_TX_CLK2_SELECT_INPUT</name>
|
|
<description>SPDIF_TX_CLK2_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_12_ALT6</name>
|
|
<description>Selecting Pad: GPIO_12 for Mode: ALT6</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_06_ALT4</name>
|
|
<description>Selecting Pad: GPIO_06 for Mode: ALT4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB_OTG_OC_SELECT_INPUT</name>
|
|
<description>USB_OTG_OC_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x21C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_01_ALT6</name>
|
|
<description>Selecting Pad: GPIO_AD_01 for Mode: ALT6</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_12_ALT3</name>
|
|
<description>Selecting Pad: GPIO_12 for Mode: ALT3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XEV_GLUE_RXEV_SELECT_INPUT</name>
|
|
<description>XEV_GLUE_RXEV_SELECT_INPUT DAISY Register</description>
|
|
<addressOffset>0x220</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAISY</name>
|
|
<description>Selecting Pads Involved in Daisy Chain.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>GPIO_AD_07_ALT2</name>
|
|
<description>Selecting Pad: GPIO_AD_07 for Mode: ALT2</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_SD_00_ALT2</name>
|
|
<description>Selecting Pad: GPIO_SD_00 for Mode: ALT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>KPP</name>
|
|
<description>KPP Registers</description>
|
|
<groupName>KPP</groupName>
|
|
<prependToName>KPP_</prependToName>
|
|
<baseAddress>0x401FC000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>KPP</name>
|
|
<value>39</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>KPCR</name>
|
|
<description>Keypad Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KRE</name>
|
|
<description>Keypad Row Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KRE_0</name>
|
|
<description>Row is not included in the keypad key press detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KRE_1</name>
|
|
<description>Row is included in the keypad key press detect.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KCO</name>
|
|
<description>Keypad Column Strobe Open-Drain Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TOTEM_POLE</name>
|
|
<description>Column strobe output is totem pole drive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN</name>
|
|
<description>Column strobe output is open drain.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KPSR</name>
|
|
<description>Keypad Status Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x400</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KPKD</name>
|
|
<description>Keypad Key Depress</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KPKD_0</name>
|
|
<description>No key presses detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KPKD_1</name>
|
|
<description>A key has been depressed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KPKR</name>
|
|
<description>Keypad Key Release</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KPKR_0</name>
|
|
<description>No key release detected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KPKR_1</name>
|
|
<description>All keys have been released</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KDSC</name>
|
|
<description>Key Depress Synchronizer Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KDSC_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KDSC_1</name>
|
|
<description>Set bits that clear the keypad depress synchronizer chain</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRSS</name>
|
|
<description>Key Release Synchronizer Set</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KRSS_0</name>
|
|
<description>No effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KRSS_1</name>
|
|
<description>Set bits which sets keypad release synchronizer chain</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KDIE</name>
|
|
<description>Keypad Key Depress Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KDIE_0</name>
|
|
<description>No interrupt request is generated when KPKD is set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KDIE_1</name>
|
|
<description>An interrupt request is generated when KPKD is set.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KRIE</name>
|
|
<description>Keypad Release Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>KRIE_0</name>
|
|
<description>No interrupt request is generated when KPKR is set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>KRIE_1</name>
|
|
<description>An interrupt request is generated when KPKR is set.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KDDR</name>
|
|
<description>Keypad Data Direction Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KRDD</name>
|
|
<description>Keypad Row Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>ROWn pin configured as an input.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT</name>
|
|
<description>ROWn pin configured as an output.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KCDD</name>
|
|
<description>Keypad Column Data Direction Register</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>COLn pin is configured as an input.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT</name>
|
|
<description>COLn pin is configured as an output.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KPDR</name>
|
|
<description>Keypad Data Register</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>KRD</name>
|
|
<description>Keypad Row Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>KCD</name>
|
|
<description>Keypad Column Data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SystemControl</name>
|
|
<description>System Control Block</description>
|
|
<groupName>SCB</groupName>
|
|
<prependToName>SCB_</prependToName>
|
|
<baseAddress>0xE000E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFAC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ACTLR</name>
|
|
<description>Auxiliary Control Register,</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DISFOLD</name>
|
|
<description>Disables folding of IT instructions.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISFOLD_0</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FPEXCODIS</name>
|
|
<description>Disables FPU exception outputs.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FPEXCODIS_0</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FPEXCODIS_1</name>
|
|
<description>FPU exception outputs are disabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISRAMODE</name>
|
|
<description>Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISRAMODE_0</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISRAMODE_1</name>
|
|
<description>Dynamic disabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISITMATBFLUSH</name>
|
|
<description>Disables ITM and DWT ATB flush.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISITMATBFLUSH_1</name>
|
|
<description>ITM and DWT ATB flush disabled, this bit is always 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISBTACREAD</name>
|
|
<description>Disables BTAC read.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISBTACREAD_0</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISBTACREAD_1</name>
|
|
<description>BTAC is not used and only static branch prediction can occur.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISBTACALLOC</name>
|
|
<description>Disables BTAC allocate.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISBTACALLOC_0</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISBTACALLOC_1</name>
|
|
<description>No new entries are allocated in Branch Target Address Cache (BTAC), but existing entries can be updated.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCRITAXIRUR</name>
|
|
<description>Disables critical AXI Read-Under-Read.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCRITAXIRUR_0</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCRITAXIRUR_1</name>
|
|
<description>An AXI read to Strongly-Ordered or Device memory, or an LDREX to Shareable memory, is not put on AXI if there are any outstanding reads on AXI. Transactions on AXI cannot be interrupted. This bit might reduce the time that these transactions are in progress and might improve worst case interrupt latency. Performance is decreased when this bit is set.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISDI</name>
|
|
<description>Disables dual-issued.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISDI_0</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISDI_1</name>
|
|
<description>Nothing can be dual-issued when this instruction type is in channel 0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISISSCH1</name>
|
|
<description>Disables dual-issued.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISISSCH1_0</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISISSCH1_1</name>
|
|
<description>Nothing can be dual-issued when this instruction type is in channel 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISDYNADD</name>
|
|
<description>Disables dynamic allocation of ADD and SUB instructions</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISDYNADD_0</name>
|
|
<description>Normal operation. Some ADD and SUB instrctions are resolved in EX1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISDYNADD_1</name>
|
|
<description>All ADD and SUB instructions are resolved in EX2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISCRITAXIRUW</name>
|
|
<description>Disables critical AXI read-under-write</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISCRITAXIRUW_0</name>
|
|
<description>Normal operation. This is backwards compatible with r0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISCRITAXIRUW_1</name>
|
|
<description>AXI reads to DEV/SO memory. Exclusive reads to Shareable memory are not initiated on the AXIM AR channel until all outstanding stores on AXI are complete.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISFPUISSOPT</name>
|
|
<description>Disables critical AXI read-under-write</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DISFPUISSOPT_0</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPUID</name>
|
|
<description>CPUID Base Register</description>
|
|
<addressOffset>0xD00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x410FC240</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REVISION</name>
|
|
<description>Indicates patch release: 0x0 = Patch 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PARTNO</name>
|
|
<description>Indicates part number</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARCHITECTURE</name>
|
|
<description>ARCHITECTURE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VARIANT</name>
|
|
<description>Indicates processor revision: 0x2 = Revision 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IMPLEMENTER</name>
|
|
<description>Implementer code</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSR</name>
|
|
<description>Interrupt Control and State Register</description>
|
|
<addressOffset>0xD04</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VECTACTIVE</name>
|
|
<description>Active exception number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RETTOBASE</name>
|
|
<description>Indicates whether there are preempted active exceptions</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RETTOBASE_0</name>
|
|
<description>there are preempted active exceptions to execute</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETTOBASE_1</name>
|
|
<description>there are no active exceptions, or the currently-executing exception is the only active exception</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VECTPENDING</name>
|
|
<description>Exception number of the highest priority pending enabled exception</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ISRPENDING</name>
|
|
<description>Interrupt pending flag, excluding NMI and Faults</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ISRPENDING_0</name>
|
|
<description>No external interrupt pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISRPENDING_1</name>
|
|
<description>External interrupt pending.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTCLR</name>
|
|
<description>SysTick exception clear-pending bit</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PENDSTCLR_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDSTCLR_1</name>
|
|
<description>removes the pending state from the SysTick exception</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTSET</name>
|
|
<description>SysTick exception set-pending bit</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PENDSTSET_0</name>
|
|
<description>write: no effect; read: SysTick exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDSTSET_1</name>
|
|
<description>write: changes SysTick exception state to pending; read: SysTick exception is pending</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVCLR</name>
|
|
<description>PendSV clear-pending bit</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PENDSVCLR_0</name>
|
|
<description>no effect</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDSVCLR_1</name>
|
|
<description>removes the pending state from the PendSV exception</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVSET</name>
|
|
<description>PendSV set-pending bit</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PENDSVSET_0</name>
|
|
<description>write: no effect; read: PendSV exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDSVSET_1</name>
|
|
<description>write: changes PendSV exception state to pending; read: PendSV exception is pending</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMIPENDSET</name>
|
|
<description>NMI set-pending bit</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NMIPENDSET_0</name>
|
|
<description>write: no effect; read: NMI exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NMIPENDSET_1</name>
|
|
<description>write: changes NMI exception state to pending; read: NMI exception is pending</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VTOR</name>
|
|
<description>Vector Table Offset Register</description>
|
|
<addressOffset>0xD08</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TBLOFF</name>
|
|
<description>Vector table base offset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>25</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIRCR</name>
|
|
<description>Application Interrupt and Reset Control Register</description>
|
|
<addressOffset>0xD0C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFA050000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VECTRESET</name>
|
|
<description>Writing 1 to this bit causes a local system reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VECTRESET_0</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VECTRESET_1</name>
|
|
<description>Causes a local system reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VECTCLRACTIVE</name>
|
|
<description>Writing 1 to this bit clears all active state information for fixed and configurable exceptions.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VECTCLRACTIVE_0</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VECTCLRACTIVE_1</name>
|
|
<description>Clears all active state information for fixed and configurable exceptions</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSRESETREQ</name>
|
|
<description>System reset request</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSRESETREQ_0</name>
|
|
<description>no system reset request</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSRESETREQ_1</name>
|
|
<description>asserts a signal to the outer system that requests a reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRIGROUP</name>
|
|
<description>Interrupt priority grouping field. This field determines the split of group priority from subpriority.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENDIANNESS</name>
|
|
<description>Data endianness</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ENDIANNESS_0</name>
|
|
<description>Little-endian</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDIANNESS_1</name>
|
|
<description>Big-endian</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VECTKEY</name>
|
|
<description>Register key</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>System Control Register</description>
|
|
<addressOffset>0xD10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPONEXIT</name>
|
|
<description>Indicates sleep-on-exit when returning from Handler mode to Thread mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLEEPONEXIT_0</name>
|
|
<description>o not sleep when returning to Thread mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLEEPONEXIT_1</name>
|
|
<description>enter sleep, or deep sleep, on return from an ISR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPDEEP</name>
|
|
<description>Controls whether the processor uses sleep or deep sleep as its low power mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SLEEPDEEP_0</name>
|
|
<description>sleep</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLEEPDEEP_1</name>
|
|
<description>deep sleep</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEVONPEND</name>
|
|
<description>Send Event on Pending bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SEVONPEND_0</name>
|
|
<description>only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEVONPEND_1</name>
|
|
<description>enabled events and all interrupts, including disabled interrupts, can wakeup the processor</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Configuration and Control Register</description>
|
|
<addressOffset>0xD14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NONBASETHRDENA</name>
|
|
<description>Indicates how the processor enters Thread mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NONBASETHRDENA_0</name>
|
|
<description>processor can enter Thread mode only when no exception is active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NONBASETHRDENA_1</name>
|
|
<description>processor can enter Thread mode from any level under the control of an EXC_RETURN value</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USERSETMPEND</name>
|
|
<description>Enables unprivileged software access to the STIR</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USERSETMPEND_0</name>
|
|
<description>disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USERSETMPEND_1</name>
|
|
<description>enable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UNALIGN_TRP</name>
|
|
<description>Enables unaligned access traps</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNALIGN_TRP_0</name>
|
|
<description>do not trap unaligned halfword and word accesses</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNALIGN_TRP_1</name>
|
|
<description>trap unaligned halfword and word accesses</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIV_0_TRP</name>
|
|
<description>Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIV_0_TRP_0</name>
|
|
<description>do not trap divide by 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV_0_TRP_1</name>
|
|
<description>trap divide by 0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BFHFNMIGN</name>
|
|
<description>Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BFHFNMIGN_0</name>
|
|
<description>data bus faults caused by load and store instructions cause a lock-up</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BFHFNMIGN_1</name>
|
|
<description>handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STKALIGN</name>
|
|
<description>Indicates stack alignment on exception entry</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STKALIGN_0</name>
|
|
<description>4-byte aligned</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STKALIGN_1</name>
|
|
<description>8-byte aligned</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DC</name>
|
|
<description>Enables L1 data cache.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DC_0</name>
|
|
<description>L1 data cache disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DC_1</name>
|
|
<description>L1 data cache enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IC</name>
|
|
<description>Enables L1 instruction cache.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IC_0</name>
|
|
<description>L1 instruction cache disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IC_1</name>
|
|
<description>L1 instruction cache enabled</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BP</name>
|
|
<description>Always reads-as-one. It indicates branch prediction is enabled.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR1</name>
|
|
<description>System Handler Priority Register 1</description>
|
|
<addressOffset>0xD18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_4</name>
|
|
<description>Priority of system handler 4, MemManage</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_5</name>
|
|
<description>Priority of system handler 5, BusFault</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_6</name>
|
|
<description>Priority of system handler 6, UsageFault</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR2</name>
|
|
<description>System Handler Priority Register 2</description>
|
|
<addressOffset>0xD1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_11</name>
|
|
<description>Priority of system handler 11, SVCall</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR3</name>
|
|
<description>System Handler Priority Register 3</description>
|
|
<addressOffset>0xD20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_14</name>
|
|
<description>Priority of system handler 14, PendSV</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRI_15</name>
|
|
<description>Priority of system handler 15, SysTick exception</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHCSR</name>
|
|
<description>System Handler Control and State Register</description>
|
|
<addressOffset>0xD24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEMFAULTACT</name>
|
|
<description>MemManage exception active bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MEMFAULTACT_0</name>
|
|
<description>exception is not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEMFAULTACT_1</name>
|
|
<description>exception is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTACT</name>
|
|
<description>BusFault exception active bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BUSFAULTACT_0</name>
|
|
<description>exception is not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUSFAULTACT_1</name>
|
|
<description>exception is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTACT</name>
|
|
<description>UsageFault exception active bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USGFAULTACT_0</name>
|
|
<description>exception is not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USGFAULTACT_1</name>
|
|
<description>exception is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SVCALLACT</name>
|
|
<description>SVCall active bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SVCALLACT_0</name>
|
|
<description>exception is not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SVCALLACT_1</name>
|
|
<description>exception is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONITORACT</name>
|
|
<description>Debug monitor active bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MONITORACT_0</name>
|
|
<description>exception is not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MONITORACT_1</name>
|
|
<description>exception is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVACT</name>
|
|
<description>PendSV exception active bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PENDSVACT_0</name>
|
|
<description>exception is not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PENDSVACT_1</name>
|
|
<description>exception is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSTICKACT</name>
|
|
<description>SysTick exception active bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSTICKACT_0</name>
|
|
<description>exception is not active</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTICKACT_1</name>
|
|
<description>exception is active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTPENDED</name>
|
|
<description>UsageFault exception pending bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USGFAULTPENDED_0</name>
|
|
<description>exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USGFAULTPENDED_1</name>
|
|
<description>exception is pending</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEMFAULTPENDED</name>
|
|
<description>MemManage exception pending bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MEMFAULTPENDED_0</name>
|
|
<description>exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEMFAULTPENDED_1</name>
|
|
<description>exception is pending</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTPENDED</name>
|
|
<description>BusFault exception pending bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BUSFAULTPENDED_0</name>
|
|
<description>exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUSFAULTPENDED_1</name>
|
|
<description>exception is pending</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SVCALLPENDED</name>
|
|
<description>SVCall pending bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SVCALLPENDED_0</name>
|
|
<description>exception is not pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SVCALLPENDED_1</name>
|
|
<description>exception is pending</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEMFAULTENA</name>
|
|
<description>MemManage enable bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MEMFAULTENA_0</name>
|
|
<description>disable the exception</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEMFAULTENA_1</name>
|
|
<description>enable the exception</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTENA</name>
|
|
<description>BusFault enable bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BUSFAULTENA_0</name>
|
|
<description>disable the exception</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUSFAULTENA_1</name>
|
|
<description>enable the exception</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTENA</name>
|
|
<description>UsageFault enable bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>USGFAULTENA_0</name>
|
|
<description>disable the exception</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USGFAULTENA_1</name>
|
|
<description>enable the exception</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFSR</name>
|
|
<description>Configurable Fault Status Register</description>
|
|
<addressOffset>0xD28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IACCVIOL</name>
|
|
<description>Instruction access violation flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IACCVIOL_0</name>
|
|
<description>no instruction access violation fault</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IACCVIOL_1</name>
|
|
<description>the processor attempted an instruction fetch from a location that does not permit execution</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACCVIOL</name>
|
|
<description>Data access violation flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DACCVIOL_0</name>
|
|
<description>no data access violation fault</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DACCVIOL_1</name>
|
|
<description>the processor attempted a load or store at a location that does not permit the operation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUNSTKERR</name>
|
|
<description>MemManage fault on unstacking for a return from exception</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MUNSTKERR_0</name>
|
|
<description>no unstacking fault</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MUNSTKERR_1</name>
|
|
<description>unstack for an exception return has caused one or more access violations</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTKERR</name>
|
|
<description>MemManage fault on stacking for exception entry</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MSTKERR_0</name>
|
|
<description>no stacking fault</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MSTKERR_1</name>
|
|
<description>stacking for an exception entry has caused one or more access violations</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MLSPERR</name>
|
|
<description>MemManage fault occurred during floating-point lazy state preservation</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MLSPERR_0</name>
|
|
<description>No MemManage fault occurred during floating-point lazy state preservation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MLSPERR_1</name>
|
|
<description>A MemManage fault occurred during floating-point lazy state preservation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MMARVALID</name>
|
|
<description>MemManage Fault Address Register (MMFAR) valid flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MMARVALID_0</name>
|
|
<description>value in MMAR is not a valid fault address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MMARVALID_1</name>
|
|
<description>MMAR holds a valid fault address</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IBUSERR</name>
|
|
<description>Instruction bus error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IBUSERR_0</name>
|
|
<description>no instruction bus error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IBUSERR_1</name>
|
|
<description>instruction bus error</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRECISERR</name>
|
|
<description>Precise data bus error</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PRECISERR_0</name>
|
|
<description>no precise data bus error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PRECISERR_1</name>
|
|
<description>a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMPRECISERR</name>
|
|
<description>Imprecise data bus error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IMPRECISERR_0</name>
|
|
<description>no imprecise data bus error</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IMPRECISERR_1</name>
|
|
<description>a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UNSTKERR</name>
|
|
<description>BusFault on unstacking for a return from exception</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNSTKERR_0</name>
|
|
<description>no unstacking fault</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNSTKERR_1</name>
|
|
<description>unstack for an exception return has caused one or more BusFaults</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STKERR</name>
|
|
<description>BusFault on stacking for exception entry</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STKERR_0</name>
|
|
<description>no stacking fault</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STKERR_1</name>
|
|
<description>stacking for an exception entry has caused one or more BusFaults</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSPERR</name>
|
|
<description>Bus fault occurred during floating-point lazy state preservation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LSPERR_0</name>
|
|
<description>No bus fault occurred during floating-point lazy state preservation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSPERR_1</name>
|
|
<description>A bus fault occurred during floating-point lazy state preservation</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BFARVALID</name>
|
|
<description>BusFault Address Register (BFAR) valid flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BFARVALID_0</name>
|
|
<description>value in BFAR is not a valid fault address</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BFARVALID_1</name>
|
|
<description>BFAR holds a valid fault address</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UNDEFINSTR</name>
|
|
<description>Undefined instruction UsageFault</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNDEFINSTR_0</name>
|
|
<description>no undefined instruction UsageFault</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEFINSTR_1</name>
|
|
<description>the processor has attempted to execute an undefined instruction</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVSTATE</name>
|
|
<description>Invalid state UsageFault</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INVSTATE_0</name>
|
|
<description>no invalid state UsageFault</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVSTATE_1</name>
|
|
<description>the processor has attempted to execute an instruction that makes illegal use of the EPSR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVPC</name>
|
|
<description>Invalid PC load UsageFault, caused by an invalid PC load by EXC_RETURN</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INVPC_0</name>
|
|
<description>no invalid PC load UsageFault</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVPC_1</name>
|
|
<description>the processor has attempted an illegal load of EXC_RETURN to the PC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOCP</name>
|
|
<description>No coprocessor UsageFault</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NOCP_0</name>
|
|
<description>no UsageFault caused by attempting to access a coprocessor</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOCP_1</name>
|
|
<description>the processor has attempted to access a coprocessor</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UNALIGNED</name>
|
|
<description>Unaligned access UsageFault</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNALIGNED_0</name>
|
|
<description>no unaligned access fault, or unaligned access trapping not enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNALIGNED_1</name>
|
|
<description>the processor has made an unaligned memory access</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVBYZERO</name>
|
|
<description>Divide by zero UsageFault</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVBYZERO_0</name>
|
|
<description>no divide by zero fault, or divide by zero trapping not enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVBYZERO_1</name>
|
|
<description>the processor has executed an SDIV or UDIV instruction with a divisor of 0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFSR</name>
|
|
<description>HardFault Status register</description>
|
|
<addressOffset>0xD2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VECTTBL</name>
|
|
<description>Indicates a BusFault on a vector table read during exception processing.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VECTTBL_0</name>
|
|
<description>no BusFault on vector table read</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VECTTBL_1</name>
|
|
<description>BusFault on vector table read</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCED</name>
|
|
<description>Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FORCED_0</name>
|
|
<description>no forced HardFault</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED_1</name>
|
|
<description>forced HardFault</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEBUGEVT</name>
|
|
<description>Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DEBUGEVT_0</name>
|
|
<description>No Debug event has occurred.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEBUGEVT_1</name>
|
|
<description>Debug event has occurred. The Debug Fault Status Register has been updated.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFSR</name>
|
|
<description>Debug Fault Status Register</description>
|
|
<addressOffset>0xD30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HALTED</name>
|
|
<description>Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>HALTED_0</name>
|
|
<description>No active halt request debug event</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALTED_1</name>
|
|
<description>Halt request debug event active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BKPT</name>
|
|
<description>Debug event generated by BKPT instruction execution or a breakpoint match in FPB</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BKPT_0</name>
|
|
<description>No current breakpoint debug event</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BKPT_1</name>
|
|
<description>At least one current breakpoint debug event</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DWTTRAP</name>
|
|
<description>Debug event generated by the DWT</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DWTTRAP_0</name>
|
|
<description>No current debug events generated by the DWT</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DWTTRAP_1</name>
|
|
<description>At least one current debug event generated by the DWT</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VCATCH</name>
|
|
<description>Indicates triggering of a Vector catch</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>VCATCH_0</name>
|
|
<description>No Vector catch triggered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VCATCH_1</name>
|
|
<description>Vector catch triggered</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTERNAL</name>
|
|
<description>Debug event generated because of the assertion of an external debug request</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EXTERNAL_0</name>
|
|
<description>No external debug request debug event</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTERNAL_1</name>
|
|
<description>External debug request debug event</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMFAR</name>
|
|
<description>MemManage Fault Address Register</description>
|
|
<addressOffset>0xD34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Address of MemManage fault location</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BFAR</name>
|
|
<description>BusFault Address Register</description>
|
|
<addressOffset>0xD38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Address of the BusFault location</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_PFR0</name>
|
|
<description>Processor Feature Register 0</description>
|
|
<addressOffset>0xD40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATE0</name>
|
|
<description>ARM instruction set support</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STATE0_0</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE0_1</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE0_2</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE0_3</name>
|
|
<description>Support for Thumb encoding including Thumb-2 technology, with all basic 16-bit and 32-bit instructions.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATE1</name>
|
|
<description>Thumb instruction set support</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>STATE1_0</name>
|
|
<description>The processor does not support the ARM instruction set.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE1_1</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATE2</name>
|
|
<description>ARMv7-M unused</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STATE3</name>
|
|
<description>ARMv7-M unused</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_PFR1</name>
|
|
<description>Processor Feature Register 1</description>
|
|
<addressOffset>0xD44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PROGMODEL</name>
|
|
<description>M profile programmers' model</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PROGMODEL_0</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PROGMODEL_2</name>
|
|
<description>Two-stack programmers' model supported</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_DFR0</name>
|
|
<description>Debug Feature Register</description>
|
|
<addressOffset>0xD48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEBUGMODEL</name>
|
|
<description>Support for memory-mapped debug model for M profile processors</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DEBUGMODEL_0</name>
|
|
<description>Not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEBUGMODEL_1</name>
|
|
<description>Support for M profile Debug architecture, with memory-mapped access.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_AFR0</name>
|
|
<description>Auxiliary Feature Register</description>
|
|
<addressOffset>0xD4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMPLEMENTATION_DEFINED0</name>
|
|
<description>Gives information about the IMPLEMENTATION DEFINED features of a processor implementation.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IMPLEMENTATION_DEFINED1</name>
|
|
<description>Gives information about the IMPLEMENTATION DEFINED features of a processor implementation.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IMPLEMENTATION_DEFINED2</name>
|
|
<description>Gives information about the IMPLEMENTATION DEFINED features of a processor implementation.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IMPLEMENTATION_DEFINED3</name>
|
|
<description>Gives information about the IMPLEMENTATION DEFINED features of a processor implementation.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_MMFR0</name>
|
|
<description>Memory Model Feature Register 0</description>
|
|
<addressOffset>0xD50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMSASUPPORT</name>
|
|
<description>Indicates support for a PMSA</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PMSASUPPORT_0</name>
|
|
<description>Not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PMSASUPPORT_1</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PMSASUPPORT_2</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PMSASUPPORT_3</name>
|
|
<description>PMSAv7, providing support for a base region and subregions.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTERMOST_SHAREABILITY</name>
|
|
<description>Indicates the outermost shareability domain implemented</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_0</name>
|
|
<description>Implemented as Non-cacheable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_1</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_2</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_3</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_4</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_5</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_6</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_7</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_8</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_9</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_10</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_11</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_12</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_13</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_14</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTERMOST_SHAREABILITY_15</name>
|
|
<description>Shareability ignored.</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SHAREABILITY_LEVELS</name>
|
|
<description>Indicates the number of shareability levels implemented</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SHAREABILITY_LEVELS_0</name>
|
|
<description>One level of shareability implemented</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHAREABILITY_LEVELS_1</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCM_SUPPORT</name>
|
|
<description>Indicates the support for Tightly Coupled Memory</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TCM_SUPPORT_0</name>
|
|
<description>No tightly coupled memories implemented.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCM_SUPPORT_1</name>
|
|
<description>Tightly coupled memories implemented with IMPLEMENTATION DEFINED control.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TCM_SUPPORT_2</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUXILIARY_REGISTERS</name>
|
|
<description>Indicates the support for Auxiliary registers</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AUXILIARY_REGISTERS_0</name>
|
|
<description>Not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUXILIARY_REGISTERS_1</name>
|
|
<description>Support for Auxiliary Control Register only.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUXILIARY_REGISTERS_2</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_MMFR1</name>
|
|
<description>Memory Model Feature Register 1</description>
|
|
<addressOffset>0xD54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID_MMFR1</name>
|
|
<description>Gives information about the implemented memory model and memory management support.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_MMFR2</name>
|
|
<description>Memory Model Feature Register 2</description>
|
|
<addressOffset>0xD58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WFI_STALL</name>
|
|
<description>Indicates the support for Wait For Interrupt (WFI) stalling</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WFI_STALL_0</name>
|
|
<description>Not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WFI_STALL_1</name>
|
|
<description>Support for WFI stalling</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_MMFR3</name>
|
|
<description>Memory Model Feature Register 3</description>
|
|
<addressOffset>0xD5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID_MMFR3</name>
|
|
<description>Gives information about the implemented memory model and memory management support.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_ISAR0</name>
|
|
<description>Instruction Set Attributes Register 0</description>
|
|
<addressOffset>0xD60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITCOUNT_INSTRS</name>
|
|
<description>Indicates the supported Bit Counting instructions</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BITCOUNT_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BITCOUNT_INSTRS_1</name>
|
|
<description>Adds support for the CLZ instruction</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BITFIELD_INSTRS</name>
|
|
<description>Indicates the supported BitField instructions</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BITFIELD_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BITFIELD_INSTRS_1</name>
|
|
<description>Adds support for the BFC, BFI, SBFX, and UBFX instructions</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMPBRANCH_INSTRS</name>
|
|
<description>Indicates the supported combined Compare and Branch instructions</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CMPBRANCH_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CMPBRANCH_INSTRS_1</name>
|
|
<description>Adds support for the CBNZ and CBZ instructions</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COPROC_INSTRS</name>
|
|
<description>Indicates the supported Coprocessor instructions</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COPROC_INSTRS_0</name>
|
|
<description>None supported, except for separately attributed architectures, for example the Floating-point extension</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COPROC_INSTRS_1</name>
|
|
<description>Adds support for generic CDP, LDC, MCR, MRC, and STC instructions</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COPROC_INSTRS_2</name>
|
|
<description>As for 1, and adds support for generic CDP2, LDC2, MCR2, MRC2, and STC2 instructions</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COPROC_INSTRS_3</name>
|
|
<description>As for 2, and adds support for generic MCRR and MRRC instructions</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COPROC_INSTRS_4</name>
|
|
<description>As for 3, and adds support for generic MCRR2 and MRRC2 instructions</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEBUG_INSTRS</name>
|
|
<description>Indicates the supported Debug instructions</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DEBUG_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEBUG_INSTRS_1</name>
|
|
<description>Adds support for the BKPT instruction</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVIDE_INSTRS</name>
|
|
<description>Indicates the supported Divide instructions</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_INSTRS_1</name>
|
|
<description>Adds support for the SDIV and UDIV instructions</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_ISAR1</name>
|
|
<description>Instruction Set Attributes Register 1</description>
|
|
<addressOffset>0xD64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTEND_INSTRS</name>
|
|
<description>Indicates the supported Extend instructions</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EXTEND_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTEND_INSTRS_1</name>
|
|
<description>Adds support for the SXTB, SXTH, UXTB, and UXTH instructions</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTEND_INSTRS_2</name>
|
|
<description>As for 1, and adds support for the SXTAB, SXTAB16, SXTAH, SXTB16, UXTAB, UXTAB16, UXTAH, and UXTB16 instructions</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IFTHEN_INSTRS</name>
|
|
<description>Indicates the supported IfThen instructions</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IFTHEN_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IFTHEN_INSTRS_1</name>
|
|
<description>Adds support for the IT instructions, and for the IT bits in the PSRs</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMMEDIATE_INSTRS</name>
|
|
<description>Indicates the support for data-processing instructions with long immediate</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IMMEDIATE_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IMMEDIATE_INSTRS_1</name>
|
|
<description>Adds support for the ADDW, MOVW, MOVT, and SUBW instructions</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTERWORK_INSTRS</name>
|
|
<description>Indicates the supported Interworking instructions</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>INTERWORK_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERWORK_INSTRS_1</name>
|
|
<description>Adds support for the BX instruction, and the T bit in the PSR</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERWORK_INSTRS_2</name>
|
|
<description>As for 1, and adds support for the BLX instruction, and PC loads have BX-like behavior</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERWORK_INSTRS_3</name>
|
|
<description>ARMv7-M unused</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_ISAR2</name>
|
|
<description>Instruction Set Attributes Register 2</description>
|
|
<addressOffset>0xD68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOADSTORE_INSTRS</name>
|
|
<description>Indicates the supported additional load and store instructions</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOADSTORE_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOADSTORE_INSTRS_1</name>
|
|
<description>Adds support for the LDRD and STRD instructions</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEMHINT_INSTRS</name>
|
|
<description>Indicates the supported Memory Hint instructions</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MEMHINT_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEMHINT_INSTRS_1</name>
|
|
<description>Adds support for the PLD instruction, ARMv7-M unused.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEMHINT_INSTRS_2</name>
|
|
<description>As for 1, ARMv7-M unused.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEMHINT_INSTRS_3</name>
|
|
<description>As for 1 or 2, and adds support for the PLI instruction.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MULTIACCESSINT_INSTRS</name>
|
|
<description>Indicates the support for multi-access interruptible instructions</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MULTIACCESSINT_INSTRS_0</name>
|
|
<description>None supported. This means the LDM and STM instructions are not interruptible. ARMv7-M unused.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTIACCESSINT_INSTRS_1</name>
|
|
<description>LDM and STM instructions are restartable.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTIACCESSINT_INSTRS_2</name>
|
|
<description>LDM and STM instructions are continuable.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MULT_INSTRS</name>
|
|
<description>Indicates the supported additional Multiply instructions</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MULT_INSTRS_0</name>
|
|
<description>None supported. This means only MUL is supported. ARMv7-M unused.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULT_INSTRS_1</name>
|
|
<description>Adds support for the MLA instruction, ARMv7-M unused.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULT_INSTRS_2</name>
|
|
<description>As for 1, and adds support for the MLS instruction.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MULTS_INSTRS</name>
|
|
<description>Indicates the supported advanced signed Multiply instructions</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MULTS_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTS_INSTRS_1</name>
|
|
<description>Adds support for the SMULL and SMLAL instructions</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTS_INSTRS_2</name>
|
|
<description>As for 1, and adds support for the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTS_INSTRS_3</name>
|
|
<description>As for 2, and adds support for the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MULTU_INSTRS</name>
|
|
<description>Indicates the supported advanced unsigned Multiply instructions</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>MULTU_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTU_INSTRS_1</name>
|
|
<description>Adds support for the UMULL and UMLAL instructions.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MULTU_INSTRS_2</name>
|
|
<description>As for 1, and adds support for the UMAAL instruction.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REVERSAL_INSTRS</name>
|
|
<description>Indicates the supported Reversal instructions</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>REVERSAL_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REVERSAL_INSTRS_1</name>
|
|
<description>Adds support for the REV, REV16, and REVSH instructions, ARMv7-M unused.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REVERSAL_INSTRS_2</name>
|
|
<description>As for 1, and adds support for the RBIT instruction.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_ISAR3</name>
|
|
<description>Instruction Set Attributes Register 3</description>
|
|
<addressOffset>0xD6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SATURATE_INSTRS</name>
|
|
<description>Indicates the supported Saturate instructions</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SATURATE_INSTRS_0</name>
|
|
<description>None supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SATURATE_INSTRS_1</name>
|
|
<description>Adds support for the QADD, QDADD, QDSUB, and QSUB instructions, and for the Q bit in the PSRs.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIMD_INSTRS</name>
|
|
<description>Indicates the supported SIMD instructions</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SIMD_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIMD_INSTRS_1</name>
|
|
<description>Adds support for the SSAT and USAT instructions, and for the Q bit in the PSRs.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIMD_INSTRS_3</name>
|
|
<description>As for 1, and adds support for the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions. Also adds support for the GE[3:0] bits in the PSRs.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SVC_INSTRS</name>
|
|
<description>Indicates the supported SVC instructions</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SVC_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SVC_INSTRS_1</name>
|
|
<description>Adds support for the SVC instruction.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCHPRIM_INSTRS</name>
|
|
<description>Together with the ID_ISAR4[SYNCHPRIM_INSTRS_FRAC] indicates the supported Synchronization Primitives</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TABBRANCH_INSTRS</name>
|
|
<description>Indicates the supported Table Branch instructions</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TABBRANCH_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TABBRANCH_INSTRS_1</name>
|
|
<description>Adds support for the TBB and TBH instructions.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THUMBCOPY_INSTRS</name>
|
|
<description>Indicates the supported non flag-setting MOV instructions</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>THUMBCOPY_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THUMBCOPY_INSTRS_1</name>
|
|
<description>Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRUENOP_INSTRS</name>
|
|
<description>Indicates the supported non flag-setting MOV instructions</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TRUENOP_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRUENOP_INSTRS_1</name>
|
|
<description>Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ID_ISAR4</name>
|
|
<description>Instruction Set Attributes Register 4</description>
|
|
<addressOffset>0xD70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UNPRIV_INSTRS</name>
|
|
<description>Indicates the supported unprivileged instructions. These are the instruction variants indicated by a T suffix.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UNPRIV_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNPRIV_INSTRS_1</name>
|
|
<description>Adds support for the LDRBT, LDRT, STRBT, and STRT instructions.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNPRIV_INSTRS_2</name>
|
|
<description>As for 1, and adds support for the LDRHT, LDRSBT, LDRSHT, and STRHT instructions.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WITHSHIFTS_INSTRS</name>
|
|
<description>Indicates the support for instructions with shifts</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WITHSHIFTS_INSTRS_0</name>
|
|
<description>Nonzero shifts supported only in MOV and shift instructions.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WITHSHIFTS_INSTRS_1</name>
|
|
<description>Adds support for shifts of loads and stores over the range LSL 0-3.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WITHSHIFTS_INSTRS_3</name>
|
|
<description>As for 1, and adds support for other constant shift options, on loads, stores, and other instructions.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WITHSHIFTS_INSTRS_4</name>
|
|
<description>ARMv7-M unused.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WRITEBACK_INSTRS</name>
|
|
<description>Indicates the support for Writeback addressing modes</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WRITEBACK_INSTRS_0</name>
|
|
<description>Basic support. Only the LDM, STM, PUSH, and POP instructions support writeback addressing modes. ARMv7-M unused.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITEBACK_INSTRS_1</name>
|
|
<description>Adds support for all of the writeback addressing modes defined in the ARMv7-M architecture.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BARRIER_INSTRS</name>
|
|
<description>Indicates the supported Barrier instructions</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>BARRIER_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BARRIER_INSTRS_1</name>
|
|
<description>Adds support for the DMB, DSB, and ISB barrier instructions.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCHPRIM_INSTRS_FRAC</name>
|
|
<description>Together with the ID_ISAR3[SYNCHPRIM_INSTRS] indicates the supported Synchronization Primitives</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PSR_M_INSTRS</name>
|
|
<description>Indicates the supported M profile instructions to modify the PSRs</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PSR_M_INSTRS_0</name>
|
|
<description>None supported, ARMv7-M unused.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PSR_M_INSTRS_1</name>
|
|
<description>Adds support for the M-profile forms of the CPS, MRS, and MSR instructions, to access the PSRs.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLIDR</name>
|
|
<description>Cache Level ID register</description>
|
|
<addressOffset>0xD78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CL1</name>
|
|
<description>Indicate the type of cache implemented at level 1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CL1_0</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL1_1</name>
|
|
<description>Instruction cache only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL1_2</name>
|
|
<description>Data cache only</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL1_3</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL1_4</name>
|
|
<description>Unified cache</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CL2</name>
|
|
<description>Indicate the type of cache implemented at level 2.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CL2_0</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL2_1</name>
|
|
<description>Instruction cache only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL2_2</name>
|
|
<description>Data cache only</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL2_3</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL2_4</name>
|
|
<description>Unified cache</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CL3</name>
|
|
<description>Indicate the type of cache implemented at level 3.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CL3_0</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL3_1</name>
|
|
<description>Instruction cache only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL3_2</name>
|
|
<description>Data cache only</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL3_3</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL3_4</name>
|
|
<description>Unified cache</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CL4</name>
|
|
<description>Indicate the type of cache implemented at level 4.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CL4_0</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL4_1</name>
|
|
<description>Instruction cache only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL4_2</name>
|
|
<description>Data cache only</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL4_3</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL4_4</name>
|
|
<description>Unified cache</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CL5</name>
|
|
<description>Indicate the type of cache implemented at level 5.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CL5_0</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL5_1</name>
|
|
<description>Instruction cache only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL5_2</name>
|
|
<description>Data cache only</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL5_3</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL5_4</name>
|
|
<description>Unified cache</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CL6</name>
|
|
<description>Indicate the type of cache implemented at level 6.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CL6_0</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL6_1</name>
|
|
<description>Instruction cache only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL6_2</name>
|
|
<description>Data cache only</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL6_3</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL6_4</name>
|
|
<description>Unified cache</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CL7</name>
|
|
<description>Indicate the type of cache implemented at level 7.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CL7_0</name>
|
|
<description>No cache</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL7_1</name>
|
|
<description>Instruction cache only</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL7_2</name>
|
|
<description>Data cache only</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL7_3</name>
|
|
<description>Separate instruction and data caches</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CL7_4</name>
|
|
<description>Unified cache</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOUIS</name>
|
|
<description>Level of Unification Inner Shareable for the cache hierarchy. This field is RAZ.</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOUIS_0</name>
|
|
<description>0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOUIS_1</name>
|
|
<description>1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOUIS_2</name>
|
|
<description>2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOUIS_3</name>
|
|
<description>3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOUIS_4</name>
|
|
<description>4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOUIS_5</name>
|
|
<description>5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOUIS_6</name>
|
|
<description>6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOUIS_7</name>
|
|
<description>7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOC</name>
|
|
<description>Level of Coherency for the cache hierarchy</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOC_0</name>
|
|
<description>0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC_1</name>
|
|
<description>1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC_2</name>
|
|
<description>2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC_3</name>
|
|
<description>3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC_4</name>
|
|
<description>4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC_5</name>
|
|
<description>5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC_6</name>
|
|
<description>6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOC_7</name>
|
|
<description>7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOU</name>
|
|
<description>Level of Unification for the cache hierarchy</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LOU_0</name>
|
|
<description>0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOU_1</name>
|
|
<description>1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOU_2</name>
|
|
<description>2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOU_3</name>
|
|
<description>3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOU_4</name>
|
|
<description>4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOU_5</name>
|
|
<description>5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOU_6</name>
|
|
<description>6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOU_7</name>
|
|
<description>7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTR</name>
|
|
<description>Cache Type register</description>
|
|
<addressOffset>0xD7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x8000C000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMINLINE</name>
|
|
<description>Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DMINLINE</name>
|
|
<description>Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERG</name>
|
|
<description>Exclusives Reservation Granule. The maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions, encoded as Log2 of the number of words.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CWG</name>
|
|
<description>Cache Write-back Granule. The maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified, encoded as Log2 of the number of words.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FORMAT</name>
|
|
<description>Indicates the implemented CTR format.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FORMAT_4</name>
|
|
<description>ARMv7 format.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCSIDR</name>
|
|
<description>Cache Size ID Register</description>
|
|
<addressOffset>0xD80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LINESIZE</name>
|
|
<description>(Log2(Number of words in cache line)) - 2.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LINESIZE_0</name>
|
|
<description>The line length of 4 words.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINESIZE_1</name>
|
|
<description>The line length of 8 words.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINESIZE_2</name>
|
|
<description>The line length of 16 words.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINESIZE_3</name>
|
|
<description>The line length of 32 words.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINESIZE_4</name>
|
|
<description>The line length of 64 words.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINESIZE_5</name>
|
|
<description>The line length of 128 words.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINESIZE_6</name>
|
|
<description>The line length of 256 words.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LINESIZE_7</name>
|
|
<description>The line length of 512 words.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASSOCIATIVITY</name>
|
|
<description>(Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NUMSETS</name>
|
|
<description>(Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WA</name>
|
|
<description>Indicates whether the cache level supports write-allocation</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WA_0</name>
|
|
<description>Feature not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WA_1</name>
|
|
<description>Feature supported</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RA</name>
|
|
<description>Indicates whether the cache level supports read-allocation</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RA_0</name>
|
|
<description>Feature not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RA_1</name>
|
|
<description>Feature supported</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WB</name>
|
|
<description>Indicates whether the cache level supports write-back</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WB_0</name>
|
|
<description>Feature not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WB_1</name>
|
|
<description>Feature supported</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WT</name>
|
|
<description>Indicates whether the cache level supports write-through</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>WT_0</name>
|
|
<description>Feature not supported</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WT_1</name>
|
|
<description>Feature supported</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSSELR</name>
|
|
<description>Cache Size Selection Register</description>
|
|
<addressOffset>0xD84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IND</name>
|
|
<description>Instruction not data bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>IND_0</name>
|
|
<description>Data or unified cache.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IND_1</name>
|
|
<description>Instruction cache.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LEVEL</name>
|
|
<description>Cache level of required cache</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>LEVEL_0</name>
|
|
<description>Level 1 cache.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_1</name>
|
|
<description>Level 2 cache.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_2</name>
|
|
<description>Level 3 cache.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_3</name>
|
|
<description>Level 4 cache.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_4</name>
|
|
<description>Level 5 cache.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_5</name>
|
|
<description>Level 6 cache.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_6</name>
|
|
<description>Level 7 cache.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPACR</name>
|
|
<description>Coprocessor Access Control Register</description>
|
|
<addressOffset>0xD88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CP0</name>
|
|
<description>Access privileges for coprocessor 0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CP0_0</name>
|
|
<description>Access denied. Any attempted access generates a NOCP UsageFault.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP0_1</name>
|
|
<description>Privileged access only. An unprivileged access generates a NOCP UsageFault.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP0_3</name>
|
|
<description>Full access.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CP1</name>
|
|
<description>Access privileges for coprocessor 1.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CP1_0</name>
|
|
<description>Access denied. Any attempted access generates a NOCP UsageFault.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP1_1</name>
|
|
<description>Privileged access only. An unprivileged access generates a NOCP UsageFault.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP1_3</name>
|
|
<description>Full access.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CP2</name>
|
|
<description>Access privileges for coprocessor 2.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CP2_0</name>
|
|
<description>Access denied. Any attempted access generates a NOCP UsageFault.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP2_1</name>
|
|
<description>Privileged access only. An unprivileged access generates a NOCP UsageFault.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP2_3</name>
|
|
<description>Full access.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CP3</name>
|
|
<description>Access privileges for coprocessor 3.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CP3_0</name>
|
|
<description>Access denied. Any attempted access generates a NOCP UsageFault.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP3_1</name>
|
|
<description>Privileged access only. An unprivileged access generates a NOCP UsageFault.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP3_3</name>
|
|
<description>Full access.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CP4</name>
|
|
<description>Access privileges for coprocessor 4.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CP4_0</name>
|
|
<description>Access denied. Any attempted access generates a NOCP UsageFault.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP4_1</name>
|
|
<description>Privileged access only. An unprivileged access generates a NOCP UsageFault.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP4_3</name>
|
|
<description>Full access.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CP5</name>
|
|
<description>Access privileges for coprocessor 5.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CP5_0</name>
|
|
<description>Access denied. Any attempted access generates a NOCP UsageFault.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP5_1</name>
|
|
<description>Privileged access only. An unprivileged access generates a NOCP UsageFault.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP5_3</name>
|
|
<description>Full access.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CP6</name>
|
|
<description>Access privileges for coprocessor 6.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CP6_0</name>
|
|
<description>Access denied. Any attempted access generates a NOCP UsageFault.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP6_1</name>
|
|
<description>Privileged access only. An unprivileged access generates a NOCP UsageFault.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP6_3</name>
|
|
<description>Full access.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CP7</name>
|
|
<description>Access privileges for coprocessor 7.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CP7_0</name>
|
|
<description>Access denied. Any attempted access generates a NOCP UsageFault.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP7_1</name>
|
|
<description>Privileged access only. An unprivileged access generates a NOCP UsageFault.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP7_3</name>
|
|
<description>Full access.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CP10</name>
|
|
<description>Access privileges for coprocessor 10.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CP10_0</name>
|
|
<description>Access denied. Any attempted access generates a NOCP UsageFault.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP10_1</name>
|
|
<description>Privileged access only. An unprivileged access generates a NOCP UsageFault.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP10_3</name>
|
|
<description>Full access.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CP11</name>
|
|
<description>Access privileges for coprocessor 11.</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CP11_0</name>
|
|
<description>Access denied. Any attempted access generates a NOCP UsageFault.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP11_1</name>
|
|
<description>Privileged access only. An unprivileged access generates a NOCP UsageFault.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CP11_3</name>
|
|
<description>Full access.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STIR</name>
|
|
<description>Instruction cache invalidate all to Point of Unification (PoU)</description>
|
|
<addressOffset>0xF00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Indicates the interrupt to be triggered</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICIALLU</name>
|
|
<description>Instruction cache invalidate all to Point of Unification (PoU)</description>
|
|
<addressOffset>0xF50</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICIALLU</name>
|
|
<description>I-cache invalidate all to PoU</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICIMVAU</name>
|
|
<description>Instruction cache invalidate by address to PoU</description>
|
|
<addressOffset>0xF58</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICIMVAU</name>
|
|
<description>I-cache invalidate by MVA to PoU</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCIMVAC</name>
|
|
<description>Data cache invalidate by address to Point of Coherency (PoC)</description>
|
|
<addressOffset>0xF5C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCIMVAC</name>
|
|
<description>D-cache invalidate by MVA to PoC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCISW</name>
|
|
<description>Data cache invalidate by set/way</description>
|
|
<addressOffset>0xF60</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCISW</name>
|
|
<description>D-cache invalidate by set-way</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCMVAU</name>
|
|
<description>Data cache by address to PoU</description>
|
|
<addressOffset>0xF64</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCCMVAU</name>
|
|
<description>D-cache clean by MVA to PoU</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCMVAC</name>
|
|
<description>Data cache clean by address to PoC</description>
|
|
<addressOffset>0xF68</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCCMVAC</name>
|
|
<description>D-cache clean by MVA to PoC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCSW</name>
|
|
<description>Data cache clean by set/way</description>
|
|
<addressOffset>0xF6C</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCCSW</name>
|
|
<description>D-cache clean by set-way</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCIMVAC</name>
|
|
<description>Data cache clean and invalidate by address to PoC</description>
|
|
<addressOffset>0xF70</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCCIMVAC</name>
|
|
<description>D-cache clean and invalidate by MVA to PoC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCCISW</name>
|
|
<description>Data cache clean and invalidate by set/way</description>
|
|
<addressOffset>0xF74</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCCISW</name>
|
|
<description>D-cache clean and invalidate by set-way</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CM7_ITCMCR</name>
|
|
<description>Instruction Tightly-Coupled Memory Control Register</description>
|
|
<addressOffset>0xF90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>TCM enable. When a TCM is disabled all accesses are made to the AXIM interface.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN_0</name>
|
|
<description>TCM disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_1</name>
|
|
<description>TCM enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RMW</name>
|
|
<description>Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RMW_0</name>
|
|
<description>RMW disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RMW_1</name>
|
|
<description>RMW enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RETEN</name>
|
|
<description>Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RETEN_0</name>
|
|
<description>Retry phase disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETEN_1</name>
|
|
<description>Retry phase enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SZ</name>
|
|
<description>TCM size. Indicates the size of the relevant TCM.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SZ_0</name>
|
|
<description>No TCM implemented.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_3</name>
|
|
<description>4KB.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_4</name>
|
|
<description>8KB.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_5</name>
|
|
<description>16KB.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_6</name>
|
|
<description>32KB.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_7</name>
|
|
<description>64KB.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_8</name>
|
|
<description>128KB.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_9</name>
|
|
<description>256KB.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_10</name>
|
|
<description>512KB.</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_11</name>
|
|
<description>1MB.</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_12</name>
|
|
<description>2MB.</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_13</name>
|
|
<description>4MB.</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_14</name>
|
|
<description>8MB.</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_15</name>
|
|
<description>16MB.</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CM7_DTCMCR</name>
|
|
<description>Data Tightly-Coupled Memory Control Register</description>
|
|
<addressOffset>0xF94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>TCM enable. When a TCM is disabled all accesses are made to the AXIM interface.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN_0</name>
|
|
<description>TCM disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_1</name>
|
|
<description>TCM enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RMW</name>
|
|
<description>Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RMW_0</name>
|
|
<description>RMW disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RMW_1</name>
|
|
<description>RMW enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RETEN</name>
|
|
<description>Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>RETEN_0</name>
|
|
<description>Retry phase disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RETEN_1</name>
|
|
<description>Retry phase enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SZ</name>
|
|
<description>TCM size. Indicates the size of the relevant TCM.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SZ_0</name>
|
|
<description>No TCM implemented.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_3</name>
|
|
<description>4KB.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_4</name>
|
|
<description>8KB.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_5</name>
|
|
<description>16KB.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_6</name>
|
|
<description>32KB.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_7</name>
|
|
<description>64KB.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_8</name>
|
|
<description>128KB.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_9</name>
|
|
<description>256KB.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_10</name>
|
|
<description>512KB.</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_11</name>
|
|
<description>1MB.</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_12</name>
|
|
<description>2MB.</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_13</name>
|
|
<description>4MB.</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_14</name>
|
|
<description>8MB.</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_15</name>
|
|
<description>16MB.</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CM7_AHBPCR</name>
|
|
<description>AHBP Control Register</description>
|
|
<addressOffset>0xF98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>AHBP enable.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>EN_0</name>
|
|
<description>AHBP disabled. When disabled all accesses are made to the AXIM interface.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EN_1</name>
|
|
<description>AHBP enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SZ</name>
|
|
<description>AHBP size.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SZ_0</name>
|
|
<description>0MB. AHBP disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_1</name>
|
|
<description>64MB.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_2</name>
|
|
<description>128MB.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_3</name>
|
|
<description>256MB.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SZ_4</name>
|
|
<description>512MB.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CM7_CACR</name>
|
|
<description>L1 Cache Control Register</description>
|
|
<addressOffset>0xF9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIWT</name>
|
|
<description>Shared cacheable-is-WT for data cache. Enables limited cache coherency usage.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SIWT_0</name>
|
|
<description>Normal Cacheable Shared locations are treated as being Non-cacheable. Default mode of operation for Shared memory.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SIWT_1</name>
|
|
<description>Normal Cacheable shared locations are treated as Write-Through.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECCDIS</name>
|
|
<description>Enables ECC in the instruction and data cache.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ECCDIS_0</name>
|
|
<description>Enables ECC in the instruction and data cache.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ECCDIS_1</name>
|
|
<description>Disables ECC in the instruction and data cache.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FORCEWT</name>
|
|
<description>Enables Force Write-Through in the data cache.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>FORCEWT_0</name>
|
|
<description>Disables Force Write-Through.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCEWT_1</name>
|
|
<description>Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CM7_AHBSCR</name>
|
|
<description>AHB Slave Control Register</description>
|
|
<addressOffset>0xFA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTL</name>
|
|
<description>AHBS prioritization control.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>CTL_0</name>
|
|
<description>AHBS access priority demoted. This is the reset value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTL_1</name>
|
|
<description>Software access priority demoted.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTL_2</name>
|
|
<description>AHBS access priority demoted by initializing the fairness counter to the CM7_AHBSCR[INITCOUNT] value when the software execution priority is higher than or equal to the threshold level programed in CM7_AHBSCR[TPRI].</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTL_3</name>
|
|
<description>AHBSPRI signal has control of access priority.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPRI</name>
|
|
<description>Threshold execution priority for AHBS traffic demotion.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INITCOUNT</name>
|
|
<description>Fairness counter initialization value.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CM7_ABFSR</name>
|
|
<description>Auxiliary Bus Fault Status Register</description>
|
|
<addressOffset>0xFA8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ITCM</name>
|
|
<description>Asynchronous fault on ITCM interface.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTCM</name>
|
|
<description>Asynchronous fault on DTCM interface.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBP</name>
|
|
<description>Asynchronous fault on AHBP interface.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AXIM</name>
|
|
<description>Asynchronous fault on AXIM interface.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPPB</name>
|
|
<description>Asynchronous fault on EPPB interface.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AXIMTYPE</name>
|
|
<description>Indicates the type of fault on the AXIM interface. Only valid when AXIM is 1.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>AXIMTYPE_0</name>
|
|
<description>OKAY.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AXIMTYPE_1</name>
|
|
<description>EXOKAY.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AXIMTYPE_2</name>
|
|
<description>SLVERR.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AXIMTYPE_3</name>
|
|
<description>DECERR.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>NVIC</name>
|
|
<description>Nested Vectored Interrupt Controller</description>
|
|
<groupName>NVIC</groupName>
|
|
<baseAddress>0xE000E100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xE04</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMA0</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA2</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA3</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA4</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA5</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA6</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA7</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA8</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA9</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA10</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA11</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA12</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA13</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA14</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA15</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_ERROR</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CTI0_ERROR</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CTI1_ERROR</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CORE</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>LPUART1</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>LPUART2</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>LPUART3</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>LPUART4</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIT</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USB_OTG1</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>FLEXSPI</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>FLEXRAM</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>LPI2C1</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>LPI2C2</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>GPT1</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>GPT2</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>LPSPI1</name>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>LPSPI2</name>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PWM1_0</name>
|
|
<value>34</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PWM1_1</name>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PWM1_2</name>
|
|
<value>36</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PWM1_3</name>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PWM1_FAULT</name>
|
|
<value>38</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>KPP</name>
|
|
<value>39</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SRC</name>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>GPR_IRQ</name>
|
|
<value>41</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CCM_1</name>
|
|
<value>42</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CCM_2</name>
|
|
<value>43</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EWM</name>
|
|
<value>44</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>WDOG2</name>
|
|
<value>45</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SNVS_HP_WRAPPER</name>
|
|
<value>46</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SNVS_HP_WRAPPER_TZ</name>
|
|
<value>47</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SNVS_LP_WRAPPER</name>
|
|
<value>48</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CSU</name>
|
|
<value>49</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DCP</name>
|
|
<value>50</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DCP_VMI</name>
|
|
<value>51</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>Reserved68</name>
|
|
<value>52</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TRNG</name>
|
|
<value>53</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>Reserved70</name>
|
|
<value>54</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>Reserved71</name>
|
|
<value>55</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SAI1</name>
|
|
<value>56</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>RTWDOG</name>
|
|
<value>57</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SAI3_RX</name>
|
|
<value>58</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SAI3_TX</name>
|
|
<value>59</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>SPDIF</name>
|
|
<value>60</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PMU</name>
|
|
<value>61</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>XBAR1_IRQ_0_1_2_3</name>
|
|
<value>62</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TEMP_LOW_HIGH</name>
|
|
<value>63</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TEMP_PANIC</name>
|
|
<value>64</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USB_PHY</name>
|
|
<value>65</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>GPC</name>
|
|
<value>66</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC1</name>
|
|
<value>67</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>FLEXIO1</name>
|
|
<value>68</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DCDC</name>
|
|
<value>69</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>GPIO1_Combined_0_15</name>
|
|
<value>70</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>GPIO1_Combined_16_31</name>
|
|
<value>71</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>GPIO2_Combined_0_15</name>
|
|
<value>72</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>GPIO5_Combined_0_15</name>
|
|
<value>73</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>WDOG1</name>
|
|
<value>74</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC_ETC_IRQ0</name>
|
|
<value>75</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC_ETC_IRQ1</name>
|
|
<value>76</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC_ETC_IRQ2</name>
|
|
<value>77</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC_ETC_IRQ3</name>
|
|
<value>78</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ADC_ETC_ERROR_IRQ</name>
|
|
<value>79</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>NVICISER0</name>
|
|
<description>Interrupt Set Enable Register n</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>Interrupt set enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISER1</name>
|
|
<description>Interrupt Set Enable Register n</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>Interrupt set enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISER2</name>
|
|
<description>Interrupt Set Enable Register n</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>Interrupt set enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISER3</name>
|
|
<description>Interrupt Set Enable Register n</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>Interrupt set enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICER0</name>
|
|
<description>Interrupt Clear Enable Register n</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>Interrupt clear-enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICER1</name>
|
|
<description>Interrupt Clear Enable Register n</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>Interrupt clear-enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICER2</name>
|
|
<description>Interrupt Clear Enable Register n</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>Interrupt clear-enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICER3</name>
|
|
<description>Interrupt Clear Enable Register n</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>Interrupt clear-enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISPR0</name>
|
|
<description>Interrupt Set Pending Register n</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>Interrupt set-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISPR1</name>
|
|
<description>Interrupt Set Pending Register n</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>Interrupt set-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISPR2</name>
|
|
<description>Interrupt Set Pending Register n</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>Interrupt set-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICISPR3</name>
|
|
<description>Interrupt Set Pending Register n</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>Interrupt set-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICPR0</name>
|
|
<description>Interrupt Clear Pending Register n</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>Interrupt clear-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICPR1</name>
|
|
<description>Interrupt Clear Pending Register n</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>Interrupt clear-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICPR2</name>
|
|
<description>Interrupt Clear Pending Register n</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>Interrupt clear-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICICPR3</name>
|
|
<description>Interrupt Clear Pending Register n</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>Interrupt clear-pending bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<modifiedWriteValues>oneToClear</modifiedWriteValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIABR0</name>
|
|
<description>Interrupt Active bit Register n</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Interrupt active flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIABR1</name>
|
|
<description>Interrupt Active bit Register n</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Interrupt active flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIABR2</name>
|
|
<description>Interrupt Active bit Register n</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Interrupt active flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIABR3</name>
|
|
<description>Interrupt Active bit Register n</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Interrupt active flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP0</name>
|
|
<description>Interrupt Priority Register 0</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI0</name>
|
|
<description>Priority of the INT_DMA0 interrupt 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP1</name>
|
|
<description>Interrupt Priority Register 1</description>
|
|
<addressOffset>0x301</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI1</name>
|
|
<description>Priority of the INT_DMA1 interrupt 1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP2</name>
|
|
<description>Interrupt Priority Register 2</description>
|
|
<addressOffset>0x302</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI2</name>
|
|
<description>Priority of the INT_DMA2 interrupt 2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP3</name>
|
|
<description>Interrupt Priority Register 3</description>
|
|
<addressOffset>0x303</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI3</name>
|
|
<description>Priority of the INT_DMA3 interrupt 3</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP4</name>
|
|
<description>Interrupt Priority Register 4</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI4</name>
|
|
<description>Priority of the INT_DMA4 interrupt 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP5</name>
|
|
<description>Interrupt Priority Register 5</description>
|
|
<addressOffset>0x305</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI5</name>
|
|
<description>Priority of the INT_DMA5 interrupt 5</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP6</name>
|
|
<description>Interrupt Priority Register 6</description>
|
|
<addressOffset>0x306</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI6</name>
|
|
<description>Priority of the INT_DMA6 interrupt 6</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP7</name>
|
|
<description>Interrupt Priority Register 7</description>
|
|
<addressOffset>0x307</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI7</name>
|
|
<description>Priority of the INT_DMA7 interrupt 7</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP8</name>
|
|
<description>Interrupt Priority Register 8</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI8</name>
|
|
<description>Priority of the INT_DMA8 interrupt 8</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP9</name>
|
|
<description>Interrupt Priority Register 9</description>
|
|
<addressOffset>0x309</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI9</name>
|
|
<description>Priority of the INT_DMA9 interrupt 9</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP10</name>
|
|
<description>Interrupt Priority Register 10</description>
|
|
<addressOffset>0x30A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI10</name>
|
|
<description>Priority of the INT_DMA10 interrupt 10</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP11</name>
|
|
<description>Interrupt Priority Register 11</description>
|
|
<addressOffset>0x30B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI11</name>
|
|
<description>Priority of the INT_DMA11 interrupt 11</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP12</name>
|
|
<description>Interrupt Priority Register 12</description>
|
|
<addressOffset>0x30C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI12</name>
|
|
<description>Priority of the INT_DMA12 interrupt 12</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP13</name>
|
|
<description>Interrupt Priority Register 13</description>
|
|
<addressOffset>0x30D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI13</name>
|
|
<description>Priority of the INT_DMA13 interrupt 13</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP14</name>
|
|
<description>Interrupt Priority Register 14</description>
|
|
<addressOffset>0x30E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI14</name>
|
|
<description>Priority of the INT_DMA14 interrupt 14</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP15</name>
|
|
<description>Interrupt Priority Register 15</description>
|
|
<addressOffset>0x30F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI15</name>
|
|
<description>Priority of the INT_DMA15 interrupt 15</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP16</name>
|
|
<description>Interrupt Priority Register 16</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI16</name>
|
|
<description>Priority of the INT_DMA_ERROR interrupt 16</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP17</name>
|
|
<description>Interrupt Priority Register 17</description>
|
|
<addressOffset>0x311</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI17</name>
|
|
<description>Priority of the INT_CTI0_ERROR interrupt 17</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP18</name>
|
|
<description>Interrupt Priority Register 18</description>
|
|
<addressOffset>0x312</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI18</name>
|
|
<description>Priority of the INT_CTI1_ERROR interrupt 18</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP19</name>
|
|
<description>Interrupt Priority Register 19</description>
|
|
<addressOffset>0x313</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI19</name>
|
|
<description>Priority of the INT_CORE interrupt 19</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP20</name>
|
|
<description>Interrupt Priority Register 20</description>
|
|
<addressOffset>0x314</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI20</name>
|
|
<description>Priority of the INT_LPUART1 interrupt 20</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP21</name>
|
|
<description>Interrupt Priority Register 21</description>
|
|
<addressOffset>0x315</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI21</name>
|
|
<description>Priority of the INT_LPUART2 interrupt 21</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP22</name>
|
|
<description>Interrupt Priority Register 22</description>
|
|
<addressOffset>0x316</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI22</name>
|
|
<description>Priority of the INT_LPUART3 interrupt 22</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP23</name>
|
|
<description>Interrupt Priority Register 23</description>
|
|
<addressOffset>0x317</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI23</name>
|
|
<description>Priority of the INT_LPUART4 interrupt 23</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP24</name>
|
|
<description>Interrupt Priority Register 24</description>
|
|
<addressOffset>0x318</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI24</name>
|
|
<description>Priority of the INT_PIT interrupt 24</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP25</name>
|
|
<description>Interrupt Priority Register 25</description>
|
|
<addressOffset>0x319</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI25</name>
|
|
<description>Priority of the INT_USB_OTG1 interrupt 25</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP26</name>
|
|
<description>Interrupt Priority Register 26</description>
|
|
<addressOffset>0x31A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI26</name>
|
|
<description>Priority of the INT_FLEXSPI interrupt 26</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP27</name>
|
|
<description>Interrupt Priority Register 27</description>
|
|
<addressOffset>0x31B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI27</name>
|
|
<description>Priority of the INT_FLEXRAM interrupt 27</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP28</name>
|
|
<description>Interrupt Priority Register 28</description>
|
|
<addressOffset>0x31C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI28</name>
|
|
<description>Priority of the INT_LPI2C1 interrupt 28</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP29</name>
|
|
<description>Interrupt Priority Register 29</description>
|
|
<addressOffset>0x31D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI29</name>
|
|
<description>Priority of the INT_LPI2C2 interrupt 29</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP30</name>
|
|
<description>Interrupt Priority Register 30</description>
|
|
<addressOffset>0x31E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI30</name>
|
|
<description>Priority of the INT_GPT1 interrupt 30</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP31</name>
|
|
<description>Interrupt Priority Register 31</description>
|
|
<addressOffset>0x31F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI31</name>
|
|
<description>Priority of the INT_GPT2 interrupt 31</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP32</name>
|
|
<description>Interrupt Priority Register 32</description>
|
|
<addressOffset>0x320</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI32</name>
|
|
<description>Priority of the INT_LPSPI1 interrupt 32</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP33</name>
|
|
<description>Interrupt Priority Register 33</description>
|
|
<addressOffset>0x321</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI33</name>
|
|
<description>Priority of the INT_LPSPI2 interrupt 33</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP34</name>
|
|
<description>Interrupt Priority Register 34</description>
|
|
<addressOffset>0x322</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI34</name>
|
|
<description>Priority of the INT_PWM1_0 interrupt 34</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP35</name>
|
|
<description>Interrupt Priority Register 35</description>
|
|
<addressOffset>0x323</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI35</name>
|
|
<description>Priority of the INT_PWM1_1 interrupt 35</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP36</name>
|
|
<description>Interrupt Priority Register 36</description>
|
|
<addressOffset>0x324</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI36</name>
|
|
<description>Priority of the INT_PWM1_2 interrupt 36</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP37</name>
|
|
<description>Interrupt Priority Register 37</description>
|
|
<addressOffset>0x325</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI37</name>
|
|
<description>Priority of the INT_PWM1_3 interrupt 37</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP38</name>
|
|
<description>Interrupt Priority Register 38</description>
|
|
<addressOffset>0x326</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI38</name>
|
|
<description>Priority of the INT_PWM1_FAULT interrupt 38</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP39</name>
|
|
<description>Interrupt Priority Register 39</description>
|
|
<addressOffset>0x327</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI39</name>
|
|
<description>Priority of the INT_KPP interrupt 39</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP40</name>
|
|
<description>Interrupt Priority Register 40</description>
|
|
<addressOffset>0x328</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI40</name>
|
|
<description>Priority of the INT_SRC interrupt 40</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP41</name>
|
|
<description>Interrupt Priority Register 41</description>
|
|
<addressOffset>0x329</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI41</name>
|
|
<description>Priority of the INT_GPR_IRQ interrupt 41</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP42</name>
|
|
<description>Interrupt Priority Register 42</description>
|
|
<addressOffset>0x32A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI42</name>
|
|
<description>Priority of the INT_CCM_1 interrupt 42</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP43</name>
|
|
<description>Interrupt Priority Register 43</description>
|
|
<addressOffset>0x32B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI43</name>
|
|
<description>Priority of the INT_CCM_2 interrupt 43</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP44</name>
|
|
<description>Interrupt Priority Register 44</description>
|
|
<addressOffset>0x32C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI44</name>
|
|
<description>Priority of the INT_EWM interrupt 44</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP45</name>
|
|
<description>Interrupt Priority Register 45</description>
|
|
<addressOffset>0x32D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI45</name>
|
|
<description>Priority of the INT_WDOG2 interrupt 45</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP46</name>
|
|
<description>Interrupt Priority Register 46</description>
|
|
<addressOffset>0x32E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI46</name>
|
|
<description>Priority of the INT_SNVS_HP_WRAPPER interrupt 46</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP47</name>
|
|
<description>Interrupt Priority Register 47</description>
|
|
<addressOffset>0x32F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI47</name>
|
|
<description>Priority of the INT_SNVS_HP_WRAPPER_TZ interrupt 47</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP48</name>
|
|
<description>Interrupt Priority Register 48</description>
|
|
<addressOffset>0x330</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI48</name>
|
|
<description>Priority of the INT_SNVS_LP_WRAPPER interrupt 48</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP49</name>
|
|
<description>Interrupt Priority Register 49</description>
|
|
<addressOffset>0x331</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI49</name>
|
|
<description>Priority of the INT_CSU interrupt 49</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP50</name>
|
|
<description>Interrupt Priority Register 50</description>
|
|
<addressOffset>0x332</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI50</name>
|
|
<description>Priority of the INT_DCP interrupt 50</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP51</name>
|
|
<description>Interrupt Priority Register 51</description>
|
|
<addressOffset>0x333</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI51</name>
|
|
<description>Priority of the INT_DCP_VMI interrupt 51</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP52</name>
|
|
<description>Interrupt Priority Register 52</description>
|
|
<addressOffset>0x334</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI52</name>
|
|
<description>Priority of the INT_Reserved68 interrupt 52</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP53</name>
|
|
<description>Interrupt Priority Register 53</description>
|
|
<addressOffset>0x335</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI53</name>
|
|
<description>Priority of the INT_TRNG interrupt 53</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP54</name>
|
|
<description>Interrupt Priority Register 54</description>
|
|
<addressOffset>0x336</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI54</name>
|
|
<description>Priority of the INT_Reserved70 interrupt 54</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP55</name>
|
|
<description>Interrupt Priority Register 55</description>
|
|
<addressOffset>0x337</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI55</name>
|
|
<description>Priority of the INT_Reserved71 interrupt 55</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP56</name>
|
|
<description>Interrupt Priority Register 56</description>
|
|
<addressOffset>0x338</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI56</name>
|
|
<description>Priority of the INT_SAI1 interrupt 56</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP57</name>
|
|
<description>Interrupt Priority Register 57</description>
|
|
<addressOffset>0x339</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI57</name>
|
|
<description>Priority of the INT_RTWDOG interrupt 57</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP58</name>
|
|
<description>Interrupt Priority Register 58</description>
|
|
<addressOffset>0x33A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI58</name>
|
|
<description>Priority of the INT_SAI3_RX interrupt 58</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP59</name>
|
|
<description>Interrupt Priority Register 59</description>
|
|
<addressOffset>0x33B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI59</name>
|
|
<description>Priority of the INT_SAI3_TX interrupt 59</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP60</name>
|
|
<description>Interrupt Priority Register 60</description>
|
|
<addressOffset>0x33C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI60</name>
|
|
<description>Priority of the INT_SPDIF interrupt 60</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP61</name>
|
|
<description>Interrupt Priority Register 61</description>
|
|
<addressOffset>0x33D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI61</name>
|
|
<description>Priority of the INT_PMU interrupt 61</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP62</name>
|
|
<description>Interrupt Priority Register 62</description>
|
|
<addressOffset>0x33E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI62</name>
|
|
<description>Priority of the INT_XBAR1_IRQ_0_1_2_3 interrupt 62</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP63</name>
|
|
<description>Interrupt Priority Register 63</description>
|
|
<addressOffset>0x33F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI63</name>
|
|
<description>Priority of the INT_TEMP_LOW_HIGH interrupt 63</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP64</name>
|
|
<description>Interrupt Priority Register 64</description>
|
|
<addressOffset>0x340</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI64</name>
|
|
<description>Priority of the INT_TEMP_PANIC interrupt 64</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP65</name>
|
|
<description>Interrupt Priority Register 65</description>
|
|
<addressOffset>0x341</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI65</name>
|
|
<description>Priority of the INT_USB_PHY interrupt 65</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP66</name>
|
|
<description>Interrupt Priority Register 66</description>
|
|
<addressOffset>0x342</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI66</name>
|
|
<description>Priority of the INT_GPC interrupt 66</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP67</name>
|
|
<description>Interrupt Priority Register 67</description>
|
|
<addressOffset>0x343</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI67</name>
|
|
<description>Priority of the INT_ADC1 interrupt 67</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP68</name>
|
|
<description>Interrupt Priority Register 68</description>
|
|
<addressOffset>0x344</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI68</name>
|
|
<description>Priority of the INT_FLEXIO1 interrupt 68</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP69</name>
|
|
<description>Interrupt Priority Register 69</description>
|
|
<addressOffset>0x345</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI69</name>
|
|
<description>Priority of the INT_DCDC interrupt 69</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP70</name>
|
|
<description>Interrupt Priority Register 70</description>
|
|
<addressOffset>0x346</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI70</name>
|
|
<description>Priority of the INT_GPIO1_Combined_0_15 interrupt 70</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP71</name>
|
|
<description>Interrupt Priority Register 71</description>
|
|
<addressOffset>0x347</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI71</name>
|
|
<description>Priority of the INT_GPIO1_Combined_16_31 interrupt 71</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP72</name>
|
|
<description>Interrupt Priority Register 72</description>
|
|
<addressOffset>0x348</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI72</name>
|
|
<description>Priority of the INT_GPIO2_Combined_0_15 interrupt 72</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP73</name>
|
|
<description>Interrupt Priority Register 73</description>
|
|
<addressOffset>0x349</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI73</name>
|
|
<description>Priority of the INT_GPIO5_Combined_0_15 interrupt 73</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP74</name>
|
|
<description>Interrupt Priority Register 74</description>
|
|
<addressOffset>0x34A</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI74</name>
|
|
<description>Priority of the INT_WDOG1 interrupt 74</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP75</name>
|
|
<description>Interrupt Priority Register 75</description>
|
|
<addressOffset>0x34B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI75</name>
|
|
<description>Priority of the INT_ADC_ETC_IRQ0 interrupt 75</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP76</name>
|
|
<description>Interrupt Priority Register 76</description>
|
|
<addressOffset>0x34C</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI76</name>
|
|
<description>Priority of the INT_ADC_ETC_IRQ1 interrupt 76</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP77</name>
|
|
<description>Interrupt Priority Register 77</description>
|
|
<addressOffset>0x34D</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI77</name>
|
|
<description>Priority of the INT_ADC_ETC_IRQ2 interrupt 77</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP78</name>
|
|
<description>Interrupt Priority Register 78</description>
|
|
<addressOffset>0x34E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI78</name>
|
|
<description>Priority of the INT_ADC_ETC_IRQ3 interrupt 78</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICIP79</name>
|
|
<description>Interrupt Priority Register 79</description>
|
|
<addressOffset>0x34F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRI79</name>
|
|
<description>Priority of the INT_ADC_ETC_ERROR_IRQ interrupt 79</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NVICSTIR</name>
|
|
<description>Software Trigger Interrupt Register</description>
|
|
<addressOffset>0xE00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device> |