nxp.com MIMXRT1011 1.0 MIMXRT1011DAE5A Copyright 2016-2019 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause CM7 r0p1 little true true true 4 false 8 32 AIPSTZ1 AIPSTZ Control Registers AIPSTZ AIPSTZ1_ AIPSTZ 0x4007C000 0 0x54 registers MPR Master Priviledge Registers 0 32 read-write 0x77000000 0xFFFFFFFF MPROT5 Master 5 Priviledge, Buffer, Read, Write Control. 8 4 read-write MPL0 Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. #xxx0 MPL1 Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. #xxx1 MPROT3 Master 3 Priviledge, Buffer, Read, Write Control. 16 4 read-write MPL0 Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. #xxx0 MPL1 Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. #xxx1 MPROT2 Master 2 Priviledge, Buffer, Read, Write Control 20 4 read-write MPL0 Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. #xxx0 MPL1 Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. #xxx1 MPROT1 Master 1 Priviledge, Buffer, Read, Write Control 24 4 read-write MPL0 Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. #xxx0 MPL1 Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. #xxx1 MPROT0 Master 0 Priviledge, Buffer, Read, Write Control 28 4 read-write MPL0 Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. #xxx0 MPL1 Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. #xxx1 OPACR Off-Platform Peripheral Access Control Registers 0x40 32 read-write 0x44444444 0xFFFFFFFF OPAC7 Off-platform Peripheral Access Control 7 0 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC6 Off-platform Peripheral Access Control 6 4 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC5 Off-platform Peripheral Access Control 5 8 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC4 Off-platform Peripheral Access Control 4 12 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC3 Off-platform Peripheral Access Control 3 16 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC2 Off-platform Peripheral Access Control 2 20 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC1 Off-platform Peripheral Access Control 1 24 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC0 Off-platform Peripheral Access Control 0 28 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPACR1 Off-Platform Peripheral Access Control Registers 0x44 32 read-write 0x44444444 0xFFFFFFFF OPAC15 Off-platform Peripheral Access Control 15 0 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC14 Off-platform Peripheral Access Control 14 4 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC13 Off-platform Peripheral Access Control 13 8 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC12 Off-platform Peripheral Access Control 12 12 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC11 Off-platform Peripheral Access Control 11 16 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC10 Off-platform Peripheral Access Control 10 20 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC9 Off-platform Peripheral Access Control 9 24 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC8 Off-platform Peripheral Access Control 8 28 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPACR2 Off-Platform Peripheral Access Control Registers 0x48 32 read-write 0x44444444 0xFFFFFFFF OPAC23 Off-platform Peripheral Access Control 23 0 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC22 Off-platform Peripheral Access Control 22 4 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC21 Off-platform Peripheral Access Control 21 8 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC20 Off-platform Peripheral Access Control 20 12 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC19 Off-platform Peripheral Access Control 19 16 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC18 Off-platform Peripheral Access Control 18 20 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC17 Off-platform Peripheral Access Control 17 24 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC16 Off-platform Peripheral Access Control 16 28 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPACR3 Off-Platform Peripheral Access Control Registers 0x4C 32 read-write 0x44444444 0xFFFFFFFF OPAC31 Off-platform Peripheral Access Control 31 0 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC30 Off-platform Peripheral Access Control 30 4 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC29 Off-platform Peripheral Access Control 29 8 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC28 Off-platform Peripheral Access Control 28 12 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC27 Off-platform Peripheral Access Control 27 16 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC26 Off-platform Peripheral Access Control 26 20 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC25 Off-platform Peripheral Access Control 25 24 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC24 Off-platform Peripheral Access Control 24 28 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPACR4 Off-Platform Peripheral Access Control Registers 0x50 32 read-write 0x44444444 0xFFFFFFFF OPAC33 Off-platform Peripheral Access Control 33 24 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 OPAC32 Off-platform Peripheral Access Control 32 28 4 read-write TP0 Accesses from an untrusted master are allowed. #xxx0 TP1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. #xxx1 AIPSTZ2 AIPSTZ Control Registers AIPSTZ AIPSTZ2_ 0x4017C000 0 0x54 registers DCDC DCDC DCDC 0x40080000 0 0x1000 registers DCDC 69 REG0 DCDC Register 0 0 32 read-write 0x14030111 0xFFFFFFFF PWD_ZCD power down the zero cross detection function for discontinuous conductor mode 0 1 read-write DISABLE_AUTO_CLK_SWITCH Disable automatic clock switch from internal osc to xtal clock. 1 1 read-write SEL_CLK select 24 MHz Crystal clock for DCDC, when dcdc_disable_auto_clk_switch is set. 2 1 read-write PWD_OSC_INT Power down internal osc. Only set this bit, when 24 MHz crystal osc is available 3 1 read-write PWD_CUR_SNS_CMP The power down signal of the current detector. 4 1 read-write CUR_SNS_THRSH Set the threshold of current detector, if the peak current of the inductor exceeds the threshold, the current detector will assert 5 3 read-write PWD_OVERCUR_DET power down overcurrent detection comparator 8 1 read-write OVERCUR_TRIG_ADJ The threshold of over current detection in run mode and power save mode: run mode power save mode 0x0 1 A 0 9 2 read-write PWD_CMP_BATT_DET set to "1" to power down the low voltage detection comparator 11 1 read-write ADJ_POSLIMIT_BUCK adjust value to poslimit_buck register 12 4 read-write EN_LP_OVERLOAD_SNS enable the overload detection in power save mode, if current is larger than the overloading threshold (typical value is 50 mA), DCDC will switch to the run mode automatically 16 1 read-write PWD_HIGH_VOLT_DET power down overvoltage detection comparator 17 1 read-write LP_OVERLOAD_THRSH the threshold of the counting number of charging times during the period that lp_overload_freq_sel sets in power save mode 18 2 read-write LP_OVERLOAD_FREQ_SEL the period of counting the charging times in power save mode 0: eight 32k cycle 1: sixteen 32k cycle 20 1 read-write LP_HIGH_HYS Adjust hysteretic value in low power from 12.5mV to 25mV 21 1 read-write PWD_CMP_OFFSET power down output range comparator 26 1 read-write XTALOK_DISABLE 1'b1: Disable xtalok detection circuit 1'b0: Enable xtalok detection circuit 27 1 read-write CURRENT_ALERT_RESET reset current alert signal 28 1 read-write XTAL_24M_OK set to 1 to switch internal ring osc to xtal 24M 29 1 read-write STS_DC_OK Status register to indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling 31 1 read-only REG1 DCDC Register 1 0x4 32 read-write 0x111BA29C 0xFFFFFFFF REG_FBK_SEL select the feedback point of the internal regulator 7 2 read-write REG_RLOAD_SW control the load resistor of the internal regulator of DCDC, the load resistor is connected as default "1", and need set to "0" to disconnect the load resistor 9 1 read-write LP_CMP_ISRC_SEL set the current bias of low power comparator 0x0: 50 nA 0x1: 100 nA 0x2: 200 nA 0x3: 400 nA 12 2 read-write LOOPCTRL_HST_THRESH increase the threshold detection for common mode analog comparator 21 1 read-write LOOPCTRL_EN_HYST Enable hysteresis in switching converter common mode analog comparators 23 1 read-write VBG_TRIM trim bandgap voltage 24 5 read-write REG2 DCDC Register 2 0x8 32 read-write 0x9 0xFFFFFFFF LOOPCTRL_DC_C Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and can be used to optimize efficiency and loop response 0 2 read-write LOOPCTRL_DC_R Magnitude of proportional control parameter in the switching DC-DC converter control loop. 2 4 read-write LOOPCTRL_DC_FF Two's complement feed forward step in duty cycle in the switching DC-DC converter 6 3 read-write LOOPCTRL_EN_RCSCALE Enable analog circuit of DC-DC converter to respond faster under transient load conditions. 9 3 read-write LOOPCTRL_RCSCALE_THRSH Increase the threshold detection for RC scale circuit. 12 1 read-write LOOPCTRL_HYST_SIGN Invert the sign of the hysteresis in DC-DC analog comparators. 13 1 read-write BATTMONITOR_EN_BATADJ This bit enables the DC-DC to improve efficiency and minimize ripple using the information from the BATT_VAL field 15 1 read-write DISABLE_PULSE_SKIP Set to "0" : stop charging if the duty cycle is lower than what set by dcdc_neglimit_in 27 1 read-write DCM_SET_CTRL Set high to improve the transition from heavy load to light load 28 1 read-write REG3 DCDC Register 3 0xC 32 read-write 0x10E 0xFFFFFFFF TRG Target value of VDD_SOC, 25 mV each step 0x0: 0.8V 0xE: 1.15V 0x1F:1.575V 0 5 read-write TARGET_LP Target value of standby (low power) mode 0x0: 0 8 3 read-write MINPWR_DC_HALFCLK Set DCDC clock to half freqeuncy for continuous mode 24 1 read-write MISC_DELAY_TIMING Ajust delay to reduce ground noise 27 1 read-write MISC_DISABLEFET_LOGIC Reserved 28 1 read-write DISABLE_STEP Disable stepping for the output VDD_SOC of DCDC 30 1 read-write PIT PIT PIT 0x40084000 0 0x140 registers PIT 24 MCR PIT Module Control Register 0 32 read-write 0x2 0xFFFFFFFF FRZ Freeze 0 1 read-write FRZ_0 Timers continue to run in Debug mode. 0 FRZ_1 Timers are stopped in Debug mode. 0x1 MDIS Module Disable for PIT 1 1 read-write MDIS_0 Clock for standard PIT timers is enabled. 0 MDIS_1 Clock for standard PIT timers is disabled. 0x1 LTMR64H PIT Upper Lifetime Timer Register 0xE0 32 read-only 0 0xFFFFFFFF LTH Life Timer value 0 32 read-only LTMR64L PIT Lower Lifetime Timer Register 0xE4 32 read-only 0 0xFFFFFFFF LTL Life Timer value 0 32 read-only 4 0x10 TIMER[%s] no description available 0x100 LDVAL Timer Load Value Register 0 32 read-write 0 0xFFFFFFFF TSV Timer Start Value 0 32 read-write CVAL Current Timer Value Register 0x4 32 read-only 0 0xFFFFFFFF TVL Current Timer Value 0 32 read-only TCTRL Timer Control Register 0x8 32 read-write 0 0xFFFFFFFF TEN Timer Enable 0 1 read-write TEN_0 Timer n is disabled. 0 TEN_1 Timer n is enabled. 0x1 TIE Timer Interrupt Enable 1 1 read-write TIE_0 Interrupt requests from Timer n are disabled. 0 TIE_1 Interrupt is requested whenever TIF is set. 0x1 CHN Chain Mode 2 1 read-write CHN_0 Timer is not chained. 0 CHN_1 Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1. 0x1 TFLG Timer Flag Register 0xC 32 read-write 0 0xFFFFFFFF TIF Timer Interrupt Flag 0 1 read-write oneToClear TIF_0 Timeout has not yet occurred. 0 TIF_1 Timeout has occurred. 0x1 ADC_ETC ADC_ETC ADC_ETC 0x40088000 0 0x150 registers ADC_ETC_IRQ0 75 ADC_ETC_IRQ1 76 ADC_ETC_IRQ2 77 ADC_ETC_IRQ3 78 ADC_ETC_ERROR_IRQ 79 CTRL ADC_ETC Global Control Register 0 32 read-write 0xC0000000 0xFFFFFFFF TRIG_ENABLE TRIG enable register 0 8 read-write EXT0_TRIG_ENABLE TSC0 TRIG enable register. 1'b1: enable external TSC0 trigger. 1'b0: disable external TSC0 trigger. 8 1 read-write EXT0_TRIG_PRIORITY External TSC0 trigger priority, 7 is Highest, 0 is lowest . 9 3 read-write EXT1_TRIG_ENABLE TSC1 TRIG enable register. 1'b1: enable external TSC1 trigger. 1'b0: disable external TSC1 trigger. 12 1 read-write EXT1_TRIG_PRIORITY External TSC1 trigger priority, 7 is Highest, 0 is lowest . 13 3 read-write PRE_DIVIDER Pre-divider for trig delay and interval . 16 8 read-write DMA_MODE_SEL 1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared 29 1 read-write TSC_BYPASS 1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared. 30 1 read-write SOFTRST Software reset, high active. When write 1 ,all logical will be reset. 31 1 read-write DONE0_1_IRQ ETC DONE0 and DONE1 IRQ State Register 0x4 32 read-write 0 0xFFFFFFFF TRIG0_DONE0 TRIG0 done0 interrupt detection 0 1 read-write TRIG1_DONE0 TRIG1 done0 interrupt detection 1 1 read-write TRIG2_DONE0 TRIG2 done0 interrupt detection 2 1 read-write TRIG3_DONE0 TRIG3 done0 interrupt detection 3 1 read-write TRIG4_DONE0 TRIG4 done0 interrupt detection 4 1 read-write TRIG5_DONE0 TRIG5 done0 interrupt detection 5 1 read-write TRIG6_DONE0 TRIG6 done0 interrupt detection 6 1 read-write TRIG7_DONE0 TRIG7 done0 interrupt detection 7 1 read-write TRIG0_DONE1 TRIG0 done1 interrupt detection 16 1 read-write TRIG1_DONE1 TRIG1 done1 interrupt detection 17 1 read-write TRIG2_DONE1 TRIG2 done1 interrupt detection 18 1 read-write TRIG3_DONE1 TRIG3 done1 interrupt detection 19 1 read-write TRIG4_DONE1 TRIG4 done1 interrupt detection 20 1 read-write TRIG5_DONE1 TRIG5 done1 interrupt detection 21 1 read-write TRIG6_DONE1 TRIG6 done1 interrupt detection 22 1 read-write TRIG7_DONE1 TRIG7 done1 interrupt detection 23 1 read-write DONE2_ERR_IRQ ETC DONE_2 and DONE_ERR IRQ State Register 0x8 32 read-write 0 0xFFFFFFFF TRIG0_DONE2 TRIG0 done2 interrupt detection 0 1 read-write TRIG1_DONE2 TRIG1 done2 interrupt detection 1 1 read-write TRIG2_DONE2 TRIG2 done2 interrupt detection 2 1 read-write TRIG3_DONE2 TRIG3 done2 interrupt detection 3 1 read-write TRIG4_DONE2 TRIG4 done2 interrupt detection 4 1 read-write TRIG5_DONE2 TRIG5 done2 interrupt detection 5 1 read-write TRIG6_DONE2 TRIG6 done2 interrupt detection 6 1 read-write TRIG7_DONE2 TRIG7 done2 interrupt detection 7 1 read-write TRIG0_DONE3 TRIG0 done3 interrupt detection 8 1 read-write TRIG1_DONE3 TRIG1 done3 interrupt detection 9 1 read-write TRIG2_DONE3 TRIG2 done3 interrupt detection 10 1 read-write TRIG3_DONE3 TRIG3 done3 interrupt detection 11 1 read-write TRIG4_DONE3 TRIG4 done3 interrupt detection 12 1 read-write TRIG5_DONE3 TRIG5 done3 interrupt detection 13 1 read-write TRIG6_DONE3 TRIG6 done3 interrupt detection 14 1 read-write TRIG7_DONE3 TRIG7 done3 interrupt detection 15 1 read-write TRIG0_ERR TRIG0 error interrupt detection 16 1 read-write TRIG1_ERR TRIG1 error interrupt detection 17 1 read-write TRIG2_ERR TRIG2 error interrupt detection 18 1 read-write TRIG3_ERR TRIG3 error interrupt detection 19 1 read-write TRIG4_ERR TRIG4 error interrupt detection 20 1 read-write TRIG5_ERR TRIG5 error interrupt detection 21 1 read-write TRIG6_ERR TRIG6 error interrupt detection 22 1 read-write TRIG7_ERR TRIG7 error interrupt detection 23 1 read-write DMA_CTRL ETC DMA control Register 0xC 32 read-write 0 0xFFFFFFFF TRIG0_ENABLE When TRIG0 done enable DMA request 0 1 read-write TRIG1_ENABLE When TRIG1 done enable DMA request 1 1 read-write TRIG2_ENABLE When TRIG2 done enable DMA request 2 1 read-write TRIG3_ENABLE When TRIG3 done enable DMA request 3 1 read-write TRIG4_ENABLE When TRIG4 done enable DMA request 4 1 read-write TRIG5_ENABLE When TRIG5 done enable DMA request 5 1 read-write TRIG6_ENABLE When TRIG6 done enable DMA request 6 1 read-write TRIG7_ENABLE When TRIG7 done enable DMA request 7 1 read-write TRIG0_REQ When TRIG0 done DMA request detection 16 1 read-write TRIG1_REQ When TRIG1 done DMA request detection 17 1 read-write TRIG2_REQ When TRIG2 done DMA request detection 18 1 read-write TRIG3_REQ When TRIG3 done DMA request detection 19 1 read-write TRIG4_REQ When TRIG4 done DMA request detection 20 1 read-write TRIG5_REQ When TRIG5 done DMA request detection 21 1 read-write TRIG6_REQ When TRIG6 done DMA request detection 22 1 read-write TRIG7_REQ When TRIG7 done DMA request detection 23 1 read-write TRIG0_CTRL ETC_TRIG Control Register 0x10 32 read-write 0 0xFFFFFFFF SW_TRIG Software write 1 as the TRIGGER. This register is self-clearing. 0 1 read-write TRIG_MODE TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. 4 1 read-write TRIG_CHAIN TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; 8 3 read-write TRIG_PRIORITY External trigger priority, 7 is highest, 0 is lowest . 12 3 read-write SYNC_MODE TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode 16 1 read-write CHAINx_DONE CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits 24 8 read-write TRIG0_COUNTER ETC_TRIG Counter Register 0x14 32 read-write 0 0xFFFFFFFF INIT_DELAY TRIGGER initial delay counter 0 16 read-write SAMPLE_INTERVAL TRIGGER sampling interval counter 16 16 read-write TRIG0_CHAIN_1_0 ETC_TRIG Chain 0/1 Register 0x18 32 read-write 0 0xFFFFFFFF CSEL0 CHAIN0 CSEL ADC channel selection 0 4 read-write HWTS0 CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. 4 8 read-write B2B0 CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger 12 1 read-write IE0 CHAIN0 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3 13 2 read-write IE0_EN IRQ enable 15 1 read-write CSEL1 CHAIN1 CSEL ADC channel selection 16 4 read-write HWTS1 CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. 20 8 read-write B2B1 CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger 28 1 read-write IE1 CHAIN1 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3 29 2 read-write IE1_EN IRQ enable 31 1 read-write TRIG0_CHAIN_3_2 ETC_TRIG Chain 2/3 Register 0x1C 32 read-write 0 0xFFFFFFFF CSEL2 CHAIN2 CSEL 0 4 read-write HWTS2 CHAIN2 HWTS 4 8 read-write B2B2 CHAIN2 B2B 12 1 read-write IE2 CHAIN2 IE 13 2 read-write IE2_EN IRQ enable 15 1 read-write CSEL3 CHAIN3 CSEL 16 4 read-write HWTS3 CHAIN3 HWTS 20 8 read-write B2B3 CHAIN3 B2B 28 1 read-write IE3 CHAIN3 IE 29 2 read-write IE3_EN IRQ enable 31 1 read-write TRIG0_CHAIN_5_4 ETC_TRIG Chain 4/5 Register 0x20 32 read-write 0 0xFFFFFFFF CSEL4 CHAIN4 CSEL 0 4 read-write HWTS4 CHAIN4 HWTS 4 8 read-write B2B4 CHAIN4 B2B 12 1 read-write IE4 CHAIN4 IE 13 2 read-write IE4_EN IRQ enable 15 1 read-write CSEL5 CHAIN5 CSEL 16 4 read-write HWTS5 CHAIN5 HWTS 20 8 read-write B2B5 CHAIN5 B2B 28 1 read-write IE5 CHAIN5 IE 29 2 read-write IE5_EN IRQ enable 31 1 read-write TRIG0_CHAIN_7_6 ETC_TRIG Chain 6/7 Register 0x24 32 read-write 0 0xFFFFFFFF CSEL6 CHAIN6 CSEL 0 4 read-write HWTS6 CHAIN6 HWTS 4 8 read-write B2B6 CHAIN6 B2B 12 1 read-write IE6 CHAIN6 IE 13 2 read-write IE6_EN IRQ enable 15 1 read-write CSEL7 CHAIN7 CSEL 16 4 read-write HWTS7 CHAIN7 HWTS 20 8 read-write B2B7 CHAIN7 B2B 28 1 read-write IE7 CHAIN7 IE 29 2 read-write IE7_EN IRQ enable 31 1 read-write TRIG0_RESULT_1_0 ETC_TRIG Result Data 1/0 Register 0x28 32 read-only 0 0xFFFFFFFF DATA0 Result DATA0 0 12 read-only DATA1 Result DATA1 16 12 read-only TRIG0_RESULT_3_2 ETC_TRIG Result Data 3/2 Register 0x2C 32 read-only 0 0xFFFFFFFF DATA2 Result DATA2 0 12 read-only DATA3 Result DATA3 16 12 read-only TRIG0_RESULT_5_4 ETC_TRIG Result Data 5/4 Register 0x30 32 read-only 0 0xFFFFFFFF DATA4 Result DATA4 0 12 read-only DATA5 Result DATA5 16 12 read-only TRIG0_RESULT_7_6 ETC_TRIG Result Data 7/6 Register 0x34 32 read-only 0 0xFFFFFFFF DATA6 Result DATA6 0 12 read-only DATA7 Result DATA7 16 12 read-only TRIG1_CTRL ETC_TRIG Control Register 0x38 32 read-write 0 0xFFFFFFFF SW_TRIG Software write 1 as the TRIGGER. This register is self-clearing. 0 1 read-write TRIG_MODE TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. 4 1 read-write TRIG_CHAIN TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; 8 3 read-write TRIG_PRIORITY External trigger priority, 7 is highest, 0 is lowest . 12 3 read-write SYNC_MODE TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode 16 1 read-write CHAINx_DONE CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits 24 8 read-write TRIG1_COUNTER ETC_TRIG Counter Register 0x3C 32 read-write 0 0xFFFFFFFF INIT_DELAY TRIGGER initial delay counter 0 16 read-write SAMPLE_INTERVAL TRIGGER sampling interval counter 16 16 read-write TRIG1_CHAIN_1_0 ETC_TRIG Chain 0/1 Register 0x40 32 read-write 0 0xFFFFFFFF CSEL0 CHAIN0 CSEL ADC channel selection 0 4 read-write HWTS0 CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. 4 8 read-write B2B0 CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger 12 1 read-write IE0 CHAIN0 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3 13 2 read-write IE0_EN IRQ enable 15 1 read-write CSEL1 CHAIN1 CSEL ADC channel selection 16 4 read-write HWTS1 CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. 20 8 read-write B2B1 CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger 28 1 read-write IE1 CHAIN1 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3 29 2 read-write IE1_EN IRQ enable 31 1 read-write TRIG1_CHAIN_3_2 ETC_TRIG Chain 2/3 Register 0x44 32 read-write 0 0xFFFFFFFF CSEL2 CHAIN2 CSEL 0 4 read-write HWTS2 CHAIN2 HWTS 4 8 read-write B2B2 CHAIN2 B2B 12 1 read-write IE2 CHAIN2 IE 13 2 read-write IE2_EN IRQ enable 15 1 read-write CSEL3 CHAIN3 CSEL 16 4 read-write HWTS3 CHAIN3 HWTS 20 8 read-write B2B3 CHAIN3 B2B 28 1 read-write IE3 CHAIN3 IE 29 2 read-write IE3_EN IRQ enable 31 1 read-write TRIG1_CHAIN_5_4 ETC_TRIG Chain 4/5 Register 0x48 32 read-write 0 0xFFFFFFFF CSEL4 CHAIN4 CSEL 0 4 read-write HWTS4 CHAIN4 HWTS 4 8 read-write B2B4 CHAIN4 B2B 12 1 read-write IE4 CHAIN4 IE 13 2 read-write IE4_EN IRQ enable 15 1 read-write CSEL5 CHAIN5 CSEL 16 4 read-write HWTS5 CHAIN5 HWTS 20 8 read-write B2B5 CHAIN5 B2B 28 1 read-write IE5 CHAIN5 IE 29 2 read-write IE5_EN IRQ enable 31 1 read-write TRIG1_CHAIN_7_6 ETC_TRIG Chain 6/7 Register 0x4C 32 read-write 0 0xFFFFFFFF CSEL6 CHAIN6 CSEL 0 4 read-write HWTS6 CHAIN6 HWTS 4 8 read-write B2B6 CHAIN6 B2B 12 1 read-write IE6 CHAIN6 IE 13 2 read-write IE6_EN IRQ enable 15 1 read-write CSEL7 CHAIN7 CSEL 16 4 read-write HWTS7 CHAIN7 HWTS 20 8 read-write B2B7 CHAIN7 B2B 28 1 read-write IE7 CHAIN7 IE 29 2 read-write IE7_EN IRQ enable 31 1 read-write TRIG1_RESULT_1_0 ETC_TRIG Result Data 1/0 Register 0x50 32 read-only 0 0xFFFFFFFF DATA0 Result DATA0 0 12 read-only DATA1 Result DATA1 16 12 read-only TRIG1_RESULT_3_2 ETC_TRIG Result Data 3/2 Register 0x54 32 read-only 0 0xFFFFFFFF DATA2 Result DATA2 0 12 read-only DATA3 Result DATA3 16 12 read-only TRIG1_RESULT_5_4 ETC_TRIG Result Data 5/4 Register 0x58 32 read-only 0 0xFFFFFFFF DATA4 Result DATA4 0 12 read-only DATA5 Result DATA5 16 12 read-only TRIG1_RESULT_7_6 ETC_TRIG Result Data 7/6 Register 0x5C 32 read-only 0 0xFFFFFFFF DATA6 Result DATA6 0 12 read-only DATA7 Result DATA7 16 12 read-only TRIG2_CTRL ETC_TRIG Control Register 0x60 32 read-write 0 0xFFFFFFFF SW_TRIG Software write 1 as the TRIGGER. This register is self-clearing. 0 1 read-write TRIG_MODE TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. 4 1 read-write TRIG_CHAIN TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; 8 3 read-write TRIG_PRIORITY External trigger priority, 7 is highest, 0 is lowest . 12 3 read-write SYNC_MODE TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode 16 1 read-write CHAINx_DONE CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits 24 8 read-write TRIG2_COUNTER ETC_TRIG Counter Register 0x64 32 read-write 0 0xFFFFFFFF INIT_DELAY TRIGGER initial delay counter 0 16 read-write SAMPLE_INTERVAL TRIGGER sampling interval counter 16 16 read-write TRIG2_CHAIN_1_0 ETC_TRIG Chain 0/1 Register 0x68 32 read-write 0 0xFFFFFFFF CSEL0 CHAIN0 CSEL ADC channel selection 0 4 read-write HWTS0 CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. 4 8 read-write B2B0 CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger 12 1 read-write IE0 CHAIN0 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3 13 2 read-write IE0_EN IRQ enable 15 1 read-write CSEL1 CHAIN1 CSEL ADC channel selection 16 4 read-write HWTS1 CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. 20 8 read-write B2B1 CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger 28 1 read-write IE1 CHAIN1 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3 29 2 read-write IE1_EN IRQ enable 31 1 read-write TRIG2_CHAIN_3_2 ETC_TRIG Chain 2/3 Register 0x6C 32 read-write 0 0xFFFFFFFF CSEL2 CHAIN2 CSEL 0 4 read-write HWTS2 CHAIN2 HWTS 4 8 read-write B2B2 CHAIN2 B2B 12 1 read-write IE2 CHAIN2 IE 13 2 read-write IE2_EN IRQ enable 15 1 read-write CSEL3 CHAIN3 CSEL 16 4 read-write HWTS3 CHAIN3 HWTS 20 8 read-write B2B3 CHAIN3 B2B 28 1 read-write IE3 CHAIN3 IE 29 2 read-write IE3_EN IRQ enable 31 1 read-write TRIG2_CHAIN_5_4 ETC_TRIG Chain 4/5 Register 0x70 32 read-write 0 0xFFFFFFFF CSEL4 CHAIN4 CSEL 0 4 read-write HWTS4 CHAIN4 HWTS 4 8 read-write B2B4 CHAIN4 B2B 12 1 read-write IE4 CHAIN4 IE 13 2 read-write IE4_EN IRQ enable 15 1 read-write CSEL5 CHAIN5 CSEL 16 4 read-write HWTS5 CHAIN5 HWTS 20 8 read-write B2B5 CHAIN5 B2B 28 1 read-write IE5 CHAIN5 IE 29 2 read-write IE5_EN IRQ enable 31 1 read-write TRIG2_CHAIN_7_6 ETC_TRIG Chain 6/7 Register 0x74 32 read-write 0 0xFFFFFFFF CSEL6 CHAIN6 CSEL 0 4 read-write HWTS6 CHAIN6 HWTS 4 8 read-write B2B6 CHAIN6 B2B 12 1 read-write IE6 CHAIN6 IE 13 2 read-write IE6_EN IRQ enable 15 1 read-write CSEL7 CHAIN7 CSEL 16 4 read-write HWTS7 CHAIN7 HWTS 20 8 read-write B2B7 CHAIN7 B2B 28 1 read-write IE7 CHAIN7 IE 29 2 read-write IE7_EN IRQ enable 31 1 read-write TRIG2_RESULT_1_0 ETC_TRIG Result Data 1/0 Register 0x78 32 read-only 0 0xFFFFFFFF DATA0 Result DATA0 0 12 read-only DATA1 Result DATA1 16 12 read-only TRIG2_RESULT_3_2 ETC_TRIG Result Data 3/2 Register 0x7C 32 read-only 0 0xFFFFFFFF DATA2 Result DATA2 0 12 read-only DATA3 Result DATA3 16 12 read-only TRIG2_RESULT_5_4 ETC_TRIG Result Data 5/4 Register 0x80 32 read-only 0 0xFFFFFFFF DATA4 Result DATA4 0 12 read-only DATA5 Result DATA5 16 12 read-only TRIG2_RESULT_7_6 ETC_TRIG Result Data 7/6 Register 0x84 32 read-only 0 0xFFFFFFFF DATA6 Result DATA6 0 12 read-only DATA7 Result DATA7 16 12 read-only TRIG3_CTRL ETC_TRIG Control Register 0x88 32 read-write 0 0xFFFFFFFF SW_TRIG Software write 1 as the TRIGGER. This register is self-clearing. 0 1 read-write TRIG_MODE TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. 4 1 read-write TRIG_CHAIN TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; 8 3 read-write TRIG_PRIORITY External trigger priority, 7 is highest, 0 is lowest . 12 3 read-write SYNC_MODE TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode 16 1 read-write CHAINx_DONE CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits 24 8 read-write TRIG3_COUNTER ETC_TRIG Counter Register 0x8C 32 read-write 0 0xFFFFFFFF INIT_DELAY TRIGGER initial delay counter 0 16 read-write SAMPLE_INTERVAL TRIGGER sampling interval counter 16 16 read-write TRIG3_CHAIN_1_0 ETC_TRIG Chain 0/1 Register 0x90 32 read-write 0 0xFFFFFFFF CSEL0 CHAIN0 CSEL ADC channel selection 0 4 read-write HWTS0 CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. 4 8 read-write B2B0 CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger 12 1 read-write IE0 CHAIN0 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3 13 2 read-write IE0_EN IRQ enable 15 1 read-write CSEL1 CHAIN1 CSEL ADC channel selection 16 4 read-write HWTS1 CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. 20 8 read-write B2B1 CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger 28 1 read-write IE1 CHAIN1 IE 2'b00: Finished Interrupt on Done0 2'b01: Finished Interrupt on Done1 2'b10: Finished Interrupt on Done2 2'b11: Finished Interrupt on Done3 29 2 read-write IE1_EN IRQ enable 31 1 read-write TRIG3_CHAIN_3_2 ETC_TRIG Chain 2/3 Register 0x94 32 read-write 0 0xFFFFFFFF CSEL2 CHAIN2 CSEL 0 4 read-write HWTS2 CHAIN2 HWTS 4 8 read-write B2B2 CHAIN2 B2B 12 1 read-write IE2 CHAIN2 IE 13 2 read-write IE2_EN IRQ enable 15 1 read-write CSEL3 CHAIN3 CSEL 16 4 read-write HWTS3 CHAIN3 HWTS 20 8 read-write B2B3 CHAIN3 B2B 28 1 read-write IE3 CHAIN3 IE 29 2 read-write IE3_EN IRQ enable 31 1 read-write TRIG3_CHAIN_5_4 ETC_TRIG Chain 4/5 Register 0x98 32 read-write 0 0xFFFFFFFF CSEL4 CHAIN4 CSEL 0 4 read-write HWTS4 CHAIN4 HWTS 4 8 read-write B2B4 CHAIN4 B2B 12 1 read-write IE4 CHAIN4 IE 13 2 read-write IE4_EN IRQ enable 15 1 read-write CSEL5 CHAIN5 CSEL 16 4 read-write HWTS5 CHAIN5 HWTS 20 8 read-write B2B5 CHAIN5 B2B 28 1 read-write IE5 CHAIN5 IE 29 2 read-write IE5_EN IRQ enable 31 1 read-write TRIG3_CHAIN_7_6 ETC_TRIG Chain 6/7 Register 0x9C 32 read-write 0 0xFFFFFFFF CSEL6 CHAIN6 CSEL 0 4 read-write HWTS6 CHAIN6 HWTS 4 8 read-write B2B6 CHAIN6 B2B 12 1 read-write IE6 CHAIN6 IE 13 2 read-write IE6_EN IRQ enable 15 1 read-write CSEL7 CHAIN7 CSEL 16 4 read-write HWTS7 CHAIN7 HWTS 20 8 read-write B2B7 CHAIN7 B2B 28 1 read-write IE7 CHAIN7 IE 29 2 read-write IE7_EN IRQ enable 31 1 read-write TRIG3_RESULT_1_0 ETC_TRIG Result Data 1/0 Register 0xA0 32 read-only 0 0xFFFFFFFF DATA0 Result DATA0 0 12 read-only DATA1 Result DATA1 16 12 read-only TRIG3_RESULT_3_2 ETC_TRIG Result Data 3/2 Register 0xA4 32 read-only 0 0xFFFFFFFF DATA2 Result DATA2 0 12 read-only DATA3 Result DATA3 16 12 read-only TRIG3_RESULT_5_4 ETC_TRIG Result Data 5/4 Register 0xA8 32 read-only 0 0xFFFFFFFF DATA4 Result DATA4 0 12 read-only DATA5 Result DATA5 16 12 read-only TRIG3_RESULT_7_6 ETC_TRIG Result Data 7/6 Register 0xAC 32 read-only 0 0xFFFFFFFF DATA6 Result DATA6 0 12 read-only DATA7 Result DATA7 16 12 read-only AOI AND/OR/INVERT module AOI AOI_ 0x40094000 0 0x10 registers 4 0x4 0,1,2,3 BFCRT01%s Boolean Function Term 0 and 1 Configuration Register for EVENTn 0 16 read-write 0 0xFFFF PT1_DC Product term 1, D input configuration 0 2 read-write PT1_DC_0 Force the D input in this product term to a logical zero 0 PT1_DC_1 Pass the D input in this product term 0x1 PT1_DC_2 Complement the D input in this product term 0x2 PT1_DC_3 Force the D input in this product term to a logical one 0x3 PT1_CC Product term 1, C input configuration 2 2 read-write PT1_CC_0 Force the C input in this product term to a logical zero 0 PT1_CC_1 Pass the C input in this product term 0x1 PT1_CC_2 Complement the C input in this product term 0x2 PT1_CC_3 Force the C input in this product term to a logical one 0x3 PT1_BC Product term 1, B input configuration 4 2 read-write PT1_BC_0 Force the B input in this product term to a logical zero 0 PT1_BC_1 Pass the B input in this product term 0x1 PT1_BC_2 Complement the B input in this product term 0x2 PT1_BC_3 Force the B input in this product term to a logical one 0x3 PT1_AC Product term 1, A input configuration 6 2 read-write PT1_AC_0 Force the A input in this product term to a logical zero 0 PT1_AC_1 Pass the A input in this product term 0x1 PT1_AC_2 Complement the A input in this product term 0x2 PT1_AC_3 Force the A input in this product term to a logical one 0x3 PT0_DC Product term 0, D input configuration 8 2 read-write PT0_DC_0 Force the D input in this product term to a logical zero 0 PT0_DC_1 Pass the D input in this product term 0x1 PT0_DC_2 Complement the D input in this product term 0x2 PT0_DC_3 Force the D input in this product term to a logical one 0x3 PT0_CC Product term 0, C input configuration 10 2 read-write PT0_CC_0 Force the C input in this product term to a logical zero 0 PT0_CC_1 Pass the C input in this product term 0x1 PT0_CC_2 Complement the C input in this product term 0x2 PT0_CC_3 Force the C input in this product term to a logical one 0x3 PT0_BC Product term 0, B input configuration 12 2 read-write PT0_BC_0 Force the B input in this product term to a logical zero 0 PT0_BC_1 Pass the B input in this product term 0x1 PT0_BC_2 Complement the B input in this product term 0x2 PT0_BC_3 Force the B input in this product term to a logical one 0x3 PT0_AC Product term 0, A input configuration 14 2 read-write PT0_AC_0 Force the A input in this product term to a logical zero 0 PT0_AC_1 Pass the A input in this product term 0x1 PT0_AC_2 Complement the A input in this product term 0x2 PT0_AC_3 Force the A input in this product term to a logical one 0x3 4 0x4 0,1,2,3 BFCRT23%s Boolean Function Term 2 and 3 Configuration Register for EVENTn 0x2 16 read-write 0 0xFFFF PT3_DC Product term 3, D input configuration 0 2 read-write PT3_DC_0 Force the D input in this product term to a logical zero 0 PT3_DC_1 Pass the D input in this product term 0x1 PT3_DC_2 Complement the D input in this product term 0x2 PT3_DC_3 Force the D input in this product term to a logical one 0x3 PT3_CC Product term 3, C input configuration 2 2 read-write PT3_CC_0 Force the C input in this product term to a logical zero 0 PT3_CC_1 Pass the C input in this product term 0x1 PT3_CC_2 Complement the C input in this product term 0x2 PT3_CC_3 Force the C input in this product term to a logical one 0x3 PT3_BC Product term 3, B input configuration 4 2 read-write PT3_BC_0 Force the B input in this product term to a logical zero 0 PT3_BC_1 Pass the B input in this product term 0x1 PT3_BC_2 Complement the B input in this product term 0x2 PT3_BC_3 Force the B input in this product term to a logical one 0x3 PT3_AC Product term 3, A input configuration 6 2 read-write PT3_AC_0 Force the A input in this product term to a logical zero 0 PT3_AC_1 Pass the A input in this product term 0x1 PT3_AC_2 Complement the A input in this product term 0x2 PT3_AC_3 Force the A input in this product term to a logical one 0x3 PT2_DC Product term 2, D input configuration 8 2 read-write PT2_DC_0 Force the D input in this product term to a logical zero 0 PT2_DC_1 Pass the D input in this product term 0x1 PT2_DC_2 Complement the D input in this product term 0x2 PT2_DC_3 Force the D input in this product term to a logical one 0x3 PT2_CC Product term 2, C input configuration 10 2 read-write PT2_CC_0 Force the C input in this product term to a logical zero 0 PT2_CC_1 Pass the C input in this product term 0x1 PT2_CC_2 Complement the C input in this product term 0x2 PT2_CC_3 Force the C input in this product term to a logical one 0x3 PT2_BC Product term 2, B input configuration 12 2 read-write PT2_BC_0 Force the B input in this product term to a logical zero 0 PT2_BC_1 Pass the B input in this product term 0x1 PT2_BC_2 Complement the B input in this product term 0x2 PT2_BC_3 Force the B input in this product term to a logical one 0x3 PT2_AC Product term 2, A input configuration 14 2 read-write PT2_AC_0 Force the A input in this product term to a logical zero 0 PT2_AC_1 Pass the A input in this product term 0x1 PT2_AC_2 Complement the A input in this product term 0x2 PT2_AC_3 Force the A input in this product term to a logical one 0x3 XBARA Crossbar Switch XBARA XBARA_ 0x40098000 0 0x88 registers SEL0 Crossbar A Select Register 0 0 16 read-write 0 0xFFFF SEL0 Input (XBARA_INn) to be muxed to XBARA_OUT0 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL1 Input (XBARA_INn) to be muxed to XBARA_OUT1 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL1 Crossbar A Select Register 1 0x2 16 read-write 0 0xFFFF SEL2 Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL3 Input (XBARA_INn) to be muxed to XBARA_OUT3 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL2 Crossbar A Select Register 2 0x4 16 read-write 0 0xFFFF SEL4 Input (XBARA_INn) to be muxed to XBARA_OUT4 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL5 Input (XBARA_INn) to be muxed to XBARA_OUT5 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL3 Crossbar A Select Register 3 0x6 16 read-write 0 0xFFFF SEL6 Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL7 Input (XBARA_INn) to be muxed to XBARA_OUT7 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL4 Crossbar A Select Register 4 0x8 16 read-write 0 0xFFFF SEL8 Input (XBARA_INn) to be muxed to XBARA_OUT8 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL9 Input (XBARA_INn) to be muxed to XBARA_OUT9 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL5 Crossbar A Select Register 5 0xA 16 read-write 0 0xFFFF SEL10 Input (XBARA_INn) to be muxed to XBARA_OUT10 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL11 Input (XBARA_INn) to be muxed to XBARA_OUT11 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL6 Crossbar A Select Register 6 0xC 16 read-write 0 0xFFFF SEL12 Input (XBARA_INn) to be muxed to XBARA_OUT12 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL13 Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL7 Crossbar A Select Register 7 0xE 16 read-write 0 0xFFFF SEL14 Input (XBARA_INn) to be muxed to XBARA_OUT14 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL15 Input (XBARA_INn) to be muxed to XBARA_OUT15 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL8 Crossbar A Select Register 8 0x10 16 read-write 0 0xFFFF SEL16 Input (XBARA_INn) to be muxed to XBARA_OUT16 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL17 Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL9 Crossbar A Select Register 9 0x12 16 read-write 0 0xFFFF SEL18 Input (XBARA_INn) to be muxed to XBARA_OUT18 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL19 Input (XBARA_INn) to be muxed to XBARA_OUT19 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL10 Crossbar A Select Register 10 0x14 16 read-write 0 0xFFFF SEL20 Input (XBARA_INn) to be muxed to XBARA_OUT20 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL21 Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL11 Crossbar A Select Register 11 0x16 16 read-write 0 0xFFFF SEL22 Input (XBARA_INn) to be muxed to XBARA_OUT22 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL23 Input (XBARA_INn) to be muxed to XBARA_OUT23 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL12 Crossbar A Select Register 12 0x18 16 read-write 0 0xFFFF SEL24 Input (XBARA_INn) to be muxed to XBARA_OUT24 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL25 Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL13 Crossbar A Select Register 13 0x1A 16 read-write 0 0xFFFF SEL26 Input (XBARA_INn) to be muxed to XBARA_OUT26 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL27 Input (XBARA_INn) to be muxed to XBARA_OUT27 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL14 Crossbar A Select Register 14 0x1C 16 read-write 0 0xFFFF SEL28 Input (XBARA_INn) to be muxed to XBARA_OUT28 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL29 Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL15 Crossbar A Select Register 15 0x1E 16 read-write 0 0xFFFF SEL30 Input (XBARA_INn) to be muxed to XBARA_OUT30 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL31 Input (XBARA_INn) to be muxed to XBARA_OUT31 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL16 Crossbar A Select Register 16 0x20 16 read-write 0 0xFFFF SEL32 Input (XBARA_INn) to be muxed to XBARA_OUT32 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL33 Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL17 Crossbar A Select Register 17 0x22 16 read-write 0 0xFFFF SEL34 Input (XBARA_INn) to be muxed to XBARA_OUT34 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL35 Input (XBARA_INn) to be muxed to XBARA_OUT35 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL18 Crossbar A Select Register 18 0x24 16 read-write 0 0xFFFF SEL36 Input (XBARA_INn) to be muxed to XBARA_OUT36 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL37 Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL19 Crossbar A Select Register 19 0x26 16 read-write 0 0xFFFF SEL38 Input (XBARA_INn) to be muxed to XBARA_OUT38 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL39 Input (XBARA_INn) to be muxed to XBARA_OUT39 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL20 Crossbar A Select Register 20 0x28 16 read-write 0 0xFFFF SEL40 Input (XBARA_INn) to be muxed to XBARA_OUT40 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL41 Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL21 Crossbar A Select Register 21 0x2A 16 read-write 0 0xFFFF SEL42 Input (XBARA_INn) to be muxed to XBARA_OUT42 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL43 Input (XBARA_INn) to be muxed to XBARA_OUT43 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL22 Crossbar A Select Register 22 0x2C 16 read-write 0 0xFFFF SEL44 Input (XBARA_INn) to be muxed to XBARA_OUT44 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL45 Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL23 Crossbar A Select Register 23 0x2E 16 read-write 0 0xFFFF SEL46 Input (XBARA_INn) to be muxed to XBARA_OUT46 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL47 Input (XBARA_INn) to be muxed to XBARA_OUT47 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL24 Crossbar A Select Register 24 0x30 16 read-write 0 0xFFFF SEL48 Input (XBARA_INn) to be muxed to XBARA_OUT48 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL49 Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL25 Crossbar A Select Register 25 0x32 16 read-write 0 0xFFFF SEL50 Input (XBARA_INn) to be muxed to XBARA_OUT50 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL51 Input (XBARA_INn) to be muxed to XBARA_OUT51 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL26 Crossbar A Select Register 26 0x34 16 read-write 0 0xFFFF SEL52 Input (XBARA_INn) to be muxed to XBARA_OUT52 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL53 Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL27 Crossbar A Select Register 27 0x36 16 read-write 0 0xFFFF SEL54 Input (XBARA_INn) to be muxed to XBARA_OUT54 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL55 Input (XBARA_INn) to be muxed to XBARA_OUT55 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL28 Crossbar A Select Register 28 0x38 16 read-write 0 0xFFFF SEL56 Input (XBARA_INn) to be muxed to XBARA_OUT56 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL57 Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL29 Crossbar A Select Register 29 0x3A 16 read-write 0 0xFFFF SEL58 Input (XBARA_INn) to be muxed to XBARA_OUT58 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL59 Input (XBARA_INn) to be muxed to XBARA_OUT59 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL30 Crossbar A Select Register 30 0x3C 16 read-write 0 0xFFFF SEL60 Input (XBARA_INn) to be muxed to XBARA_OUT60 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL61 Input (XBARA_INn) to be muxed to XBARA_OUT61 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL31 Crossbar A Select Register 31 0x3E 16 read-write 0 0xFFFF SEL62 Input (XBARA_INn) to be muxed to XBARA_OUT62 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL63 Input (XBARA_INn) to be muxed to XBARA_OUT63 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL32 Crossbar A Select Register 32 0x40 16 read-write 0 0xFFFF SEL64 Input (XBARA_INn) to be muxed to XBARA_OUT64 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL65 Input (XBARA_INn) to be muxed to XBARA_OUT65 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL33 Crossbar A Select Register 33 0x42 16 read-write 0 0xFFFF SEL66 Input (XBARA_INn) to be muxed to XBARA_OUT66 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL67 Input (XBARA_INn) to be muxed to XBARA_OUT67 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL34 Crossbar A Select Register 34 0x44 16 read-write 0 0xFFFF SEL68 Input (XBARA_INn) to be muxed to XBARA_OUT68 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL69 Input (XBARA_INn) to be muxed to XBARA_OUT69 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL35 Crossbar A Select Register 35 0x46 16 read-write 0 0xFFFF SEL70 Input (XBARA_INn) to be muxed to XBARA_OUT70 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL71 Input (XBARA_INn) to be muxed to XBARA_OUT71 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL36 Crossbar A Select Register 36 0x48 16 read-write 0 0xFFFF SEL72 Input (XBARA_INn) to be muxed to XBARA_OUT72 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL73 Input (XBARA_INn) to be muxed to XBARA_OUT73 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL37 Crossbar A Select Register 37 0x4A 16 read-write 0 0xFFFF SEL74 Input (XBARA_INn) to be muxed to XBARA_OUT74 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL75 Input (XBARA_INn) to be muxed to XBARA_OUT75 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL38 Crossbar A Select Register 38 0x4C 16 read-write 0 0xFFFF SEL76 Input (XBARA_INn) to be muxed to XBARA_OUT76 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL77 Input (XBARA_INn) to be muxed to XBARA_OUT77 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL39 Crossbar A Select Register 39 0x4E 16 read-write 0 0xFFFF SEL78 Input (XBARA_INn) to be muxed to XBARA_OUT78 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL79 Input (XBARA_INn) to be muxed to XBARA_OUT79 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL40 Crossbar A Select Register 40 0x50 16 read-write 0 0xFFFF SEL80 Input (XBARA_INn) to be muxed to XBARA_OUT80 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL81 Input (XBARA_INn) to be muxed to XBARA_OUT81 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL41 Crossbar A Select Register 41 0x52 16 read-write 0 0xFFFF SEL82 Input (XBARA_INn) to be muxed to XBARA_OUT82 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL83 Input (XBARA_INn) to be muxed to XBARA_OUT83 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL42 Crossbar A Select Register 42 0x54 16 read-write 0 0xFFFF SEL84 Input (XBARA_INn) to be muxed to XBARA_OUT84 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL85 Input (XBARA_INn) to be muxed to XBARA_OUT85 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL43 Crossbar A Select Register 43 0x56 16 read-write 0 0xFFFF SEL86 Input (XBARA_INn) to be muxed to XBARA_OUT86 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL87 Input (XBARA_INn) to be muxed to XBARA_OUT87 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL44 Crossbar A Select Register 44 0x58 16 read-write 0 0xFFFF SEL88 Input (XBARA_INn) to be muxed to XBARA_OUT88 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL89 Input (XBARA_INn) to be muxed to XBARA_OUT89 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL45 Crossbar A Select Register 45 0x5A 16 read-write 0 0xFFFF SEL90 Input (XBARA_INn) to be muxed to XBARA_OUT90 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL91 Input (XBARA_INn) to be muxed to XBARA_OUT91 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL46 Crossbar A Select Register 46 0x5C 16 read-write 0 0xFFFF SEL92 Input (XBARA_INn) to be muxed to XBARA_OUT92 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL93 Input (XBARA_INn) to be muxed to XBARA_OUT93 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL47 Crossbar A Select Register 47 0x5E 16 read-write 0 0xFFFF SEL94 Input (XBARA_INn) to be muxed to XBARA_OUT94 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL95 Input (XBARA_INn) to be muxed to XBARA_OUT95 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL48 Crossbar A Select Register 48 0x60 16 read-write 0 0xFFFF SEL96 Input (XBARA_INn) to be muxed to XBARA_OUT96 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL97 Input (XBARA_INn) to be muxed to XBARA_OUT97 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL49 Crossbar A Select Register 49 0x62 16 read-write 0 0xFFFF SEL98 Input (XBARA_INn) to be muxed to XBARA_OUT98 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL99 Input (XBARA_INn) to be muxed to XBARA_OUT99 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL50 Crossbar A Select Register 50 0x64 16 read-write 0 0xFFFF SEL100 Input (XBARA_INn) to be muxed to XBARA_OUT100 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL101 Input (XBARA_INn) to be muxed to XBARA_OUT101 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL51 Crossbar A Select Register 51 0x66 16 read-write 0 0xFFFF SEL102 Input (XBARA_INn) to be muxed to XBARA_OUT102 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL103 Input (XBARA_INn) to be muxed to XBARA_OUT103 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL52 Crossbar A Select Register 52 0x68 16 read-write 0 0xFFFF SEL104 Input (XBARA_INn) to be muxed to XBARA_OUT104 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL105 Input (XBARA_INn) to be muxed to XBARA_OUT105 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL53 Crossbar A Select Register 53 0x6A 16 read-write 0 0xFFFF SEL106 Input (XBARA_INn) to be muxed to XBARA_OUT106 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL107 Input (XBARA_INn) to be muxed to XBARA_OUT107 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL54 Crossbar A Select Register 54 0x6C 16 read-write 0 0xFFFF SEL108 Input (XBARA_INn) to be muxed to XBARA_OUT108 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL109 Input (XBARA_INn) to be muxed to XBARA_OUT109 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL55 Crossbar A Select Register 55 0x6E 16 read-write 0 0xFFFF SEL110 Input (XBARA_INn) to be muxed to XBARA_OUT110 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL111 Input (XBARA_INn) to be muxed to XBARA_OUT111 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL56 Crossbar A Select Register 56 0x70 16 read-write 0 0xFFFF SEL112 Input (XBARA_INn) to be muxed to XBARA_OUT112 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL113 Input (XBARA_INn) to be muxed to XBARA_OUT113 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL57 Crossbar A Select Register 57 0x72 16 read-write 0 0xFFFF SEL114 Input (XBARA_INn) to be muxed to XBARA_OUT114 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL115 Input (XBARA_INn) to be muxed to XBARA_OUT115 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL58 Crossbar A Select Register 58 0x74 16 read-write 0 0xFFFF SEL116 Input (XBARA_INn) to be muxed to XBARA_OUT116 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL117 Input (XBARA_INn) to be muxed to XBARA_OUT117 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL59 Crossbar A Select Register 59 0x76 16 read-write 0 0xFFFF SEL118 Input (XBARA_INn) to be muxed to XBARA_OUT118 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL119 Input (XBARA_INn) to be muxed to XBARA_OUT119 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL60 Crossbar A Select Register 60 0x78 16 read-write 0 0xFFFF SEL120 Input (XBARA_INn) to be muxed to XBARA_OUT120 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL121 Input (XBARA_INn) to be muxed to XBARA_OUT121 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL61 Crossbar A Select Register 61 0x7A 16 read-write 0 0xFFFF SEL122 Input (XBARA_INn) to be muxed to XBARA_OUT122 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL123 Input (XBARA_INn) to be muxed to XBARA_OUT123 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL62 Crossbar A Select Register 62 0x7C 16 read-write 0 0xFFFF SEL124 Input (XBARA_INn) to be muxed to XBARA_OUT124 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL125 Input (XBARA_INn) to be muxed to XBARA_OUT125 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL63 Crossbar A Select Register 63 0x7E 16 read-write 0 0xFFFF SEL126 Input (XBARA_INn) to be muxed to XBARA_OUT126 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL127 Input (XBARA_INn) to be muxed to XBARA_OUT127 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL64 Crossbar A Select Register 64 0x80 16 read-write 0 0xFFFF SEL128 Input (XBARA_INn) to be muxed to XBARA_OUT128 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL129 Input (XBARA_INn) to be muxed to XBARA_OUT129 (refer to Functional Description section for input/output assignment) 8 7 read-write SEL65 Crossbar A Select Register 65 0x82 16 read-write 0 0xFFFF SEL130 Input (XBARA_INn) to be muxed to XBARA_OUT130 (refer to Functional Description section for input/output assignment) 0 7 read-write SEL131 Input (XBARA_INn) to be muxed to XBARA_OUT131 (refer to Functional Description section for input/output assignment) 8 7 read-write CTRL0 Crossbar A Control Register 0 0x84 16 read-write 0 0xFFFF DEN0 DMA Enable for XBAR_OUT0 0 1 read-write DEN0_0 DMA disabled 0 DEN0_1 DMA enabled 0x1 IEN0 Interrupt Enable for XBAR_OUT0 1 1 read-write IEN0_0 Interrupt disabled 0 IEN0_1 Interrupt enabled 0x1 EDGE0 Active edge for edge detection on XBAR_OUT0 2 2 read-write EDGE0_0 STS0 never asserts 0 EDGE0_1 STS0 asserts on rising edges of XBAR_OUT0 0x1 EDGE0_2 STS0 asserts on falling edges of XBAR_OUT0 0x2 EDGE0_3 STS0 asserts on rising and falling edges of XBAR_OUT0 0x3 STS0 Edge detection status for XBAR_OUT0 4 1 read-write oneToClear STS0_0 Active edge not yet detected on XBAR_OUT0 0 STS0_1 Active edge detected on XBAR_OUT0 0x1 DEN1 DMA Enable for XBAR_OUT1 8 1 read-write DEN1_0 DMA disabled 0 DEN1_1 DMA enabled 0x1 IEN1 Interrupt Enable for XBAR_OUT1 9 1 read-write IEN1_0 Interrupt disabled 0 IEN1_1 Interrupt enabled 0x1 EDGE1 Active edge for edge detection on XBAR_OUT1 10 2 read-write EDGE1_0 STS1 never asserts 0 EDGE1_1 STS1 asserts on rising edges of XBAR_OUT1 0x1 EDGE1_2 STS1 asserts on falling edges of XBAR_OUT1 0x2 EDGE1_3 STS1 asserts on rising and falling edges of XBAR_OUT1 0x3 STS1 Edge detection status for XBAR_OUT1 12 1 read-write oneToClear STS1_0 Active edge not yet detected on XBAR_OUT1 0 STS1_1 Active edge detected on XBAR_OUT1 0x1 CTRL1 Crossbar A Control Register 1 0x86 16 read-write 0 0xFFFF DEN2 DMA Enable for XBAR_OUT2 0 1 read-write DEN2_0 DMA disabled 0 DEN2_1 DMA enabled 0x1 IEN2 Interrupt Enable for XBAR_OUT2 1 1 read-write IEN2_0 Interrupt disabled 0 IEN2_1 Interrupt enabled 0x1 EDGE2 Active edge for edge detection on XBAR_OUT2 2 2 read-write EDGE2_0 STS2 never asserts 0 EDGE2_1 STS2 asserts on rising edges of XBAR_OUT2 0x1 EDGE2_2 STS2 asserts on falling edges of XBAR_OUT2 0x2 EDGE2_3 STS2 asserts on rising and falling edges of XBAR_OUT2 0x3 STS2 Edge detection status for XBAR_OUT2 4 1 read-write oneToClear STS2_0 Active edge not yet detected on XBAR_OUT2 0 STS2_1 Active edge detected on XBAR_OUT2 0x1 DEN3 DMA Enable for XBAR_OUT3 8 1 read-write DEN3_0 DMA disabled 0 DEN3_1 DMA enabled 0x1 IEN3 Interrupt Enable for XBAR_OUT3 9 1 read-write IEN3_0 Interrupt disabled 0 IEN3_1 Interrupt enabled 0x1 EDGE3 Active edge for edge detection on XBAR_OUT3 10 2 read-write EDGE3_0 STS3 never asserts 0 EDGE3_1 STS3 asserts on rising edges of XBAR_OUT3 0x1 EDGE3_2 STS3 asserts on falling edges of XBAR_OUT3 0x2 EDGE3_3 STS3 asserts on rising and falling edges of XBAR_OUT3 0x3 STS3 Edge detection status for XBAR_OUT3 12 1 read-write oneToClear STS3_0 Active edge not yet detected on XBAR_OUT3 0 STS3_1 Active edge detected on XBAR_OUT3 0x1 FLEXSPI FlexSPI FlexSPI 0x400A0000 0 0x400 registers FLEXSPI 26 MCR0 Module Control Register 0 0 32 read-write 0xFFFF80C2 0xFFFFFFFF SWRESET Software Reset 0 1 read-write MDIS Module Disable 1 1 read-write RXCLKSRC Sample Clock source selection for Flash Reading 4 2 read-write RXCLKSRC_0 Dummy Read strobe generated by FlexSPI Controller and loopback internally. 0 RXCLKSRC_1 Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. 0x1 RXCLKSRC_3 Flash provided Read strobe and input from DQS pad 0x3 ARDFEN Enable AHB bus Read Access to IP RX FIFO. 6 1 read-write ARDFEN_0 IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. 0 ARDFEN_1 IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. 0x1 ATDFEN Enable AHB bus Write Access to IP TX FIFO. 7 1 read-write ATDFEN_0 IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. 0 ATDFEN_1 IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. 0x1 SERCLKDIV The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking. 8 3 read-write SERCLKDIV_0 Divided by 1 0 SERCLKDIV_1 Divided by 2 0x1 SERCLKDIV_2 Divided by 3 0x2 SERCLKDIV_3 Divided by 4 0x3 SERCLKDIV_4 Divided by 5 0x4 SERCLKDIV_5 Divided by 6 0x5 SERCLKDIV_6 Divided by 7 0x6 SERCLKDIV_7 Divided by 8 0x7 HSEN Half Speed Serial Flash access Enable. 11 1 read-write HSEN_0 Disable divide by 2 of serial flash clock for half speed commands. 0 HSEN_1 Enable divide by 2 of serial flash clock for half speed commands. 0x1 DOZEEN Doze mode enable bit 12 1 read-write DOZEEN_0 Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. 0 DOZEEN_1 Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. 0x1 COMBINATIONEN This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]). 13 1 read-write COMBINATIONEN_0 Disable. 0 COMBINATIONEN_1 Enable. 0x1 SCKFREERUNEN This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). 14 1 read-write SCKFREERUNEN_0 Disable. 0 SCKFREERUNEN_1 Enable. 0x1 IPGRANTWAIT Time out wait cycle for IP command grant. 16 8 read-write AHBGRANTWAIT Timeout wait cycle for AHB command grant. 24 8 read-write MCR1 Module Control Register 1 0x4 32 read-write 0xFFFFFFFF 0xFFFFFFFF AHBBUSWAIT AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response 0 16 read-write SEQWAIT Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles 16 16 read-write MCR2 Module Control Register 2 0x8 32 read-write 0x200081F7 0xFFFFFFFF CLRAHBBUFOPT This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. 11 1 read-write CLRAHBBUFOPT_0 AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. 0 CLRAHBBUFOPT_1 AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. 0x1 CLRLEARNPHASE The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately. 14 1 read-write SAMEDEVICEEN All external devices are same devices (both in types and size) for A1/A2/B1/B2. 15 1 read-write SAMEDEVICEEN_0 In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. 0 SAMEDEVICEEN_1 FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. 0x1 SCKBDIFFOPT B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set. 19 1 read-write SCKBDIFFOPT_0 B_SCLK pad is used as port B SCLK clock output. Port B flash access is available. 0 SCKBDIFFOPT_1 B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available. 0x1 RESUMEWAIT Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. 24 8 read-write AHBCR AHB Bus Control Register 0xC 32 read-write 0x18 0xFFFFFFFF APAREN Parallel mode enabled for AHB triggered Command (both read and write) . 0 1 read-write APAREN_0 Flash will be accessed in Individual mode. 0 APAREN_1 Flash will be accessed in Parallel mode. 0x1 CLRAHBRXBUF Clear the status/pointers of AHB RX Buffer. Auto-cleared. 1 1 read-write CLRAHBTXBUF Clear the status/pointers of AHB TX Buffer. Auto-cleared. 2 1 read-write CACHABLEEN Enable AHB bus cachable read access support. 3 1 read-write CACHABLEEN_0 Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. 0 CACHABLEEN_1 Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. 0x1 BUFFERABLEEN Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. 4 1 read-write BUFFERABLEEN_0 Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. 0 BUFFERABLEEN_1 Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished. 0x1 PREFETCHEN AHB Read Prefetch Enable. 5 1 read-write READADDROPT AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. 6 1 read-write READADDROPT_0 There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. 0 READADDROPT_1 There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement. 0x1 READSZALIGN AHB Read Size Alignment 10 1 read-write READSZALIGN_0 AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN... 0 READSZALIGN_1 AHB read size to up size to 8 bytes aligned, no prefetching 0x1 INTEN Interrupt Enable Register 0x10 32 read-write 0 0xFFFFFFFF IPCMDDONEEN IP triggered Command Sequences Execution finished interrupt enable. 0 1 read-write IPCMDGEEN IP triggered Command Sequences Grant Timeout interrupt enable. 1 1 read-write AHBCMDGEEN AHB triggered Command Sequences Grant Timeout interrupt enable. 2 1 read-write IPCMDERREN IP triggered Command Sequences Error Detected interrupt enable. 3 1 read-write AHBCMDERREN AHB triggered Command Sequences Error Detected interrupt enable. 4 1 read-write IPRXWAEN IP RX FIFO WaterMark available interrupt enable. 5 1 read-write IPTXWEEN IP TX FIFO WaterMark empty interrupt enable. 6 1 read-write SCKSTOPBYRDEN SCLK is stopped during command sequence because Async RX FIFO full interrupt enable. 8 1 read-write SCKSTOPBYWREN SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable. 9 1 read-write AHBBUSERROREN AHB Bus error interrupt enable.Refer Interrupts chapter for more details. 10 1 read-write SEQTIMEOUTEN Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. 11 1 read-write KEYDONEEN OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details. 12 1 read-write KEYERROREN OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details. 13 1 read-write INTR Interrupt Register 0x14 32 read-write 0 0xFFFFFFFF IPCMDDONE IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated. 0 1 read-write oneToClear IPCMDGE IP triggered Command Sequences Grant Timeout interrupt. 1 1 read-write oneToClear AHBCMDGE AHB triggered Command Sequences Grant Timeout interrupt. 2 1 read-write oneToClear IPCMDERR IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all. 3 1 read-write oneToClear AHBCMDERR AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all. 4 1 read-write oneToClear IPRXWA IP RX FIFO watermark available interrupt. 5 1 read-write oneToClear IPTXWE IP TX FIFO watermark empty interrupt. 6 1 read-write oneToClear SCKSTOPBYRD SCLK is stopped during command sequence because Async RX FIFO full interrupt. 8 1 read-write oneToClear SCKSTOPBYWR SCLK is stopped during command sequence because Async TX FIFO empty interrupt. 9 1 read-write oneToClear AHBBUSERROR AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt. 10 1 read-write oneToClear SEQTIMEOUT Sequence execution timeout interrupt. 11 1 read-write oneToClear KEYDONE OTFAD key blob processing done interrupt. 12 1 read-write oneToClear KEYERROR OTFAD key blob processing error interrupt. 13 1 read-only LUTKEY LUT Key Register 0x18 32 read-write 0x5AF05AF0 0xFFFFFFFF KEY The Key to lock or unlock LUT. 0 32 read-write LUTCR LUT Control Register 0x1C 32 read-write 0x2 0xFFFFFFFF LOCK Lock LUT 0 1 read-write UNLOCK Unlock LUT 1 1 read-write AHBRXBUF0CR0 AHB RX Buffer 0 Control Register 0 0x20 32 read-write 0x80000020 0xFFFFFFFF BUFSZ AHB RX Buffer Size in 64 bits. 0 8 read-write MSTRID This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). 16 4 read-write PRIORITY This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. 24 2 read-write PREFETCHEN AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. 31 1 read-write AHBRXBUF1CR0 AHB RX Buffer 1 Control Register 0 0x24 32 read-write 0x80010020 0xFFFFFFFF BUFSZ AHB RX Buffer Size in 64 bits. 0 8 read-write MSTRID This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). 16 4 read-write PRIORITY This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. 24 2 read-write PREFETCHEN AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. 31 1 read-write AHBRXBUF2CR0 AHB RX Buffer 2 Control Register 0 0x28 32 read-write 0x80020020 0xFFFFFFFF BUFSZ AHB RX Buffer Size in 64 bits. 0 8 read-write MSTRID This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). 16 4 read-write PRIORITY This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. 24 2 read-write PREFETCHEN AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. 31 1 read-write AHBRXBUF3CR0 AHB RX Buffer 3 Control Register 0 0x2C 32 read-write 0x80030020 0xFFFFFFFF BUFSZ AHB RX Buffer Size in 64 bits. 0 8 read-write MSTRID This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). 16 4 read-write PRIORITY This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. 24 2 read-write PREFETCHEN AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. 31 1 read-write FLSHA1CR0 Flash Control Register 0 0x60 32 read-write 0x10000 0xFFFFFFFF FLSHSZ Flash Size in KByte. 0 23 read-write FLSHA2CR0 Flash Control Register 0 0x64 32 read-write 0x10000 0xFFFFFFFF FLSHSZ Flash Size in KByte. 0 23 read-write FLSHB1CR0 Flash Control Register 0 0x68 32 read-write 0x10000 0xFFFFFFFF FLSHSZ Flash Size in KByte. 0 23 read-write FLSHB2CR0 Flash Control Register 0 0x6C 32 read-write 0x10000 0xFFFFFFFF FLSHSZ Flash Size in KByte. 0 23 read-write 4 0x4 A1,A2,B1,B2 FLSHCR1%s Flash Control Register 1 0x70 32 read-write 0x63 0xFFFFFFFF TCSS Serial Flash CS setup time. 0 5 read-write TCSH Serial Flash CS Hold time. 5 5 read-write WA Word Addressable. 10 1 read-write CAS Column Address Size. 11 4 read-write CSINTERVALUNIT CS interval unit 15 1 read-write CSINTERVALUNIT_0 The CS interval unit is 1 serial clock cycle 0 CSINTERVALUNIT_1 The CS interval unit is 256 serial clock cycle 0x1 CSINTERVAL This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0. 16 16 read-write 4 0x4 A1,A2,B1,B2 FLSHCR2%s Flash Control Register 2 0x80 32 read-write 0 0xFFFFFFFF ARDSEQID Sequence Index for AHB Read triggered Command in LUT. 0 4 read-write ARDSEQNUM Sequence Number for AHB Read triggered Command in LUT. 5 3 read-write AWRSEQID Sequence Index for AHB Write triggered Command. 8 4 read-write AWRSEQNUM Sequence Number for AHB Write triggered Command. 13 3 read-write AWRWAIT For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface 16 12 read-write AWRWAITUNIT AWRWAIT unit 28 3 read-write AWRWAITUNIT_0 The AWRWAIT unit is 2 ahb clock cycle 0 AWRWAITUNIT_1 The AWRWAIT unit is 8 ahb clock cycle 0x1 AWRWAITUNIT_2 The AWRWAIT unit is 32 ahb clock cycle 0x2 AWRWAITUNIT_3 The AWRWAIT unit is 128 ahb clock cycle 0x3 AWRWAITUNIT_4 The AWRWAIT unit is 512 ahb clock cycle 0x4 AWRWAITUNIT_5 The AWRWAIT unit is 2048 ahb clock cycle 0x5 AWRWAITUNIT_6 The AWRWAIT unit is 8192 ahb clock cycle 0x6 AWRWAITUNIT_7 The AWRWAIT unit is 32768 ahb clock cycle 0x7 CLRINSTRPTR Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details. 31 1 read-write FLSHCR4 Flash Control Register 4 0x94 32 read-write 0 0xFFFFFFFF WMOPT1 Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. 0 1 read-write WMOPT1_0 DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. 0 WMOPT1_1 DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode. 0x1 WMENA Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. 2 1 read-write WMENA_0 Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 0 WMENA_1 Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. 0x1 WMENB Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. 3 1 read-write WMENB_0 Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 0 WMENB_1 Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. 0x1 IPCR0 IP Control Register 0 0xA0 32 read-write 0 0xFFFFFFFF SFAR Serial Flash Address for IP command. 0 32 read-write IPCR1 IP Control Register 1 0xA4 32 read-write 0 0xFFFFFFFF IDATSZ Flash Read/Program Data Size (in Bytes) for IP command. 0 16 read-write ISEQID Sequence Index in LUT for IP command. 16 4 read-write ISEQNUM Sequence Number for IP command: ISEQNUM+1. 24 3 read-write IPAREN Parallel mode Enabled for IP command. 31 1 read-write IPAREN_0 Flash will be accessed in Individual mode. 0 IPAREN_1 Flash will be accessed in Parallel mode. 0x1 IPCMD IP Command Register 0xB0 32 read-write 0 0xFFFFFFFF TRG Setting this bit will trigger an IP Command. 0 1 read-write IPRXFCR IP RX FIFO Control Register 0xB8 32 read-write 0 0xFFFFFFFF CLRIPRXF Clear all valid data entries in IP RX FIFO. 0 1 read-write RXDMAEN IP RX FIFO reading by DMA enabled. 1 1 read-write RXDMAEN_0 IP RX FIFO would be read by processor. 0 RXDMAEN_1 IP RX FIFO would be read by DMA. 0x1 RXWMRK Watermark level is (RXWMRK+1)*64 Bits. 2 4 read-write IPTXFCR IP TX FIFO Control Register 0xBC 32 read-write 0 0xFFFFFFFF CLRIPTXF Clear all valid data entries in IP TX FIFO. 0 1 read-write TXDMAEN IP TX FIFO filling by DMA enabled. 1 1 read-write TXDMAEN_0 IP TX FIFO would be filled by processor. 0 TXDMAEN_1 IP TX FIFO would be filled by DMA. 0x1 TXWMRK Watermark level is (TXWMRK+1)*64 Bits. 2 4 read-write 2 0x4 A,B DLLCR%s DLL Control Register 0 0xC0 32 read-write 0x100 0xFFFFFFFF DLLEN DLL calibration enable. 0 1 read-write DLLRESET Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation). 1 1 read-write SLVDLYTARGET The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1, OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended. 3 4 read-write OVRDEN Slave clock delay line delay cell number selection override enable. 8 1 read-write OVRDVAL Slave clock delay line delay cell number selection override value. 9 6 read-write STS0 Status Register 0 0xE0 32 read-only 0x2 0xFFFFFFFF SEQIDLE This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface. 0 1 read-only ARBIDLE This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. 1 1 read-only ARBCMDSRC This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). 2 2 read-only ARBCMDSRC_0 Triggered by AHB read command (triggered by AHB read). 0 ARBCMDSRC_1 Triggered by AHB write command (triggered by AHB Write). 0x1 ARBCMDSRC_2 Triggered by IP command (triggered by setting register bit IPCMD.TRG). 0x2 ARBCMDSRC_3 Triggered by suspended command (resumed). 0x3 STS1 Status Register 1 0xE4 32 read-only 0 0xFFFFFFFF AHBCMDERRID Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). 0 4 read-only AHBCMDERRCODE Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). 8 4 read-only AHBCMDERRCODE_0 No error. 0 AHBCMDERRCODE_2 AHB Write command with JMP_ON_CS instruction used in the sequence. 0x2 AHBCMDERRCODE_3 There is unknown instruction opcode in the sequence. 0x3 AHBCMDERRCODE_4 Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. 0x4 AHBCMDERRCODE_5 Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. 0x5 AHBCMDERRCODE_14 Sequence execution timeout. 0xE IPCMDERRID Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). 16 4 read-only IPCMDERRCODE Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). 24 4 read-only IPCMDERRCODE_0 No error. 0 IPCMDERRCODE_2 IP command with JMP_ON_CS instruction used in the sequence. 0x2 IPCMDERRCODE_3 There is unknown instruction opcode in the sequence. 0x3 IPCMDERRCODE_4 Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. 0x4 IPCMDERRCODE_5 Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. 0x5 IPCMDERRCODE_6 Flash access start address exceed the whole flash address range (A1/A2/B1/B2). 0x6 IPCMDERRCODE_14 Sequence execution timeout. 0xE IPCMDERRCODE_15 Flash boundary crossed. 0xF STS2 Status Register 2 0xE8 32 read-only 0x1000100 0xFFFFFFFF ASLVLOCK Flash A sample clock slave delay line locked. 0 1 read-only AREFLOCK Flash A sample clock reference delay line locked. 1 1 read-only ASLVSEL Flash A sample clock slave delay line delay cell number selection . 2 6 read-only AREFSEL Flash A sample clock reference delay line delay cell number selection. 8 6 read-only BSLVLOCK Flash B sample clock slave delay line locked. 16 1 read-only BREFLOCK Flash B sample clock reference delay line locked. 17 1 read-only BSLVSEL Flash B sample clock slave delay line delay cell number selection. 18 6 read-only BREFSEL Flash B sample clock reference delay line delay cell number selection. 24 6 read-only AHBSPNDSTS AHB Suspend Status Register 0xEC 32 read-only 0 0xFFFFFFFF ACTIVE Indicates if an AHB read prefetch command sequence has been suspended. 0 1 read-only BUFID AHB RX BUF ID for suspended command sequence. 1 3 read-only DATLFT Left Data size for suspended command sequence (in byte). 16 16 read-only IPRXFSTS IP RX FIFO Status Register 0xF0 32 read-only 0 0xFFFFFFFF FILL Fill level of IP RX FIFO. 0 8 read-only RDCNTR Total Read Data Counter: RDCNTR * 64 Bits. 16 16 read-only IPTXFSTS IP TX FIFO Status Register 0xF4 32 read-only 0 0xFFFFFFFF FILL Fill level of IP TX FIFO. 0 8 read-only WRCNTR Total Write Data Counter: WRCNTR * 64 Bits. 16 16 read-only 32 0x4 RFDR[%s] IP RX FIFO Data Register 0 0x100 32 read-only 0 0xFFFFFFFF RXDATA RX Data 0 32 read-only 32 0x4 TFDR[%s] IP TX FIFO Data Register 0 0x180 32 write-only 0 0xFFFFFFFF TXDATA TX Data 0 32 write-only 64 0x4 LUT[%s] LUT 0 0x200 32 read-write 0 0 OPERAND0 OPERAND0 0 8 read-write NUM_PADS0 NUM_PADS0 8 2 read-write OPCODE0 OPCODE 10 6 read-write OPERAND1 OPERAND1 16 8 read-write NUM_PADS1 NUM_PADS1 24 2 read-write OPCODE1 OPCODE1 26 6 read-write OTFAD OTFAD FLEXSPI OTFAD 0x400A0000 0 0xDE0 registers CR Control Register 0xC00 32 read-write 0 0xFFFFFFFF IRQE IRQE 0 1 read-write IRQE_0 SR[KBERR] = 1 does not generate an interrupt request. 0 IRQE_1 SR[KBERR] = 1 generates an interrupt request. 0x1 FERR Force Error 1 1 read-write FERR_0 No effect on the SR[KBERE] indicator. 0 FERR_1 SR[KBERR] is immediately set after a write with this data bit set. 0x1 FSVM Force Security Violation Mode 2 1 read-write FSVM_0 No effect on the operating mode. 0 FSVM_1 Force entry into SVM after a write with this data bit set and the data bit associated with FLDM cleared. SR[MODE] signals the operating mode. 0x1 FLDM Force Logically Disabled Mode 3 1 read-write FLDM_0 No effect on the operating mode. 0 FLDM_1 Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode. 0x1 KBSE Key Blob Scramble Enable 4 1 read-write KBSE_0 Key blob KEK scrambling is disabled. 0 KBSE_1 Key blob KEK scrambling is enabled. 0x1 KBPE Key Blob Processing Enable 5 1 read-write KBPE_0 Key blob processing is disabled. 0 KBPE_1 Key blob processing is enabled. 0x1 KBCE Key Blob CRC Enable 6 1 read-write KBCE_0 CRC-32 during key blob processing is disabled. 0 KBCE_1 CRC-32 during key blob processing is enabled. 0x1 RRAE Restricted Register Access Enable 7 1 read-write RRAE_0 Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". 0 RRAE_1 Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI. 0x1 SKBP Start key blob processing 30 1 read-write SKBP_0 Key blob processing is not initiated. 0 SKBP_1 Properly-enabled key blob processing is initiated. 0x1 GE Global OTFAD Enable 31 1 read-write GE_0 OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing. 0 GE_1 OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration. 0x1 SR Status Register 0xC04 32 read-write 0x40 0xFFFFFFFF KBERR Key Blob Error 0 1 read-write oneToClear KBERR_0 No key blob error detected. 0 KBERR_1 One or more key blob errors has been detected. 0x1 MDPCP MDPC Present 1 1 read-only MODE Operating Mode 2 2 read-only MODE_0 Operating in Normal mode (NRM) 0 MODE_1 Unused (reserved) 0x1 MODE_2 Operating in Security Violation Mode (SVM) 0x2 MODE_3 Operating in Logically Disabled Mode (LDM) 0x3 NCTX Number of Contexts 4 4 read-only CTXER0 Context Error 8 1 read-only NOERROR No key blob error was detected for context "n". 0 ERROR Either a key blob integrity error or a key blob CRC error was detected in context "n". 0x1 CTXER1 Context Error 9 1 read-only NOERROR No key blob error was detected for context "n". 0 ERROR Either a key blob integrity error or a key blob CRC error was detected in context "n". 0x1 CTXER2 Context Error 10 1 read-only NOERROR No key blob error was detected for context "n". 0 ERROR Either a key blob integrity error or a key blob CRC error was detected in context "n". 0x1 CTXER3 Context Error 11 1 read-only NOERROR No key blob error was detected for context "n". 0 ERROR Either a key blob integrity error or a key blob CRC error was detected in context "n". 0x1 CTXIE0 Context Integrity Error 16 1 read-only NOINTEGRITYERR No key blob integrity error was detected for context "n". 0 INTEGRITYERR A key blob integrity error was detected in context "n". 0x1 CTXIE1 Context Integrity Error 17 1 read-only NOINTEGRITYERR No key blob integrity error was detected for context "n". 0 INTEGRITYERR A key blob integrity error was detected in context "n". 0x1 CTXIE2 Context Integrity Error 18 1 read-only NOINTEGRITYERR No key blob integrity error was detected for context "n". 0 INTEGRITYERR A key blob integrity error was detected in context "n". 0x1 CTXIE3 Context Integrity Error 19 1 read-only NOINTEGRITYERR No key blob integrity error was detected for context "n". 0 INTEGRITYERR A key blob integrity error was detected in context "n". 0x1 HRL Hardware Revision Level 24 4 read-only RRAM Restricted Register Access Mode 28 1 read-only RRAM_0 Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". 0 RRAM_1 Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI. 0x1 GEM Global Enable Mode 29 1 read-only GEM_0 OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing. 0 GEM_1 OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration. 0x1 KBPE Key Blob Processing Enable 30 1 read-only KBPE_0 Key blob processing is not enabled. 0 KBPE_1 Key blob processing is enabled. 0x1 KBD Key Blob Processing Done 31 1 read-only KBD_0 Key blob processing was not enabled, or is not complete. 0 KBD_1 Key blob processing was enabled and is complete. 0x1 4 0x40 CTX[%s] no description available 0xD00 4 0x4 0,1,2,3 CTX_KEY%s AES Key Word 0 32 read-write 0 0xFFFFFFFF KEY AES Key 0 32 read-write 2 0x4 0,1 CTX_CTR%s AES Counter Word 0x10 32 read-write 0 0xFFFFFFFF CTR AES Counter 0 32 read-write CTX_RGD_W0 AES Region Descriptor Word0 0x18 32 read-write 0 0xFFFFFFFF SRTADDR Start Address 10 22 read-write CTX_RGD_W1 AES Region Descriptor Word1 0x1C 32 read-write 0x3F8 0xFFFFFFFF VLD Valid 0 1 read-write VLD_0 Context is invalid. 0 VLD_1 Context is valid. 0x1 ADE AES Decryption Enable. 1 1 read-write ADE_0 Bypass the fetched data. 0 ADE_1 Perform the CTR-AES128 mode decryption on the fetched data. 0x1 RO Read-Only 2 1 read-write RO_0 The context registers can be accessed normally (as defined by SR[RRAM]). 0 RO_1 The context registers are read-only and accesses may be further restricted based on SR[RRAM]. 0x1 ENDADDR End Address 10 22 read-write IOMUXC_SNVS_GPR IOMUXC IOMUXC_SNVS_GPR IOMUXC_SNVS_GPR_ 0x400A4000 0 0x10 registers GPR0 GPR0 General Purpose Register 0 32 read-only 0 0xFFFFFFFF GPR1 GPR1 General Purpose Register 0x4 32 read-only 0 0xFFFFFFFF GPR2 GPR2 General Purpose Register 0x8 32 read-only 0 0xFFFFFFFF GPR3 GPR3 General Purpose Register 0xC 32 read-write 0 0xFFFFFFFF LPSR_MODE_ENABLE Set to enable LPSR mode. 0 1 read-write DCDC_STATUS_CAPT_CLR DCDC captured status clear 1 1 read-write POR_PULL_TYPE POR_B pad control 2 2 read-write DCDC_IN_LOW_VOL DCDC_IN low voltage detect. 16 1 read-only DCDC_OVER_CUR DCDC output over current alert 17 1 read-only DCDC_OVER_VOL DCDC output over voltage alert 18 1 read-only DCDC_STS_DC_OK DCDC status OK 19 1 read-only IOMUXC_SNVS IOMUXC_SNVS IOMUXC_SNVS IOMUXC_SNVS_ 0x400A8000 0 0x14 registers SW_MUX_CTL_PAD_PMIC_ON_REQ SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register 0 32 read-write 0 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp 0 ALT5 Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad PMIC_ON_REQ 0x1 SW_PAD_CTL_PAD_TEST_MODE SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register 0x4 32 read-write 0x30A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-only SPEED medium(100MHz) 0x2 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_POR_B SW_PAD_CTL_PAD_POR_B SW PAD Control Register 0x8 32 read-write 0x1B0A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-only SPEED medium(100MHz) 0x2 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_ONOFF SW_PAD_CTL_PAD_ONOFF SW PAD Control Register 0xC 32 read-write 0x1B0A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-only SPEED medium(100MHz) 0x2 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_PMIC_ON_REQ SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register 0x10 32 read-write 0xB8A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-only SPEED medium(100MHz) 0x2 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 IOMUXC_GPR IOMUXC_GPR IOMUXC_GPR IOMUXC_GPR_ 0x400AC000 0 0x78 registers GPR0 GPR0 General Purpose Register 0 32 read-only 0 0xFFFFFFFF GPR1 GPR1 General Purpose Register 0x4 32 read-write 0 0xFFFFFFFF SAI1_MCLK1_SEL SAI1 MCLK1 source select 0 3 read-write SAI1_MCLK1_SEL_0 ccm.ssi1_clk_root 0 SAI1_MCLK1_SEL_2 ccm.ssi3_clk_root 0x2 SAI1_MCLK1_SEL_3 iomux.sai1_ipg_clk_sai_mclk 0x3 SAI1_MCLK1_SEL_5 iomux.sai3_ipg_clk_sai_mclk 0x5 SAI1_MCLK2_SEL SAI1 MCLK2 source select 3 3 read-write SAI1_MCLK2_SEL_0 ccm.ssi1_clk_root 0 SAI1_MCLK2_SEL_2 ccm.ssi3_clk_root 0x2 SAI1_MCLK2_SEL_3 iomux.sai1_ipg_clk_sai_mclk 0x3 SAI1_MCLK2_SEL_5 iomux.sai3_ipg_clk_sai_mclk 0x5 SAI1_MCLK3_SEL SAI1 MCLK3 source select 6 2 read-write SAI1_MCLK3_SEL_0 ccm.spdif0_clk_root 0 SAI1_MCLK3_SEL_1 SPDIF_EXT_CLK 0x1 SAI1_MCLK3_SEL_2 spdif.spdif_srclk 0x2 SAI1_MCLK3_SEL_3 spdif.spdif_outclock 0x3 SAI3_MCLK3_SEL SAI3 MCLK3 source select 10 2 read-write SAI3_MCLK3_SEL_0 ccm.spdif0_clk_root 0 SAI3_MCLK3_SEL_1 SPDIF_EXT_CLK 0x1 SAI3_MCLK3_SEL_2 spdif.spdif_srclk 0x2 SAI3_MCLK3_SEL_3 spdif.spdif_outclock 0x3 GINT Global Interrupt 12 1 read-write GINT_0 Global interrupt request is not asserted. 0 GINT_1 Global interrupt request is asserted. 0x1 SAI1_MCLK_DIR sai1.MCLK signal direction control 19 1 read-write SAI1_MCLK_DIR_0 sai1.MCLK is input signal 0 SAI1_MCLK_DIR_1 sai1.MCLK is output signal 0x1 SAI3_MCLK_DIR sai3.MCLK signal direction control 21 1 read-write SAI3_MCLK_DIR_0 sai3.MCLK is input signal 0 SAI3_MCLK_DIR_1 sai3.MCLK is output signal 0x1 EXC_MON Exclusive monitor response select of illegal command 22 1 read-write EXC_MON_0 OKAY response 0 EXC_MON_1 SLVError response 0x1 CM7_FORCE_HCLK_EN ARM CM7 platform AHB clock enable 31 1 read-write CM7_FORCE_HCLK_EN_0 AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible. 0 CM7_FORCE_HCLK_EN_1 AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible. 0x1 GPR2 GPR2 General Purpose Register 0x8 32 read-write 0 0xFFFFFFFF AXBS_P_M0_HIGH_PRIORITY AXBS_P M0 master has higher priority.Do not set both M1 and M0 to high priority. 3 1 read-write AXBS_P_M0_HIGH_PRIORITY_0 AXBS_P M0 master doesn't have high priority 0 AXBS_P_M0_HIGH_PRIORITY_1 AXBS_P M0 master has high priority 0x1 AXBS_P_M1_HIGH_PRIORITY AXBS_P M1 master has higher priority.Do not set both M1 and M0 to high priority. 4 1 read-write AXBS_P_M1_HIGH_PRIORITY_0 AXBS_P M1 master does not have high priority 0 AXBS_P_M1_HIGH_PRIORITY_1 AXBS_P M1 master has high priority 0x1 AXBS_P_FORCE_ROUND_ROBIN Force Round Robin in AXBS_P. This bit can override master M0 M1 high priority configuration. 5 1 read-write AXBS_P_FORCE_ROUND_ROBIN_0 AXBS_P masters are not arbitored in round robin, depending on M0/M1 master priority settings. 0 AXBS_P_FORCE_ROUND_ROBIN_1 AXBS_P masters are arbitored in round robin 0x1 L2_MEM_EN_POWERSAVING Enable power saving features on L2 memory 12 1 read-write L2_MEM_EN_POWERSAVING_0 Enters power saving mode only when chip is in SUSPEND mode 0 L2_MEM_EN_POWERSAVING_1 Controlled by L2_MEM_DEEPSLEEP bitfield 0x1 RAM_AUTO_CLK_GATING_EN Automatically gate off RAM clock when RAM is not accessed. 13 1 read-write RAM_AUTO_CLK_GATING_EN_0 disable automatically gate off RAM clock 0 RAM_AUTO_CLK_GATING_EN_1 enable automatically gate off RAM clock 0x1 L2_MEM_DEEPSLEEP This bit controls how memory (OCRAM) enters Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low 14 1 read-write L2_MEM_DEEPSLEEP_0 No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode) 0 L2_MEM_DEEPSLEEP_1 Force memory into deep sleep mode (OCRAM in power saving mode) 0x1 MQS_CLK_DIV Divider ratio control for mclk from hmclk 16 8 read-write MQS_CLK_DIV_0 mclk frequency = hmclk frequency 0 MQS_CLK_DIV_1 mclk frequency = 1/2 * hmclk frequency 0x1 MQS_CLK_DIV_2 mclk frequency = 1/3 * hmclk frequency 0x2 MQS_CLK_DIV_255 mclk frequency = 1/256 * hmclk frequency 0xFF MQS_SW_RST MQS software reset 24 1 read-write MQS_SW_RST_0 Exit software reset for MQS 0 MQS_SW_RST_1 Enable software reset for MQS 0x1 MQS_EN MQS enable. 25 1 read-write MQS_EN_0 Disable MQS 0 MQS_EN_1 Enable MQS 0x1 MQS_OVERSAMPLE Medium Quality Sound (MQS) Oversample 26 1 read-write MQS_OVERSAMPLE_0 32 0 MQS_OVERSAMPLE_1 64 0x1 GPR3 GPR3 General Purpose Register 0xC 32 read-write 0xFF0 0xFFFFFFFF DCP_KEY_SEL Select 128-bit DCP key from 256-bit key from SNVS Master Key 4 1 read-write DCP_KEY_SEL_0 Select [127:0] from SNVS Master Key as DCP key 0 DCP_KEY_SEL_1 Select [255:128] from SNVS Master Key as DCP key 0x1 GPR4 GPR4 General Purpose Register 0x10 32 read-write 0 0xFFFFFFFF EDMA_STOP_REQ EDMA stop request. 0 1 read-write EDMA_STOP_REQ_0 stop request off 0 EDMA_STOP_REQ_1 stop request on 0x1 TRNG_STOP_REQ TRNG stop request. 3 1 read-write TRNG_STOP_REQ_0 stop request off 0 TRNG_STOP_REQ_1 stop request on 0x1 SAI1_STOP_REQ SAI1 stop request. 5 1 read-write SAI1_STOP_REQ_0 stop request off 0 SAI1_STOP_REQ_1 stop request on 0x1 SAI3_STOP_REQ SAI3 stop request. 7 1 read-write SAI3_STOP_REQ_0 stop request off 0 SAI3_STOP_REQ_1 stop request on 0x1 PIT_STOP_REQ PIT stop request. 10 1 read-write PIT_STOP_REQ_0 stop request off 0 PIT_STOP_REQ_1 stop request on 0x1 FLEXSPI_STOP_REQ FlexSPI stop request. 11 1 read-write FLEXSPI_STOP_REQ_0 stop request off 0 FLEXSPI_STOP_REQ_1 stop request on 0x1 FLEXIO1_STOP_REQ FlexIO1 stop request. 12 1 read-write FLEXIO1_STOP_REQ_0 stop request off 0 FLEXIO1_STOP_REQ_1 stop request on 0x1 EDMA_STOP_ACK EDMA stop acknowledge. This is a status (read-only) bit 16 1 read-only EDMA_STOP_ACK_0 EDMA stop acknowledge is not asserted 0 EDMA_STOP_ACK_1 EDMA stop acknowledge is asserted (EDMA is in STOP mode). 0x1 TRNG_STOP_ACK TRNG stop acknowledge 19 1 read-only TRNG_STOP_ACK_0 TRNG stop acknowledge is not asserted 0 TRNG_STOP_ACK_1 TRNG stop acknowledge is asserted 0x1 SAI1_STOP_ACK SAI1 stop acknowledge 21 1 read-only SAI1_STOP_ACK_0 SAI1 stop acknowledge is not asserted 0 SAI1_STOP_ACK_1 SAI1 stop acknowledge is asserted 0x1 SAI3_STOP_ACK SAI3 stop acknowledge 23 1 read-only SAI3_STOP_ACK_0 SAI3 stop acknowledge is not asserted 0 SAI3_STOP_ACK_1 SAI3 stop acknowledge is asserted 0x1 PIT_STOP_ACK PIT stop acknowledge 26 1 read-only PIT_STOP_ACK_0 PIT stop acknowledge is not asserted 0 PIT_STOP_ACK_1 PIT stop acknowledge is asserted 0x1 FLEXSPI_STOP_ACK FLEXSPI stop acknowledge 27 1 read-only FLEXSPI_STOP_ACK_0 FLEXSPI stop acknowledge is not asserted 0 FLEXSPI_STOP_ACK_1 FLEXSPI stop acknowledge is asserted 0x1 FLEXIO1_STOP_ACK FLEXIO1 stop acknowledge 28 1 read-only FLEXIO1_STOP_ACK_0 FLEXIO1 stop acknowledge is not asserted 0 FLEXIO1_STOP_ACK_1 FLEXIO1 stop acknowledge is asserted 0x1 GPR5 GPR5 General Purpose Register 0x14 32 read-write 0 0xFFFFFFFF WDOG1_MASK WDOG1 Timeout Mask 6 1 read-write WDOG1_MASK_0 WDOG1 Timeout behaves normally 0 WDOG1_MASK_1 WDOG1 Timeout is masked 0x1 WDOG2_MASK WDOG2 Timeout Mask 7 1 read-write WDOG2_MASK_0 WDOG2 Timeout behaves normally 0 WDOG2_MASK_1 WDOG2 Timeout is masked 0x1 VREF_1M_CLK_GPT1 GPT1 1 MHz clock source select 28 1 read-write VREF_1M_CLK_GPT1_0 GPT1 ipg_clk_highfreq driven by IPG_PERCLK 0 VREF_1M_CLK_GPT1_1 GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock 0x1 VREF_1M_CLK_GPT2 GPT2 1 MHz clock source select 29 1 read-write VREF_1M_CLK_GPT2_0 GPT2 ipg_clk_highfreq driven by IPG_PERCLK 0 VREF_1M_CLK_GPT2_1 GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock 0x1 GPR6 GPR6 General Purpose Register 0x18 32 read-write 0 0xFFFFFFFF IOMUXC_XBAR_DIR_SEL_2 IOMUXC XBAR_INOUT2 function direction select 16 1 read-write IOMUXC_XBAR_DIR_SEL_2_0 XBAR_INOUT as input 0 IOMUXC_XBAR_DIR_SEL_2_1 XBAR_INOUT as output 0x1 IOMUXC_XBAR_DIR_SEL_3 IOMUXC XBAR_INOUT3 function direction select 17 1 read-write IOMUXC_XBAR_DIR_SEL_3_0 XBAR_INOUT as input 0 IOMUXC_XBAR_DIR_SEL_3_1 XBAR_INOUT as output 0x1 GPR7 GPR7 General Purpose Register 0x1C 32 read-write 0 0xFFFFFFFF LPI2C1_STOP_REQ LPI2C1 stop request 0 1 read-write LPI2C1_STOP_REQ_0 stop request off 0 LPI2C1_STOP_REQ_1 stop request on 0x1 LPI2C2_STOP_REQ LPI2C2 stop request 1 1 read-write LPI2C2_STOP_REQ_0 stop request off 0 LPI2C2_STOP_REQ_1 stop request on 0x1 LPSPI1_STOP_REQ LPSPI1 stop request 4 1 read-write LPSPI1_STOP_REQ_0 stop request off 0 LPSPI1_STOP_REQ_1 stop request on 0x1 LPSPI2_STOP_REQ LPSPI2 stop request 5 1 read-write LPSPI2_STOP_REQ_0 stop request off 0 LPSPI2_STOP_REQ_1 stop request on 0x1 LPUART1_STOP_REQ LPUART1 stop request 8 1 read-write LPUART1_STOP_REQ_0 stop request off 0 LPUART1_STOP_REQ_1 stop request on 0x1 LPUART2_STOP_REQ LPUART1 stop request 9 1 read-write LPUART2_STOP_REQ_0 stop request off 0 LPUART2_STOP_REQ_1 stop request on 0x1 LPUART3_STOP_REQ LPUART3 stop request 10 1 read-write LPUART3_STOP_REQ_0 stop request off 0 LPUART3_STOP_REQ_1 stop request on 0x1 LPUART4_STOP_REQ LPUART4 stop request 11 1 read-write LPUART4_STOP_REQ_0 stop request off 0 LPUART4_STOP_REQ_1 stop request on 0x1 LPI2C1_STOP_ACK LPI2C1 stop acknowledge 16 1 read-only LPI2C1_STOP_ACK_0 stop acknowledge is not asserted 0 LPI2C1_STOP_ACK_1 stop acknowledge is asserted (the module is in Stop mode) 0x1 LPI2C2_STOP_ACK LPI2C2 stop acknowledge 17 1 read-only LPI2C2_STOP_ACK_0 stop acknowledge is not asserted 0 LPI2C2_STOP_ACK_1 stop acknowledge is asserted 0x1 LPSPI1_STOP_ACK LPSPI1 stop acknowledge 20 1 read-only LPSPI1_STOP_ACK_0 stop acknowledge is not asserted 0 LPSPI1_STOP_ACK_1 stop acknowledge is asserted 0x1 LPSPI2_STOP_ACK LPSPI2 stop acknowledge 21 1 read-only LPSPI2_STOP_ACK_0 stop acknowledge is not asserted 0 LPSPI2_STOP_ACK_1 stop acknowledge is asserted 0x1 LPUART1_STOP_ACK LPUART1 stop acknowledge 24 1 read-only LPUART1_STOP_ACK_0 stop acknowledge is not asserted 0 LPUART1_STOP_ACK_1 stop acknowledge is asserted 0x1 LPUART2_STOP_ACK LPUART1 stop acknowledge 25 1 read-only LPUART2_STOP_ACK_0 stop acknowledge is not asserted 0 LPUART2_STOP_ACK_1 stop acknowledge is asserted 0x1 LPUART3_STOP_ACK LPUART3 stop acknowledge 26 1 read-only LPUART3_STOP_ACK_0 stop acknowledge is not asserted 0 LPUART3_STOP_ACK_1 stop acknowledge is asserted 0x1 LPUART4_STOP_ACK LPUART4 stop acknowledge 27 1 read-only LPUART4_STOP_ACK_0 stop acknowledge is not asserted 0 LPUART4_STOP_ACK_1 stop acknowledge is asserted 0x1 GPR8 GPR8 General Purpose Register 0x20 32 read-write 0 0xFFFFFFFF LPI2C1_IPG_STOP_MODE LPI2C1 stop mode selection, cannot change when ipg_stop is asserted. 0 1 read-write LPI2C1_IPG_STOP_MODE_0 the module is functional in Stop mode 0 LPI2C1_IPG_STOP_MODE_1 the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted 0x1 LPI2C1_IPG_DOZE LPI2C1 ipg_doze mode 1 1 read-write LPI2C1_IPG_DOZE_0 not in doze mode 0 LPI2C1_IPG_DOZE_1 in doze mode 0x1 LPI2C2_IPG_STOP_MODE LPI2C2 stop mode selection, cannot change when ipg_stop is asserted. 2 1 read-write LPI2C2_IPG_STOP_MODE_0 the module is functional in Stop mode 0 LPI2C2_IPG_STOP_MODE_1 the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted 0x1 LPI2C2_IPG_DOZE LPI2C2 ipg_doze mode 3 1 read-write LPI2C2_IPG_DOZE_0 not in doze mode 0 LPI2C2_IPG_DOZE_1 in doze mode 0x1 LPSPI1_IPG_STOP_MODE LPSPI1 stop mode selection, cannot change when ipg_stop is asserted. 8 1 read-write LPSPI1_IPG_STOP_MODE_0 the module is functional in Stop mode 0 LPSPI1_IPG_STOP_MODE_1 the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted 0x1 LPSPI1_IPG_DOZE LPSPI1 ipg_doze mode 9 1 read-write LPSPI1_IPG_DOZE_0 not in doze mode 0 LPSPI1_IPG_DOZE_1 in doze mode 0x1 LPSPI2_IPG_STOP_MODE LPSPI2 stop mode selection, cannot change when ipg_stop is asserted. 10 1 read-write LPSPI2_IPG_STOP_MODE_0 the module is functional in Stop mode 0 LPSPI2_IPG_STOP_MODE_1 the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted 0x1 LPSPI2_IPG_DOZE LPSPI2 ipg_doze mode 11 1 read-write LPSPI2_IPG_DOZE_0 not in doze mode 0 LPSPI2_IPG_DOZE_1 in doze mode 0x1 LPUART1_IPG_STOP_MODE LPUART1 stop mode selection, cannot change when ipg_stop is asserted. 16 1 read-write LPUART1_IPG_STOP_MODE_0 the module is functional in Stop mode 0 LPUART1_IPG_STOP_MODE_1 the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted 0x1 LPUART1_IPG_DOZE LPUART1 ipg_doze mode 17 1 read-write LPUART1_IPG_DOZE_0 not in doze mode 0 LPUART1_IPG_DOZE_1 in doze mode 0x1 LPUART2_IPG_STOP_MODE LPUART2 stop mode selection, cannot change when ipg_stop is asserted. 18 1 read-write LPUART2_IPG_STOP_MODE_0 the module is functional in Stop mode 0 LPUART2_IPG_STOP_MODE_1 the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted 0x1 LPUART2_IPG_DOZE LPUART2 ipg_doze mode 19 1 read-write LPUART2_IPG_DOZE_0 not in doze mode 0 LPUART2_IPG_DOZE_1 in doze mode 0x1 LPUART3_IPG_STOP_MODE LPUART3 stop mode selection, cannot change when ipg_stop is asserted. 20 1 read-write LPUART3_IPG_STOP_MODE_0 the module is functional in Stop mode 0 LPUART3_IPG_STOP_MODE_1 the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted 0x1 LPUART3_IPG_DOZE LPUART3 ipg_doze mode 21 1 read-write LPUART3_IPG_DOZE_0 not in doze mode 0 LPUART3_IPG_DOZE_1 in doze mode 0x1 LPUART4_IPG_STOP_MODE LPUART4 stop mode selection, cannot change when ipg_stop is asserted. 22 1 read-write LPUART4_IPG_STOP_MODE_0 the module is functional in Stop mode 0 LPUART4_IPG_STOP_MODE_1 the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted 0x1 LPUART4_IPG_DOZE LPUART4 ipg_doze mode 23 1 read-write LPUART4_IPG_DOZE_0 not in doze mode 0 LPUART4_IPG_DOZE_1 in doze mode 0x1 GPR9 GPR9 General Purpose Register 0x24 32 read-only 0 0xFFFFFFFF GPR10 GPR10 General Purpose Register 0x28 32 read-write 0x7 0xFFFFFFFF NIDEN ARM non-secure (non-invasive) debug enable 0 1 read-write NIDEN_0 Debug turned off. 0 NIDEN_1 Debug enabled (default). 0x1 DBG_EN ARM invasive debug enable 1 1 read-write DBG_EN_0 Debug turned off. 0 DBG_EN_1 Debug enabled (default). 0x1 SEC_ERR_RESP Security error response enable for all security gaskets (on both AHB and AXI buses) 2 1 read-write SEC_ERR_RESP_0 OKEY response 0 SEC_ERR_RESP_1 SLVError (default) 0x1 DCPKEY_OCOTP_OR_KEYMUX DCP Key selection bit. 4 1 read-write DCPKEY_OCOTP_OR_KEYMUX_0 Select key from SNVS Master Key. 0 DCPKEY_OCOTP_OR_KEYMUX_1 Select key from OCOTP (SW_GP2). 0x1 OCRAM_TZ_EN OCRAM TrustZone (TZ) enable. 8 1 read-write OCRAM_TZ_EN_0 The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). 0 OCRAM_TZ_EN_1 The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. 0x1 OCRAM_TZ_ADDR OCRAM TrustZone (TZ) start address 9 5 read-write LOCK_NIDEN Lock NIDEN field for changes 16 1 read-write LOCK_NIDEN_0 Field is not locked 0 LOCK_NIDEN_1 Field is locked (read access only) 0x1 LOCK_DBG_EN Lock DBG_EN field for changes 17 1 read-write LOCK_DBG_EN_0 Field is not locked 0 LOCK_DBG_EN_1 Field is locked (read access only) 0x1 LOCK_SEC_ERR_RESP Lock SEC_ERR_RESP field for changes 18 1 read-write LOCK_SEC_ERR_RESP_0 Field is not locked 0 LOCK_SEC_ERR_RESP_1 Field is locked (read access only) 0x1 LOCK_DCPKEY_OCOTP_OR_KEYMUX Lock DCP Key OCOTP/Key MUX selection bit 20 1 read-write LOCK_DCPKEY_OCOTP_OR_KEYMUX_0 Field is not locked 0 LOCK_DCPKEY_OCOTP_OR_KEYMUX_1 Field is locked (read access only) 0x1 LOCK_OCRAM_TZ_EN Lock OCRAM_TZ_EN field for changes 24 1 read-write LOCK_OCRAM_TZ_EN_0 Field is not locked 0 LOCK_OCRAM_TZ_EN_1 Field is locked (read access only) 0x1 LOCK_OCRAM_TZ_ADDR Lock OCRAM_TZ_ADDR field for changes 25 5 read-write LOCK_OCRAM_TZ_ADDR_0 Field is not locked 0 LOCK_OCRAM_TZ_ADDR_1 Field is locked (read access only) 0x1 GPR11 GPR11 General Purpose Register 0x2C 32 read-write 0 0xFFFFFFFF M7_APC_AC_R0_CTRL Access control of memory region-0 0 2 read-write M7_APC_AC_R0_CTRL_0 No access protection 0 M7_APC_AC_R0_CTRL_1 M7 debug protection enabled 0x1 M7_APC_AC_R1_CTRL Access control of memory region-1 2 2 read-write M7_APC_AC_R1_CTRL_0 No access protection 0 M7_APC_AC_R1_CTRL_1 M7 debug protection enabled 0x1 M7_APC_AC_R2_CTRL Access control of memory region-2 4 2 read-write M7_APC_AC_R2_CTRL_0 No access protection 0 M7_APC_AC_R2_CTRL_1 M7 debug protection enabled 0x1 M7_APC_AC_R3_CTRL Access control of memory region-3 6 2 read-write M7_APC_AC_R3_CTRL_0 No access protection 0 M7_APC_AC_R3_CTRL_1 M7 debug protection enabled 0x1 LOCK_M7_APC_AC_R0_CTRL Lock M7_APC_AC_R0_CTRL field for changes 16 2 read-write LOCK_M7_APC_AC_R1_CTRL Lock M7_APC_AC_R1_CTRL field for changes 18 2 read-write LOCK_M7_APC_AC_R2_CTRL Lock M7_APC_AC_R2_CTRL field for changes 20 2 read-write LOCK_M7_APC_AC_R3_CTRL Lock M7_APC_AC_R3_CTRL field for changes 22 2 read-write GPR12 GPR12 General Purpose Register 0x30 32 read-write 0 0xFFFFFFFF FLEXIO1_IPG_STOP_MODE FlexIO1 stop mode selection. Cannot change when ipg_stop is asserted. 0 1 read-write FLEXIO1_IPG_STOP_MODE_0 FlexIO1 is functional in Stop mode. 0 FLEXIO1_IPG_STOP_MODE_1 When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode. 0x1 FLEXIO1_IPG_DOZE FLEXIO1 ipg_doze mode 1 1 read-write FLEXIO1_IPG_DOZE_0 FLEXIO1 is not in doze mode 0 FLEXIO1_IPG_DOZE_1 FLEXIO1 is in doze mode 0x1 GPR13 GPR13 General Purpose Register 0x34 32 read-write 0 0xFFFFFFFF CACHE_USB USB block cacheable attribute value of AXI transactions 13 1 read-write CACHE_USB_0 Cacheable attribute is off for read/write transactions. 0 CACHE_USB_1 Cacheable attribute is on for read/write transactions. 0x1 GPR14 GPR14 General Purpose Register 0x38 32 read-write 0x880000 0xFFFFFFFF CM7_CFGITCMSZ ITCM total size configuration 16 4 read-write CM7_CFGITCMSZ_0 0 KB (No ITCM) 0 CM7_CFGITCMSZ_3 4 KB 0x3 CM7_CFGITCMSZ_4 8 KB 0x4 CM7_CFGITCMSZ_5 16 KB 0x5 CM7_CFGITCMSZ_6 32 KB 0x6 CM7_CFGITCMSZ_7 64 KB 0x7 CM7_CFGITCMSZ_8 128 KB 0x8 CM7_CFGDTCMSZ DTCM total size configuration 20 4 read-write CM7_CFGDTCMSZ_0 0 KB (No DTCM) 0 CM7_CFGDTCMSZ_3 4 KB 0x3 CM7_CFGDTCMSZ_4 8 KB 0x4 CM7_CFGDTCMSZ_5 16 KB 0x5 CM7_CFGDTCMSZ_6 32 KB 0x6 CM7_CFGDTCMSZ_7 64 KB 0x7 CM7_CFGDTCMSZ_8 128 KB 0x8 GPR15 GPR15 General Purpose Register 0x3C 32 read-only 0xFFFFFFFF 0xFFFFFFFF GPR16 GPR16 General Purpose Register 0x40 32 read-write 0x200003 0xFFFFFFFF INIT_ITCM_EN ITCM enable initialization out of reset 0 1 read-write INIT_ITCM_EN_0 ITCM is disabled 0 INIT_ITCM_EN_1 ITCM is enabled 0x1 INIT_DTCM_EN DTCM enable initialization out of reset 1 1 read-write INIT_DTCM_EN_0 DTCM is disabled 0 INIT_DTCM_EN_1 DTCM is enabled 0x1 FLEXRAM_BANK_CFG_SEL FlexRAM bank config source select 2 1 read-write FLEXRAM_BANK_CFG_SEL_0 use fuse value to config 0 FLEXRAM_BANK_CFG_SEL_1 use FLEXRAM_BANK_CFG to config 0x1 LOCK_VTOR Lock CM7_INIT_VTOR field for changes 6 1 read-write LOCK_VTOR_0 CM7_INIT_VTOR field is not locked. 0 LOCK_VTOR_1 CM7_INIT_VTOR field is locked (read access only). 0x1 CM7_INIT_VTOR Vector table offset register out of reset 7 25 read-write GPR17 GPR17 General Purpose Register 0x44 32 read-write 0 0xFFFFFFFF FLEXRAM_BANK_CFG FlexRAM bank config value 0 8 read-write GPR18 GPR18 General Purpose Register 0x48 32 read-write 0 0xFFFFFFFF LOCK_M7_APC_AC_R0_BOT lock M7_APC_AC_R0_BOT field for changes 0 1 read-write LOCK_M7_APC_AC_R0_BOT_0 Register field [31:1] is not locked 0 LOCK_M7_APC_AC_R0_BOT_1 Register field [31:1] is locked (read access only) 0x1 M7_APC_AC_R0_BOT APC end address of memory region-0 3 29 read-write GPR19 GPR19 General Purpose Register 0x4C 32 read-write 0 0xFFFFFFFF LOCK_M7_APC_AC_R0_TOP lock M7_APC_AC_R0_TOP field for changes 0 1 read-write LOCK_M7_APC_AC_R0_TOP_0 Register field [31:1] is not locked 0 LOCK_M7_APC_AC_R0_TOP_1 Register field [31:1] is locked (read access only) 0x1 M7_APC_AC_R0_TOP APC start address of memory region-0 3 29 read-write GPR20 GPR20 General Purpose Register 0x50 32 read-write 0 0xFFFFFFFF LOCK_M7_APC_AC_R1_BOT lock M7_APC_AC_R1_BOT field for changes 0 1 read-write LOCK_M7_APC_AC_R1_BOT_0 Register field [31:1] is not locked 0 LOCK_M7_APC_AC_R1_BOT_1 Register field [31:1] is locked (read access only) 0x1 M7_APC_AC_R1_BOT APC end address of memory region-1 3 29 read-write GPR21 GPR21 General Purpose Register 0x54 32 read-write 0 0xFFFFFFFF LOCK_M7_APC_AC_R1_TOP lock M7_APC_AC_R1_TOP field for changes 0 1 read-write LOCK_M7_APC_AC_R1_TOP_0 Register field [31:1] is not locked 0 LOCK_M7_APC_AC_R1_TOP_1 Register field [31:1] is locked (read access only) 0x1 M7_APC_AC_R1_TOP APC start address of memory region-1 3 29 read-write GPR22 GPR22 General Purpose Register 0x58 32 read-write 0 0xFFFFFFFF LOCK_M7_APC_AC_R2_BOT lock M7_APC_AC_R2_BOT field for changes 0 1 read-write LOCK_M7_APC_AC_R2_BOT_0 Register field [31:1] is not locked 0 LOCK_M7_APC_AC_R2_BOT_1 Register field [31:1] is locked (read access only) 0x1 M7_APC_AC_R2_BOT APC end address of memory region-2 3 29 read-write GPR23 GPR23 General Purpose Register 0x5C 32 read-write 0 0xFFFFFFFF LOCK_M7_APC_AC_R2_TOP lock M7_APC_AC_R2_TOP field for changes 0 1 read-write LOCK_M7_APC_AC_R2_TOP_0 Register field [31:1] is not locked 0 LOCK_M7_APC_AC_R2_TOP_1 Register field [31:1] is locked (read access only) 0x1 M7_APC_AC_R2_TOP APC start address of memory region-2 3 29 read-write GPR24 GPR24 General Purpose Register 0x60 32 read-write 0 0xFFFFFFFF LOCK_M7_APC_AC_R3_BOT lock M7_APC_AC_R3_BOT field for changes 0 1 read-write LOCK_M7_APC_AC_R3_BOT_0 Register field [31:1] is not locked 0 LOCK_M7_APC_AC_R3_BOT_1 Register field [31:1] is locked (read access only) 0x1 M7_APC_AC_R3_BOT APC end address of memory region-3 3 29 read-write GPR25 GPR25 General Purpose Register 0x64 32 read-write 0 0xFFFFFFFF LOCK_M7_APC_AC_R3_TOP lock M7_APC_AC_R3_TOP field for changes 0 1 read-write LOCK_M7_APC_AC_R3_TOP_0 Register field [31:1] is not locked 0 LOCK_M7_APC_AC_R3_TOP_1 Register field [31:1] is locked (read access only) 0x1 M7_APC_AC_R3_TOP APC start address of memory region-3 3 29 read-write GPR26 GPR26 General Purpose Register 0x68 32 read-write 0 0xFFFFFFFF GPIO_SEL Select GPIO1 or GPIO2 0 32 read-write GPR27 GPR27 General Purpose Register 0x6C 32 read-write 0 0xFFFFFFFF FLEXSPI_REMAP_ADDR_START Start address of flexspi1 12 20 read-write GPR28 GPR28 General Purpose Register 0x70 32 read-write 0 0xFFFFFFFF FLEXSPI_REMAP_ADDR_END End address of flexspi1 12 20 read-write GPR29 GPR29 General Purpose Register 0x74 32 read-write 0 0xFFFFFFFF FLEXSPI_REMAP_ADDR_OFFSET Offset address of flexspi1 12 20 read-write FLEXRAM FLEXRAM FLEXRAM 0x400B0000 0 0x1000 registers FLEXRAM 27 TCM_CTRL TCM CRTL Register 0 32 read-write 0 0xFFFFFFFF TCM_WWAIT_EN TCM Write Wait Mode Enable 0 1 read-write TCM_WWAIT_EN_0 TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. 0 TCM_WWAIT_EN_1 TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. 0x1 TCM_RWAIT_EN TCM Read Wait Mode Enable 1 1 read-write TCM_RWAIT_EN_0 TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. 0 TCM_RWAIT_EN_1 TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. 0x1 FORCE_CLK_ON Force RAM Clock Always On 2 1 read-write OCRAM_MAGIC_ADDR OCRAM Magic Address Register 0x4 32 read-write 0 0xFFFFFFFF OCRAM_WR_RD_SEL OCRAM Write Read Select 0 1 read-write OCRAM_WR_RD_SEL_0 When OCRAM read access hits magic address, it will generate interrupt. 0 OCRAM_WR_RD_SEL_1 When OCRAM write access hits magic address, it will generate interrupt. 0x1 OCRAM_MAGIC_ADDR OCRAM Magic Address 1 14 read-write DTCM_MAGIC_ADDR DTCM Magic Address Register 0x8 32 read-write 0 0xFFFFFFFF DTCM_WR_RD_SEL DTCM Write Read Select 0 1 read-write DTCM_WR_RD_SEL_0 When DTCM read access hits magic address, it will generate interrupt. 0 DTCM_WR_RD_SEL_1 When DTCM write access hits magic address, it will generate interrupt. 0x1 DTCM_MAGIC_ADDR DTCM Magic Address 1 14 read-write ITCM_MAGIC_ADDR ITCM Magic Address Register 0xC 32 read-write 0 0xFFFFFFFF ITCM_WR_RD_SEL ITCM Write Read Select 0 1 read-write ITCM_WR_RD_SEL_0 When ITCM read access hits magic address, it will generate interrupt. 0 ITCM_WR_RD_SEL_1 When ITCM write access hits magic address, it will generate interrupt. 0x1 ITCM_MAGIC_ADDR ITCM Magic Address 1 14 read-write INT_STATUS Interrupt Status Register 0x10 32 read-write 0 0xFFFFFFFF ITCM_MAM_STATUS ITCM Magic Address Match Status 0 1 read-write oneToClear ITCM_MAM_STATUS_0 ITCM did not access magic address. 0 ITCM_MAM_STATUS_1 ITCM accessed magic address. 0x1 DTCM_MAM_STATUS DTCM Magic Address Match Status 1 1 read-write oneToClear DTCM_MAM_STATUS_0 DTCM did not access magic address. 0 DTCM_MAM_STATUS_1 DTCM accessed magic address. 0x1 OCRAM_MAM_STATUS OCRAM Magic Address Match Status 2 1 read-write oneToClear OCRAM_MAM_STATUS_0 OCRAM did not access magic address. 0 OCRAM_MAM_STATUS_1 OCRAM accessed magic address. 0x1 ITCM_ERR_STATUS ITCM Access Error Status 3 1 read-write oneToClear ITCM_ERR_STATUS_0 ITCM access error does not happen 0 ITCM_ERR_STATUS_1 ITCM access error happens. 0x1 DTCM_ERR_STATUS DTCM Access Error Status 4 1 read-write oneToClear DTCM_ERR_STATUS_0 DTCM access error does not happen 0 DTCM_ERR_STATUS_1 DTCM access error happens. 0x1 OCRAM_ERR_STATUS OCRAM Access Error Status 5 1 read-write oneToClear OCRAM_ERR_STATUS_0 OCRAM access error does not happen 0 OCRAM_ERR_STATUS_1 OCRAM access error happens. 0x1 INT_STAT_EN Interrupt Status Enable Register 0x14 32 read-write 0 0xFFFFFFFF ITCM_MAM_STAT_EN ITCM Magic Address Match Status Enable 0 1 read-write ITCM_MAM_STAT_EN_0 Masked 0 ITCM_MAM_STAT_EN_1 Enabled 0x1 DTCM_MAM_STAT_EN DTCM Magic Address Match Status Enable 1 1 read-write DTCM_MAM_STAT_EN_0 Masked 0 DTCM_MAM_STAT_EN_1 Enabled 0x1 OCRAM_MAM_STAT_EN OCRAM Magic Address Match Status Enable 2 1 read-write OCRAM_MAM_STAT_EN_0 Masked 0 OCRAM_MAM_STAT_EN_1 Enabled 0x1 ITCM_ERR_STAT_EN ITCM Access Error Status Enable 3 1 read-write ITCM_ERR_STAT_EN_0 Masked 0 ITCM_ERR_STAT_EN_1 Enabled 0x1 DTCM_ERR_STAT_EN DTCM Access Error Status Enable 4 1 read-write DTCM_ERR_STAT_EN_0 Masked 0 DTCM_ERR_STAT_EN_1 Enabled 0x1 OCRAM_ERR_STAT_EN OCRAM Access Error Status Enable 5 1 read-write OCRAM_ERR_STAT_EN_0 Masked 0 OCRAM_ERR_STAT_EN_1 Enabled 0x1 INT_SIG_EN Interrupt Enable Register 0x18 32 read-write 0 0xFFFFFFFF ITCM_MAM_SIG_EN ITCM Magic Address Match Interrupt Enable 0 1 read-write ITCM_MAM_SIG_EN_0 Masked 0 ITCM_MAM_SIG_EN_1 Enabled 0x1 DTCM_MAM_SIG_EN DTCM Magic Address Match Interrupt Enable 1 1 read-write DTCM_MAM_SIG_EN_0 Masked 0 DTCM_MAM_SIG_EN_1 Enabled 0x1 OCRAM_MAM_SIG_EN OCRAM Magic Address Match Interrupt Enable 2 1 read-write OCRAM_MAM_SIG_EN_0 Masked 0 OCRAM_MAM_SIG_EN_1 Enabled 0x1 ITCM_ERR_SIG_EN ITCM Access Error Interrupt Enable 3 1 read-write ITCM_ERR_SIG_EN_0 Masked 0 ITCM_ERR_SIG_EN_1 Enabled 0x1 DTCM_ERR_SIG_EN DTCM Access Error Interrupt Enable 4 1 read-write DTCM_ERR_SIG_EN_0 Masked 0 DTCM_ERR_SIG_EN_1 Enabled 0x1 OCRAM_ERR_SIG_EN OCRAM Access Error Interrupt Enable 5 1 read-write OCRAM_ERR_SIG_EN_0 Masked 0 OCRAM_ERR_SIG_EN_1 Enabled 0x1 EWM EWM EWM 0x400B4000 0 0x6 registers EWM 44 CTRL Control Register 0 8 read-write 0 0xFF EWMEN EWM enable. 0 1 read-writeOnce ASSIN EWM_in's Assertion State Select. 1 1 read-writeOnce INEN Input Enable. 2 1 read-writeOnce INTEN Interrupt Enable. 3 1 read-write SERV Service Register 0x1 8 read-write 0 0xFF SERVICE SERVICE 0 8 read-write CMPL Compare Low Register 0x2 8 read-writeOnce 0 0xFF COMPAREL COMPAREL 0 8 read-writeOnce CMPH Compare High Register 0x3 8 read-writeOnce 0xFF 0xFF COMPAREH COMPAREH 0 8 read-writeOnce CLKCTRL Clock Control Register 0x4 8 read-write 0 0xFF CLKSEL CLKSEL 0 2 read-writeOnce CLKPRESCALER Clock Prescaler Register 0x5 8 read-writeOnce 0 0xFF CLK_DIV CLK_DIV 0 8 read-writeOnce WDOG1 WDOG WDOG WDOG 0x400B8000 0 0xA registers WDOG1 74 WCR Watchdog Control Register 0 16 read-write 0x30 0xFFFF WDZST WDZST 0 1 read-write WDZST_0 Continue timer operation (Default). 0 WDZST_1 Suspend the watchdog timer. 0x1 WDBG WDBG 1 1 read-write WDBG_0 Continue WDOG timer operation (Default). 0 WDBG_1 Suspend the watchdog timer. 0x1 WDE WDE 2 1 read-write WDE_0 Disable the Watchdog (Default). 0 WDE_1 Enable the Watchdog. 0x1 WDT WDT 3 1 read-write WDT_0 No effect on WDOG_B (Default). 0 WDT_1 Assert WDOG_B upon a Watchdog Time-out event. 0x1 SRS SRS 4 1 read-write SRS_0 Assert system reset signal. 0 SRS_1 No effect on the system (Default). 0x1 WDA WDA 5 1 read-write WDA_0 Assert WDOG_B output. 0 WDA_1 No effect on system (Default). 0x1 SRE software reset extension, an option way to generate software reset 6 1 read-write SRE_0 using original way to generate software reset (default) 0 SRE_1 using new way to generate software reset. 0x1 WDW WDW 7 1 read-write WDW_0 Continue WDOG timer operation (Default). 0 WDW_1 Suspend WDOG timer operation. 0x1 WT WT 8 8 read-write WT_0 - 0.5 Seconds (Default). 0 WT_1 - 1.0 Seconds. 0x1 WT_2 - 1.5 Seconds. 0x2 WT_3 - 2.0 Seconds. 0x3 WT_255 - 128 Seconds. 0xFF WSR Watchdog Service Register 0x2 16 read-write 0 0xFFFF WSR WSR 0 16 read-write WSR_21845 Write to the Watchdog Service Register (WDOG_WSR). 0x5555 WSR_43690 Write to the Watchdog Service Register (WDOG_WSR). 0xAAAA WRSR Watchdog Reset Status Register 0x4 16 read-only 0x10 0xFFFF SFTW SFTW 0 1 read-only SFTW_0 Reset is not the result of a software reset. 0 SFTW_1 Reset is the result of a software reset. 0x1 TOUT TOUT 1 1 read-only TOUT_0 Reset is not the result of a WDOG timeout. 0 TOUT_1 Reset is the result of a WDOG timeout. 0x1 POR POR 4 1 read-only POR_0 Reset is not the result of a power on reset. 0 POR_1 Reset is the result of a power on reset. 0x1 WICR Watchdog Interrupt Control Register 0x6 16 read-write 0x4 0xFFFF WICT WICT 0 8 read-write WICT_0 WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. 0 WICT_1 WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. 0x1 WICT_4 WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). 0x4 WICT_255 WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. 0xFF WTIS WTIS 14 1 read-write oneToClear WTIS_0 No interrupt has occurred (Default). 0 WTIS_1 Interrupt has occurred 0x1 WIE WIE 15 1 read-write WIE_0 Disable Interrupt (Default). 0 WIE_1 Enable Interrupt. 0x1 WMCR Watchdog Miscellaneous Control Register 0x8 16 read-write 0x1 0xFFFF PDE PDE 0 1 read-write PDE_0 Power Down Counter of WDOG is disabled. 0 PDE_1 Power Down Counter of WDOG is enabled (Default). 0x1 WDOG2 WDOG WDOG 0x400D0000 0 0xA registers WDOG2 45 RTWDOG WDOG RTWDOG 0x400BC000 0 0x10 registers RTWDOG 57 CS Watchdog Control and Status Register 0 32 read-write 0x2980 0xFFFFFFFF STOP Stop Enable 0 1 read-write STOP_0 Watchdog disabled in chip stop mode. 0 STOP_1 Watchdog enabled in chip stop mode. 0x1 WAIT Wait Enable 1 1 read-write WAIT_0 Watchdog disabled in chip wait mode. 0 WAIT_1 Watchdog enabled in chip wait mode. 0x1 DBG Debug Enable 2 1 read-write DBG_0 Watchdog disabled in chip debug mode. 0 DBG_1 Watchdog enabled in chip debug mode. 0x1 TST Watchdog Test 3 2 read-write TST_0 Watchdog test mode disabled. 0 TST_1 Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. 0x1 TST_2 Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. 0x2 TST_3 Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. 0x3 UPDATE Allow updates 5 1 read-write UPDATE_0 Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. 0 UPDATE_1 Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. 0x1 INT Watchdog Interrupt 6 1 read-write INT_0 Watchdog interrupts are disabled. Watchdog resets are not delayed. 0 INT_1 Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. 0x1 EN Watchdog Enable 7 1 read-write EN_0 Watchdog disabled. 0 EN_1 Watchdog enabled. 0x1 CLK Watchdog Clock 8 2 read-write CLK_0 Bus clock 0 CLK_1 LPO clock 0x1 CLK_2 INTCLK (internal clock) 0x2 CLK_3 ERCLK (external reference clock) 0x3 RCS Reconfiguration Success 10 1 read-only RCS_0 Reconfiguring WDOG. 0 RCS_1 Reconfiguration is successful. 0x1 ULK Unlock status 11 1 read-only ULK_0 WDOG is locked. 0 ULK_1 WDOG is unlocked. 0x1 PRES Watchdog prescaler 12 1 read-write PRES_0 256 prescaler disabled. 0 PRES_1 256 prescaler enabled. 0x1 CMD32EN Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words 13 1 read-write CMD32EN_0 Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. 0 CMD32EN_1 Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. 0x1 FLG Watchdog Interrupt Flag 14 1 read-write oneToClear FLG_0 No interrupt occurred. 0 FLG_1 An interrupt occurred. 0x1 WIN Watchdog Window 15 1 read-write WIN_0 Window mode disabled. 0 WIN_1 Window mode enabled. 0x1 CNT Watchdog Counter Register 0x4 32 read-write 0 0xFFFFFFFF CNTLOW Low byte of the Watchdog Counter 0 8 read-write CNTHIGH High byte of the Watchdog Counter 8 8 read-write TOVAL Watchdog Timeout Value Register 0x8 32 read-write 0x400 0xFFFFFFFF TOVALLOW Low byte of the timeout value 0 8 read-write TOVALHIGH High byte of the timeout value 8 8 read-write WIN Watchdog Window Register 0xC 32 read-write 0 0xFFFFFFFF WINLOW Low byte of Watchdog Window 0 8 read-write WINHIGH High byte of Watchdog Window 8 8 read-write ADC1 Analog-to-Digital Converter ADC ADC1_ 0x400C4000 0 0x5C registers ADC1 67 HC0 Control register for hardware triggers 0 32 read-write 0x1F 0xFFFFFFFF ADCH Input Channel Select 0 5 read-write ADCH_16 External channel selection from ADC_ETC 0x10 ADCH_25 VREFSH = internal channel, for ADC self-test, hard connected to VRH internally 0x19 ADCH_31 Conversion Disabled. Hardware Triggers will not initiate any conversion. 0x1F AIEN Conversion Complete Interrupt Enable/Disable Control 7 1 read-write AIEN_0 Conversion complete interrupt disabled 0 AIEN_1 Conversion complete interrupt enabled 0x1 7 0x4 1,2,3,4,5,6,7 HC%s Control register for hardware triggers 0x4 32 read-write 0x1F 0xFFFFFFFF ADCH Input Channel Select 0 5 read-write ADCH_16 External channel selection from ADC_ETC 0x10 ADCH_25 VREFSH = internal channel, for ADC self-test, hard connected to VRH internally 0x19 ADCH_31 Conversion Disabled. Hardware Triggers will not initiate any conversion. 0x1F AIEN Conversion Complete Interrupt Enable/Disable Control 7 1 read-write AIEN_0 Conversion complete interrupt disabled 0 AIEN_1 Conversion complete interrupt enabled 0x1 HS Status register for HW triggers 0x20 32 read-only 0 0xFFFFFFFF COCO0 Conversion Complete Flag 0 1 read-only R0 Data result register for HW triggers 0x24 32 read-only 0 0xFFFFFFFF CDATA Data (result of an ADC conversion) 0 12 read-only 7 0x4 1,2,3,4,5,6,7 R%s Data result register for HW triggers 0x28 32 read-only 0 0xFFFFFFFF CDATA Data (result of an ADC conversion) 0 12 read-only CFG Configuration register 0x44 32 read-write 0x200 0xFFFFFFFF ADICLK Input Clock Select 0 2 read-write ADICLK_0 IPG clock 0 ADICLK_1 IPG clock divided by 2 0x1 ADICLK_2 Alternate clock (ALTCLK) 0x2 ADICLK_3 Asynchronous clock (ADACK) 0x3 MODE Conversion Mode Selection 2 2 read-write MODE_0 8-bit conversion 0 MODE_1 10-bit conversion 0x1 MODE_2 12-bit conversion 0x2 ADLSMP Long Sample Time Configuration 4 1 read-write ADLSMP_0 Short sample mode. 0 ADLSMP_1 Long sample mode. 0x1 ADIV Clock Divide Select 5 2 read-write ADIV_0 Input clock 0 ADIV_1 Input clock / 2 0x1 ADIV_2 Input clock / 4 0x2 ADIV_3 Input clock / 8 0x3 ADLPC Low-Power Configuration 7 1 read-write ADLPC_0 ADC hard block not in low power mode. 0 ADLPC_1 ADC hard block in low power mode. 0x1 ADSTS Defines the sample time duration 8 2 read-write ADSTS_0 Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b 0 ADSTS_1 Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b 0x1 ADSTS_2 Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b 0x2 ADSTS_3 Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b 0x3 ADHSC High Speed Configuration 10 1 read-write ADHSC_0 Normal conversion selected. 0 ADHSC_1 High speed conversion selected. 0x1 REFSEL Voltage Reference Selection 11 2 read-write REFSEL_0 Selects VREFH/VREFL as reference voltage. 0 ADTRG Conversion Trigger Select 13 1 read-write ADTRG_0 Software trigger selected 0 ADTRG_1 Hardware trigger selected 0x1 AVGS Hardware Average select 14 2 read-write AVGS_0 4 samples averaged 0 AVGS_1 8 samples averaged 0x1 AVGS_2 16 samples averaged 0x2 AVGS_3 32 samples averaged 0x3 OVWREN Data Overwrite Enable 16 1 read-write OVWREN_0 Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. 0 OVWREN_1 Enable the overwriting. 0x1 GC General control register 0x48 32 read-write 0 0xFFFFFFFF ADACKEN Asynchronous clock output enable 0 1 read-write ADACKEN_0 Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. 0 ADACKEN_1 Asynchronous clock and clock output enabled regardless of the state of the ADC 0x1 DMAEN DMA Enable 1 1 read-write DMAEN_0 DMA disabled (default) 0 DMAEN_1 DMA enabled 0x1 ACREN Compare Function Range Enable 2 1 read-write ACREN_0 Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. 0 ACREN_1 Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. 0x1 ACFGT Compare Function Greater Than Enable 3 1 read-write ACFGT_0 Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. 0 ACFGT_1 Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers. 0x1 ACFE Compare Function Enable 4 1 read-write ACFE_0 Compare function disabled 0 ACFE_1 Compare function enabled 0x1 AVGE Hardware average enable 5 1 read-write AVGE_0 Hardware average function disabled 0 AVGE_1 Hardware average function enabled 0x1 ADCO Continuous Conversion Enable 6 1 read-write ADCO_0 One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. 0 ADCO_1 Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. 0x1 CAL Calibration 7 1 read-write GS General status register 0x4C 32 read-write 0 0xFFFFFFFF ADACT Conversion Active 0 1 read-only ADACT_0 Conversion not in progress. 0 ADACT_1 Conversion in progress. 0x1 CALF Calibration Failed Flag 1 1 read-write oneToClear CALF_0 Calibration completed normally. 0 CALF_1 Calibration failed. ADC accuracy specifications are not guaranteed. 0x1 AWKST Asynchronous wakeup interrupt status 2 1 read-write oneToClear AWKST_0 No asynchronous interrupt. 0 AWKST_1 Asynchronous wake up interrupt occurred in stop mode. 0x1 CV Compare value register 0x50 32 read-write 0 0xFFFFFFFF CV1 Compare Value 1 0 12 read-write CV2 Compare Value 2 16 12 read-write OFS Offset correction value register 0x54 32 read-write 0 0xFFFFFFFF OFS Offset value 0 12 read-write SIGN Sign bit 12 1 read-write SIGN_0 The offset value is added with the raw result 0 SIGN_1 The offset value is subtracted from the raw converted value 0x1 CAL Calibration value register 0x58 32 read-write 0 0xFFFFFFFF CAL_CODE Calibration Result Value 0 4 read-write TRNG TRNG TRNG 0x400CC000 0 0xFF registers TRNG 53 MCTL Miscellaneous Control Register 0 32 read-write 0x12001 0xFFFFFFFF SAMP_MODE Sample Mode 0 2 read-write SAMP_MODE_0 use Von Neumann data into both Entropy shifter and Statistical Checker 0 SAMP_MODE_1 use raw data into both Entropy shifter and Statistical Checker 0x1 SAMP_MODE_2 use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker 0x2 SAMP_MODE_3 undefined/reserved. 0x3 OSC_DIV Oscillator Divide 2 2 read-write OSC_DIV_0 use ring oscillator with no divide 0 OSC_DIV_1 use ring oscillator divided-by-2 0x1 OSC_DIV_2 use ring oscillator divided-by-4 0x2 OSC_DIV_3 use ring oscillator divided-by-8 0x3 UNUSED4 This bit is unused. Always reads zero. 4 1 read-only UNUSED5 This bit is unused. Always reads zero. 5 1 read-only RST_DEF Reset Defaults 6 1 write-only FOR_SCLK Force System Clock 7 1 read-write FCT_FAIL Read only: Frequency Count Fail 8 1 read-only FCT_VAL Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. 9 1 read-only ENT_VAL Read only: Entropy Valid 10 1 read-only TST_OUT Read only: Test point inside ring oscillator. 11 1 read-only ERR Read: Error status 12 1 read-write oneToClear TSTOP_OK TRNG_OK_TO_STOP 13 1 read-only LRUN_CONT Long run count continues between entropy generations 14 1 read-write PRGM Programming Mode Select 16 1 read-write SCMISC Statistical Check Miscellaneous Register 0x4 32 read-write 0x10022 0xFFFFFFFF LRUN_MAX LONG RUN MAX LIMIT 0 8 read-write RTY_CT RETRY COUNT 16 4 read-write PKRRNG Poker Range Register 0x8 32 read-write 0x9A3 0xFFFFFFFF PKR_RNG Poker Range 0 16 read-write PKRMAX Poker Maximum Limit Register MAX_SQ 0xC 32 read-write 0x6920 0xFFFFFFFF PKR_MAX Poker Maximum Limit. 0 24 read-write PKRSQ Poker Square Calculation Result Register MAX_SQ 0xC 32 read-only 0 0xFFFFFFFF PKR_SQ Poker Square Calculation Result. 0 24 read-only SDCTL Seed Control Register 0x10 32 read-write 0xC8009C4 0xFFFFFFFF SAMP_SIZE Sample Size 0 16 read-write ENT_DLY Entropy Delay 16 16 read-write SBLIM Sparse Bit Limit Register SBLIM_TOTSAM 0x14 32 read-write 0x3F 0xFFFFFFFF SB_LIM Sparse Bit Limit 0 10 read-write TOTSAM Total Samples Register SBLIM_TOTSAM 0x14 32 read-only 0 0xFFFFFFFF TOT_SAM Total Samples 0 20 read-only FRQMIN Frequency Count Minimum Limit Register 0x18 32 read-write 0x640 0xFFFFFFFF FRQ_MIN Frequency Count Minimum Limit 0 22 read-write FRQCNT Frequency Count Register MAX_CNT 0x1C 32 read-only 0 0xFFFFFFFF FRQ_CT Frequency Count 0 22 read-only FRQMAX Frequency Count Maximum Limit Register MAX_CNT 0x1C 32 read-write 0x6400 0xFFFFFFFF FRQ_MAX Frequency Counter Maximum Limit 0 22 read-write SCMC Statistical Check Monobit Count Register SCML_MC 0x20 32 read-only 0 0xFFFFFFFF MONO_CT Monobit Count 0 16 read-only SCML Statistical Check Monobit Limit Register SCML_MC 0x20 32 read-write 0x10C0568 0xFFFFFFFF MONO_MAX Monobit Maximum Limit 0 16 read-write MONO_RNG Monobit Range 16 16 read-write SCR1C Statistical Check Run Length 1 Count Register SCR1L_1C 0x24 32 read-only 0 0xFFFFFFFF R1_0_CT Runs of Zero, Length 1 Count 0 15 read-only R1_1_CT Runs of One, Length 1 Count 16 15 read-only SCR1L Statistical Check Run Length 1 Limit Register SCR1L_1C 0x24 32 read-write 0xB20195 0xFFFFFFFF RUN1_MAX Run Length 1 Maximum Limit 0 15 read-write RUN1_RNG Run Length 1 Range 16 15 read-write SCR2C Statistical Check Run Length 2 Count Register SCR2L_2C 0x28 32 read-only 0 0xFFFFFFFF R2_0_CT Runs of Zero, Length 2 Count 0 14 read-only R2_1_CT Runs of One, Length 2 Count 16 14 read-only SCR2L Statistical Check Run Length 2 Limit Register SCR2L_2C 0x28 32 read-write 0x7A00DC 0xFFFFFFFF RUN2_MAX Run Length 2 Maximum Limit 0 14 read-write RUN2_RNG Run Length 2 Range 16 14 read-write SCR3C Statistical Check Run Length 3 Count Register SCR3L_3C 0x2C 32 read-only 0 0xFFFFFFFF R3_0_CT Runs of Zeroes, Length 3 Count 0 13 read-only R3_1_CT Runs of Ones, Length 3 Count 16 13 read-only SCR3L Statistical Check Run Length 3 Limit Register SCR3L_3C 0x2C 32 read-write 0x58007D 0xFFFFFFFF RUN3_MAX Run Length 3 Maximum Limit 0 13 read-write RUN3_RNG Run Length 3 Range 16 13 read-write SCR4C Statistical Check Run Length 4 Count Register SCR4L_4C 0x30 32 read-only 0 0xFFFFFFFF R4_0_CT Runs of Zero, Length 4 Count 0 12 read-only R4_1_CT Runs of One, Length 4 Count 16 12 read-only SCR4L Statistical Check Run Length 4 Limit Register SCR4L_4C 0x30 32 read-write 0x40004B 0xFFFFFFFF RUN4_MAX Run Length 4 Maximum Limit 0 12 read-write RUN4_RNG Run Length 4 Range 16 12 read-write SCR5C Statistical Check Run Length 5 Count Register SCR5L_5C 0x34 32 read-only 0 0xFFFFFFFF R5_0_CT Runs of Zero, Length 5 Count 0 11 read-only R5_1_CT Runs of One, Length 5 Count 16 11 read-only SCR5L Statistical Check Run Length 5 Limit Register SCR5L_5C 0x34 32 read-write 0x2E002F 0xFFFFFFFF RUN5_MAX Run Length 5 Maximum Limit 0 11 read-write RUN5_RNG Run Length 5 Range 16 11 read-write SCR6PC Statistical Check Run Length 6+ Count Register SCR6PL_PC 0x38 32 read-only 0 0xFFFFFFFF R6P_0_CT Runs of Zero, Length 6+ Count 0 11 read-only R6P_1_CT Runs of One, Length 6+ Count 16 11 read-only SCR6PL Statistical Check Run Length 6+ Limit Register SCR6PL_PC 0x38 32 read-write 0x2E002F 0xFFFFFFFF RUN6P_MAX Run Length 6+ Maximum Limit 0 11 read-write RUN6P_RNG Run Length 6+ Range 16 11 read-write STATUS Status Register 0x3C 32 read-only 0 0xFFFFFFFF TF1BR0 Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. 0 1 read-only TF1BR1 Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. 1 1 read-only TF2BR0 Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. 2 1 read-only TF2BR1 Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. 3 1 read-only TF3BR0 Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. 4 1 read-only TF3BR1 Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. 5 1 read-only TF4BR0 Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. 6 1 read-only TF4BR1 Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. 7 1 read-only TF5BR0 Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. 8 1 read-only TF5BR1 Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. 9 1 read-only TF6PBR0 Test Fail, 6 Plus Bit Run, Sampling 0s 10 1 read-only TF6PBR1 Test Fail, 6 Plus Bit Run, Sampling 1s 11 1 read-only TFSB Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. 12 1 read-only TFLR Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. 13 1 read-only TFP Test Fail, Poker. If TFP=1, the Poker Test has failed. 14 1 read-only TFMB Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. 15 1 read-only RETRY_CT RETRY COUNT 16 4 read-only 16 0x4 ENT[%s] Entropy Read Register 0x40 32 read-only 0 0xFFFFFFFF ENT Entropy Value 0 32 read-only PKRCNT10 Statistical Check Poker Count 1 and 0 Register 0x80 32 read-only 0 0xFFFFFFFF PKR_0_CT Poker 0h Count 0 16 read-only PKR_1_CT Poker 1h Count 16 16 read-only PKRCNT32 Statistical Check Poker Count 3 and 2 Register 0x84 32 read-only 0 0xFFFFFFFF PKR_2_CT Poker 2h Count 0 16 read-only PKR_3_CT Poker 3h Count 16 16 read-only PKRCNT54 Statistical Check Poker Count 5 and 4 Register 0x88 32 read-only 0 0xFFFFFFFF PKR_4_CT Poker 4h Count 0 16 read-only PKR_5_CT Poker 5h Count 16 16 read-only PKRCNT76 Statistical Check Poker Count 7 and 6 Register 0x8C 32 read-only 0 0xFFFFFFFF PKR_6_CT Poker 6h Count 0 16 read-only PKR_7_CT Poker 7h Count 16 16 read-only PKRCNT98 Statistical Check Poker Count 9 and 8 Register 0x90 32 read-only 0 0xFFFFFFFF PKR_8_CT Poker 8h Count 0 16 read-only PKR_9_CT Poker 9h Count 16 16 read-only PKRCNTBA Statistical Check Poker Count B and A Register 0x94 32 read-only 0 0xFFFFFFFF PKR_A_CT Poker Ah Count 0 16 read-only PKR_B_CT Poker Bh Count 16 16 read-only PKRCNTDC Statistical Check Poker Count D and C Register 0x98 32 read-only 0 0xFFFFFFFF PKR_C_CT Poker Ch Count 0 16 read-only PKR_D_CT Poker Dh Count 16 16 read-only PKRCNTFE Statistical Check Poker Count F and E Register 0x9C 32 read-only 0 0xFFFFFFFF PKR_E_CT Poker Eh Count 0 16 read-only PKR_F_CT Poker Fh Count 16 16 read-only SEC_CFG Security Configuration Register 0xA0 32 read-write 0 0xFFFFFFFF UNUSED0 This bit is unused. Ignore. 0 1 read-write NO_PRGM If set, the TRNG registers cannot be programmed 1 1 read-write NO_PRGM_0 Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. 0 NO_PRGM_1 Overides Miscellaneous Control Register access mode and prevents TRNG register programming. 0x1 UNUSED2 This bit is unused. Ignore. 2 1 read-write INT_CTRL Interrupt Control Register 0xA4 32 read-write 0x7 0xFFFFFFFF HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS register has been asserted. 0 1 read-write HW_ERR_0 Corresponding bit of INT_STATUS register cleared. 0 HW_ERR_1 Corresponding bit of INT_STATUS register active. 0x1 ENT_VAL Same behavior as bit 0 of this register. 1 1 read-write ENT_VAL_0 Same behavior as bit 0 of this register. 0 ENT_VAL_1 Same behavior as bit 0 of this register. 0x1 FRQ_CT_FAIL Same behavior as bit 0 of this register. 2 1 read-write FRQ_CT_FAIL_0 Same behavior as bit 0 of this register. 0 FRQ_CT_FAIL_1 Same behavior as bit 0 of this register. 0x1 INT_MASK Mask Register 0xA8 32 read-write 0 0xFFFFFFFF HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write HW_ERR_0 Corresponding interrupt of INT_STATUS is masked. 0 HW_ERR_1 Corresponding bit of INT_STATUS is active. 0x1 ENT_VAL Same behavior as bit 0 of this register. 1 1 read-write ENT_VAL_0 Same behavior as bit 0 of this register. 0 ENT_VAL_1 Same behavior as bit 0 of this register. 0x1 FRQ_CT_FAIL Same behavior as bit 0 of this register. 2 1 read-write FRQ_CT_FAIL_0 Same behavior as bit 0 of this register. 0 FRQ_CT_FAIL_1 Same behavior as bit 0 of this register. 0x1 INT_STATUS Interrupt Status Register 0xAC 32 read-only 0 0xFFFFFFFF HW_ERR Read: Error status 0 1 read-only HW_ERR_0 no error 0 HW_ERR_1 error detected. 0x1 ENT_VAL Read only: Entropy Valid 1 1 read-only ENT_VAL_0 Busy generation entropy. Any value read is invalid. 0 ENT_VAL_1 TRNG can be stopped and entropy is valid if read. 0x1 FRQ_CT_FAIL Read only: Frequency Count Fail 2 1 read-only FRQ_CT_FAIL_0 No hardware nor self test frequency errors. 0 FRQ_CT_FAIL_1 The frequency counter has detected a failure. 0x1 VID1 Version ID Register (MS) 0xF0 32 read-only 0x300301 0xFFFFFFFF MIN_REV Shows the IP's Minor revision of the TRNG. 0 8 read-only MIN_REV_0 Minor revision number for TRNG. 0 MAJ_REV Shows the IP's Major revision of the TRNG. 8 8 read-only MAJ_REV_1 Major revision number for TRNG. 0x1 IP_ID Shows the IP ID. 16 16 read-only IP_ID_48 ID for TRNG. 0x30 VID2 Version ID Register (LS) 0xF4 32 read-only 0 0xFFFFFFFF CONFIG_OPT Shows the IP's Configuaration options for the TRNG. 0 8 read-only CONFIG_OPT_0 TRNG_CONFIG_OPT for TRNG. 0 ECO_REV Shows the IP's ECO revision of the TRNG. 8 8 read-only ECO_REV_0 TRNG_ECO_REV for TRNG. 0 INTG_OPT Shows the integration options for the TRNG. 16 8 read-only INTG_OPT_0 INTG_OPT for TRNG. 0 ERA Shows the compile options for the TRNG. 24 8 read-only ERA_0 COMPILE_OPT for TRNG. 0 SNVS SNVS SNVS 0x400D4000 0 0x10000 registers SNVS_HP_WRAPPER 46 SNVS_HP_WRAPPER_TZ 47 SNVS_LP_WRAPPER 48 HPLR SNVS_HP Lock Register 0 32 read-write 0 0xFFFFFFFF ZMK_WSL Zeroizable Master Key Write Soft Lock When set, prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR 0 1 read-write ZMK_WSL_0 Write access is allowed 0 ZMK_WSL_1 Write access is not allowed 0x1 ZMK_RSL Zeroizable Master Key Read Soft Lock When set, prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR 1 1 read-write ZMK_RSL_0 Read access is allowed (only in software Programming mode) 0 ZMK_RSL_1 Read access is not allowed 0x1 SRTC_SL Secure Real Time Counter Soft Lock When set, prevents any writes to the SRTC Registers, SRTC_ENV, and SRTC_INV_EN bits 2 1 read-write SRTC_SL_0 Write access is allowed 0 SRTC_SL_1 Write access is not allowed 0x1 LPCALB_SL LP Calibration Soft Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) 3 1 read-write LPCALB_SL_0 Write access is allowed 0 LPCALB_SL_1 Write access is not allowed 0x1 MC_SL Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit 4 1 read-write MC_SL_0 Write access (increment) is allowed 0 MC_SL_1 Write access (increment) is not allowed 0x1 GPR_SL General Purpose Register Soft Lock When set, prevents any writes to the GPR 5 1 read-write GPR_SL_0 Write access is allowed 0 GPR_SL_1 Write access is not allowed 0x1 LPSVCR_SL LP Security Violation Control Register Soft Lock When set, prevents any writes to the LPSVCR 6 1 read-write LPSVCR_SL_0 Write access is allowed 0 LPSVCR_SL_1 Write access is not allowed 0x1 LPTDCR_SL LP Tamper Detectors Configuration Register Soft Lock When set, prevents any writes to the LPTDCR 8 1 read-write LPTDCR_SL_0 Write access is allowed 0 LPTDCR_SL_1 Write access is not allowed 0x1 MKS_SL Master Key Select Soft Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LPMKCR 9 1 read-write MKS_SL_0 Write access is allowed 0 MKS_SL_1 Write access is not allowed 0x1 HPSVCR_L HP Security Violation Control Register Lock When set, prevents any writes to the HPSVCR 16 1 read-write HPSVCR_L_0 Write access is allowed 0 HPSVCR_L_1 Write access is not allowed 0x1 HPSICR_L HP Security Interrupt Control Register Lock When set, prevents any writes to the HPSICR 17 1 read-write HPSICR_L_0 Write access is allowed 0 HPSICR_L_1 Write access is not allowed 0x1 HAC_L High Assurance Counter Lock When set, prevents any writes to HPHACIVR, HPHACR, and HAC_EN bit of HPCOMR 18 1 read-write HAC_L_0 Write access is allowed 0 HAC_L_1 Write access is not allowed 0x1 HPCOMR SNVS_HP Command Register 0x4 32 read-write 0 0xFFFFFFFF SSM_ST SSM State Transition Transition state of the system security monitor 0 1 write-only SSM_ST_DIS SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state 1 1 read-write SSM_ST_DIS_0 Secure to Trusted State transition is enabled 0 SSM_ST_DIS_1 Secure to Trusted State transition is disabled 0x1 SSM_SFNS_DIS SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state 2 1 read-write SSM_SFNS_DIS_0 Soft Fail to Non-Secure State transition is enabled 0 SSM_SFNS_DIS_1 Soft Fail to Non-Secure State transition is disabled 0x1 LP_SWR LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set 4 1 write-only LP_SWR_0 No Action 0 LP_SWR_1 Reset LP section 0x1 LP_SWR_DIS LP Software Reset Disable When set, disables the LP software reset 5 1 read-write LP_SWR_DIS_0 LP software reset is enabled 0 LP_SWR_DIS_1 LP software reset is disabled 0x1 SW_SV Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation 8 1 read-write SW_FSV Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation 9 1 read-write SW_LPSV LP Software Security Violation When set, SNVS_LP treats this bit as a security violation 10 1 read-write PROG_ZMK Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism 12 1 write-only PROG_ZMK_0 No Action 0 PROG_ZMK_1 Activate hardware key programming mechanism 0x1 MKS_EN Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default 13 1 read-write MKS_EN_0 OTP master key is selected as an SNVS master key 0 MKS_EN_1 SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR 0x1 HAC_EN High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state 16 1 read-write HAC_EN_0 High Assurance Counter is disabled 0 HAC_EN_1 High Assurance Counter is enabled 0x1 HAC_LOAD High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register 17 1 write-only HAC_LOAD_0 No Action 0 HAC_LOAD_1 Load the HAC 0x1 HAC_CLEAR High Assurance Counter Clear When set, it clears the High Assurance Counter Register 18 1 write-only HAC_CLEAR_0 No Action 0 HAC_CLEAR_1 Clear the HAC 0x1 HAC_STOP High Assurance Counter Stop This bit can be set only when SSM is in soft fail state 19 1 read-write NPSWA_EN Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only 31 1 read-write HPCR SNVS_HP Control Register 0x8 32 read-write 0 0xFFFFFFFF RTC_EN HP Real Time Counter Enable 0 1 read-write RTC_EN_0 RTC is disabled 0 RTC_EN_1 RTC is enabled 0x1 HPTA_EN HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter 1 1 read-write HPTA_EN_0 HP Time Alarm Interrupt is disabled 0 HPTA_EN_1 HP Time Alarm Interrupt is enabled 0x1 DIS_PI Disable periodic interrupt in the functional interrupt 2 1 read-write DIS_PI_0 Periodic interrupt will trigger a functional interrupt 0 DIS_PI_1 Disable periodic interrupt in the function interrupt 0x1 PI_EN HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled 3 1 read-write PI_EN_0 HP Periodic Interrupt is disabled 0 PI_EN_1 HP Periodic Interrupt is enabled 0x1 PI_FREQ Periodic Interrupt Frequency Defines frequency of the periodic interrupt 4 4 read-write PI_FREQ_0 - bit 0 of the HPRTCLR is selected as a source of the periodic interrupt 0 PI_FREQ_1 - bit 1 of the HPRTCLR is selected as a source of the periodic interrupt 0x1 PI_FREQ_2 - bit 2 of the HPRTCLR is selected as a source of the periodic interrupt 0x2 PI_FREQ_3 - bit 3 of the HPRTCLR is selected as a source of the periodic interrupt 0x3 PI_FREQ_4 - bit 4 of the HPRTCLR is selected as a source of the periodic interrupt 0x4 PI_FREQ_5 - bit 5 of the HPRTCLR is selected as a source of the periodic interrupt 0x5 PI_FREQ_6 - bit 6 of the HPRTCLR is selected as a source of the periodic interrupt 0x6 PI_FREQ_7 - bit 7 of the HPRTCLR is selected as a source of the periodic interrupt 0x7 PI_FREQ_8 - bit 8 of the HPRTCLR is selected as a source of the periodic interrupt 0x8 PI_FREQ_9 - bit 9 of the HPRTCLR is selected as a source of the periodic interrupt 0x9 PI_FREQ_10 - bit 10 of the HPRTCLR is selected as a source of the periodic interrupt 0xA PI_FREQ_11 - bit 11 of the HPRTCLR is selected as a source of the periodic interrupt 0xB PI_FREQ_12 - bit 12 of the HPRTCLR is selected as a source of the periodic interrupt 0xC PI_FREQ_13 - bit 13 of the HPRTCLR is selected as a source of the periodic interrupt 0xD PI_FREQ_14 - bit 14 of the HPRTCLR is selected as a source of the periodic interrupt 0xE PI_FREQ_15 - bit 15 of the HPRTCLR is selected as a source of the periodic interrupt 0xF HPCALB_EN HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled. 8 1 read-write HPCALB_EN_0 HP Timer calibration disabled 0 HPCALB_EN_1 HP Timer calibration enabled 0x1 HPCALB_VAL HP Calibration Value Defines signed calibration value for the HP Real Time Counter 10 5 read-write HPCALB_VAL_0 +0 counts per each 32768 ticks of the counter 0 HPCALB_VAL_1 +1 counts per each 32768 ticks of the counter 0x1 HPCALB_VAL_2 +2 counts per each 32768 ticks of the counter 0x2 HPCALB_VAL_15 +15 counts per each 32768 ticks of the counter 0xF HPCALB_VAL_16 -16 counts per each 32768 ticks of the counter 0x10 HPCALB_VAL_17 -15 counts per each 32768 ticks of the counter 0x11 HPCALB_VAL_30 -2 counts per each 32768 ticks of the counter 0x1E HPCALB_VAL_31 -1 counts per each 32768 ticks of the counter 0x1F HP_TS HP Time Synchronize 16 1 read-write HP_TS_0 No Action 0 HP_TS_1 Synchronize the HP Time Counter to the LP Time Counter 0x1 BTN_CONFIG Button Configuration 24 3 read-write BTN_MASK Button interrupt mask 27 1 read-write HPSICR SNVS_HP Security Interrupt Control Register 0xC 32 read-write 0 0xFFFFFFFF SV0_EN Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation 0 1 read-write SV0_EN_0 Security Violation 0 Interrupt is Disabled 0 SV0_EN_1 Security Violation 0 Interrupt is Enabled 0x1 SV1_EN Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation 1 1 read-write SV1_EN_0 Security Violation 1 Interrupt is Disabled 0 SV1_EN_1 Security Violation 1 Interrupt is Enabled 0x1 SV2_EN Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation 2 1 read-write SV2_EN_0 Security Violation 2 Interrupt is Disabled 0 SV2_EN_1 Security Violation 2 Interrupt is Enabled 0x1 SV3_EN Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation 3 1 read-write SV3_EN_0 Security Violation 3 Interrupt is Disabled 0 SV3_EN_1 Security Violation 3 Interrupt is Enabled 0x1 SV4_EN Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation 4 1 read-write SV4_EN_0 Security Violation 4 Interrupt is Disabled 0 SV4_EN_1 Security Violation 4 Interrupt is Enabled 0x1 SV5_EN Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation 5 1 read-write SV5_EN_0 Security Violation 5 Interrupt is Disabled 0 SV5_EN_1 Security Violation 5 Interrupt is Enabled 0x1 LPSVI_EN LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section 31 1 read-write LPSVI_EN_0 LP Security Violation Interrupt is Disabled 0 LPSVI_EN_1 LP Security Violation Interrupt is Enabled 0x1 HPSVCR SNVS_HP Security Violation Control Register 0x10 32 read-write 0 0xFFFFFFFF SV0_CFG Security Violation 0 Security Violation Configuration This field configures the Security Violation 0 Security Violation Input 0 1 read-write SV0_CFG_0 Security Violation 0 is a non-fatal violation 0 SV0_CFG_1 Security Violation 0 is a fatal violation 0x1 SV1_CFG Security Violation 1 Security Violation Configuration This field configures the Security Violation 1 Security Violation Input 1 1 read-write SV1_CFG_0 Security Violation 1 is a non-fatal violation 0 SV1_CFG_1 Security Violation 1 is a fatal violation 0x1 SV2_CFG Security Violation 2 Security Violation Configuration This field configures the Security Violation 2 Security Violation Input 2 1 read-write SV2_CFG_0 Security Violation 2 is a non-fatal violation 0 SV2_CFG_1 Security Violation 2 is a fatal violation 0x1 SV3_CFG Security Violation 3 Security Violation Configuration This field configures the Security Violation 3 Security Violation Input 3 1 read-write SV3_CFG_0 Security Violation 3 is a non-fatal violation 0 SV3_CFG_1 Security Violation 3 is a fatal violation 0x1 SV4_CFG Security Violation 4 Security Violation Configuration This field configures the Security Violation 4 Security Violation Input 4 1 read-write SV4_CFG_0 Security Violation 4 is a non-fatal violation 0 SV4_CFG_1 Security Violation 4 is a fatal violation 0x1 SV5_CFG Security Violation 5 Security Violation Configuration This field configures the Security Violation 5 Security Violation Input 5 2 read-write SV5_CFG_0 Security Violation 5 is disabled 0 SV5_CFG_1 Security Violation 5 is a non-fatal violation 0x1 SV5_CFG_2 Security Violation 5 is a fatal violation #1x LPSV_CFG LP Security Violation Configuration This field configures the LP security violation source. 30 2 read-write LPSV_CFG_0 LP security violation is disabled 0 LPSV_CFG_1 LP security violation is a non-fatal violation 0x1 LPSV_CFG_2 LP security violation is a fatal violation #1x HPSR SNVS_HP Status Register 0x14 32 read-write 0x80003000 0xFFFFFFFF HPTA HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared. 0 1 read-write oneToClear HPTA_0 No time alarm interrupt occurred. 0 HPTA_1 A time alarm interrupt occurred. 0x1 PI Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared. 1 1 read-write oneToClear PI_0 No periodic interrupt occurred. 0 PI_1 A periodic interrupt occurred. 0x1 LPDIS Low Power Disable If 1, the low power section has been disabled by means of an input signal to SNVS 4 1 read-only BTN Button Value of the BTN input 6 1 read-only BI Button Interrupt Signal ipi_snvs_btn_int_b was asserted. 7 1 read-write oneToClear SSM_STATE System Security Monitor State This field contains the encoded state of the SSM's state machine 8 4 read-only SSM_STATE_0 Init 0 SSM_STATE_1 Hard Fail 0x1 SSM_STATE_3 Soft Fail 0x3 SSM_STATE_8 Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) 0x8 SSM_STATE_9 Check 0x9 SSM_STATE_11 Non-Secure 0xB SSM_STATE_13 Trusted 0xD SSM_STATE_15 Secure 0xF SECURITY_CONFIG Security Configuration This field reflects the settings of the sys_secure_boot input and the three security configuration inputs to SNVS 12 4 read-only FAB_CONFIG FAB configuration 0 OPEN_CONFIG OPEN configuration 0x1 OPEN_CONFIG OPEN configuration 0x2 OPEN_CONFIG OPEN configuration 0x3 FIELD_RETURN_CONFIG FIELD RETURN configuration #x1xx FAB_CONFIG FAB configuration 0x8 CLOSED_CONFIG CLOSED configuration 0x9 CLOSED_CONFIG CLOSED configuration 0xA CLOSED_CONFIG CLOSED configuration 0xB OTPMK_SYNDROME One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location 16 9 read-only OTPMK_ZERO One Time Programmable Master Key is Equal to Zero 27 1 read-only OTPMK_ZERO_0 The OTPMK is not zero. 0 OTPMK_ZERO_1 The OTPMK is zero. 0x1 ZMK_ZERO Zeroizable Master Key is Equal to Zero 31 1 read-only ZMK_ZERO_0 The ZMK is not zero. 0 ZMK_ZERO_1 The ZMK is zero. 0x1 HPSVSR SNVS_HP Security Violation Status Register 0x18 32 read-write 0x80000000 0xFFFFFFFF SV0 Security Violation 0 security violation was detected. 0 1 read-write oneToClear SV0_0 No Security Violation 0 security violation was detected. 0 SV0_1 Security Violation 0 security violation was detected. 0x1 SV1 Security Violation 1 security violation was detected. 1 1 read-write oneToClear SV1_0 No Security Violation 1 security violation was detected. 0 SV1_1 Security Violation 1 security violation was detected. 0x1 SV2 Security Violation 2 security violation was detected. 2 1 read-write oneToClear SV2_0 No Security Violation 2 security violation was detected. 0 SV2_1 Security Violation 2 security violation was detected. 0x1 SV3 Security Violation 3 security violation was detected. 3 1 read-write oneToClear SV3_0 No Security Violation 3 security violation was detected. 0 SV3_1 Security Violation 3 security violation was detected. 0x1 SV4 Security Violation 4 security violation was detected. 4 1 read-write oneToClear SV4_0 No Security Violation 4 security violation was detected. 0 SV4_1 Security Violation 4 security violation was detected. 0x1 SV5 Security Violation 5 security violation was detected. 5 1 read-write oneToClear SV5_0 No Security Violation 5 security violation was detected. 0 SV5_1 Security Violation 5 security violation was detected. 0x1 SW_SV Software Security Violation This bit is a read-only copy of the SW_SV bit in the HP Command Register 13 1 read-only SW_FSV Software Fatal Security Violation This bit is a read-only copy of the SW_FSV bit in the HP Command Register 14 1 read-only SW_LPSV LP Software Security Violation This bit is a read-only copy of the SW_LPSV bit in the HP Command Register 15 1 read-only ZMK_SYNDROME Zeroizable Master Key Syndrome The ZMK syndrome indicates the single-bit error location and parity for the ZMK register 16 9 read-only ZMK_ECC_FAIL Zeroizable Master Key Error Correcting Code Check Failure When set, this bit triggers a bad key violation to the SSM and a security violation to the SNVS_LP section, which clears security sensitive data 27 1 read-write oneToClear ZMK_ECC_FAIL_0 ZMK ECC Failure was not detected. 0 ZMK_ECC_FAIL_1 ZMK ECC Failure was detected. 0x1 LP_SEC_VIO LP Security Violation A security volation was detected in the SNVS low power section. 31 1 read-only HPHACIVR SNVS_HP High Assurance Counter IV Register 0x1C 32 read-write 0 0xFFFFFFFF HAC_COUNTER_IV High Assurance Counter Initial Value This register is used to set the starting count value to the high assurance counter 0 32 read-write HPHACR SNVS_HP High Assurance Counter Register 0x20 32 read-only 0 0xFFFFFFFF HAC_COUNTER High Assurance Counter When the HAC_EN bit is set and the SSM is in the soft fail state, this counter starts to count down with the system clock 0 32 read-only HPRTCMR SNVS_HP Real Time Counter MSB Register 0x24 32 read-write 0 0xFFFFFFFF RTC HP Real Time Counter The most-significant 15 bits of the RTC 0 15 read-write HPRTCLR SNVS_HP Real Time Counter LSB Register 0x28 32 read-write 0 0xFFFFFFFF RTC HP Real Time Counter least-significant 32 bits 0 32 read-write HPTAMR SNVS_HP Time Alarm MSB Register 0x2C 32 read-write 0 0xFFFFFFFF HPTA_MS HP Time Alarm, most-significant 15 bits 0 15 read-write HPTALR SNVS_HP Time Alarm LSB Register 0x30 32 read-write 0 0xFFFFFFFF HPTA_LS HP Time Alarm, 32 least-significant bits 0 32 read-write LPLR SNVS_LP Lock Register 0x34 32 read-write 0 0xFFFFFFFF ZMK_WHL Zeroizable Master Key Write Hard Lock When set, prevents any writes (software and hardware) to the ZMK registers and ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR 0 1 read-write ZMK_WHL_0 Write access is allowed. 0 ZMK_WHL_1 Write access is not allowed. 0x1 ZMK_RHL Zeroizable Master Key Read Hard Lock When set, prevents any software reads to the ZMK registers and ZMK_ECC_VALUE field of the LPMKCR 1 1 read-write ZMK_RHL_0 Read access is allowed (only in software programming mode). 0 ZMK_RHL_1 Read access is not allowed. 0x1 SRTC_HL Secure Real Time Counter Hard Lock When set, prevents any writes to the SRTC registers, SRTC_ENV, and SRTC_INV_EN bits 2 1 read-write SRTC_HL_0 Write access is allowed. 0 SRTC_HL_1 Write access is not allowed. 0x1 LPCALB_HL LP Calibration Hard Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) 3 1 read-write LPCALB_HL_0 Write access is allowed. 0 LPCALB_HL_1 Write access is not allowed. 0x1 MC_HL Monotonic Counter Hard Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit 4 1 read-write MC_HL_0 Write access (increment) is allowed. 0 MC_HL_1 Write access (increment) is not allowed. 0x1 GPR_HL General Purpose Register Hard Lock When set, prevents any writes to the GPR 5 1 read-write GPR_HL_0 Write access is allowed. 0 GPR_HL_1 Write access is not allowed. 0x1 LPSVCR_HL LP Security Violation Control Register Hard Lock When set, prevents any writes to the LPSVCR 6 1 read-write LPSVCR_HL_0 Write access is allowed. 0 LPSVCR_HL_1 Write access is not allowed. 0x1 LPTDCR_HL LP Tamper Detectors Configuration Register Hard Lock When set, prevents any writes to the LPTDCR 8 1 read-write LPTDCR_HL_0 Write access is allowed. 0 LPTDCR_HL_1 Write access is not allowed. 0x1 MKS_HL Master Key Select Hard Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LP Master Key Control Register 9 1 read-write MKS_HL_0 Write access is allowed. 0 MKS_HL_1 Write access is not allowed. 0x1 LPCR SNVS_LP Control Register 0x38 32 read-write 0x20 0xFFFFFFFF SRTC_ENV Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational 0 1 read-write SRTC_ENV_0 SRTC is disabled or invalid. 0 SRTC_ENV_1 SRTC is enabled and valid. 0x1 LPTA_EN LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter 1 1 read-write LPTA_EN_0 LP time alarm interrupt is disabled. 0 LPTA_EN_1 LP time alarm interrupt is enabled. 0x1 MC_ENV Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR) 2 1 read-write MC_ENV_0 MC is disabled or invalid. 0 MC_ENV_1 MC is enabled and valid. 0x1 LPWUI_EN LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (tamper event, MC rollover, SRTC rollover, or time alarm ) 3 1 read-write SRTC_INV_EN If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared) 4 1 read-write SRTC_INV_EN_0 SRTC stays valid in the case of security violation. 0 SRTC_INV_EN_1 SRTC is invalidated in the case of security violation. 0x1 DP_EN Dumb PMIC Enabled When set, software can control the system power 5 1 read-write DP_EN_0 Smart PMIC enabled. 0 DP_EN_1 Dumb PMIC enabled. 0x1 TOP Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power 6 1 read-write TOP_0 Leave system power on. 0 TOP_1 Turn off system power. 0x1 PWR_GLITCH_EN Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted 7 1 read-write LPCALB_EN LP Calibration Enable When set, enables the SRTC calibration mechanism 8 1 read-write LPCALB_EN_0 SRTC Time calibration is disabled. 0 LPCALB_EN_1 SRTC Time calibration is enabled. 0x1 LPCALB_VAL LP Calibration Value Defines signed calibration value for SRTC 10 5 read-write LPCALB_VAL_0 +0 counts per each 32768 ticks of the counter clock 0 LPCALB_VAL_1 +1 counts per each 32768 ticks of the counter clock 0x1 LPCALB_VAL_2 +2 counts per each 32768 ticks of the counter clock 0x2 LPCALB_VAL_15 +15 counts per each 32768 ticks of the counter clock 0xF LPCALB_VAL_16 -16 counts per each 32768 ticks of the counter clock 0x10 LPCALB_VAL_17 -15 counts per each 32768 ticks of the counter clock 0x11 LPCALB_VAL_30 -2 counts per each 32768 ticks of the counter clock 0x1E LPCALB_VAL_31 -1 counts per each 32768 ticks of the counter clock 0x1F BTN_PRESS_TIME This field configures the button press time out values for the PMIC Logic 16 2 read-write DEBOUNCE This field configures the amount of debounce time for the BTN input signal 18 2 read-write ON_TIME The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power 20 2 read-write PK_EN PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en 22 1 read-write PK_OVERRIDE PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override 23 1 read-write GPR_Z_DIS General Purpose Registers Zeroization Disable 24 1 read-write LPMKCR SNVS_LP Master Key Control Register 0x3C 32 read-write 0 0xFFFFFFFF MASTER_KEY_SEL Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR 0 2 read-write MASTER_KEY_SEL_0 Select one time programmable master key. #0x MASTER_KEY_SEL_2 Select zeroizable master key when MKS_EN bit is set . 0x2 MASTER_KEY_SEL_3 Select combined master key when MKS_EN bit is set . 0x3 ZMK_HWP Zeroizable Master Key hardware Programming mode When set, only the hardware key programming mechanism can set the ZMK and software cannot read it 2 1 read-write ZMK_HWP_0 ZMK is in the software programming mode. 0 ZMK_HWP_1 ZMK is in the hardware programming mode. 0x1 ZMK_VAL Zeroizable Master Key Valid When set, the ZMK value can be selected by the master key control block for use by cryptographic modules 3 1 read-write ZMK_VAL_0 ZMK is not valid. 0 ZMK_VAL_1 ZMK is valid. 0x1 ZMK_ECC_EN Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register 4 1 read-write ZMK_ECC_EN_0 ZMK ECC check is disabled. 0 ZMK_ECC_EN_1 ZMK ECC check is enabled. 0x1 ZMK_ECC_VALUE Zeroizable Master Key Error Correcting Code Value This field is automatically calculated and set when one is written into ZMK_ECC_EN bit of this register 7 9 read-only LPSVCR SNVS_LP Security Violation Control Register 0x40 32 read-write 0 0xFFFFFFFF SV0_EN Security Violation 0 Enable This bit enables Security Violation 0 Input 0 1 read-write SV0_EN_0 Security Violation 0 is disabled in the LP domain. 0 SV0_EN_1 Security Violation 0 is enabled in the LP domain. 0x1 SV1_EN Security Violation 1 Enable This bit enables Security Violation 1 Input 1 1 read-write SV1_EN_0 Security Violation 1 is disabled in the LP domain. 0 SV1_EN_1 Security Violation 1 is enabled in the LP domain. 0x1 SV2_EN Security Violation 2 Enable This bit enables Security Violation 2 Input 2 1 read-write SV2_EN_0 Security Violation 2 is disabled in the LP domain. 0 SV2_EN_1 Security Violation 2 is enabled in the LP domain. 0x1 SV3_EN Security Violation 3 Enable This bit enables Security Violation 3 Input 3 1 read-write SV3_EN_0 Security Violation 3 is disabled in the LP domain. 0 SV3_EN_1 Security Violation 3 is enabled in the LP domain. 0x1 SV4_EN Security Violation 4 Enable This bit enables Security Violation 4 Input 4 1 read-write SV4_EN_0 Security Violation 4 is disabled in the LP domain. 0 SV4_EN_1 Security Violation 4 is enabled in the LP domain. 0x1 SV5_EN Security Violation 5 Enable This bit enables Security Violation 5 Input 5 1 read-write SV5_EN_0 Security Violation 5 is disabled in the LP domain. 0 SV5_EN_1 Security Violation 5 is enabled in the LP domain. 0x1 LPTDCR SNVS_LP Tamper Detectors Configuration Register 0x48 32 read-write 0 0xFFFFFFFF SRTCR_EN SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation. 1 1 read-write SRTCR_EN_0 SRTC rollover is disabled. 0 SRTCR_EN_1 SRTC rollover is enabled. 0x1 MCR_EN MC Rollover Enable When set, an MC Rollover event generates an LP security violation. 2 1 read-write MCR_EN_0 MC rollover is disabled. 0 MCR_EN_1 MC rollover is enabled. 0x1 ET1_EN External Tampering 1 Enable When set, external tampering 1 detection generates an LP security violation 9 1 read-write ET1_EN_0 External tamper 1 is disabled. 0 ET1_EN_1 External tamper 1 is enabled. 0x1 ET1P External Tampering 1 Polarity This bit is used to determine the polarity of external tamper 1. 11 1 read-write ET1P_0 External tamper 1 is active low. 0 ET1P_1 External tamper 1 is active high. 0x1 PFD_OBSERV System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block) 14 1 read-write POR_OBSERV Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS 15 1 read-write OSCB Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted 28 1 read-write OSCB_0 Normal SRTC clock oscillator not bypassed. 0 OSCB_1 Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. 0x1 LPSR SNVS_LP Status Register 0x4C 32 read-write 0x8 0xFFFFFFFF LPTA LP Time Alarm 0 1 read-write oneToClear LPTA_0 No time alarm interrupt occurred. 0 LPTA_1 A time alarm interrupt occurred. 0x1 SRTCR Secure Real Time Counter Rollover 1 1 read-write oneToClear SRTCR_0 SRTC has not reached its maximum value. 0 SRTCR_1 SRTC has reached its maximum value. 0x1 MCR Monotonic Counter Rollover 2 1 read-write oneToClear MCR_0 MC has not reached its maximum value. 0 MCR_1 MC has reached its maximum value. 0x1 PGD Power Supply Glitch Detected 0 No power supply glitch. 1 Power supply glitch is detected. 3 1 read-write oneToClear ET1D External Tampering 1 Detected 9 1 read-write oneToClear ET1D_0 External tampering 1 not detected. 0 ET1D_1 External tampering 1 detected. 0x1 ESVD External Security Violation Detected Indicates that a security violation is detected on one of the HP security violation ports 16 1 read-write oneToClear ESVD_0 No external security violation. 0 ESVD_1 External security violation is detected. 0x1 EO Emergency Off This bit is set when a power off is requested. 17 1 read-write oneToClear EO_0 Emergency off was not detected. 0 EO_1 Emergency off was detected. 0x1 SPO Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time 18 1 read-write oneToClear SPO_0 Set Power Off was not detected. 0 SPO_1 Set Power Off was detected. 0x1 SED Scan Exit Detected 20 1 read-write oneToClear SED_0 Scan exit was not detected. 0 SED_1 Scan exit was detected. 0x1 LPNS LP Section is Non-Secured Indicates that LP section was provisioned/programmed in the non-secure state 30 1 read-only LPNS_0 LP section was not programmed in the non-secure state. 0 LPNS_1 LP section was programmed in the non-secure state. 0x1 LPS LP Section is Secured Indicates that the LP section is provisioned/programmed in the secure or trusted state 31 1 read-only LPS_0 LP section was not programmed in secure or trusted state. 0 LPS_1 LP section was programmed in secure or trusted state. 0x1 LPSRTCMR SNVS_LP Secure Real Time Counter MSB Register 0x50 32 read-write 0 0xFFFFFFFF SRTC LP Secure Real Time Counter The most-significant 15 bits of the SRTC 0 15 read-write LPSRTCLR SNVS_LP Secure Real Time Counter LSB Register 0x54 32 read-write 0 0xFFFFFFFF SRTC LP Secure Real Time Counter least-significant 32 bits This register can be programmed only when SRTC is not active and not locked, meaning the SRTC_ENV, SRTC_SL, and SRTC_HL bits are not set 0 32 read-write LPTAR SNVS_LP Time Alarm Register 0x58 32 read-write 0 0xFFFFFFFF LPTA LP Time Alarm This register can be programmed only when the LP time alarm is disabled (LPTA_EN bit is not set) 0 32 read-write LPSMCMR SNVS_LP Secure Monotonic Counter MSB Register 0x5C 32 read-only 0 0xFFFFFFFF MON_COUNTER Monotonic Counter most-significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR register is detected 0 16 read-only MC_ERA_BITS Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses 16 16 read-only LPSMCLR SNVS_LP Secure Monotonic Counter LSB Register 0x60 32 read-only 0 0xFFFFFFFF MON_COUNTER Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR Register is detected 0 32 read-only LPPGDR SNVS_LP Power Glitch Detector Register 0x64 32 read-write 0 0xFFFFFFFF PGD Power Glitch Detector Value 0 32 read-write LPGPR0_legacy_alias SNVS_LP General Purpose Register 0 (legacy alias) 0x68 32 read-write 0 0xFFFFFFFF GPR General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. 0 32 read-write 8 0x4 LPZMKR[%s] SNVS_LP Zeroizable Master Key Register 0x6C 32 read-write 0 0xFFFFFFFF ZMK Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value 0 32 read-write 4 0x4 LPGPR_alias[%s] SNVS_LP General Purpose Registers 0 .. 3 0x90 32 read-write 0 0xFFFFFFFF GPR General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. 0 32 read-write 4 0x4 LPGPR[%s] SNVS_LP General Purpose Registers 0 .. 3 0x100 32 read-write 0 0xFFFFFFFF GPR General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. 0 32 read-write HPVIDR1 SNVS_HP Version ID Register 1 0xBF8 32 read-only 0x3E0104 0xFFFFFFFF MINOR_REV SNVS block minor version number 0 8 read-only MAJOR_REV SNVS block major version number 8 8 read-only IP_ID SNVS block ID 16 16 read-only HPVIDR2 SNVS_HP Version ID Register 2 0xBFC 32 read-only 0x6000000 0xFFFFFFFF CONFIG_OPT SNVS Configuration Options 0 8 read-only ECO_REV SNVS ECO Revision 8 8 read-only INTG_OPT SNVS Integration Options 16 8 read-only IP_ERA IP Era 00h - Era 1 or 2 03h - Era 3 04h - Era 4 05h - Era 5 24 8 read-only CCM_ANALOG CCM_ANALOG CCM_ANALOG CCM_ANALOG_ 0x400D8000 0 0x180 registers PLL_USB1 Analog USB1 480MHz PLL Control Register 0x10 32 read-write 0x12000 0xFFFFFFFF DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. 1 1 read-write EN_USB_CLKS Powers the 9-phase PLL outputs for USBPHYn 6 1 read-write EN_USB_CLKS_0 PLL outputs for USBPHYn off. 0 EN_USB_CLKS_1 PLL outputs for USBPHYn on. 0x1 POWER Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. 12 1 read-write ENABLE Enable the PLL clock output. 13 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write LOCK 1 - PLL is currently locked. 0 - PLL is not currently locked. 31 1 read-only PLL_USB1_SET Analog USB1 480MHz PLL Control Register 0x14 32 read-write 0x12000 0xFFFFFFFF DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. 1 1 read-write EN_USB_CLKS Powers the 9-phase PLL outputs for USBPHYn 6 1 read-write EN_USB_CLKS_0 PLL outputs for USBPHYn off. 0 EN_USB_CLKS_1 PLL outputs for USBPHYn on. 0x1 POWER Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. 12 1 read-write ENABLE Enable the PLL clock output. 13 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write LOCK 1 - PLL is currently locked. 0 - PLL is not currently locked. 31 1 read-only PLL_USB1_CLR Analog USB1 480MHz PLL Control Register 0x18 32 read-write 0x12000 0xFFFFFFFF DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. 1 1 read-write EN_USB_CLKS Powers the 9-phase PLL outputs for USBPHYn 6 1 read-write EN_USB_CLKS_0 PLL outputs for USBPHYn off. 0 EN_USB_CLKS_1 PLL outputs for USBPHYn on. 0x1 POWER Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. 12 1 read-write ENABLE Enable the PLL clock output. 13 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write LOCK 1 - PLL is currently locked. 0 - PLL is not currently locked. 31 1 read-only PLL_USB1_TOG Analog USB1 480MHz PLL Control Register 0x1C 32 read-write 0x12000 0xFFFFFFFF DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. 1 1 read-write EN_USB_CLKS Powers the 9-phase PLL outputs for USBPHYn 6 1 read-write EN_USB_CLKS_0 PLL outputs for USBPHYn off. 0 EN_USB_CLKS_1 PLL outputs for USBPHYn on. 0x1 POWER Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. 12 1 read-write ENABLE Enable the PLL clock output. 13 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write LOCK 1 - PLL is currently locked. 0 - PLL is not currently locked. 31 1 read-only PLL_SYS Analog System PLL Control Register 0x30 32 read-write 0x13001 0xFFFFFFFF DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. 0 1 read-write POWERDOWN Powers down the PLL. 12 1 read-write ENABLE Enable PLL output 13 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write LOCK 1 - PLL is currently locked; 0 - PLL is not currently locked. 31 1 read-only PLL_SYS_SET Analog System PLL Control Register 0x34 32 read-write 0x13001 0xFFFFFFFF DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. 0 1 read-write POWERDOWN Powers down the PLL. 12 1 read-write ENABLE Enable PLL output 13 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write LOCK 1 - PLL is currently locked; 0 - PLL is not currently locked. 31 1 read-only PLL_SYS_CLR Analog System PLL Control Register 0x38 32 read-write 0x13001 0xFFFFFFFF DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. 0 1 read-write POWERDOWN Powers down the PLL. 12 1 read-write ENABLE Enable PLL output 13 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write LOCK 1 - PLL is currently locked; 0 - PLL is not currently locked. 31 1 read-only PLL_SYS_TOG Analog System PLL Control Register 0x3C 32 read-write 0x13001 0xFFFFFFFF DIV_SELECT This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. 0 1 read-write POWERDOWN Powers down the PLL. 12 1 read-write ENABLE Enable PLL output 13 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write LOCK 1 - PLL is currently locked; 0 - PLL is not currently locked. 31 1 read-only PLL_SYS_SS 528MHz System PLL Spread Spectrum Register 0x40 32 read-write 0 0xFFFFFFFF STEP Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. 0 15 read-write ENABLE Enable bit 15 1 read-write ENABLE_0 Spread spectrum modulation disabled 0 ENABLE_1 Soread spectrum modulation enabled 0x1 STOP Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. 16 16 read-write PLL_SYS_NUM Numerator of 528MHz System PLL Fractional Loop Divider Register 0x50 32 read-write 0 0xFFFFFFFF A 30 bit numerator (A) of fractional loop divider (signed integer). 0 30 read-write PLL_SYS_DENOM Denominator of 528MHz System PLL Fractional Loop Divider Register 0x60 32 read-write 0x12 0xFFFFFFFF B 30 bit denominator (B) of fractional loop divider (unsigned integer). 0 30 read-write PLL_AUDIO Analog Audio PLL control Register 0x70 32 read-write 0x11006 0xFFFFFFFF DIV_SELECT This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. 0 7 read-write POWERDOWN Powers down the PLL. 12 1 read-write ENABLE Enable PLL output 13 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write POST_DIV_SELECT These bits implement a divider after the PLL, but before the enable and bypass mux. 19 2 read-write POST_DIV_SELECT_0 Divide by 4. 0 POST_DIV_SELECT_1 Divide by 2. 0x1 POST_DIV_SELECT_2 Divide by 1. 0x2 LOCK 1 - PLL is currently locked. 0 - PLL is not currently locked. 31 1 read-only PLL_AUDIO_SET Analog Audio PLL control Register 0x74 32 read-write 0x11006 0xFFFFFFFF DIV_SELECT This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. 0 7 read-write POWERDOWN Powers down the PLL. 12 1 read-write ENABLE Enable PLL output 13 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write POST_DIV_SELECT These bits implement a divider after the PLL, but before the enable and bypass mux. 19 2 read-write POST_DIV_SELECT_0 Divide by 4. 0 POST_DIV_SELECT_1 Divide by 2. 0x1 POST_DIV_SELECT_2 Divide by 1. 0x2 LOCK 1 - PLL is currently locked. 0 - PLL is not currently locked. 31 1 read-only PLL_AUDIO_CLR Analog Audio PLL control Register 0x78 32 read-write 0x11006 0xFFFFFFFF DIV_SELECT This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. 0 7 read-write POWERDOWN Powers down the PLL. 12 1 read-write ENABLE Enable PLL output 13 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write POST_DIV_SELECT These bits implement a divider after the PLL, but before the enable and bypass mux. 19 2 read-write POST_DIV_SELECT_0 Divide by 4. 0 POST_DIV_SELECT_1 Divide by 2. 0x1 POST_DIV_SELECT_2 Divide by 1. 0x2 LOCK 1 - PLL is currently locked. 0 - PLL is not currently locked. 31 1 read-only PLL_AUDIO_TOG Analog Audio PLL control Register 0x7C 32 read-write 0x11006 0xFFFFFFFF DIV_SELECT This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. 0 7 read-write POWERDOWN Powers down the PLL. 12 1 read-write ENABLE Enable PLL output 13 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write POST_DIV_SELECT These bits implement a divider after the PLL, but before the enable and bypass mux. 19 2 read-write POST_DIV_SELECT_0 Divide by 4. 0 POST_DIV_SELECT_1 Divide by 2. 0x1 POST_DIV_SELECT_2 Divide by 1. 0x2 LOCK 1 - PLL is currently locked. 0 - PLL is not currently locked. 31 1 read-only PLL_AUDIO_NUM Numerator of Audio PLL Fractional Loop Divider Register 0x80 32 read-write 0x5F5E100 0xFFFFFFFF A 30 bit numerator of fractional loop divider. 0 30 read-write PLL_AUDIO_DENOM Denominator of Audio PLL Fractional Loop Divider Register 0x90 32 read-write 0x2964619C 0xFFFFFFFF B 30 bit denominator of fractional loop divider. 0 30 read-write PLL_ENET Analog ENET PLL Control Register 0xE0 32 read-write 0x11001 0xFFFFFFFF POWERDOWN Powers down the PLL. 12 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write ENET_500M_REF_EN Enable the PLL providing ENET 500 MHz reference clock 22 1 read-write LOCK 1 - PLL is currently locked; 0 - PLL is not currently locked. 31 1 read-only PLL_ENET_SET Analog ENET PLL Control Register 0xE4 32 read-write 0x11001 0xFFFFFFFF POWERDOWN Powers down the PLL. 12 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write ENET_500M_REF_EN Enable the PLL providing ENET 500 MHz reference clock 22 1 read-write LOCK 1 - PLL is currently locked; 0 - PLL is not currently locked. 31 1 read-only PLL_ENET_CLR Analog ENET PLL Control Register 0xE8 32 read-write 0x11001 0xFFFFFFFF POWERDOWN Powers down the PLL. 12 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write ENET_500M_REF_EN Enable the PLL providing ENET 500 MHz reference clock 22 1 read-write LOCK 1 - PLL is currently locked; 0 - PLL is not currently locked. 31 1 read-only PLL_ENET_TOG Analog ENET PLL Control Register 0xEC 32 read-write 0x11001 0xFFFFFFFF POWERDOWN Powers down the PLL. 12 1 read-write BYPASS_CLK_SRC Determines the bypass source. 14 2 read-write REF_CLK_24M Select the 24MHz oscillator as source. 0 BYPASS Bypass the PLL. 16 1 read-write ENET_500M_REF_EN Enable the PLL providing ENET 500 MHz reference clock 22 1 read-write LOCK 1 - PLL is currently locked; 0 - PLL is not currently locked. 31 1 read-only PFD_480 480MHz Clock (PLL3) Phase Fractional Divider Control Register 0xF0 32 read-write 0x1311100C 0xFFFFFFFF PFD0_FRAC This field controls the fractional divide value 0 6 read-write PFD0_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 6 1 read-only PFD0_CLKGATE If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) 7 1 read-write PFD1_FRAC This field controls the fractional divide value 8 6 read-write PFD1_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 14 1 read-only PFD1_CLKGATE IO Clock Gate 15 1 read-write PFD2_FRAC This field controls the fractional divide value 16 6 read-write PFD2_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 22 1 read-only PFD2_CLKGATE IO Clock Gate 23 1 read-write PFD3_FRAC This field controls the fractional divide value 24 6 read-write PFD3_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 30 1 read-only PFD3_CLKGATE IO Clock Gate 31 1 read-write PFD_480_SET 480MHz Clock (PLL3) Phase Fractional Divider Control Register 0xF4 32 read-write 0x1311100C 0xFFFFFFFF PFD0_FRAC This field controls the fractional divide value 0 6 read-write PFD0_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 6 1 read-only PFD0_CLKGATE If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) 7 1 read-write PFD1_FRAC This field controls the fractional divide value 8 6 read-write PFD1_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 14 1 read-only PFD1_CLKGATE IO Clock Gate 15 1 read-write PFD2_FRAC This field controls the fractional divide value 16 6 read-write PFD2_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 22 1 read-only PFD2_CLKGATE IO Clock Gate 23 1 read-write PFD3_FRAC This field controls the fractional divide value 24 6 read-write PFD3_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 30 1 read-only PFD3_CLKGATE IO Clock Gate 31 1 read-write PFD_480_CLR 480MHz Clock (PLL3) Phase Fractional Divider Control Register 0xF8 32 read-write 0x1311100C 0xFFFFFFFF PFD0_FRAC This field controls the fractional divide value 0 6 read-write PFD0_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 6 1 read-only PFD0_CLKGATE If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) 7 1 read-write PFD1_FRAC This field controls the fractional divide value 8 6 read-write PFD1_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 14 1 read-only PFD1_CLKGATE IO Clock Gate 15 1 read-write PFD2_FRAC This field controls the fractional divide value 16 6 read-write PFD2_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 22 1 read-only PFD2_CLKGATE IO Clock Gate 23 1 read-write PFD3_FRAC This field controls the fractional divide value 24 6 read-write PFD3_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 30 1 read-only PFD3_CLKGATE IO Clock Gate 31 1 read-write PFD_480_TOG 480MHz Clock (PLL3) Phase Fractional Divider Control Register 0xFC 32 read-write 0x1311100C 0xFFFFFFFF PFD0_FRAC This field controls the fractional divide value 0 6 read-write PFD0_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 6 1 read-only PFD0_CLKGATE If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) 7 1 read-write PFD1_FRAC This field controls the fractional divide value 8 6 read-write PFD1_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 14 1 read-only PFD1_CLKGATE IO Clock Gate 15 1 read-write PFD2_FRAC This field controls the fractional divide value 16 6 read-write PFD2_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 22 1 read-only PFD2_CLKGATE IO Clock Gate 23 1 read-write PFD3_FRAC This field controls the fractional divide value 24 6 read-write PFD3_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 30 1 read-only PFD3_CLKGATE IO Clock Gate 31 1 read-write PFD_528 528MHz Clock (PLL2) Phase Fractional Divider Control Register 0x100 32 read-write 0x1018101B 0xFFFFFFFF PFD0_FRAC This field controls the fractional divide value 0 6 read-write PFD0_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 6 1 read-only PFD0_CLKGATE If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) 7 1 read-write PFD1_FRAC This field controls the fractional divide value 8 6 read-write PFD1_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 14 1 read-only PFD1_CLKGATE IO Clock Gate 15 1 read-write PFD2_FRAC This field controls the fractional divide value 16 6 read-write PFD2_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 22 1 read-only PFD2_CLKGATE IO Clock Gate 23 1 read-write PFD3_FRAC This field controls the fractional divide value 24 6 read-write PFD3_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 30 1 read-only PFD3_CLKGATE IO Clock Gate 31 1 read-write PFD_528_SET 528MHz Clock (PLL2) Phase Fractional Divider Control Register 0x104 32 read-write 0x1018101B 0xFFFFFFFF PFD0_FRAC This field controls the fractional divide value 0 6 read-write PFD0_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 6 1 read-only PFD0_CLKGATE If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) 7 1 read-write PFD1_FRAC This field controls the fractional divide value 8 6 read-write PFD1_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 14 1 read-only PFD1_CLKGATE IO Clock Gate 15 1 read-write PFD2_FRAC This field controls the fractional divide value 16 6 read-write PFD2_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 22 1 read-only PFD2_CLKGATE IO Clock Gate 23 1 read-write PFD3_FRAC This field controls the fractional divide value 24 6 read-write PFD3_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 30 1 read-only PFD3_CLKGATE IO Clock Gate 31 1 read-write PFD_528_CLR 528MHz Clock (PLL2) Phase Fractional Divider Control Register 0x108 32 read-write 0x1018101B 0xFFFFFFFF PFD0_FRAC This field controls the fractional divide value 0 6 read-write PFD0_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 6 1 read-only PFD0_CLKGATE If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) 7 1 read-write PFD1_FRAC This field controls the fractional divide value 8 6 read-write PFD1_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 14 1 read-only PFD1_CLKGATE IO Clock Gate 15 1 read-write PFD2_FRAC This field controls the fractional divide value 16 6 read-write PFD2_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 22 1 read-only PFD2_CLKGATE IO Clock Gate 23 1 read-write PFD3_FRAC This field controls the fractional divide value 24 6 read-write PFD3_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 30 1 read-only PFD3_CLKGATE IO Clock Gate 31 1 read-write PFD_528_TOG 528MHz Clock (PLL2) Phase Fractional Divider Control Register 0x10C 32 read-write 0x1018101B 0xFFFFFFFF PFD0_FRAC This field controls the fractional divide value 0 6 read-write PFD0_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 6 1 read-only PFD0_CLKGATE If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) 7 1 read-write PFD1_FRAC This field controls the fractional divide value 8 6 read-write PFD1_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 14 1 read-only PFD1_CLKGATE IO Clock Gate 15 1 read-write PFD2_FRAC This field controls the fractional divide value 16 6 read-write PFD2_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 22 1 read-only PFD2_CLKGATE IO Clock Gate 23 1 read-write PFD3_FRAC This field controls the fractional divide value 24 6 read-write PFD3_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code 30 1 read-only PFD3_CLKGATE IO Clock Gate 31 1 read-write MISC0 Miscellaneous Register 0 0x150 32 read-write 0x4000000 0xFFFFFFFF REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry 0 1 read-write REFTOP_SELFBIASOFF Control bit to disable the self-bias circuit in the analog bandgap 3 1 read-write REFTOP_SELFBIASOFF_0 Uses coarse bias currents for startup 0 REFTOP_SELFBIASOFF_1 Uses bandgap-based bias currents for best performance. 0x1 REFTOP_VBGADJ Not related to CCM. See Power Management Unit (PMU) 4 3 read-write REFTOP_VBGADJ_0 Nominal VBG 0 REFTOP_VBGADJ_1 VBG+0.78% 0x1 REFTOP_VBGADJ_2 VBG+1.56% 0x2 REFTOP_VBGADJ_3 VBG+2.34% 0x3 REFTOP_VBGADJ_4 VBG-0.78% 0x4 REFTOP_VBGADJ_5 VBG-1.56% 0x5 REFTOP_VBGADJ_6 VBG-2.34% 0x6 REFTOP_VBGADJ_7 VBG-3.12% 0x7 REFTOP_VBGUP Status bit that signals the analog bandgap voltage is up and stable 7 1 read-write STOP_MODE_CONFIG Configure the analog behavior in stop mode. 10 2 read-write STOP_MODE_CONFIG_0 All analog except RTC powered down on stop mode assertion. 0 STOP_MODE_CONFIG_1 Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. 0x1 STOP_MODE_CONFIG_2 Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. 0x2 STOP_MODE_CONFIG_3 Beside RTC, low-power bandgap is selected and the rest analog is powered down. 0x3 DISCON_HIGH_SNVS This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 12 1 read-write DISCON_HIGH_SNVS_0 Turn on the switch 0 DISCON_HIGH_SNVS_1 Turn off the switch 0x1 OSC_I This field determines the bias current in the 24MHz oscillator 13 2 read-write NOMINAL Nominal 0 MINUS_12_5_PERCENT Decrease current by 12.5% 0x1 MINUS_25_PERCENT Decrease current by 25.0% 0x2 MINUS_37_5_PERCENT Decrease current by 37.5% 0x3 OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable 15 1 read-only OSC_XTALOK_EN This bit enables the detector that signals when the 24MHz crystal oscillator is stable 16 1 read-write CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 25 1 read-write ALLOW_AUTO_GATE Allow the logic to automatically gate the clock when the XTAL is powered down. 0 NO_AUTO_GATE Prevent the logic from ever gating off the clock. 0x1 CLKGATE_DELAY This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 26 3 read-write CLKGATE_DELAY_0 0.5ms 0 CLKGATE_DELAY_1 1.0ms 0x1 CLKGATE_DELAY_2 2.0ms 0x2 CLKGATE_DELAY_3 3.0ms 0x3 CLKGATE_DELAY_4 4.0ms 0x4 CLKGATE_DELAY_5 5.0ms 0x5 CLKGATE_DELAY_6 6.0ms 0x6 CLKGATE_DELAY_7 7.0ms 0x7 RTC_XTAL_SOURCE This field indicates which chip source is being used for the rtc clock 29 1 read-write RTC_XTAL_SOURCE_0 Internal ring oscillator 0 RTC_XTAL_SOURCE_1 RTC_XTAL 0x1 XTAL_24M_PWD This field powers down the 24M crystal oscillator if set true 30 1 read-write MISC0_SET Miscellaneous Register 0 0x154 32 read-write 0x4000000 0xFFFFFFFF REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry 0 1 read-write REFTOP_SELFBIASOFF Control bit to disable the self-bias circuit in the analog bandgap 3 1 read-write REFTOP_SELFBIASOFF_0 Uses coarse bias currents for startup 0 REFTOP_SELFBIASOFF_1 Uses bandgap-based bias currents for best performance. 0x1 REFTOP_VBGADJ Not related to CCM. See Power Management Unit (PMU) 4 3 read-write REFTOP_VBGADJ_0 Nominal VBG 0 REFTOP_VBGADJ_1 VBG+0.78% 0x1 REFTOP_VBGADJ_2 VBG+1.56% 0x2 REFTOP_VBGADJ_3 VBG+2.34% 0x3 REFTOP_VBGADJ_4 VBG-0.78% 0x4 REFTOP_VBGADJ_5 VBG-1.56% 0x5 REFTOP_VBGADJ_6 VBG-2.34% 0x6 REFTOP_VBGADJ_7 VBG-3.12% 0x7 REFTOP_VBGUP Status bit that signals the analog bandgap voltage is up and stable 7 1 read-write STOP_MODE_CONFIG Configure the analog behavior in stop mode. 10 2 read-write STOP_MODE_CONFIG_0 All analog except RTC powered down on stop mode assertion. 0 STOP_MODE_CONFIG_1 Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. 0x1 STOP_MODE_CONFIG_2 Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. 0x2 STOP_MODE_CONFIG_3 Beside RTC, low-power bandgap is selected and the rest analog is powered down. 0x3 DISCON_HIGH_SNVS This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 12 1 read-write DISCON_HIGH_SNVS_0 Turn on the switch 0 DISCON_HIGH_SNVS_1 Turn off the switch 0x1 OSC_I This field determines the bias current in the 24MHz oscillator 13 2 read-write NOMINAL Nominal 0 MINUS_12_5_PERCENT Decrease current by 12.5% 0x1 MINUS_25_PERCENT Decrease current by 25.0% 0x2 MINUS_37_5_PERCENT Decrease current by 37.5% 0x3 OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable 15 1 read-only OSC_XTALOK_EN This bit enables the detector that signals when the 24MHz crystal oscillator is stable 16 1 read-write CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 25 1 read-write ALLOW_AUTO_GATE Allow the logic to automatically gate the clock when the XTAL is powered down. 0 NO_AUTO_GATE Prevent the logic from ever gating off the clock. 0x1 CLKGATE_DELAY This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 26 3 read-write CLKGATE_DELAY_0 0.5ms 0 CLKGATE_DELAY_1 1.0ms 0x1 CLKGATE_DELAY_2 2.0ms 0x2 CLKGATE_DELAY_3 3.0ms 0x3 CLKGATE_DELAY_4 4.0ms 0x4 CLKGATE_DELAY_5 5.0ms 0x5 CLKGATE_DELAY_6 6.0ms 0x6 CLKGATE_DELAY_7 7.0ms 0x7 RTC_XTAL_SOURCE This field indicates which chip source is being used for the rtc clock 29 1 read-write RTC_XTAL_SOURCE_0 Internal ring oscillator 0 RTC_XTAL_SOURCE_1 RTC_XTAL 0x1 XTAL_24M_PWD This field powers down the 24M crystal oscillator if set true 30 1 read-write MISC0_CLR Miscellaneous Register 0 0x158 32 read-write 0x4000000 0xFFFFFFFF REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry 0 1 read-write REFTOP_SELFBIASOFF Control bit to disable the self-bias circuit in the analog bandgap 3 1 read-write REFTOP_SELFBIASOFF_0 Uses coarse bias currents for startup 0 REFTOP_SELFBIASOFF_1 Uses bandgap-based bias currents for best performance. 0x1 REFTOP_VBGADJ Not related to CCM. See Power Management Unit (PMU) 4 3 read-write REFTOP_VBGADJ_0 Nominal VBG 0 REFTOP_VBGADJ_1 VBG+0.78% 0x1 REFTOP_VBGADJ_2 VBG+1.56% 0x2 REFTOP_VBGADJ_3 VBG+2.34% 0x3 REFTOP_VBGADJ_4 VBG-0.78% 0x4 REFTOP_VBGADJ_5 VBG-1.56% 0x5 REFTOP_VBGADJ_6 VBG-2.34% 0x6 REFTOP_VBGADJ_7 VBG-3.12% 0x7 REFTOP_VBGUP Status bit that signals the analog bandgap voltage is up and stable 7 1 read-write STOP_MODE_CONFIG Configure the analog behavior in stop mode. 10 2 read-write STOP_MODE_CONFIG_0 All analog except RTC powered down on stop mode assertion. 0 STOP_MODE_CONFIG_1 Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. 0x1 STOP_MODE_CONFIG_2 Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. 0x2 STOP_MODE_CONFIG_3 Beside RTC, low-power bandgap is selected and the rest analog is powered down. 0x3 DISCON_HIGH_SNVS This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 12 1 read-write DISCON_HIGH_SNVS_0 Turn on the switch 0 DISCON_HIGH_SNVS_1 Turn off the switch 0x1 OSC_I This field determines the bias current in the 24MHz oscillator 13 2 read-write NOMINAL Nominal 0 MINUS_12_5_PERCENT Decrease current by 12.5% 0x1 MINUS_25_PERCENT Decrease current by 25.0% 0x2 MINUS_37_5_PERCENT Decrease current by 37.5% 0x3 OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable 15 1 read-only OSC_XTALOK_EN This bit enables the detector that signals when the 24MHz crystal oscillator is stable 16 1 read-write CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 25 1 read-write ALLOW_AUTO_GATE Allow the logic to automatically gate the clock when the XTAL is powered down. 0 NO_AUTO_GATE Prevent the logic from ever gating off the clock. 0x1 CLKGATE_DELAY This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 26 3 read-write CLKGATE_DELAY_0 0.5ms 0 CLKGATE_DELAY_1 1.0ms 0x1 CLKGATE_DELAY_2 2.0ms 0x2 CLKGATE_DELAY_3 3.0ms 0x3 CLKGATE_DELAY_4 4.0ms 0x4 CLKGATE_DELAY_5 5.0ms 0x5 CLKGATE_DELAY_6 6.0ms 0x6 CLKGATE_DELAY_7 7.0ms 0x7 RTC_XTAL_SOURCE This field indicates which chip source is being used for the rtc clock 29 1 read-write RTC_XTAL_SOURCE_0 Internal ring oscillator 0 RTC_XTAL_SOURCE_1 RTC_XTAL 0x1 XTAL_24M_PWD This field powers down the 24M crystal oscillator if set true 30 1 read-write MISC0_TOG Miscellaneous Register 0 0x15C 32 read-write 0x4000000 0xFFFFFFFF REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry 0 1 read-write REFTOP_SELFBIASOFF Control bit to disable the self-bias circuit in the analog bandgap 3 1 read-write REFTOP_SELFBIASOFF_0 Uses coarse bias currents for startup 0 REFTOP_SELFBIASOFF_1 Uses bandgap-based bias currents for best performance. 0x1 REFTOP_VBGADJ Not related to CCM. See Power Management Unit (PMU) 4 3 read-write REFTOP_VBGADJ_0 Nominal VBG 0 REFTOP_VBGADJ_1 VBG+0.78% 0x1 REFTOP_VBGADJ_2 VBG+1.56% 0x2 REFTOP_VBGADJ_3 VBG+2.34% 0x3 REFTOP_VBGADJ_4 VBG-0.78% 0x4 REFTOP_VBGADJ_5 VBG-1.56% 0x5 REFTOP_VBGADJ_6 VBG-2.34% 0x6 REFTOP_VBGADJ_7 VBG-3.12% 0x7 REFTOP_VBGUP Status bit that signals the analog bandgap voltage is up and stable 7 1 read-write STOP_MODE_CONFIG Configure the analog behavior in stop mode. 10 2 read-write STOP_MODE_CONFIG_0 All analog except RTC powered down on stop mode assertion. 0 STOP_MODE_CONFIG_1 Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. 0x1 STOP_MODE_CONFIG_2 Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. 0x2 STOP_MODE_CONFIG_3 Beside RTC, low-power bandgap is selected and the rest analog is powered down. 0x3 DISCON_HIGH_SNVS This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 12 1 read-write DISCON_HIGH_SNVS_0 Turn on the switch 0 DISCON_HIGH_SNVS_1 Turn off the switch 0x1 OSC_I This field determines the bias current in the 24MHz oscillator 13 2 read-write NOMINAL Nominal 0 MINUS_12_5_PERCENT Decrease current by 12.5% 0x1 MINUS_25_PERCENT Decrease current by 25.0% 0x2 MINUS_37_5_PERCENT Decrease current by 37.5% 0x3 OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable 15 1 read-only OSC_XTALOK_EN This bit enables the detector that signals when the 24MHz crystal oscillator is stable 16 1 read-write CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 25 1 read-write ALLOW_AUTO_GATE Allow the logic to automatically gate the clock when the XTAL is powered down. 0 NO_AUTO_GATE Prevent the logic from ever gating off the clock. 0x1 CLKGATE_DELAY This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 26 3 read-write CLKGATE_DELAY_0 0.5ms 0 CLKGATE_DELAY_1 1.0ms 0x1 CLKGATE_DELAY_2 2.0ms 0x2 CLKGATE_DELAY_3 3.0ms 0x3 CLKGATE_DELAY_4 4.0ms 0x4 CLKGATE_DELAY_5 5.0ms 0x5 CLKGATE_DELAY_6 6.0ms 0x6 CLKGATE_DELAY_7 7.0ms 0x7 RTC_XTAL_SOURCE This field indicates which chip source is being used for the rtc clock 29 1 read-write RTC_XTAL_SOURCE_0 Internal ring oscillator 0 RTC_XTAL_SOURCE_1 RTC_XTAL 0x1 XTAL_24M_PWD This field powers down the 24M crystal oscillator if set true 30 1 read-write MISC1 Miscellaneous Register 1 0x160 32 read-write 0 0xFFFFFFFF PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off 16 1 read-write PFD_528_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off 17 1 read-write IRQ_TEMPPANIC This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature 27 1 read-write oneToClear IRQ_TEMPLOW This status bit is set to one when the temperature sensor low interrupt asserts for low temperature 28 1 read-write oneToClear IRQ_TEMPHIGH This status bit is set to one when the temperature sensor high interrupt asserts for high temperature 29 1 read-write oneToClear IRQ_ANA_BO This status bit is set to one when when any of the analog regulator brownout interrupts assert 30 1 read-write oneToClear IRQ_DIG_BO This status bit is set to one when when any of the digital regulator brownout interrupts assert 31 1 read-write oneToClear MISC1_SET Miscellaneous Register 1 0x164 32 read-write 0 0xFFFFFFFF PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off 16 1 read-write PFD_528_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off 17 1 read-write IRQ_TEMPPANIC This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature 27 1 read-write oneToClear IRQ_TEMPLOW This status bit is set to one when the temperature sensor low interrupt asserts for low temperature 28 1 read-write oneToClear IRQ_TEMPHIGH This status bit is set to one when the temperature sensor high interrupt asserts for high temperature 29 1 read-write oneToClear IRQ_ANA_BO This status bit is set to one when when any of the analog regulator brownout interrupts assert 30 1 read-write oneToClear IRQ_DIG_BO This status bit is set to one when when any of the digital regulator brownout interrupts assert 31 1 read-write oneToClear MISC1_CLR Miscellaneous Register 1 0x168 32 read-write 0 0xFFFFFFFF PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off 16 1 read-write PFD_528_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off 17 1 read-write IRQ_TEMPPANIC This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature 27 1 read-write oneToClear IRQ_TEMPLOW This status bit is set to one when the temperature sensor low interrupt asserts for low temperature 28 1 read-write oneToClear IRQ_TEMPHIGH This status bit is set to one when the temperature sensor high interrupt asserts for high temperature 29 1 read-write oneToClear IRQ_ANA_BO This status bit is set to one when when any of the analog regulator brownout interrupts assert 30 1 read-write oneToClear IRQ_DIG_BO This status bit is set to one when when any of the digital regulator brownout interrupts assert 31 1 read-write oneToClear MISC1_TOG Miscellaneous Register 1 0x16C 32 read-write 0 0xFFFFFFFF PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off 16 1 read-write PFD_528_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off 17 1 read-write IRQ_TEMPPANIC This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature 27 1 read-write oneToClear IRQ_TEMPLOW This status bit is set to one when the temperature sensor low interrupt asserts for low temperature 28 1 read-write oneToClear IRQ_TEMPHIGH This status bit is set to one when the temperature sensor high interrupt asserts for high temperature 29 1 read-write oneToClear IRQ_ANA_BO This status bit is set to one when when any of the analog regulator brownout interrupts assert 30 1 read-write oneToClear IRQ_DIG_BO This status bit is set to one when when any of the digital regulator brownout interrupts assert 31 1 read-write oneToClear MISC2 Miscellaneous Register 2 0x170 32 read-write 0x272727 0xFFFFFFFF REG0_BO_OFFSET This field defines the brown out voltage offset for the CORE power domain 0 3 read-only REG0_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG0_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG0_BO_STATUS Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) 3 1 read-only REG0_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG0_ENABLE_BO Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) 5 1 read-write REG0_OK ARM supply Not related to CCM. See Power Management Unit (PMU) 6 1 read-only PLL3_DISABLE When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode 7 1 read-write PLL3_DISABLE_0 PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode 0 PLL3_DISABLE_1 PLL3 can be disabled when the SoC is not in any low power mode 0x1 REG1_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 8 3 read-only REG1_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG1_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG1_BO_STATUS Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) 11 1 read-only REG1_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG1_ENABLE_BO Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) 13 1 read-write REG1_OK GPU supply Not related to CCM. See Power Management Unit (PMU) 14 1 read-only AUDIO_DIV_LSB LSB of Post-divider for Audio PLL 15 1 read-write AUDIO_DIV_LSB_0 divide by 1 (Default) 0 AUDIO_DIV_LSB_1 divide by 2 0x1 REG2_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 16 3 read-only REG2_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG2_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG2_BO_STATUS Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) 19 1 read-only REG2_ENABLE_BO Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) 21 1 read-write REG2_OK Signals that the voltage is above the brownout level for the SOC supply 22 1 read-only AUDIO_DIV_MSB MSB of Post-divider for Audio PLL 23 1 read-write AUDIO_DIV_MSB_0 divide by 1 (Default) 0 AUDIO_DIV_MSB_1 divide by 2 0x1 REG0_STEP_TIME Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 24 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG1_STEP_TIME Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 26 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG2_STEP_TIME Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 28 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 MISC2_SET Miscellaneous Register 2 0x174 32 read-write 0x272727 0xFFFFFFFF REG0_BO_OFFSET This field defines the brown out voltage offset for the CORE power domain 0 3 read-only REG0_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG0_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG0_BO_STATUS Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) 3 1 read-only REG0_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG0_ENABLE_BO Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) 5 1 read-write REG0_OK ARM supply Not related to CCM. See Power Management Unit (PMU) 6 1 read-only PLL3_DISABLE When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode 7 1 read-write PLL3_DISABLE_0 PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode 0 PLL3_DISABLE_1 PLL3 can be disabled when the SoC is not in any low power mode 0x1 REG1_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 8 3 read-only REG1_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG1_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG1_BO_STATUS Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) 11 1 read-only REG1_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG1_ENABLE_BO Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) 13 1 read-write REG1_OK GPU supply Not related to CCM. See Power Management Unit (PMU) 14 1 read-only AUDIO_DIV_LSB LSB of Post-divider for Audio PLL 15 1 read-write AUDIO_DIV_LSB_0 divide by 1 (Default) 0 AUDIO_DIV_LSB_1 divide by 2 0x1 REG2_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 16 3 read-only REG2_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG2_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG2_BO_STATUS Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) 19 1 read-only REG2_ENABLE_BO Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) 21 1 read-write REG2_OK Signals that the voltage is above the brownout level for the SOC supply 22 1 read-only AUDIO_DIV_MSB MSB of Post-divider for Audio PLL 23 1 read-write AUDIO_DIV_MSB_0 divide by 1 (Default) 0 AUDIO_DIV_MSB_1 divide by 2 0x1 REG0_STEP_TIME Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 24 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG1_STEP_TIME Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 26 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG2_STEP_TIME Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 28 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 MISC2_CLR Miscellaneous Register 2 0x178 32 read-write 0x272727 0xFFFFFFFF REG0_BO_OFFSET This field defines the brown out voltage offset for the CORE power domain 0 3 read-only REG0_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG0_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG0_BO_STATUS Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) 3 1 read-only REG0_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG0_ENABLE_BO Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) 5 1 read-write REG0_OK ARM supply Not related to CCM. See Power Management Unit (PMU) 6 1 read-only PLL3_DISABLE When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode 7 1 read-write PLL3_DISABLE_0 PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode 0 PLL3_DISABLE_1 PLL3 can be disabled when the SoC is not in any low power mode 0x1 REG1_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 8 3 read-only REG1_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG1_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG1_BO_STATUS Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) 11 1 read-only REG1_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG1_ENABLE_BO Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) 13 1 read-write REG1_OK GPU supply Not related to CCM. See Power Management Unit (PMU) 14 1 read-only AUDIO_DIV_LSB LSB of Post-divider for Audio PLL 15 1 read-write AUDIO_DIV_LSB_0 divide by 1 (Default) 0 AUDIO_DIV_LSB_1 divide by 2 0x1 REG2_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 16 3 read-only REG2_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG2_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG2_BO_STATUS Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) 19 1 read-only REG2_ENABLE_BO Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) 21 1 read-write REG2_OK Signals that the voltage is above the brownout level for the SOC supply 22 1 read-only AUDIO_DIV_MSB MSB of Post-divider for Audio PLL 23 1 read-write AUDIO_DIV_MSB_0 divide by 1 (Default) 0 AUDIO_DIV_MSB_1 divide by 2 0x1 REG0_STEP_TIME Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 24 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG1_STEP_TIME Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 26 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG2_STEP_TIME Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 28 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 MISC2_TOG Miscellaneous Register 2 0x17C 32 read-write 0x272727 0xFFFFFFFF REG0_BO_OFFSET This field defines the brown out voltage offset for the CORE power domain 0 3 read-only REG0_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG0_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG0_BO_STATUS Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) 3 1 read-only REG0_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG0_ENABLE_BO Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) 5 1 read-write REG0_OK ARM supply Not related to CCM. See Power Management Unit (PMU) 6 1 read-only PLL3_DISABLE When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode 7 1 read-write PLL3_DISABLE_0 PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode 0 PLL3_DISABLE_1 PLL3 can be disabled when the SoC is not in any low power mode 0x1 REG1_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 8 3 read-only REG1_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG1_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG1_BO_STATUS Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) 11 1 read-only REG1_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG1_ENABLE_BO Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) 13 1 read-write REG1_OK GPU supply Not related to CCM. See Power Management Unit (PMU) 14 1 read-only AUDIO_DIV_LSB LSB of Post-divider for Audio PLL 15 1 read-write AUDIO_DIV_LSB_0 divide by 1 (Default) 0 AUDIO_DIV_LSB_1 divide by 2 0x1 REG2_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 16 3 read-only REG2_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG2_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG2_BO_STATUS Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) 19 1 read-only REG2_ENABLE_BO Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) 21 1 read-write REG2_OK Signals that the voltage is above the brownout level for the SOC supply 22 1 read-only AUDIO_DIV_MSB MSB of Post-divider for Audio PLL 23 1 read-write AUDIO_DIV_MSB_0 divide by 1 (Default) 0 AUDIO_DIV_MSB_1 divide by 2 0x1 REG0_STEP_TIME Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 24 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG1_STEP_TIME Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 26 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG2_STEP_TIME Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 28 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 PMU PMU CCM_ANALOG PMU PMU_ 0x400D8000 0 0x180 registers PMU 61 REG_1P1 Regulator 1P1 Register 0x110 32 read-write 0x1073 0xFFFFFFFF ENABLE_LINREG Control bit to enable the regulator output. 0 1 read-write ENABLE_BO Control bit to enable the brownout circuitry in the regulator. 1 1 read-write ENABLE_ILIMIT Control bit to enable the current-limit circuitry in the regulator. 2 1 read-write ENABLE_PULLDOWN Control bit to enable the pull-down circuitry in the regulator 3 1 read-write BO_OFFSET Control bits to adjust the regulator brownout offset voltage in 25mV steps 4 3 read-write OUTPUT_TRG Control bits to adjust the regulator output voltage 8 5 read-write OUTPUT_TRG_4 0.8V 0x4 OUTPUT_TRG_16 1.1V 0x10 BO_VDD1P1 Status bit that signals when a brownout is detected on the regulator output. 16 1 read-only OK_VDD1P1 Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target 17 1 read-only ENABLE_WEAK_LINREG Enables the weak 1p1 regulator 18 1 read-write SELREF_WEAK_LINREG Selects the source for the reference voltage of the weak 1p1 regulator. 19 1 read-write SELREF_WEAK_LINREG_0 Weak-linreg output tracks low-power-bandgap voltage 0 SELREF_WEAK_LINREG_1 Weak-linreg output tracks VDD_SOC_IN voltage 0x1 REG_1P1_SET Regulator 1P1 Register 0x114 32 read-write 0x1073 0xFFFFFFFF ENABLE_LINREG Control bit to enable the regulator output. 0 1 read-write ENABLE_BO Control bit to enable the brownout circuitry in the regulator. 1 1 read-write ENABLE_ILIMIT Control bit to enable the current-limit circuitry in the regulator. 2 1 read-write ENABLE_PULLDOWN Control bit to enable the pull-down circuitry in the regulator 3 1 read-write BO_OFFSET Control bits to adjust the regulator brownout offset voltage in 25mV steps 4 3 read-write OUTPUT_TRG Control bits to adjust the regulator output voltage 8 5 read-write OUTPUT_TRG_4 0.8V 0x4 OUTPUT_TRG_16 1.1V 0x10 BO_VDD1P1 Status bit that signals when a brownout is detected on the regulator output. 16 1 read-only OK_VDD1P1 Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target 17 1 read-only ENABLE_WEAK_LINREG Enables the weak 1p1 regulator 18 1 read-write SELREF_WEAK_LINREG Selects the source for the reference voltage of the weak 1p1 regulator. 19 1 read-write SELREF_WEAK_LINREG_0 Weak-linreg output tracks low-power-bandgap voltage 0 SELREF_WEAK_LINREG_1 Weak-linreg output tracks VDD_SOC_IN voltage 0x1 REG_1P1_CLR Regulator 1P1 Register 0x118 32 read-write 0x1073 0xFFFFFFFF ENABLE_LINREG Control bit to enable the regulator output. 0 1 read-write ENABLE_BO Control bit to enable the brownout circuitry in the regulator. 1 1 read-write ENABLE_ILIMIT Control bit to enable the current-limit circuitry in the regulator. 2 1 read-write ENABLE_PULLDOWN Control bit to enable the pull-down circuitry in the regulator 3 1 read-write BO_OFFSET Control bits to adjust the regulator brownout offset voltage in 25mV steps 4 3 read-write OUTPUT_TRG Control bits to adjust the regulator output voltage 8 5 read-write OUTPUT_TRG_4 0.8V 0x4 OUTPUT_TRG_16 1.1V 0x10 BO_VDD1P1 Status bit that signals when a brownout is detected on the regulator output. 16 1 read-only OK_VDD1P1 Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target 17 1 read-only ENABLE_WEAK_LINREG Enables the weak 1p1 regulator 18 1 read-write SELREF_WEAK_LINREG Selects the source for the reference voltage of the weak 1p1 regulator. 19 1 read-write SELREF_WEAK_LINREG_0 Weak-linreg output tracks low-power-bandgap voltage 0 SELREF_WEAK_LINREG_1 Weak-linreg output tracks VDD_SOC_IN voltage 0x1 REG_1P1_TOG Regulator 1P1 Register 0x11C 32 read-write 0x1073 0xFFFFFFFF ENABLE_LINREG Control bit to enable the regulator output. 0 1 read-write ENABLE_BO Control bit to enable the brownout circuitry in the regulator. 1 1 read-write ENABLE_ILIMIT Control bit to enable the current-limit circuitry in the regulator. 2 1 read-write ENABLE_PULLDOWN Control bit to enable the pull-down circuitry in the regulator 3 1 read-write BO_OFFSET Control bits to adjust the regulator brownout offset voltage in 25mV steps 4 3 read-write OUTPUT_TRG Control bits to adjust the regulator output voltage 8 5 read-write OUTPUT_TRG_4 0.8V 0x4 OUTPUT_TRG_16 1.1V 0x10 BO_VDD1P1 Status bit that signals when a brownout is detected on the regulator output. 16 1 read-only OK_VDD1P1 Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target 17 1 read-only ENABLE_WEAK_LINREG Enables the weak 1p1 regulator 18 1 read-write SELREF_WEAK_LINREG Selects the source for the reference voltage of the weak 1p1 regulator. 19 1 read-write SELREF_WEAK_LINREG_0 Weak-linreg output tracks low-power-bandgap voltage 0 SELREF_WEAK_LINREG_1 Weak-linreg output tracks VDD_SOC_IN voltage 0x1 REG_3P0 Regulator 3P0 Register 0x120 32 read-write 0xF74 0xFFFFFFFF ENABLE_LINREG Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference 0 1 read-write ENABLE_BO Control bit to enable the brownout circuitry in the regulator. 1 1 read-write ENABLE_ILIMIT Control bit to enable the current-limit circuitry in the regulator. 2 1 read-write BO_OFFSET Control bits to adjust the regulator brownout offset voltage in 25mV steps 4 3 read-write VBUS_SEL Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS 7 1 read-write USB_OTG2_VBUS Utilize VBUS OTG2 power 0 USB_OTG1_VBUS Utilize VBUS OTG1 power 0x1 OUTPUT_TRG Control bits to adjust the regulator output voltage 8 5 read-write OUTPUT_TRG_0 2.625V 0 OUTPUT_TRG_15 3.000V 0xF OUTPUT_TRG_31 3.400V 0x1F BO_VDD3P0 Status bit that signals when a brownout is detected on the regulator output. 16 1 read-only OK_VDD3P0 Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target 17 1 read-only REG_3P0_SET Regulator 3P0 Register 0x124 32 read-write 0xF74 0xFFFFFFFF ENABLE_LINREG Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference 0 1 read-write ENABLE_BO Control bit to enable the brownout circuitry in the regulator. 1 1 read-write ENABLE_ILIMIT Control bit to enable the current-limit circuitry in the regulator. 2 1 read-write BO_OFFSET Control bits to adjust the regulator brownout offset voltage in 25mV steps 4 3 read-write VBUS_SEL Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS 7 1 read-write USB_OTG2_VBUS Utilize VBUS OTG2 power 0 USB_OTG1_VBUS Utilize VBUS OTG1 power 0x1 OUTPUT_TRG Control bits to adjust the regulator output voltage 8 5 read-write OUTPUT_TRG_0 2.625V 0 OUTPUT_TRG_15 3.000V 0xF OUTPUT_TRG_31 3.400V 0x1F BO_VDD3P0 Status bit that signals when a brownout is detected on the regulator output. 16 1 read-only OK_VDD3P0 Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target 17 1 read-only REG_3P0_CLR Regulator 3P0 Register 0x128 32 read-write 0xF74 0xFFFFFFFF ENABLE_LINREG Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference 0 1 read-write ENABLE_BO Control bit to enable the brownout circuitry in the regulator. 1 1 read-write ENABLE_ILIMIT Control bit to enable the current-limit circuitry in the regulator. 2 1 read-write BO_OFFSET Control bits to adjust the regulator brownout offset voltage in 25mV steps 4 3 read-write VBUS_SEL Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS 7 1 read-write USB_OTG2_VBUS Utilize VBUS OTG2 power 0 USB_OTG1_VBUS Utilize VBUS OTG1 power 0x1 OUTPUT_TRG Control bits to adjust the regulator output voltage 8 5 read-write OUTPUT_TRG_0 2.625V 0 OUTPUT_TRG_15 3.000V 0xF OUTPUT_TRG_31 3.400V 0x1F BO_VDD3P0 Status bit that signals when a brownout is detected on the regulator output. 16 1 read-only OK_VDD3P0 Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target 17 1 read-only REG_3P0_TOG Regulator 3P0 Register 0x12C 32 read-write 0xF74 0xFFFFFFFF ENABLE_LINREG Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference 0 1 read-write ENABLE_BO Control bit to enable the brownout circuitry in the regulator. 1 1 read-write ENABLE_ILIMIT Control bit to enable the current-limit circuitry in the regulator. 2 1 read-write BO_OFFSET Control bits to adjust the regulator brownout offset voltage in 25mV steps 4 3 read-write VBUS_SEL Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS 7 1 read-write USB_OTG2_VBUS Utilize VBUS OTG2 power 0 USB_OTG1_VBUS Utilize VBUS OTG1 power 0x1 OUTPUT_TRG Control bits to adjust the regulator output voltage 8 5 read-write OUTPUT_TRG_0 2.625V 0 OUTPUT_TRG_15 3.000V 0xF OUTPUT_TRG_31 3.400V 0x1F BO_VDD3P0 Status bit that signals when a brownout is detected on the regulator output. 16 1 read-only OK_VDD3P0 Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target 17 1 read-only REG_2P5 Regulator 2P5 Register 0x130 32 read-write 0x1073 0xFFFFFFFF ENABLE_LINREG Control bit to enable the regulator output. 0 1 read-write ENABLE_BO Control bit to enable the brownout circuitry in the regulator. 1 1 read-write ENABLE_ILIMIT Control bit to enable the current-limit circuitry in the regulator. 2 1 read-write ENABLE_PULLDOWN Control bit to enable the pull-down circuitry in the regulator 3 1 read-write BO_OFFSET Control bits to adjust the regulator brownout offset voltage in 25mV steps 4 3 read-write OUTPUT_TRG Control bits to adjust the regulator output voltage 8 5 read-write OUTPUT_TRG_0 2.10V 0 OUTPUT_TRG_16 2.50V 0x10 OUTPUT_TRG_31 2.875V 0x1F BO_VDD2P5 Status bit that signals when a brownout is detected on the regulator output. 16 1 read-only OK_VDD2P5 Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target 17 1 read-only ENABLE_WEAK_LINREG Enables the weak 2p5 regulator 18 1 read-write REG_2P5_SET Regulator 2P5 Register 0x134 32 read-write 0x1073 0xFFFFFFFF ENABLE_LINREG Control bit to enable the regulator output. 0 1 read-write ENABLE_BO Control bit to enable the brownout circuitry in the regulator. 1 1 read-write ENABLE_ILIMIT Control bit to enable the current-limit circuitry in the regulator. 2 1 read-write ENABLE_PULLDOWN Control bit to enable the pull-down circuitry in the regulator 3 1 read-write BO_OFFSET Control bits to adjust the regulator brownout offset voltage in 25mV steps 4 3 read-write OUTPUT_TRG Control bits to adjust the regulator output voltage 8 5 read-write OUTPUT_TRG_0 2.10V 0 OUTPUT_TRG_16 2.50V 0x10 OUTPUT_TRG_31 2.875V 0x1F BO_VDD2P5 Status bit that signals when a brownout is detected on the regulator output. 16 1 read-only OK_VDD2P5 Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target 17 1 read-only ENABLE_WEAK_LINREG Enables the weak 2p5 regulator 18 1 read-write REG_2P5_CLR Regulator 2P5 Register 0x138 32 read-write 0x1073 0xFFFFFFFF ENABLE_LINREG Control bit to enable the regulator output. 0 1 read-write ENABLE_BO Control bit to enable the brownout circuitry in the regulator. 1 1 read-write ENABLE_ILIMIT Control bit to enable the current-limit circuitry in the regulator. 2 1 read-write ENABLE_PULLDOWN Control bit to enable the pull-down circuitry in the regulator 3 1 read-write BO_OFFSET Control bits to adjust the regulator brownout offset voltage in 25mV steps 4 3 read-write OUTPUT_TRG Control bits to adjust the regulator output voltage 8 5 read-write OUTPUT_TRG_0 2.10V 0 OUTPUT_TRG_16 2.50V 0x10 OUTPUT_TRG_31 2.875V 0x1F BO_VDD2P5 Status bit that signals when a brownout is detected on the regulator output. 16 1 read-only OK_VDD2P5 Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target 17 1 read-only ENABLE_WEAK_LINREG Enables the weak 2p5 regulator 18 1 read-write REG_2P5_TOG Regulator 2P5 Register 0x13C 32 read-write 0x1073 0xFFFFFFFF ENABLE_LINREG Control bit to enable the regulator output. 0 1 read-write ENABLE_BO Control bit to enable the brownout circuitry in the regulator. 1 1 read-write ENABLE_ILIMIT Control bit to enable the current-limit circuitry in the regulator. 2 1 read-write ENABLE_PULLDOWN Control bit to enable the pull-down circuitry in the regulator 3 1 read-write BO_OFFSET Control bits to adjust the regulator brownout offset voltage in 25mV steps 4 3 read-write OUTPUT_TRG Control bits to adjust the regulator output voltage 8 5 read-write OUTPUT_TRG_0 2.10V 0 OUTPUT_TRG_16 2.50V 0x10 OUTPUT_TRG_31 2.875V 0x1F BO_VDD2P5 Status bit that signals when a brownout is detected on the regulator output. 16 1 read-only OK_VDD2P5 Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target 17 1 read-only ENABLE_WEAK_LINREG Enables the weak 2p5 regulator 18 1 read-write REG_CORE Digital Regulator Core Register 0x140 32 read-write 0x482012 0xFFFFFFFF REG0_TARG This field defines the target voltage for the ARM core power domain 0 5 read-write REG0_TARG_0 Power gated off 0 REG0_TARG_1 Target core voltage = 0.725V 0x1 REG0_TARG_2 Target core voltage = 0.750V 0x2 REG0_TARG_3 Target core voltage = 0.775V 0x3 REG0_TARG_16 Target core voltage = 1.100V 0x10 REG0_TARG_30 Target core voltage = 1.450V 0x1E REG0_TARG_31 Power FET switched full on. No regulation. 0x1F REG0_ADJ This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 5 4 read-write REG0_ADJ_0 No adjustment 0 REG0_ADJ_1 + 0.25% 0x1 REG0_ADJ_2 + 0.50% 0x2 REG0_ADJ_3 + 0.75% 0x3 REG0_ADJ_4 + 1.00% 0x4 REG0_ADJ_5 + 1.25% 0x5 REG0_ADJ_6 + 1.50% 0x6 REG0_ADJ_7 + 1.75% 0x7 REG0_ADJ_8 - 0.25% 0x8 REG0_ADJ_9 - 0.50% 0x9 REG0_ADJ_10 - 0.75% 0xA REG0_ADJ_11 - 1.00% 0xB REG0_ADJ_12 - 1.25% 0xC REG0_ADJ_13 - 1.50% 0xD REG0_ADJ_14 - 1.75% 0xE REG0_ADJ_15 - 2.00% 0xF REG1_TARG This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 9 5 read-write REG1_TARG_0 Power gated off 0 REG1_TARG_1 Target core voltage = 0.725V 0x1 REG1_TARG_2 Target core voltage = 0.750V 0x2 REG1_TARG_3 Target core voltage = 0.775V 0x3 REG1_TARG_16 Target core voltage = 1.100V 0x10 REG1_TARG_30 Target core voltage = 1.450V 0x1E REG1_TARG_31 Power FET switched full on. No regulation. 0x1F REG1_ADJ This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 14 4 read-write REG1_ADJ_0 No adjustment 0 REG1_ADJ_1 + 0.25% 0x1 REG1_ADJ_2 + 0.50% 0x2 REG1_ADJ_3 + 0.75% 0x3 REG1_ADJ_4 + 1.00% 0x4 REG1_ADJ_5 + 1.25% 0x5 REG1_ADJ_6 + 1.50% 0x6 REG1_ADJ_7 + 1.75% 0x7 REG1_ADJ_8 - 0.25% 0x8 REG1_ADJ_9 - 0.50% 0x9 REG1_ADJ_10 - 0.75% 0xA REG1_ADJ_11 - 1.00% 0xB REG1_ADJ_12 - 1.25% 0xC REG1_ADJ_13 - 1.50% 0xD REG1_ADJ_14 - 1.75% 0xE REG1_ADJ_15 - 2.00% 0xF REG2_TARG This field defines the target voltage for the SOC power domain 18 5 read-write REG2_TARG_0 Power gated off 0 REG2_TARG_1 Target core voltage = 0.725V 0x1 REG2_TARG_2 Target core voltage = 0.750V 0x2 REG2_TARG_3 Target core voltage = 0.775V 0x3 REG2_TARG_16 Target core voltage = 1.100V 0x10 REG2_TARG_30 Target core voltage = 1.450V 0x1E REG2_TARG_31 Power FET switched full on. No regulation. 0x1F REG2_ADJ This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 23 4 read-write REG2_ADJ_0 No adjustment 0 REG2_ADJ_1 + 0.25% 0x1 REG2_ADJ_2 + 0.50% 0x2 REG2_ADJ_3 + 0.75% 0x3 REG2_ADJ_4 + 1.00% 0x4 REG2_ADJ_5 + 1.25% 0x5 REG2_ADJ_6 + 1.50% 0x6 REG2_ADJ_7 + 1.75% 0x7 REG2_ADJ_8 - 0.25% 0x8 REG2_ADJ_9 - 0.50% 0x9 REG2_ADJ_10 - 0.75% 0xA REG2_ADJ_11 - 1.00% 0xB REG2_ADJ_12 - 1.25% 0xC REG2_ADJ_13 - 1.50% 0xD REG2_ADJ_14 - 1.75% 0xE REG2_ADJ_15 - 2.00% 0xF RAMP_RATE Regulator voltage ramp rate. 27 2 read-write RAMP_RATE_0 Fast 0 RAMP_RATE_1 Medium Fast 0x1 RAMP_RATE_2 Medium Slow 0x2 RAMP_RATE_3 Slow 0x3 FET_ODRIVE If set, increases the gate drive on power gating FETs to reduce leakage in the off state 29 1 read-write REG_CORE_SET Digital Regulator Core Register 0x144 32 read-write 0x482012 0xFFFFFFFF REG0_TARG This field defines the target voltage for the ARM core power domain 0 5 read-write REG0_TARG_0 Power gated off 0 REG0_TARG_1 Target core voltage = 0.725V 0x1 REG0_TARG_2 Target core voltage = 0.750V 0x2 REG0_TARG_3 Target core voltage = 0.775V 0x3 REG0_TARG_16 Target core voltage = 1.100V 0x10 REG0_TARG_30 Target core voltage = 1.450V 0x1E REG0_TARG_31 Power FET switched full on. No regulation. 0x1F REG0_ADJ This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 5 4 read-write REG0_ADJ_0 No adjustment 0 REG0_ADJ_1 + 0.25% 0x1 REG0_ADJ_2 + 0.50% 0x2 REG0_ADJ_3 + 0.75% 0x3 REG0_ADJ_4 + 1.00% 0x4 REG0_ADJ_5 + 1.25% 0x5 REG0_ADJ_6 + 1.50% 0x6 REG0_ADJ_7 + 1.75% 0x7 REG0_ADJ_8 - 0.25% 0x8 REG0_ADJ_9 - 0.50% 0x9 REG0_ADJ_10 - 0.75% 0xA REG0_ADJ_11 - 1.00% 0xB REG0_ADJ_12 - 1.25% 0xC REG0_ADJ_13 - 1.50% 0xD REG0_ADJ_14 - 1.75% 0xE REG0_ADJ_15 - 2.00% 0xF REG1_TARG This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 9 5 read-write REG1_TARG_0 Power gated off 0 REG1_TARG_1 Target core voltage = 0.725V 0x1 REG1_TARG_2 Target core voltage = 0.750V 0x2 REG1_TARG_3 Target core voltage = 0.775V 0x3 REG1_TARG_16 Target core voltage = 1.100V 0x10 REG1_TARG_30 Target core voltage = 1.450V 0x1E REG1_TARG_31 Power FET switched full on. No regulation. 0x1F REG1_ADJ This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 14 4 read-write REG1_ADJ_0 No adjustment 0 REG1_ADJ_1 + 0.25% 0x1 REG1_ADJ_2 + 0.50% 0x2 REG1_ADJ_3 + 0.75% 0x3 REG1_ADJ_4 + 1.00% 0x4 REG1_ADJ_5 + 1.25% 0x5 REG1_ADJ_6 + 1.50% 0x6 REG1_ADJ_7 + 1.75% 0x7 REG1_ADJ_8 - 0.25% 0x8 REG1_ADJ_9 - 0.50% 0x9 REG1_ADJ_10 - 0.75% 0xA REG1_ADJ_11 - 1.00% 0xB REG1_ADJ_12 - 1.25% 0xC REG1_ADJ_13 - 1.50% 0xD REG1_ADJ_14 - 1.75% 0xE REG1_ADJ_15 - 2.00% 0xF REG2_TARG This field defines the target voltage for the SOC power domain 18 5 read-write REG2_TARG_0 Power gated off 0 REG2_TARG_1 Target core voltage = 0.725V 0x1 REG2_TARG_2 Target core voltage = 0.750V 0x2 REG2_TARG_3 Target core voltage = 0.775V 0x3 REG2_TARG_16 Target core voltage = 1.100V 0x10 REG2_TARG_30 Target core voltage = 1.450V 0x1E REG2_TARG_31 Power FET switched full on. No regulation. 0x1F REG2_ADJ This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 23 4 read-write REG2_ADJ_0 No adjustment 0 REG2_ADJ_1 + 0.25% 0x1 REG2_ADJ_2 + 0.50% 0x2 REG2_ADJ_3 + 0.75% 0x3 REG2_ADJ_4 + 1.00% 0x4 REG2_ADJ_5 + 1.25% 0x5 REG2_ADJ_6 + 1.50% 0x6 REG2_ADJ_7 + 1.75% 0x7 REG2_ADJ_8 - 0.25% 0x8 REG2_ADJ_9 - 0.50% 0x9 REG2_ADJ_10 - 0.75% 0xA REG2_ADJ_11 - 1.00% 0xB REG2_ADJ_12 - 1.25% 0xC REG2_ADJ_13 - 1.50% 0xD REG2_ADJ_14 - 1.75% 0xE REG2_ADJ_15 - 2.00% 0xF RAMP_RATE Regulator voltage ramp rate. 27 2 read-write RAMP_RATE_0 Fast 0 RAMP_RATE_1 Medium Fast 0x1 RAMP_RATE_2 Medium Slow 0x2 RAMP_RATE_3 Slow 0x3 FET_ODRIVE If set, increases the gate drive on power gating FETs to reduce leakage in the off state 29 1 read-write REG_CORE_CLR Digital Regulator Core Register 0x148 32 read-write 0x482012 0xFFFFFFFF REG0_TARG This field defines the target voltage for the ARM core power domain 0 5 read-write REG0_TARG_0 Power gated off 0 REG0_TARG_1 Target core voltage = 0.725V 0x1 REG0_TARG_2 Target core voltage = 0.750V 0x2 REG0_TARG_3 Target core voltage = 0.775V 0x3 REG0_TARG_16 Target core voltage = 1.100V 0x10 REG0_TARG_30 Target core voltage = 1.450V 0x1E REG0_TARG_31 Power FET switched full on. No regulation. 0x1F REG0_ADJ This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 5 4 read-write REG0_ADJ_0 No adjustment 0 REG0_ADJ_1 + 0.25% 0x1 REG0_ADJ_2 + 0.50% 0x2 REG0_ADJ_3 + 0.75% 0x3 REG0_ADJ_4 + 1.00% 0x4 REG0_ADJ_5 + 1.25% 0x5 REG0_ADJ_6 + 1.50% 0x6 REG0_ADJ_7 + 1.75% 0x7 REG0_ADJ_8 - 0.25% 0x8 REG0_ADJ_9 - 0.50% 0x9 REG0_ADJ_10 - 0.75% 0xA REG0_ADJ_11 - 1.00% 0xB REG0_ADJ_12 - 1.25% 0xC REG0_ADJ_13 - 1.50% 0xD REG0_ADJ_14 - 1.75% 0xE REG0_ADJ_15 - 2.00% 0xF REG1_TARG This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 9 5 read-write REG1_TARG_0 Power gated off 0 REG1_TARG_1 Target core voltage = 0.725V 0x1 REG1_TARG_2 Target core voltage = 0.750V 0x2 REG1_TARG_3 Target core voltage = 0.775V 0x3 REG1_TARG_16 Target core voltage = 1.100V 0x10 REG1_TARG_30 Target core voltage = 1.450V 0x1E REG1_TARG_31 Power FET switched full on. No regulation. 0x1F REG1_ADJ This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 14 4 read-write REG1_ADJ_0 No adjustment 0 REG1_ADJ_1 + 0.25% 0x1 REG1_ADJ_2 + 0.50% 0x2 REG1_ADJ_3 + 0.75% 0x3 REG1_ADJ_4 + 1.00% 0x4 REG1_ADJ_5 + 1.25% 0x5 REG1_ADJ_6 + 1.50% 0x6 REG1_ADJ_7 + 1.75% 0x7 REG1_ADJ_8 - 0.25% 0x8 REG1_ADJ_9 - 0.50% 0x9 REG1_ADJ_10 - 0.75% 0xA REG1_ADJ_11 - 1.00% 0xB REG1_ADJ_12 - 1.25% 0xC REG1_ADJ_13 - 1.50% 0xD REG1_ADJ_14 - 1.75% 0xE REG1_ADJ_15 - 2.00% 0xF REG2_TARG This field defines the target voltage for the SOC power domain 18 5 read-write REG2_TARG_0 Power gated off 0 REG2_TARG_1 Target core voltage = 0.725V 0x1 REG2_TARG_2 Target core voltage = 0.750V 0x2 REG2_TARG_3 Target core voltage = 0.775V 0x3 REG2_TARG_16 Target core voltage = 1.100V 0x10 REG2_TARG_30 Target core voltage = 1.450V 0x1E REG2_TARG_31 Power FET switched full on. No regulation. 0x1F REG2_ADJ This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 23 4 read-write REG2_ADJ_0 No adjustment 0 REG2_ADJ_1 + 0.25% 0x1 REG2_ADJ_2 + 0.50% 0x2 REG2_ADJ_3 + 0.75% 0x3 REG2_ADJ_4 + 1.00% 0x4 REG2_ADJ_5 + 1.25% 0x5 REG2_ADJ_6 + 1.50% 0x6 REG2_ADJ_7 + 1.75% 0x7 REG2_ADJ_8 - 0.25% 0x8 REG2_ADJ_9 - 0.50% 0x9 REG2_ADJ_10 - 0.75% 0xA REG2_ADJ_11 - 1.00% 0xB REG2_ADJ_12 - 1.25% 0xC REG2_ADJ_13 - 1.50% 0xD REG2_ADJ_14 - 1.75% 0xE REG2_ADJ_15 - 2.00% 0xF RAMP_RATE Regulator voltage ramp rate. 27 2 read-write RAMP_RATE_0 Fast 0 RAMP_RATE_1 Medium Fast 0x1 RAMP_RATE_2 Medium Slow 0x2 RAMP_RATE_3 Slow 0x3 FET_ODRIVE If set, increases the gate drive on power gating FETs to reduce leakage in the off state 29 1 read-write REG_CORE_TOG Digital Regulator Core Register 0x14C 32 read-write 0x482012 0xFFFFFFFF REG0_TARG This field defines the target voltage for the ARM core power domain 0 5 read-write REG0_TARG_0 Power gated off 0 REG0_TARG_1 Target core voltage = 0.725V 0x1 REG0_TARG_2 Target core voltage = 0.750V 0x2 REG0_TARG_3 Target core voltage = 0.775V 0x3 REG0_TARG_16 Target core voltage = 1.100V 0x10 REG0_TARG_30 Target core voltage = 1.450V 0x1E REG0_TARG_31 Power FET switched full on. No regulation. 0x1F REG0_ADJ This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 5 4 read-write REG0_ADJ_0 No adjustment 0 REG0_ADJ_1 + 0.25% 0x1 REG0_ADJ_2 + 0.50% 0x2 REG0_ADJ_3 + 0.75% 0x3 REG0_ADJ_4 + 1.00% 0x4 REG0_ADJ_5 + 1.25% 0x5 REG0_ADJ_6 + 1.50% 0x6 REG0_ADJ_7 + 1.75% 0x7 REG0_ADJ_8 - 0.25% 0x8 REG0_ADJ_9 - 0.50% 0x9 REG0_ADJ_10 - 0.75% 0xA REG0_ADJ_11 - 1.00% 0xB REG0_ADJ_12 - 1.25% 0xC REG0_ADJ_13 - 1.50% 0xD REG0_ADJ_14 - 1.75% 0xE REG0_ADJ_15 - 2.00% 0xF REG1_TARG This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 9 5 read-write REG1_TARG_0 Power gated off 0 REG1_TARG_1 Target core voltage = 0.725V 0x1 REG1_TARG_2 Target core voltage = 0.750V 0x2 REG1_TARG_3 Target core voltage = 0.775V 0x3 REG1_TARG_16 Target core voltage = 1.100V 0x10 REG1_TARG_30 Target core voltage = 1.450V 0x1E REG1_TARG_31 Power FET switched full on. No regulation. 0x1F REG1_ADJ This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 14 4 read-write REG1_ADJ_0 No adjustment 0 REG1_ADJ_1 + 0.25% 0x1 REG1_ADJ_2 + 0.50% 0x2 REG1_ADJ_3 + 0.75% 0x3 REG1_ADJ_4 + 1.00% 0x4 REG1_ADJ_5 + 1.25% 0x5 REG1_ADJ_6 + 1.50% 0x6 REG1_ADJ_7 + 1.75% 0x7 REG1_ADJ_8 - 0.25% 0x8 REG1_ADJ_9 - 0.50% 0x9 REG1_ADJ_10 - 0.75% 0xA REG1_ADJ_11 - 1.00% 0xB REG1_ADJ_12 - 1.25% 0xC REG1_ADJ_13 - 1.50% 0xD REG1_ADJ_14 - 1.75% 0xE REG1_ADJ_15 - 2.00% 0xF REG2_TARG This field defines the target voltage for the SOC power domain 18 5 read-write REG2_TARG_0 Power gated off 0 REG2_TARG_1 Target core voltage = 0.725V 0x1 REG2_TARG_2 Target core voltage = 0.750V 0x2 REG2_TARG_3 Target core voltage = 0.775V 0x3 REG2_TARG_16 Target core voltage = 1.100V 0x10 REG2_TARG_30 Target core voltage = 1.450V 0x1E REG2_TARG_31 Power FET switched full on. No regulation. 0x1F REG2_ADJ This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 23 4 read-write REG2_ADJ_0 No adjustment 0 REG2_ADJ_1 + 0.25% 0x1 REG2_ADJ_2 + 0.50% 0x2 REG2_ADJ_3 + 0.75% 0x3 REG2_ADJ_4 + 1.00% 0x4 REG2_ADJ_5 + 1.25% 0x5 REG2_ADJ_6 + 1.50% 0x6 REG2_ADJ_7 + 1.75% 0x7 REG2_ADJ_8 - 0.25% 0x8 REG2_ADJ_9 - 0.50% 0x9 REG2_ADJ_10 - 0.75% 0xA REG2_ADJ_11 - 1.00% 0xB REG2_ADJ_12 - 1.25% 0xC REG2_ADJ_13 - 1.50% 0xD REG2_ADJ_14 - 1.75% 0xE REG2_ADJ_15 - 2.00% 0xF RAMP_RATE Regulator voltage ramp rate. 27 2 read-write RAMP_RATE_0 Fast 0 RAMP_RATE_1 Medium Fast 0x1 RAMP_RATE_2 Medium Slow 0x2 RAMP_RATE_3 Slow 0x3 FET_ODRIVE If set, increases the gate drive on power gating FETs to reduce leakage in the off state 29 1 read-write MISC0 Miscellaneous Register 0 0x150 32 read-write 0x4000000 0xFFFFFFFF REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry 0 1 read-write REFTOP_PWDVBGUP Control bit to power down the VBG-up detection circuitry in the analog bandgap. 1 1 read-write REFTOP_LOWPOWER Control bit to enable the low-power mode in the analog bandgap. 2 1 read-write REFTOP_SELFBIASOFF Control bit to disable the self-bias circuit in the analog bandgap 3 1 read-write REFTOP_SELFBIASOFF_0 Uses coarse bias currents for startup 0 REFTOP_SELFBIASOFF_1 Uses bandgap-based bias currents for best performance. 0x1 REFTOP_VBGADJ no description available 4 3 read-write REFTOP_VBGADJ_0 Nominal VBG 0 REFTOP_VBGADJ_1 VBG+0.78% 0x1 REFTOP_VBGADJ_2 VBG+1.56% 0x2 REFTOP_VBGADJ_3 VBG+2.34% 0x3 REFTOP_VBGADJ_4 VBG-0.78% 0x4 REFTOP_VBGADJ_5 VBG-1.56% 0x5 REFTOP_VBGADJ_6 VBG-2.34% 0x6 REFTOP_VBGADJ_7 VBG-3.12% 0x7 REFTOP_VBGUP Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. 7 1 read-write STOP_MODE_CONFIG Configure the analog behavior in stop mode. 10 2 read-write STOP_MODE_CONFIG_0 SUSPEND (DSM) 0 STANDBY Analog regulators are ON. 0x1 STOP_MODE_CONFIG_2 STOP (lower power) 0x2 STOP_MODE_CONFIG_3 STOP (very lower power) 0x3 DISCON_HIGH_SNVS This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 12 1 read-write DISCON_HIGH_SNVS_0 Turn on the switch 0 DISCON_HIGH_SNVS_1 Turn off the switch 0x1 OSC_I This field determines the bias current in the 24MHz oscillator 13 2 read-write NOMINAL Nominal 0 MINUS_12_5_PERCENT Decrease current by 12.5% 0x1 MINUS_25_PERCENT Decrease current by 25.0% 0x2 MINUS_37_5_PERCENT Decrease current by 37.5% 0x3 OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable 15 1 read-only OSC_XTALOK_EN This bit enables the detector that signals when the 24MHz crystal oscillator is stable 16 1 read-write CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 25 1 read-write ALLOW_AUTO_GATE Allow the logic to automatically gate the clock when the XTAL is powered down. 0 NO_AUTO_GATE Prevent the logic from ever gating off the clock. 0x1 CLKGATE_DELAY This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 26 3 read-write CLKGATE_DELAY_0 0.5ms 0 CLKGATE_DELAY_1 1.0ms 0x1 CLKGATE_DELAY_2 2.0ms 0x2 CLKGATE_DELAY_3 3.0ms 0x3 CLKGATE_DELAY_4 4.0ms 0x4 CLKGATE_DELAY_5 5.0ms 0x5 CLKGATE_DELAY_6 6.0ms 0x6 CLKGATE_DELAY_7 7.0ms 0x7 RTC_XTAL_SOURCE This field indicates which chip source is being used for the rtc clock. 29 1 read-only RTC_XTAL_SOURCE_0 Internal ring oscillator 0 RTC_XTAL_SOURCE_1 RTC_XTAL 0x1 XTAL_24M_PWD This field powers down the 24M crystal oscillator if set true. 30 1 read-write MISC0_SET Miscellaneous Register 0 0x154 32 read-write 0x4000000 0xFFFFFFFF REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry 0 1 read-write REFTOP_PWDVBGUP Control bit to power down the VBG-up detection circuitry in the analog bandgap. 1 1 read-write REFTOP_LOWPOWER Control bit to enable the low-power mode in the analog bandgap. 2 1 read-write REFTOP_SELFBIASOFF Control bit to disable the self-bias circuit in the analog bandgap 3 1 read-write REFTOP_SELFBIASOFF_0 Uses coarse bias currents for startup 0 REFTOP_SELFBIASOFF_1 Uses bandgap-based bias currents for best performance. 0x1 REFTOP_VBGADJ no description available 4 3 read-write REFTOP_VBGADJ_0 Nominal VBG 0 REFTOP_VBGADJ_1 VBG+0.78% 0x1 REFTOP_VBGADJ_2 VBG+1.56% 0x2 REFTOP_VBGADJ_3 VBG+2.34% 0x3 REFTOP_VBGADJ_4 VBG-0.78% 0x4 REFTOP_VBGADJ_5 VBG-1.56% 0x5 REFTOP_VBGADJ_6 VBG-2.34% 0x6 REFTOP_VBGADJ_7 VBG-3.12% 0x7 REFTOP_VBGUP Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. 7 1 read-write STOP_MODE_CONFIG Configure the analog behavior in stop mode. 10 2 read-write STOP_MODE_CONFIG_0 SUSPEND (DSM) 0 STANDBY Analog regulators are ON. 0x1 STOP_MODE_CONFIG_2 STOP (lower power) 0x2 STOP_MODE_CONFIG_3 STOP (very lower power) 0x3 DISCON_HIGH_SNVS This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 12 1 read-write DISCON_HIGH_SNVS_0 Turn on the switch 0 DISCON_HIGH_SNVS_1 Turn off the switch 0x1 OSC_I This field determines the bias current in the 24MHz oscillator 13 2 read-write NOMINAL Nominal 0 MINUS_12_5_PERCENT Decrease current by 12.5% 0x1 MINUS_25_PERCENT Decrease current by 25.0% 0x2 MINUS_37_5_PERCENT Decrease current by 37.5% 0x3 OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable 15 1 read-only OSC_XTALOK_EN This bit enables the detector that signals when the 24MHz crystal oscillator is stable 16 1 read-write CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 25 1 read-write ALLOW_AUTO_GATE Allow the logic to automatically gate the clock when the XTAL is powered down. 0 NO_AUTO_GATE Prevent the logic from ever gating off the clock. 0x1 CLKGATE_DELAY This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 26 3 read-write CLKGATE_DELAY_0 0.5ms 0 CLKGATE_DELAY_1 1.0ms 0x1 CLKGATE_DELAY_2 2.0ms 0x2 CLKGATE_DELAY_3 3.0ms 0x3 CLKGATE_DELAY_4 4.0ms 0x4 CLKGATE_DELAY_5 5.0ms 0x5 CLKGATE_DELAY_6 6.0ms 0x6 CLKGATE_DELAY_7 7.0ms 0x7 RTC_XTAL_SOURCE This field indicates which chip source is being used for the rtc clock. 29 1 read-only RTC_XTAL_SOURCE_0 Internal ring oscillator 0 RTC_XTAL_SOURCE_1 RTC_XTAL 0x1 XTAL_24M_PWD This field powers down the 24M crystal oscillator if set true. 30 1 read-write MISC0_CLR Miscellaneous Register 0 0x158 32 read-write 0x4000000 0xFFFFFFFF REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry 0 1 read-write REFTOP_PWDVBGUP Control bit to power down the VBG-up detection circuitry in the analog bandgap. 1 1 read-write REFTOP_LOWPOWER Control bit to enable the low-power mode in the analog bandgap. 2 1 read-write REFTOP_SELFBIASOFF Control bit to disable the self-bias circuit in the analog bandgap 3 1 read-write REFTOP_SELFBIASOFF_0 Uses coarse bias currents for startup 0 REFTOP_SELFBIASOFF_1 Uses bandgap-based bias currents for best performance. 0x1 REFTOP_VBGADJ no description available 4 3 read-write REFTOP_VBGADJ_0 Nominal VBG 0 REFTOP_VBGADJ_1 VBG+0.78% 0x1 REFTOP_VBGADJ_2 VBG+1.56% 0x2 REFTOP_VBGADJ_3 VBG+2.34% 0x3 REFTOP_VBGADJ_4 VBG-0.78% 0x4 REFTOP_VBGADJ_5 VBG-1.56% 0x5 REFTOP_VBGADJ_6 VBG-2.34% 0x6 REFTOP_VBGADJ_7 VBG-3.12% 0x7 REFTOP_VBGUP Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. 7 1 read-write STOP_MODE_CONFIG Configure the analog behavior in stop mode. 10 2 read-write STOP_MODE_CONFIG_0 SUSPEND (DSM) 0 STANDBY Analog regulators are ON. 0x1 STOP_MODE_CONFIG_2 STOP (lower power) 0x2 STOP_MODE_CONFIG_3 STOP (very lower power) 0x3 DISCON_HIGH_SNVS This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 12 1 read-write DISCON_HIGH_SNVS_0 Turn on the switch 0 DISCON_HIGH_SNVS_1 Turn off the switch 0x1 OSC_I This field determines the bias current in the 24MHz oscillator 13 2 read-write NOMINAL Nominal 0 MINUS_12_5_PERCENT Decrease current by 12.5% 0x1 MINUS_25_PERCENT Decrease current by 25.0% 0x2 MINUS_37_5_PERCENT Decrease current by 37.5% 0x3 OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable 15 1 read-only OSC_XTALOK_EN This bit enables the detector that signals when the 24MHz crystal oscillator is stable 16 1 read-write CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 25 1 read-write ALLOW_AUTO_GATE Allow the logic to automatically gate the clock when the XTAL is powered down. 0 NO_AUTO_GATE Prevent the logic from ever gating off the clock. 0x1 CLKGATE_DELAY This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 26 3 read-write CLKGATE_DELAY_0 0.5ms 0 CLKGATE_DELAY_1 1.0ms 0x1 CLKGATE_DELAY_2 2.0ms 0x2 CLKGATE_DELAY_3 3.0ms 0x3 CLKGATE_DELAY_4 4.0ms 0x4 CLKGATE_DELAY_5 5.0ms 0x5 CLKGATE_DELAY_6 6.0ms 0x6 CLKGATE_DELAY_7 7.0ms 0x7 RTC_XTAL_SOURCE This field indicates which chip source is being used for the rtc clock. 29 1 read-only RTC_XTAL_SOURCE_0 Internal ring oscillator 0 RTC_XTAL_SOURCE_1 RTC_XTAL 0x1 XTAL_24M_PWD This field powers down the 24M crystal oscillator if set true. 30 1 read-write MISC0_TOG Miscellaneous Register 0 0x15C 32 read-write 0x4000000 0xFFFFFFFF REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry 0 1 read-write REFTOP_PWDVBGUP Control bit to power down the VBG-up detection circuitry in the analog bandgap. 1 1 read-write REFTOP_LOWPOWER Control bit to enable the low-power mode in the analog bandgap. 2 1 read-write REFTOP_SELFBIASOFF Control bit to disable the self-bias circuit in the analog bandgap 3 1 read-write REFTOP_SELFBIASOFF_0 Uses coarse bias currents for startup 0 REFTOP_SELFBIASOFF_1 Uses bandgap-based bias currents for best performance. 0x1 REFTOP_VBGADJ no description available 4 3 read-write REFTOP_VBGADJ_0 Nominal VBG 0 REFTOP_VBGADJ_1 VBG+0.78% 0x1 REFTOP_VBGADJ_2 VBG+1.56% 0x2 REFTOP_VBGADJ_3 VBG+2.34% 0x3 REFTOP_VBGADJ_4 VBG-0.78% 0x4 REFTOP_VBGADJ_5 VBG-1.56% 0x5 REFTOP_VBGADJ_6 VBG-2.34% 0x6 REFTOP_VBGADJ_7 VBG-3.12% 0x7 REFTOP_VBGUP Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. 7 1 read-write STOP_MODE_CONFIG Configure the analog behavior in stop mode. 10 2 read-write STOP_MODE_CONFIG_0 SUSPEND (DSM) 0 STANDBY Analog regulators are ON. 0x1 STOP_MODE_CONFIG_2 STOP (lower power) 0x2 STOP_MODE_CONFIG_3 STOP (very lower power) 0x3 DISCON_HIGH_SNVS This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 12 1 read-write DISCON_HIGH_SNVS_0 Turn on the switch 0 DISCON_HIGH_SNVS_1 Turn off the switch 0x1 OSC_I This field determines the bias current in the 24MHz oscillator 13 2 read-write NOMINAL Nominal 0 MINUS_12_5_PERCENT Decrease current by 12.5% 0x1 MINUS_25_PERCENT Decrease current by 25.0% 0x2 MINUS_37_5_PERCENT Decrease current by 37.5% 0x3 OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable 15 1 read-only OSC_XTALOK_EN This bit enables the detector that signals when the 24MHz crystal oscillator is stable 16 1 read-write CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 25 1 read-write ALLOW_AUTO_GATE Allow the logic to automatically gate the clock when the XTAL is powered down. 0 NO_AUTO_GATE Prevent the logic from ever gating off the clock. 0x1 CLKGATE_DELAY This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 26 3 read-write CLKGATE_DELAY_0 0.5ms 0 CLKGATE_DELAY_1 1.0ms 0x1 CLKGATE_DELAY_2 2.0ms 0x2 CLKGATE_DELAY_3 3.0ms 0x3 CLKGATE_DELAY_4 4.0ms 0x4 CLKGATE_DELAY_5 5.0ms 0x5 CLKGATE_DELAY_6 6.0ms 0x6 CLKGATE_DELAY_7 7.0ms 0x7 RTC_XTAL_SOURCE This field indicates which chip source is being used for the rtc clock. 29 1 read-only RTC_XTAL_SOURCE_0 Internal ring oscillator 0 RTC_XTAL_SOURCE_1 RTC_XTAL 0x1 XTAL_24M_PWD This field powers down the 24M crystal oscillator if set true. 30 1 read-write MISC1 Miscellaneous Register 1 0x160 32 read-write 0 0xFFFFFFFF PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off 16 1 read-write PFD_528_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off 17 1 read-write IRQ_TEMPPANIC This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature 27 1 read-write oneToClear IRQ_TEMPLOW This status bit is set to one when the temperature sensor low interrupt asserts for low temperature 28 1 read-write oneToClear IRQ_TEMPHIGH This status bit is set to one when the temperature sensor high interrupt asserts for high temperature 29 1 read-write oneToClear IRQ_ANA_BO This status bit is set to one when when any of the analog regulator brownout interrupts assert 30 1 read-write oneToClear IRQ_DIG_BO This status bit is set to one when when any of the digital regulator brownout interrupts assert 31 1 read-write oneToClear MISC1_SET Miscellaneous Register 1 0x164 32 read-write 0 0xFFFFFFFF PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off 16 1 read-write PFD_528_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off 17 1 read-write IRQ_TEMPPANIC This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature 27 1 read-write oneToClear IRQ_TEMPLOW This status bit is set to one when the temperature sensor low interrupt asserts for low temperature 28 1 read-write oneToClear IRQ_TEMPHIGH This status bit is set to one when the temperature sensor high interrupt asserts for high temperature 29 1 read-write oneToClear IRQ_ANA_BO This status bit is set to one when when any of the analog regulator brownout interrupts assert 30 1 read-write oneToClear IRQ_DIG_BO This status bit is set to one when when any of the digital regulator brownout interrupts assert 31 1 read-write oneToClear MISC1_CLR Miscellaneous Register 1 0x168 32 read-write 0 0xFFFFFFFF PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off 16 1 read-write PFD_528_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off 17 1 read-write IRQ_TEMPPANIC This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature 27 1 read-write oneToClear IRQ_TEMPLOW This status bit is set to one when the temperature sensor low interrupt asserts for low temperature 28 1 read-write oneToClear IRQ_TEMPHIGH This status bit is set to one when the temperature sensor high interrupt asserts for high temperature 29 1 read-write oneToClear IRQ_ANA_BO This status bit is set to one when when any of the analog regulator brownout interrupts assert 30 1 read-write oneToClear IRQ_DIG_BO This status bit is set to one when when any of the digital regulator brownout interrupts assert 31 1 read-write oneToClear MISC1_TOG Miscellaneous Register 1 0x16C 32 read-write 0 0xFFFFFFFF PFD_480_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off 16 1 read-write PFD_528_AUTOGATE_EN This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off 17 1 read-write IRQ_TEMPPANIC This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature 27 1 read-write oneToClear IRQ_TEMPLOW This status bit is set to one when the temperature sensor low interrupt asserts for low temperature 28 1 read-write oneToClear IRQ_TEMPHIGH This status bit is set to one when the temperature sensor high interrupt asserts for high temperature 29 1 read-write oneToClear IRQ_ANA_BO This status bit is set to one when when any of the analog regulator brownout interrupts assert 30 1 read-write oneToClear IRQ_DIG_BO This status bit is set to one when when any of the digital regulator brownout interrupts assert 31 1 read-write oneToClear MISC2 Miscellaneous Control Register 0x170 32 read-write 0x272727 0xFFFFFFFF REG0_BO_OFFSET This field defines the brown out voltage offset for the CORE power domain 0 3 read-only REG0_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG0_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG0_BO_STATUS Reg0 brownout status bit. 3 1 read-only REG0_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG0_ENABLE_BO Enables the brownout detection. 5 1 read-write PLL3_disable Default value of "0" 7 1 read-write REG1_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 8 3 read-only REG1_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG1_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG1_BO_STATUS Reg1 brownout status bit. 11 1 read-only REG1_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG1_ENABLE_BO Enables the brownout detection. 13 1 read-write AUDIO_DIV_LSB LSB of Post-divider for Audio PLL 15 1 read-write AUDIO_DIV_LSB_0 divide by 1 (Default) 0 AUDIO_DIV_LSB_1 divide by 2 0x1 REG2_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 16 3 read-only REG2_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG2_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG2_BO_STATUS Reg2 brownout status bit. 19 1 read-only REG2_ENABLE_BO Enables the brownout detection. 21 1 read-write REG2_OK Signals that the voltage is above the brownout level for the SOC supply 22 1 read-only AUDIO_DIV_MSB MSB of Post-divider for Audio PLL 23 1 read-write AUDIO_DIV_MSB_0 divide by 1 (Default) 0 AUDIO_DIV_MSB_1 divide by 2 0x1 REG0_STEP_TIME Number of clock periods (24MHz clock). 24 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG1_STEP_TIME Number of clock periods (24MHz clock). 26 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG2_STEP_TIME Number of clock periods (24MHz clock). 28 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 MISC2_SET Miscellaneous Control Register 0x174 32 read-write 0x272727 0xFFFFFFFF REG0_BO_OFFSET This field defines the brown out voltage offset for the CORE power domain 0 3 read-only REG0_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG0_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG0_BO_STATUS Reg0 brownout status bit. 3 1 read-only REG0_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG0_ENABLE_BO Enables the brownout detection. 5 1 read-write PLL3_disable Default value of "0" 7 1 read-write REG1_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 8 3 read-only REG1_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG1_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG1_BO_STATUS Reg1 brownout status bit. 11 1 read-only REG1_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG1_ENABLE_BO Enables the brownout detection. 13 1 read-write AUDIO_DIV_LSB LSB of Post-divider for Audio PLL 15 1 read-write AUDIO_DIV_LSB_0 divide by 1 (Default) 0 AUDIO_DIV_LSB_1 divide by 2 0x1 REG2_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 16 3 read-only REG2_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG2_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG2_BO_STATUS Reg2 brownout status bit. 19 1 read-only REG2_ENABLE_BO Enables the brownout detection. 21 1 read-write REG2_OK Signals that the voltage is above the brownout level for the SOC supply 22 1 read-only AUDIO_DIV_MSB MSB of Post-divider for Audio PLL 23 1 read-write AUDIO_DIV_MSB_0 divide by 1 (Default) 0 AUDIO_DIV_MSB_1 divide by 2 0x1 REG0_STEP_TIME Number of clock periods (24MHz clock). 24 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG1_STEP_TIME Number of clock periods (24MHz clock). 26 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG2_STEP_TIME Number of clock periods (24MHz clock). 28 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 MISC2_CLR Miscellaneous Control Register 0x178 32 read-write 0x272727 0xFFFFFFFF REG0_BO_OFFSET This field defines the brown out voltage offset for the CORE power domain 0 3 read-only REG0_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG0_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG0_BO_STATUS Reg0 brownout status bit. 3 1 read-only REG0_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG0_ENABLE_BO Enables the brownout detection. 5 1 read-write PLL3_disable Default value of "0" 7 1 read-write REG1_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 8 3 read-only REG1_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG1_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG1_BO_STATUS Reg1 brownout status bit. 11 1 read-only REG1_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG1_ENABLE_BO Enables the brownout detection. 13 1 read-write AUDIO_DIV_LSB LSB of Post-divider for Audio PLL 15 1 read-write AUDIO_DIV_LSB_0 divide by 1 (Default) 0 AUDIO_DIV_LSB_1 divide by 2 0x1 REG2_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 16 3 read-only REG2_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG2_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG2_BO_STATUS Reg2 brownout status bit. 19 1 read-only REG2_ENABLE_BO Enables the brownout detection. 21 1 read-write REG2_OK Signals that the voltage is above the brownout level for the SOC supply 22 1 read-only AUDIO_DIV_MSB MSB of Post-divider for Audio PLL 23 1 read-write AUDIO_DIV_MSB_0 divide by 1 (Default) 0 AUDIO_DIV_MSB_1 divide by 2 0x1 REG0_STEP_TIME Number of clock periods (24MHz clock). 24 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG1_STEP_TIME Number of clock periods (24MHz clock). 26 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG2_STEP_TIME Number of clock periods (24MHz clock). 28 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 MISC2_TOG Miscellaneous Control Register 0x17C 32 read-write 0x272727 0xFFFFFFFF REG0_BO_OFFSET This field defines the brown out voltage offset for the CORE power domain 0 3 read-only REG0_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG0_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG0_BO_STATUS Reg0 brownout status bit. 3 1 read-only REG0_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG0_ENABLE_BO Enables the brownout detection. 5 1 read-write PLL3_disable Default value of "0" 7 1 read-write REG1_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 8 3 read-only REG1_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG1_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG1_BO_STATUS Reg1 brownout status bit. 11 1 read-only REG1_BO_STATUS_1 Brownout, supply is below target minus brownout offset. 0x1 REG1_ENABLE_BO Enables the brownout detection. 13 1 read-write AUDIO_DIV_LSB LSB of Post-divider for Audio PLL 15 1 read-write AUDIO_DIV_LSB_0 divide by 1 (Default) 0 AUDIO_DIV_LSB_1 divide by 2 0x1 REG2_BO_OFFSET This field defines the brown out voltage offset for the xPU power domain 16 3 read-only REG2_BO_OFFSET_4 Brownout offset = 0.100V 0x4 REG2_BO_OFFSET_7 Brownout offset = 0.175V 0x7 REG2_BO_STATUS Reg2 brownout status bit. 19 1 read-only REG2_ENABLE_BO Enables the brownout detection. 21 1 read-write REG2_OK Signals that the voltage is above the brownout level for the SOC supply 22 1 read-only AUDIO_DIV_MSB MSB of Post-divider for Audio PLL 23 1 read-write AUDIO_DIV_MSB_0 divide by 1 (Default) 0 AUDIO_DIV_MSB_1 divide by 2 0x1 REG0_STEP_TIME Number of clock periods (24MHz clock). 24 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG1_STEP_TIME Number of clock periods (24MHz clock). 26 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 REG2_STEP_TIME Number of clock periods (24MHz clock). 28 2 read-write 64_CLOCKS 64 0 128_CLOCKS 128 0x1 256_CLOCKS 256 0x2 512_CLOCKS 512 0x3 TEMPMON Temperature Monitor CCM_ANALOG TEMPMON TEMPMON_ 0x400D8000 0 0x2A0 registers TEMP_LOW_HIGH 63 TEMP_PANIC 64 TEMPSENSE0 Tempsensor Control Register 0 0x180 32 read-write 0x1 0xFFFFFFFF POWER_DOWN This bit powers down the temperature sensor. 0 1 read-write POWER_UP Enable power to the temperature sensor. 0 POWER_DOWN Power down the temperature sensor. 0x1 MEASURE_TEMP Starts the measurement process 1 1 read-write STOP Do not start the measurement process. 0 START Start the measurement process. 0x1 FINISHED Indicates that the latest temp is valid 2 1 read-only INVALID Last measurement is not ready yet. 0 VALID Last measurement is valid. 0x1 TEMP_CNT This bit field contains the last measured temperature count. 8 12 read-only ALARM_VALUE This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field 20 12 read-write TEMPSENSE0_SET Tempsensor Control Register 0 0x184 32 read-write 0x1 0xFFFFFFFF POWER_DOWN This bit powers down the temperature sensor. 0 1 read-write POWER_UP Enable power to the temperature sensor. 0 POWER_DOWN Power down the temperature sensor. 0x1 MEASURE_TEMP Starts the measurement process 1 1 read-write STOP Do not start the measurement process. 0 START Start the measurement process. 0x1 FINISHED Indicates that the latest temp is valid 2 1 read-only INVALID Last measurement is not ready yet. 0 VALID Last measurement is valid. 0x1 TEMP_CNT This bit field contains the last measured temperature count. 8 12 read-only ALARM_VALUE This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field 20 12 read-write TEMPSENSE0_CLR Tempsensor Control Register 0 0x188 32 read-write 0x1 0xFFFFFFFF POWER_DOWN This bit powers down the temperature sensor. 0 1 read-write POWER_UP Enable power to the temperature sensor. 0 POWER_DOWN Power down the temperature sensor. 0x1 MEASURE_TEMP Starts the measurement process 1 1 read-write STOP Do not start the measurement process. 0 START Start the measurement process. 0x1 FINISHED Indicates that the latest temp is valid 2 1 read-only INVALID Last measurement is not ready yet. 0 VALID Last measurement is valid. 0x1 TEMP_CNT This bit field contains the last measured temperature count. 8 12 read-only ALARM_VALUE This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field 20 12 read-write TEMPSENSE0_TOG Tempsensor Control Register 0 0x18C 32 read-write 0x1 0xFFFFFFFF POWER_DOWN This bit powers down the temperature sensor. 0 1 read-write POWER_UP Enable power to the temperature sensor. 0 POWER_DOWN Power down the temperature sensor. 0x1 MEASURE_TEMP Starts the measurement process 1 1 read-write STOP Do not start the measurement process. 0 START Start the measurement process. 0x1 FINISHED Indicates that the latest temp is valid 2 1 read-only INVALID Last measurement is not ready yet. 0 VALID Last measurement is valid. 0x1 TEMP_CNT This bit field contains the last measured temperature count. 8 12 read-only ALARM_VALUE This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field 20 12 read-write TEMPSENSE1 Tempsensor Control Register 1 0x190 32 read-write 0x1 0xFFFFFFFF MEASURE_FREQ This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement 0 16 read-write TEMPSENSE1_SET Tempsensor Control Register 1 0x194 32 read-write 0x1 0xFFFFFFFF MEASURE_FREQ This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement 0 16 read-write TEMPSENSE1_CLR Tempsensor Control Register 1 0x198 32 read-write 0x1 0xFFFFFFFF MEASURE_FREQ This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement 0 16 read-write TEMPSENSE1_TOG Tempsensor Control Register 1 0x19C 32 read-write 0x1 0xFFFFFFFF MEASURE_FREQ This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement 0 16 read-write TEMPSENSE2 Tempsensor Control Register 2 0x290 32 read-write 0 0xFFFFFFFF LOW_ALARM_VALUE This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT 0 12 read-write PANIC_ALARM_VALUE This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field 16 12 read-write TEMPSENSE2_SET Tempsensor Control Register 2 0x294 32 read-write 0 0xFFFFFFFF LOW_ALARM_VALUE This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT 0 12 read-write PANIC_ALARM_VALUE This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field 16 12 read-write TEMPSENSE2_CLR Tempsensor Control Register 2 0x298 32 read-write 0 0xFFFFFFFF LOW_ALARM_VALUE This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT 0 12 read-write PANIC_ALARM_VALUE This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field 16 12 read-write TEMPSENSE2_TOG Tempsensor Control Register 2 0x29C 32 read-write 0 0xFFFFFFFF LOW_ALARM_VALUE This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT 0 12 read-write PANIC_ALARM_VALUE This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field 16 12 read-write USB_ANALOG USB Analog CCM_ANALOG USB_ANALOG USB_ANALOG_ 0x400D8000 0 0x264 registers USB1_VBUS_DETECT USB VBUS Detect Register 0x1A0 32 read-write 0x100004 0xFFFFFFFF VBUSVALID_THRESH Set the threshold for the VBUSVALID comparator 0 3 read-write 4V0 4.0V 0 4V1 4.1V 0x1 4V2 4.2V 0x2 4V3 4.3V 0x3 4V4 4.4V (default) 0x4 4V5 4.5V 0x5 4V6 4.6V 0x6 4V7 4.7V 0x7 VBUSVALID_PWRUP_CMPS Powers up comparators for vbus_valid detector. 20 1 read-write DISCHARGE_VBUS USB OTG discharge VBUS. 26 1 read-write CHARGE_VBUS USB OTG charge VBUS. 27 1 read-write USB1_VBUS_DETECT_SET USB VBUS Detect Register 0x1A4 32 read-write 0x100004 0xFFFFFFFF VBUSVALID_THRESH Set the threshold for the VBUSVALID comparator 0 3 read-write 4V0 4.0V 0 4V1 4.1V 0x1 4V2 4.2V 0x2 4V3 4.3V 0x3 4V4 4.4V (default) 0x4 4V5 4.5V 0x5 4V6 4.6V 0x6 4V7 4.7V 0x7 VBUSVALID_PWRUP_CMPS Powers up comparators for vbus_valid detector. 20 1 read-write DISCHARGE_VBUS USB OTG discharge VBUS. 26 1 read-write CHARGE_VBUS USB OTG charge VBUS. 27 1 read-write USB1_VBUS_DETECT_CLR USB VBUS Detect Register 0x1A8 32 read-write 0x100004 0xFFFFFFFF VBUSVALID_THRESH Set the threshold for the VBUSVALID comparator 0 3 read-write 4V0 4.0V 0 4V1 4.1V 0x1 4V2 4.2V 0x2 4V3 4.3V 0x3 4V4 4.4V (default) 0x4 4V5 4.5V 0x5 4V6 4.6V 0x6 4V7 4.7V 0x7 VBUSVALID_PWRUP_CMPS Powers up comparators for vbus_valid detector. 20 1 read-write DISCHARGE_VBUS USB OTG discharge VBUS. 26 1 read-write CHARGE_VBUS USB OTG charge VBUS. 27 1 read-write USB1_VBUS_DETECT_TOG USB VBUS Detect Register 0x1AC 32 read-write 0x100004 0xFFFFFFFF VBUSVALID_THRESH Set the threshold for the VBUSVALID comparator 0 3 read-write 4V0 4.0V 0 4V1 4.1V 0x1 4V2 4.2V 0x2 4V3 4.3V 0x3 4V4 4.4V (default) 0x4 4V5 4.5V 0x5 4V6 4.6V 0x6 4V7 4.7V 0x7 VBUSVALID_PWRUP_CMPS Powers up comparators for vbus_valid detector. 20 1 read-write DISCHARGE_VBUS USB OTG discharge VBUS. 26 1 read-write CHARGE_VBUS USB OTG charge VBUS. 27 1 read-write USB1_CHRG_DETECT USB Charger Detect Register 0x1B0 32 read-write 0 0xFFFFFFFF CHK_CONTACT Check the contact of USB plug 18 1 read-write NO_CHECK Do not check the contact of USB plug. 0 CHECK Check whether the USB plug has been in contact with each other 0x1 CHK_CHRG_B Check the charger connection 19 1 read-write CHECK Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. 0 NO_CHECK Do not check whether a charger is connected to the USB port. 0x1 EN_B Control the charger detector. 20 1 read-write ENABLE Enable the charger detector. 0 DISABLE Disable the charger detector. 0x1 USB1_CHRG_DETECT_SET USB Charger Detect Register 0x1B4 32 read-write 0 0xFFFFFFFF CHK_CONTACT Check the contact of USB plug 18 1 read-write NO_CHECK Do not check the contact of USB plug. 0 CHECK Check whether the USB plug has been in contact with each other 0x1 CHK_CHRG_B Check the charger connection 19 1 read-write CHECK Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. 0 NO_CHECK Do not check whether a charger is connected to the USB port. 0x1 EN_B Control the charger detector. 20 1 read-write ENABLE Enable the charger detector. 0 DISABLE Disable the charger detector. 0x1 USB1_CHRG_DETECT_CLR USB Charger Detect Register 0x1B8 32 read-write 0 0xFFFFFFFF CHK_CONTACT Check the contact of USB plug 18 1 read-write NO_CHECK Do not check the contact of USB plug. 0 CHECK Check whether the USB plug has been in contact with each other 0x1 CHK_CHRG_B Check the charger connection 19 1 read-write CHECK Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. 0 NO_CHECK Do not check whether a charger is connected to the USB port. 0x1 EN_B Control the charger detector. 20 1 read-write ENABLE Enable the charger detector. 0 DISABLE Disable the charger detector. 0x1 USB1_CHRG_DETECT_TOG USB Charger Detect Register 0x1BC 32 read-write 0 0xFFFFFFFF CHK_CONTACT Check the contact of USB plug 18 1 read-write NO_CHECK Do not check the contact of USB plug. 0 CHECK Check whether the USB plug has been in contact with each other 0x1 CHK_CHRG_B Check the charger connection 19 1 read-write CHECK Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. 0 NO_CHECK Do not check whether a charger is connected to the USB port. 0x1 EN_B Control the charger detector. 20 1 read-write ENABLE Enable the charger detector. 0 DISABLE Disable the charger detector. 0x1 USB1_VBUS_DETECT_STAT USB VBUS Detect Status Register 0x1C0 32 read-only 0 0xFFFFFFFF SESSEND Session End for USB OTG 0 1 read-only BVALID Indicates VBus is valid for a B-peripheral 1 1 read-only AVALID Indicates VBus is valid for a A-peripheral 2 1 read-only VBUS_VALID VBus valid for USB OTG 3 1 read-only USB1_CHRG_DETECT_STAT USB Charger Detect Status Register 0x1D0 32 read-only 0 0xFFFFFFFF PLUG_CONTACT State of the USB plug contact detector. 0 1 read-only NO_CONTACT The USB plug has not made contact. 0 GOOD_CONTACT The USB plug has made good contact. 0x1 CHRG_DETECTED State of charger detection. This bit is a read only version of the state of the analog signal. 1 1 read-only CHARGER_NOT_PRESENT The USB port is not connected to a charger. 0 CHARGER_PRESENT A charger (either a dedicated charger or a host charger) is connected to the USB port. 0x1 DM_STATE DM line state output of the charger detector. 2 1 read-only DP_STATE DP line state output of the charger detector. 3 1 read-only USB1_LOOPBACK USB Loopback Test Register 0x1E0 32 read-write 0 0xFFFFFFFF UTMI_TESTSTART Setting this bit can enable 1 0 1 read-write USB1_LOOPBACK_SET USB Loopback Test Register 0x1E4 32 read-write 0 0xFFFFFFFF UTMI_TESTSTART Setting this bit can enable 1 0 1 read-write USB1_LOOPBACK_CLR USB Loopback Test Register 0x1E8 32 read-write 0 0xFFFFFFFF UTMI_TESTSTART Setting this bit can enable 1 0 1 read-write USB1_LOOPBACK_TOG USB Loopback Test Register 0x1EC 32 read-write 0 0xFFFFFFFF UTMI_TESTSTART Setting this bit can enable 1 0 1 read-write USB1_MISC USB Misc Register 0x1F0 32 read-write 0x2 0xFFFFFFFF HS_USE_EXTERNAL_R Use external resistor to generate the current bias for the high speed transmitter 0 1 read-write EN_DEGLITCH Enable the deglitching circuit of the USB PLL output. 1 1 read-write EN_CLK_UTMI Enables the clk to the UTMI block. 30 1 read-write USB1_MISC_SET USB Misc Register 0x1F4 32 read-write 0x2 0xFFFFFFFF HS_USE_EXTERNAL_R Use external resistor to generate the current bias for the high speed transmitter 0 1 read-write EN_DEGLITCH Enable the deglitching circuit of the USB PLL output. 1 1 read-write EN_CLK_UTMI Enables the clk to the UTMI block. 30 1 read-write USB1_MISC_CLR USB Misc Register 0x1F8 32 read-write 0x2 0xFFFFFFFF HS_USE_EXTERNAL_R Use external resistor to generate the current bias for the high speed transmitter 0 1 read-write EN_DEGLITCH Enable the deglitching circuit of the USB PLL output. 1 1 read-write EN_CLK_UTMI Enables the clk to the UTMI block. 30 1 read-write USB1_MISC_TOG USB Misc Register 0x1FC 32 read-write 0x2 0xFFFFFFFF HS_USE_EXTERNAL_R Use external resistor to generate the current bias for the high speed transmitter 0 1 read-write EN_DEGLITCH Enable the deglitching circuit of the USB PLL output. 1 1 read-write EN_CLK_UTMI Enables the clk to the UTMI block. 30 1 read-write DIGPROG Chip Silicon Version 0x260 32 read-only 0x6D0000 0xFFFFFFFF SILICON_REVISION Chip silicon revision 0 32 read-only SILICON_REVISION_7143424 Silicon revision 1.0 0x6D0000 XTALOSC24M XTALOSC24M CCM_ANALOG XTALOSC24M XTALOSC24M_ 0x400D8000 0 0x2D0 registers MISC0 Miscellaneous Register 0 0x150 32 read-write 0x4000000 0xFFFFFFFF REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry 0 1 read-write REFTOP_SELFBIASOFF Control bit to disable the self-bias circuit in the analog bandgap 3 1 read-write REFTOP_SELFBIASOFF_0 Uses coarse bias currents for startup 0 REFTOP_SELFBIASOFF_1 Uses bandgap-based bias currents for best performance. 0x1 REFTOP_VBGADJ Not related to oscillator. 4 3 read-write REFTOP_VBGADJ_0 Nominal VBG 0 REFTOP_VBGADJ_1 VBG+0.78% 0x1 REFTOP_VBGADJ_2 VBG+1.56% 0x2 REFTOP_VBGADJ_3 VBG+2.34% 0x3 REFTOP_VBGADJ_4 VBG-0.78% 0x4 REFTOP_VBGADJ_5 VBG-1.56% 0x5 REFTOP_VBGADJ_6 VBG-2.34% 0x6 REFTOP_VBGADJ_7 VBG-3.12% 0x7 REFTOP_VBGUP Status bit that signals the analog bandgap voltage is up and stable 7 1 read-write STOP_MODE_CONFIG Configure the analog behavior in stop mode.Not related to oscillator. 10 2 read-write STOP_MODE_CONFIG_0 All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 0 STOP_MODE_CONFIG_1 Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 0x1 STOP_MODE_CONFIG_2 XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 0x2 STOP_MODE_CONFIG_3 XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. 0x3 DISCON_HIGH_SNVS This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 12 1 read-write DISCON_HIGH_SNVS_0 Turn on the switch 0 DISCON_HIGH_SNVS_1 Turn off the switch 0x1 OSC_I This field determines the bias current in the 24MHz oscillator 13 2 read-write NOMINAL Nominal 0 MINUS_12_5_PERCENT Decrease current by 12.5% 0x1 MINUS_25_PERCENT Decrease current by 25.0% 0x2 MINUS_37_5_PERCENT Decrease current by 37.5% 0x3 OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable 15 1 read-only OSC_XTALOK_EN This bit enables the detector that signals when the 24MHz crystal oscillator is stable. 16 1 read-write CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 25 1 read-write ALLOW_AUTO_GATE Allow the logic to automatically gate the clock when the XTAL is powered down. 0 NO_AUTO_GATE Prevent the logic from ever gating off the clock. 0x1 CLKGATE_DELAY This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 26 3 read-write CLKGATE_DELAY_0 0.5ms 0 CLKGATE_DELAY_1 1.0ms 0x1 CLKGATE_DELAY_2 2.0ms 0x2 CLKGATE_DELAY_3 3.0ms 0x3 CLKGATE_DELAY_4 4.0ms 0x4 CLKGATE_DELAY_5 5.0ms 0x5 CLKGATE_DELAY_6 6.0ms 0x6 CLKGATE_DELAY_7 7.0ms 0x7 RTC_XTAL_SOURCE This field indicates which chip source is being used for the rtc clock. 29 1 read-only RTC_XTAL_SOURCE_0 Internal ring oscillator 0 RTC_XTAL_SOURCE_1 RTC_XTAL 0x1 XTAL_24M_PWD This field powers down the 24M crystal oscillator if set true. 30 1 read-write VID_PLL_PREDIV Predivider for the source clock of the PLL's. Not related to oscillator. 31 1 read-write VID_PLL_PREDIV_0 Divide by 1 0 VID_PLL_PREDIV_1 Divide by 2 0x1 MISC0_SET Miscellaneous Register 0 0x154 32 read-write 0x4000000 0xFFFFFFFF REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry 0 1 read-write REFTOP_SELFBIASOFF Control bit to disable the self-bias circuit in the analog bandgap 3 1 read-write REFTOP_SELFBIASOFF_0 Uses coarse bias currents for startup 0 REFTOP_SELFBIASOFF_1 Uses bandgap-based bias currents for best performance. 0x1 REFTOP_VBGADJ Not related to oscillator. 4 3 read-write REFTOP_VBGADJ_0 Nominal VBG 0 REFTOP_VBGADJ_1 VBG+0.78% 0x1 REFTOP_VBGADJ_2 VBG+1.56% 0x2 REFTOP_VBGADJ_3 VBG+2.34% 0x3 REFTOP_VBGADJ_4 VBG-0.78% 0x4 REFTOP_VBGADJ_5 VBG-1.56% 0x5 REFTOP_VBGADJ_6 VBG-2.34% 0x6 REFTOP_VBGADJ_7 VBG-3.12% 0x7 REFTOP_VBGUP Status bit that signals the analog bandgap voltage is up and stable 7 1 read-write STOP_MODE_CONFIG Configure the analog behavior in stop mode.Not related to oscillator. 10 2 read-write STOP_MODE_CONFIG_0 All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 0 STOP_MODE_CONFIG_1 Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 0x1 STOP_MODE_CONFIG_2 XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 0x2 STOP_MODE_CONFIG_3 XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. 0x3 DISCON_HIGH_SNVS This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 12 1 read-write DISCON_HIGH_SNVS_0 Turn on the switch 0 DISCON_HIGH_SNVS_1 Turn off the switch 0x1 OSC_I This field determines the bias current in the 24MHz oscillator 13 2 read-write NOMINAL Nominal 0 MINUS_12_5_PERCENT Decrease current by 12.5% 0x1 MINUS_25_PERCENT Decrease current by 25.0% 0x2 MINUS_37_5_PERCENT Decrease current by 37.5% 0x3 OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable 15 1 read-only OSC_XTALOK_EN This bit enables the detector that signals when the 24MHz crystal oscillator is stable. 16 1 read-write CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 25 1 read-write ALLOW_AUTO_GATE Allow the logic to automatically gate the clock when the XTAL is powered down. 0 NO_AUTO_GATE Prevent the logic from ever gating off the clock. 0x1 CLKGATE_DELAY This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 26 3 read-write CLKGATE_DELAY_0 0.5ms 0 CLKGATE_DELAY_1 1.0ms 0x1 CLKGATE_DELAY_2 2.0ms 0x2 CLKGATE_DELAY_3 3.0ms 0x3 CLKGATE_DELAY_4 4.0ms 0x4 CLKGATE_DELAY_5 5.0ms 0x5 CLKGATE_DELAY_6 6.0ms 0x6 CLKGATE_DELAY_7 7.0ms 0x7 RTC_XTAL_SOURCE This field indicates which chip source is being used for the rtc clock. 29 1 read-only RTC_XTAL_SOURCE_0 Internal ring oscillator 0 RTC_XTAL_SOURCE_1 RTC_XTAL 0x1 XTAL_24M_PWD This field powers down the 24M crystal oscillator if set true. 30 1 read-write VID_PLL_PREDIV Predivider for the source clock of the PLL's. Not related to oscillator. 31 1 read-write VID_PLL_PREDIV_0 Divide by 1 0 VID_PLL_PREDIV_1 Divide by 2 0x1 MISC0_CLR Miscellaneous Register 0 0x158 32 read-write 0x4000000 0xFFFFFFFF REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry 0 1 read-write REFTOP_SELFBIASOFF Control bit to disable the self-bias circuit in the analog bandgap 3 1 read-write REFTOP_SELFBIASOFF_0 Uses coarse bias currents for startup 0 REFTOP_SELFBIASOFF_1 Uses bandgap-based bias currents for best performance. 0x1 REFTOP_VBGADJ Not related to oscillator. 4 3 read-write REFTOP_VBGADJ_0 Nominal VBG 0 REFTOP_VBGADJ_1 VBG+0.78% 0x1 REFTOP_VBGADJ_2 VBG+1.56% 0x2 REFTOP_VBGADJ_3 VBG+2.34% 0x3 REFTOP_VBGADJ_4 VBG-0.78% 0x4 REFTOP_VBGADJ_5 VBG-1.56% 0x5 REFTOP_VBGADJ_6 VBG-2.34% 0x6 REFTOP_VBGADJ_7 VBG-3.12% 0x7 REFTOP_VBGUP Status bit that signals the analog bandgap voltage is up and stable 7 1 read-write STOP_MODE_CONFIG Configure the analog behavior in stop mode.Not related to oscillator. 10 2 read-write STOP_MODE_CONFIG_0 All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 0 STOP_MODE_CONFIG_1 Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 0x1 STOP_MODE_CONFIG_2 XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 0x2 STOP_MODE_CONFIG_3 XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. 0x3 DISCON_HIGH_SNVS This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 12 1 read-write DISCON_HIGH_SNVS_0 Turn on the switch 0 DISCON_HIGH_SNVS_1 Turn off the switch 0x1 OSC_I This field determines the bias current in the 24MHz oscillator 13 2 read-write NOMINAL Nominal 0 MINUS_12_5_PERCENT Decrease current by 12.5% 0x1 MINUS_25_PERCENT Decrease current by 25.0% 0x2 MINUS_37_5_PERCENT Decrease current by 37.5% 0x3 OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable 15 1 read-only OSC_XTALOK_EN This bit enables the detector that signals when the 24MHz crystal oscillator is stable. 16 1 read-write CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 25 1 read-write ALLOW_AUTO_GATE Allow the logic to automatically gate the clock when the XTAL is powered down. 0 NO_AUTO_GATE Prevent the logic from ever gating off the clock. 0x1 CLKGATE_DELAY This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 26 3 read-write CLKGATE_DELAY_0 0.5ms 0 CLKGATE_DELAY_1 1.0ms 0x1 CLKGATE_DELAY_2 2.0ms 0x2 CLKGATE_DELAY_3 3.0ms 0x3 CLKGATE_DELAY_4 4.0ms 0x4 CLKGATE_DELAY_5 5.0ms 0x5 CLKGATE_DELAY_6 6.0ms 0x6 CLKGATE_DELAY_7 7.0ms 0x7 RTC_XTAL_SOURCE This field indicates which chip source is being used for the rtc clock. 29 1 read-only RTC_XTAL_SOURCE_0 Internal ring oscillator 0 RTC_XTAL_SOURCE_1 RTC_XTAL 0x1 XTAL_24M_PWD This field powers down the 24M crystal oscillator if set true. 30 1 read-write VID_PLL_PREDIV Predivider for the source clock of the PLL's. Not related to oscillator. 31 1 read-write VID_PLL_PREDIV_0 Divide by 1 0 VID_PLL_PREDIV_1 Divide by 2 0x1 MISC0_TOG Miscellaneous Register 0 0x15C 32 read-write 0x4000000 0xFFFFFFFF REFTOP_PWD Control bit to power-down the analog bandgap reference circuitry 0 1 read-write REFTOP_SELFBIASOFF Control bit to disable the self-bias circuit in the analog bandgap 3 1 read-write REFTOP_SELFBIASOFF_0 Uses coarse bias currents for startup 0 REFTOP_SELFBIASOFF_1 Uses bandgap-based bias currents for best performance. 0x1 REFTOP_VBGADJ Not related to oscillator. 4 3 read-write REFTOP_VBGADJ_0 Nominal VBG 0 REFTOP_VBGADJ_1 VBG+0.78% 0x1 REFTOP_VBGADJ_2 VBG+1.56% 0x2 REFTOP_VBGADJ_3 VBG+2.34% 0x3 REFTOP_VBGADJ_4 VBG-0.78% 0x4 REFTOP_VBGADJ_5 VBG-1.56% 0x5 REFTOP_VBGADJ_6 VBG-2.34% 0x6 REFTOP_VBGADJ_7 VBG-3.12% 0x7 REFTOP_VBGUP Status bit that signals the analog bandgap voltage is up and stable 7 1 read-write STOP_MODE_CONFIG Configure the analog behavior in stop mode.Not related to oscillator. 10 2 read-write STOP_MODE_CONFIG_0 All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 0 STOP_MODE_CONFIG_1 Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 0x1 STOP_MODE_CONFIG_2 XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 0x2 STOP_MODE_CONFIG_3 XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. 0x3 DISCON_HIGH_SNVS This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 12 1 read-write DISCON_HIGH_SNVS_0 Turn on the switch 0 DISCON_HIGH_SNVS_1 Turn off the switch 0x1 OSC_I This field determines the bias current in the 24MHz oscillator 13 2 read-write NOMINAL Nominal 0 MINUS_12_5_PERCENT Decrease current by 12.5% 0x1 MINUS_25_PERCENT Decrease current by 25.0% 0x2 MINUS_37_5_PERCENT Decrease current by 37.5% 0x3 OSC_XTALOK Status bit that signals that the output of the 24-MHz crystal oscillator is stable 15 1 read-only OSC_XTALOK_EN This bit enables the detector that signals when the 24MHz crystal oscillator is stable. 16 1 read-write CLKGATE_CTRL This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 25 1 read-write ALLOW_AUTO_GATE Allow the logic to automatically gate the clock when the XTAL is powered down. 0 NO_AUTO_GATE Prevent the logic from ever gating off the clock. 0x1 CLKGATE_DELAY This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 26 3 read-write CLKGATE_DELAY_0 0.5ms 0 CLKGATE_DELAY_1 1.0ms 0x1 CLKGATE_DELAY_2 2.0ms 0x2 CLKGATE_DELAY_3 3.0ms 0x3 CLKGATE_DELAY_4 4.0ms 0x4 CLKGATE_DELAY_5 5.0ms 0x5 CLKGATE_DELAY_6 6.0ms 0x6 CLKGATE_DELAY_7 7.0ms 0x7 RTC_XTAL_SOURCE This field indicates which chip source is being used for the rtc clock. 29 1 read-only RTC_XTAL_SOURCE_0 Internal ring oscillator 0 RTC_XTAL_SOURCE_1 RTC_XTAL 0x1 XTAL_24M_PWD This field powers down the 24M crystal oscillator if set true. 30 1 read-write VID_PLL_PREDIV Predivider for the source clock of the PLL's. Not related to oscillator. 31 1 read-write VID_PLL_PREDIV_0 Divide by 1 0 VID_PLL_PREDIV_1 Divide by 2 0x1 LOWPWR_CTRL XTAL OSC (LP) Control Register 0x270 32 read-write 0x4001 0xFFFFFFFF RC_OSC_EN RC Osc. enable control. 0 1 read-write RC_OSC_EN_0 Use XTAL OSC to source the 24MHz clock 0 RC_OSC_EN_1 Use RC OSC 0x1 OSC_SEL Select the source for the 24MHz clock. 4 1 read-write OSC_SEL_0 XTAL OSC 0 OSC_SEL_1 RC OSC 0x1 LPBG_SEL Bandgap select. Not related to oscillator. 5 1 read-write LPBG_SEL_0 Normal power bandgap 0 LPBG_SEL_1 Low power bandgap 0x1 LPBG_TEST Low power bandgap test bit. Not related to oscillator. 6 1 read-write REFTOP_IBIAS_OFF Low power reftop ibias disable. Not related to oscillator. 7 1 read-write L1_PWRGATE L1 power gate control. Used as software override. Not related to oscillator. 8 1 read-write L2_PWRGATE L2 power gate control. Used as software override. Not related to oscillator. 9 1 read-write CPU_PWRGATE CPU power gate control. Used as software override. Test purpose only Not related to oscillator. 10 1 read-write DISPLAY_PWRGATE Display logic power gate control. Used as software override. Not related to oscillator. 11 1 read-write RCOSC_CG_OVERRIDE For debug purposes only 13 1 read-write XTALOSC_PWRUP_DELAY Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use 14 2 read-write XTALOSC_PWRUP_DELAY_0 0.25ms 0 XTALOSC_PWRUP_DELAY_1 0.5ms 0x1 XTALOSC_PWRUP_DELAY_2 1ms 0x2 XTALOSC_PWRUP_DELAY_3 2ms 0x3 XTALOSC_PWRUP_STAT Status of the 24MHz xtal oscillator. 16 1 read-only XTALOSC_PWRUP_STAT_0 Not stable 0 XTALOSC_PWRUP_STAT_1 Stable and ready to use 0x1 MIX_PWRGATE Display power gate control. Used as software mask. Set to zero to force ungated. 17 1 read-write GPU_PWRGATE GPU power gate control. Used as software mask. Set to zero to force ungated. 18 1 read-write LOWPWR_CTRL_SET XTAL OSC (LP) Control Register 0x274 32 read-write 0x4001 0xFFFFFFFF RC_OSC_EN RC Osc. enable control. 0 1 read-write RC_OSC_EN_0 Use XTAL OSC to source the 24MHz clock 0 RC_OSC_EN_1 Use RC OSC 0x1 OSC_SEL Select the source for the 24MHz clock. 4 1 read-write OSC_SEL_0 XTAL OSC 0 OSC_SEL_1 RC OSC 0x1 LPBG_SEL Bandgap select. Not related to oscillator. 5 1 read-write LPBG_SEL_0 Normal power bandgap 0 LPBG_SEL_1 Low power bandgap 0x1 LPBG_TEST Low power bandgap test bit. Not related to oscillator. 6 1 read-write REFTOP_IBIAS_OFF Low power reftop ibias disable. Not related to oscillator. 7 1 read-write L1_PWRGATE L1 power gate control. Used as software override. Not related to oscillator. 8 1 read-write L2_PWRGATE L2 power gate control. Used as software override. Not related to oscillator. 9 1 read-write CPU_PWRGATE CPU power gate control. Used as software override. Test purpose only Not related to oscillator. 10 1 read-write DISPLAY_PWRGATE Display logic power gate control. Used as software override. Not related to oscillator. 11 1 read-write RCOSC_CG_OVERRIDE For debug purposes only 13 1 read-write XTALOSC_PWRUP_DELAY Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use 14 2 read-write XTALOSC_PWRUP_DELAY_0 0.25ms 0 XTALOSC_PWRUP_DELAY_1 0.5ms 0x1 XTALOSC_PWRUP_DELAY_2 1ms 0x2 XTALOSC_PWRUP_DELAY_3 2ms 0x3 XTALOSC_PWRUP_STAT Status of the 24MHz xtal oscillator. 16 1 read-only XTALOSC_PWRUP_STAT_0 Not stable 0 XTALOSC_PWRUP_STAT_1 Stable and ready to use 0x1 MIX_PWRGATE Display power gate control. Used as software mask. Set to zero to force ungated. 17 1 read-write GPU_PWRGATE GPU power gate control. Used as software mask. Set to zero to force ungated. 18 1 read-write LOWPWR_CTRL_CLR XTAL OSC (LP) Control Register 0x278 32 read-write 0x4001 0xFFFFFFFF RC_OSC_EN RC Osc. enable control. 0 1 read-write RC_OSC_EN_0 Use XTAL OSC to source the 24MHz clock 0 RC_OSC_EN_1 Use RC OSC 0x1 OSC_SEL Select the source for the 24MHz clock. 4 1 read-write OSC_SEL_0 XTAL OSC 0 OSC_SEL_1 RC OSC 0x1 LPBG_SEL Bandgap select. Not related to oscillator. 5 1 read-write LPBG_SEL_0 Normal power bandgap 0 LPBG_SEL_1 Low power bandgap 0x1 LPBG_TEST Low power bandgap test bit. Not related to oscillator. 6 1 read-write REFTOP_IBIAS_OFF Low power reftop ibias disable. Not related to oscillator. 7 1 read-write L1_PWRGATE L1 power gate control. Used as software override. Not related to oscillator. 8 1 read-write L2_PWRGATE L2 power gate control. Used as software override. Not related to oscillator. 9 1 read-write CPU_PWRGATE CPU power gate control. Used as software override. Test purpose only Not related to oscillator. 10 1 read-write DISPLAY_PWRGATE Display logic power gate control. Used as software override. Not related to oscillator. 11 1 read-write RCOSC_CG_OVERRIDE For debug purposes only 13 1 read-write XTALOSC_PWRUP_DELAY Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use 14 2 read-write XTALOSC_PWRUP_DELAY_0 0.25ms 0 XTALOSC_PWRUP_DELAY_1 0.5ms 0x1 XTALOSC_PWRUP_DELAY_2 1ms 0x2 XTALOSC_PWRUP_DELAY_3 2ms 0x3 XTALOSC_PWRUP_STAT Status of the 24MHz xtal oscillator. 16 1 read-only XTALOSC_PWRUP_STAT_0 Not stable 0 XTALOSC_PWRUP_STAT_1 Stable and ready to use 0x1 MIX_PWRGATE Display power gate control. Used as software mask. Set to zero to force ungated. 17 1 read-write GPU_PWRGATE GPU power gate control. Used as software mask. Set to zero to force ungated. 18 1 read-write LOWPWR_CTRL_TOG XTAL OSC (LP) Control Register 0x27C 32 read-write 0x4001 0xFFFFFFFF RC_OSC_EN RC Osc. enable control. 0 1 read-write RC_OSC_EN_0 Use XTAL OSC to source the 24MHz clock 0 RC_OSC_EN_1 Use RC OSC 0x1 OSC_SEL Select the source for the 24MHz clock. 4 1 read-write OSC_SEL_0 XTAL OSC 0 OSC_SEL_1 RC OSC 0x1 LPBG_SEL Bandgap select. Not related to oscillator. 5 1 read-write LPBG_SEL_0 Normal power bandgap 0 LPBG_SEL_1 Low power bandgap 0x1 LPBG_TEST Low power bandgap test bit. Not related to oscillator. 6 1 read-write REFTOP_IBIAS_OFF Low power reftop ibias disable. Not related to oscillator. 7 1 read-write L1_PWRGATE L1 power gate control. Used as software override. Not related to oscillator. 8 1 read-write L2_PWRGATE L2 power gate control. Used as software override. Not related to oscillator. 9 1 read-write CPU_PWRGATE CPU power gate control. Used as software override. Test purpose only Not related to oscillator. 10 1 read-write DISPLAY_PWRGATE Display logic power gate control. Used as software override. Not related to oscillator. 11 1 read-write RCOSC_CG_OVERRIDE For debug purposes only 13 1 read-write XTALOSC_PWRUP_DELAY Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use 14 2 read-write XTALOSC_PWRUP_DELAY_0 0.25ms 0 XTALOSC_PWRUP_DELAY_1 0.5ms 0x1 XTALOSC_PWRUP_DELAY_2 1ms 0x2 XTALOSC_PWRUP_DELAY_3 2ms 0x3 XTALOSC_PWRUP_STAT Status of the 24MHz xtal oscillator. 16 1 read-only XTALOSC_PWRUP_STAT_0 Not stable 0 XTALOSC_PWRUP_STAT_1 Stable and ready to use 0x1 MIX_PWRGATE Display power gate control. Used as software mask. Set to zero to force ungated. 17 1 read-write GPU_PWRGATE GPU power gate control. Used as software mask. Set to zero to force ungated. 18 1 read-write OSC_CONFIG0 XTAL OSC Configuration 0 Register 0x2A0 32 read-write 0x1020 0xFFFFFFFF START Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. 0 1 read-write ENABLE Enables the tuning logic to calculate new RC tuning values 1 1 read-write BYPASS Bypasses any calculated RC tuning value and uses the programmed register value. 2 1 read-write INVERT Invert the stepping of the calculated RC tuning value. 3 1 read-write RC_OSC_PROG RC osc. tuning values. 4 8 read-write HYST_PLUS Positive hysteresis value 12 4 read-write HYST_MINUS Negative hysteresis value 16 4 read-write RC_OSC_PROG_CUR The current tuning value in use. 24 8 read-write OSC_CONFIG0_SET XTAL OSC Configuration 0 Register 0x2A4 32 read-write 0x1020 0xFFFFFFFF START Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. 0 1 read-write ENABLE Enables the tuning logic to calculate new RC tuning values 1 1 read-write BYPASS Bypasses any calculated RC tuning value and uses the programmed register value. 2 1 read-write INVERT Invert the stepping of the calculated RC tuning value. 3 1 read-write RC_OSC_PROG RC osc. tuning values. 4 8 read-write HYST_PLUS Positive hysteresis value 12 4 read-write HYST_MINUS Negative hysteresis value 16 4 read-write RC_OSC_PROG_CUR The current tuning value in use. 24 8 read-write OSC_CONFIG0_CLR XTAL OSC Configuration 0 Register 0x2A8 32 read-write 0x1020 0xFFFFFFFF START Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. 0 1 read-write ENABLE Enables the tuning logic to calculate new RC tuning values 1 1 read-write BYPASS Bypasses any calculated RC tuning value and uses the programmed register value. 2 1 read-write INVERT Invert the stepping of the calculated RC tuning value. 3 1 read-write RC_OSC_PROG RC osc. tuning values. 4 8 read-write HYST_PLUS Positive hysteresis value 12 4 read-write HYST_MINUS Negative hysteresis value 16 4 read-write RC_OSC_PROG_CUR The current tuning value in use. 24 8 read-write OSC_CONFIG0_TOG XTAL OSC Configuration 0 Register 0x2AC 32 read-write 0x1020 0xFFFFFFFF START Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. 0 1 read-write ENABLE Enables the tuning logic to calculate new RC tuning values 1 1 read-write BYPASS Bypasses any calculated RC tuning value and uses the programmed register value. 2 1 read-write INVERT Invert the stepping of the calculated RC tuning value. 3 1 read-write RC_OSC_PROG RC osc. tuning values. 4 8 read-write HYST_PLUS Positive hysteresis value 12 4 read-write HYST_MINUS Negative hysteresis value 16 4 read-write RC_OSC_PROG_CUR The current tuning value in use. 24 8 read-write OSC_CONFIG1 XTAL OSC Configuration 1 Register 0x2B0 32 read-write 0x2EE 0xFFFFFFFF COUNT_RC_TRG The target count used to tune the RC OSC frequency 0 12 read-write COUNT_RC_CUR The current tuning value in use. 20 12 read-write OSC_CONFIG1_SET XTAL OSC Configuration 1 Register 0x2B4 32 read-write 0x2EE 0xFFFFFFFF COUNT_RC_TRG The target count used to tune the RC OSC frequency 0 12 read-write COUNT_RC_CUR The current tuning value in use. 20 12 read-write OSC_CONFIG1_CLR XTAL OSC Configuration 1 Register 0x2B8 32 read-write 0x2EE 0xFFFFFFFF COUNT_RC_TRG The target count used to tune the RC OSC frequency 0 12 read-write COUNT_RC_CUR The current tuning value in use. 20 12 read-write OSC_CONFIG1_TOG XTAL OSC Configuration 1 Register 0x2BC 32 read-write 0x2EE 0xFFFFFFFF COUNT_RC_TRG The target count used to tune the RC OSC frequency 0 12 read-write COUNT_RC_CUR The current tuning value in use. 20 12 read-write OSC_CONFIG2 XTAL OSC Configuration 2 Register 0x2C0 32 read-write 0x102E2 0xFFFFFFFF COUNT_1M_TRG The target count used to tune the 1MHz clock frequency 0 12 read-write ENABLE_1M Enable the 1MHz clock output. 0 - disabled; 1 - enabled. 16 1 read-write MUX_1M Mux the corrected or uncorrected 1MHz clock to the output 17 1 read-write CLK_1M_ERR_FL Flag indicates that the count_1m count wasn't reached within 1 32kHz period 31 1 read-write OSC_CONFIG2_SET XTAL OSC Configuration 2 Register 0x2C4 32 read-write 0x102E2 0xFFFFFFFF COUNT_1M_TRG The target count used to tune the 1MHz clock frequency 0 12 read-write ENABLE_1M Enable the 1MHz clock output. 0 - disabled; 1 - enabled. 16 1 read-write MUX_1M Mux the corrected or uncorrected 1MHz clock to the output 17 1 read-write CLK_1M_ERR_FL Flag indicates that the count_1m count wasn't reached within 1 32kHz period 31 1 read-write OSC_CONFIG2_CLR XTAL OSC Configuration 2 Register 0x2C8 32 read-write 0x102E2 0xFFFFFFFF COUNT_1M_TRG The target count used to tune the 1MHz clock frequency 0 12 read-write ENABLE_1M Enable the 1MHz clock output. 0 - disabled; 1 - enabled. 16 1 read-write MUX_1M Mux the corrected or uncorrected 1MHz clock to the output 17 1 read-write CLK_1M_ERR_FL Flag indicates that the count_1m count wasn't reached within 1 32kHz period 31 1 read-write OSC_CONFIG2_TOG XTAL OSC Configuration 2 Register 0x2CC 32 read-write 0x102E2 0xFFFFFFFF COUNT_1M_TRG The target count used to tune the 1MHz clock frequency 0 12 read-write ENABLE_1M Enable the 1MHz clock output. 0 - disabled; 1 - enabled. 16 1 read-write MUX_1M Mux the corrected or uncorrected 1MHz clock to the output 17 1 read-write CLK_1M_ERR_FL Flag indicates that the count_1m count wasn't reached within 1 32kHz period 31 1 read-write USBPHY USBPHY Register Reference Index USBPHY USBPHY_ 0x400D9000 0 0x84 registers USB_PHY 65 PWD USB PHY Power-Down Register 0 32 read-write 0x1E1C00 0xFFFFFFFF RSVD0 Reserved. 0 10 read-only TXPWDFS 0 = Normal operation 10 1 read-write TXPWDIBIAS 0 = Normal operation 11 1 read-write TXPWDV2I 0 = Normal operation 12 1 read-write RSVD1 Reserved. 13 4 read-only RXPWDENV 0 = Normal operation 17 1 read-write RXPWD1PT1 0 = Normal operation 18 1 read-write RXPWDDIFF 0 = Normal operation 19 1 read-write RXPWDRX 0 = Normal operation 20 1 read-write RSVD2 Reserved. 21 11 read-only PWD_SET USB PHY Power-Down Register 0x4 32 read-write 0x1E1C00 0xFFFFFFFF RSVD0 Reserved. 0 10 read-only TXPWDFS 0 = Normal operation 10 1 read-write TXPWDIBIAS 0 = Normal operation 11 1 read-write TXPWDV2I 0 = Normal operation 12 1 read-write RSVD1 Reserved. 13 4 read-only RXPWDENV 0 = Normal operation 17 1 read-write RXPWD1PT1 0 = Normal operation 18 1 read-write RXPWDDIFF 0 = Normal operation 19 1 read-write RXPWDRX 0 = Normal operation 20 1 read-write RSVD2 Reserved. 21 11 read-only PWD_CLR USB PHY Power-Down Register 0x8 32 read-write 0x1E1C00 0xFFFFFFFF RSVD0 Reserved. 0 10 read-only TXPWDFS 0 = Normal operation 10 1 read-write TXPWDIBIAS 0 = Normal operation 11 1 read-write TXPWDV2I 0 = Normal operation 12 1 read-write RSVD1 Reserved. 13 4 read-only RXPWDENV 0 = Normal operation 17 1 read-write RXPWD1PT1 0 = Normal operation 18 1 read-write RXPWDDIFF 0 = Normal operation 19 1 read-write RXPWDRX 0 = Normal operation 20 1 read-write RSVD2 Reserved. 21 11 read-only PWD_TOG USB PHY Power-Down Register 0xC 32 read-write 0x1E1C00 0xFFFFFFFF RSVD0 Reserved. 0 10 read-only TXPWDFS 0 = Normal operation 10 1 read-write TXPWDIBIAS 0 = Normal operation 11 1 read-write TXPWDV2I 0 = Normal operation 12 1 read-write RSVD1 Reserved. 13 4 read-only RXPWDENV 0 = Normal operation 17 1 read-write RXPWD1PT1 0 = Normal operation 18 1 read-write RXPWDDIFF 0 = Normal operation 19 1 read-write RXPWDRX 0 = Normal operation 20 1 read-write RSVD2 Reserved. 21 11 read-only TX USB PHY Transmitter Control Register 0x10 32 read-write 0x10060607 0xFFFFFFFF D_CAL Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% 0 4 read-write RSVD0 Reserved. Note: This bit should remain clear. 4 4 read-write TXCAL45DN Decode to select a 45-Ohm resistance to the USB_DN output pin 8 4 read-write RSVD1 Reserved. Note: This bit should remain clear. 12 4 read-write TXCAL45DP Decode to select a 45-Ohm resistance to the USB_DP output pin 16 4 read-write RSVD2 Reserved. 20 6 read-only USBPHY_TX_EDGECTRL Controls the edge-rate of the current sensing transistors used in HS transmit 26 3 read-write RSVD5 Reserved. 29 3 read-only TX_SET USB PHY Transmitter Control Register 0x14 32 read-write 0x10060607 0xFFFFFFFF D_CAL Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% 0 4 read-write RSVD0 Reserved. Note: This bit should remain clear. 4 4 read-write TXCAL45DN Decode to select a 45-Ohm resistance to the USB_DN output pin 8 4 read-write RSVD1 Reserved. Note: This bit should remain clear. 12 4 read-write TXCAL45DP Decode to select a 45-Ohm resistance to the USB_DP output pin 16 4 read-write RSVD2 Reserved. 20 6 read-only USBPHY_TX_EDGECTRL Controls the edge-rate of the current sensing transistors used in HS transmit 26 3 read-write RSVD5 Reserved. 29 3 read-only TX_CLR USB PHY Transmitter Control Register 0x18 32 read-write 0x10060607 0xFFFFFFFF D_CAL Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% 0 4 read-write RSVD0 Reserved. Note: This bit should remain clear. 4 4 read-write TXCAL45DN Decode to select a 45-Ohm resistance to the USB_DN output pin 8 4 read-write RSVD1 Reserved. Note: This bit should remain clear. 12 4 read-write TXCAL45DP Decode to select a 45-Ohm resistance to the USB_DP output pin 16 4 read-write RSVD2 Reserved. 20 6 read-only USBPHY_TX_EDGECTRL Controls the edge-rate of the current sensing transistors used in HS transmit 26 3 read-write RSVD5 Reserved. 29 3 read-only TX_TOG USB PHY Transmitter Control Register 0x1C 32 read-write 0x10060607 0xFFFFFFFF D_CAL Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% 0 4 read-write RSVD0 Reserved. Note: This bit should remain clear. 4 4 read-write TXCAL45DN Decode to select a 45-Ohm resistance to the USB_DN output pin 8 4 read-write RSVD1 Reserved. Note: This bit should remain clear. 12 4 read-write TXCAL45DP Decode to select a 45-Ohm resistance to the USB_DP output pin 16 4 read-write RSVD2 Reserved. 20 6 read-only USBPHY_TX_EDGECTRL Controls the edge-rate of the current sensing transistors used in HS transmit 26 3 read-write RSVD5 Reserved. 29 3 read-only RX USB PHY Receiver Control Register 0x20 32 read-write 0 0xFFFFFFFF ENVADJ The ENVADJ field adjusts the trip point for the envelope detector 0 3 read-write RSVD0 Reserved. 3 1 read-only DISCONADJ The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 4 3 read-write RSVD1 Reserved. 7 15 read-only RXDBYPASS 0 = Normal operation 22 1 read-write RSVD2 Reserved. 23 9 read-only RX_SET USB PHY Receiver Control Register 0x24 32 read-write 0 0xFFFFFFFF ENVADJ The ENVADJ field adjusts the trip point for the envelope detector 0 3 read-write RSVD0 Reserved. 3 1 read-only DISCONADJ The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 4 3 read-write RSVD1 Reserved. 7 15 read-only RXDBYPASS 0 = Normal operation 22 1 read-write RSVD2 Reserved. 23 9 read-only RX_CLR USB PHY Receiver Control Register 0x28 32 read-write 0 0xFFFFFFFF ENVADJ The ENVADJ field adjusts the trip point for the envelope detector 0 3 read-write RSVD0 Reserved. 3 1 read-only DISCONADJ The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 4 3 read-write RSVD1 Reserved. 7 15 read-only RXDBYPASS 0 = Normal operation 22 1 read-write RSVD2 Reserved. 23 9 read-only RX_TOG USB PHY Receiver Control Register 0x2C 32 read-write 0 0xFFFFFFFF ENVADJ The ENVADJ field adjusts the trip point for the envelope detector 0 3 read-write RSVD0 Reserved. 3 1 read-only DISCONADJ The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 4 3 read-write RSVD1 Reserved. 7 15 read-only RXDBYPASS 0 = Normal operation 22 1 read-write RSVD2 Reserved. 23 9 read-only CTRL USB PHY General Control Register 0x30 32 read-write 0xC0200000 0xFFFFFFFF ENOTG_ID_CHG_IRQ Enable OTG_ID_CHG_IRQ. 0 1 read-write ENHOSTDISCONDETECT For host mode, enables high-speed disconnect detector 1 1 read-write ENIRQHOSTDISCON Enables interrupt for detection of disconnection to Device when in high-speed host mode 2 1 read-write HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in high-speed mode 3 1 read-write ENDEVPLUGINDETECT For device mode, enables 200-KOhm pullups for detecting connectivity to the host. 4 1 read-write DEVPLUGIN_POLARITY For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in 5 1 read-write OTG_ID_CHG_IRQ OTG ID change interrupt. Indicates the value of ID pin changed. 6 1 read-write ENOTGIDDETECT Enables circuit to detect resistance of MiniAB ID pin. 7 1 read-write RESUMEIRQSTICKY Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it 8 1 read-write ENIRQRESUMEDETECT Enables interrupt for detection of a non-J state on the USB line 9 1 read-write RESUME_IRQ Indicates that the host is sending a wake-up after suspend 10 1 read-write ENIRQDEVPLUGIN Enables interrupt for the detection of connectivity to the USB line. 11 1 read-write DEVPLUGIN_IRQ Indicates that the device is connected 12 1 read-write DATA_ON_LRADC Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. 13 1 read-write ENUTMILEVEL2 Enables UTMI+ Level2. This should be enabled if needs to support LS device 14 1 read-write ENUTMILEVEL3 Enables UTMI+ Level3 15 1 read-write ENIRQWAKEUP Enables interrupt for the wakeup events. 16 1 read-write WAKEUP_IRQ Indicates that there is a wakeup event 17 1 read-write ENAUTO_PWRON_PLL Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended 18 1 read-write ENAUTOCLR_CLKGATE Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended 19 1 read-write ENAUTOCLR_PHY_PWD Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended 20 1 read-write ENDPDMCHG_WKUP Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended 21 1 read-write ENIDCHG_WKUP Enables the feature to wakeup USB if ID is toggled when USB is suspended. 22 1 read-write ENVBUSCHG_WKUP Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. 23 1 read-write FSDLL_RST_EN Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. 24 1 read-write RSVD1 Reserved. 25 2 read-only OTG_ID_VALUE Almost same as OTGID_STATUS in USBPHYx_STATUS Register 27 1 read-only HOST_FORCE_LS_SE0 Forces the next FS packet that is transmitted to have a EOP with LS timing 28 1 read-write UTMI_SUSPENDM Used by the PHY to indicate a powered-down state 29 1 read-only CLKGATE Gate UTMI Clocks 30 1 read-write SFTRST Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers 31 1 read-write CTRL_SET USB PHY General Control Register 0x34 32 read-write 0xC0200000 0xFFFFFFFF ENOTG_ID_CHG_IRQ Enable OTG_ID_CHG_IRQ. 0 1 read-write ENHOSTDISCONDETECT For host mode, enables high-speed disconnect detector 1 1 read-write ENIRQHOSTDISCON Enables interrupt for detection of disconnection to Device when in high-speed host mode 2 1 read-write HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in high-speed mode 3 1 read-write ENDEVPLUGINDETECT For device mode, enables 200-KOhm pullups for detecting connectivity to the host. 4 1 read-write DEVPLUGIN_POLARITY For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in 5 1 read-write OTG_ID_CHG_IRQ OTG ID change interrupt. Indicates the value of ID pin changed. 6 1 read-write ENOTGIDDETECT Enables circuit to detect resistance of MiniAB ID pin. 7 1 read-write RESUMEIRQSTICKY Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it 8 1 read-write ENIRQRESUMEDETECT Enables interrupt for detection of a non-J state on the USB line 9 1 read-write RESUME_IRQ Indicates that the host is sending a wake-up after suspend 10 1 read-write ENIRQDEVPLUGIN Enables interrupt for the detection of connectivity to the USB line. 11 1 read-write DEVPLUGIN_IRQ Indicates that the device is connected 12 1 read-write DATA_ON_LRADC Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. 13 1 read-write ENUTMILEVEL2 Enables UTMI+ Level2. This should be enabled if needs to support LS device 14 1 read-write ENUTMILEVEL3 Enables UTMI+ Level3 15 1 read-write ENIRQWAKEUP Enables interrupt for the wakeup events. 16 1 read-write WAKEUP_IRQ Indicates that there is a wakeup event 17 1 read-write ENAUTO_PWRON_PLL Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended 18 1 read-write ENAUTOCLR_CLKGATE Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended 19 1 read-write ENAUTOCLR_PHY_PWD Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended 20 1 read-write ENDPDMCHG_WKUP Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended 21 1 read-write ENIDCHG_WKUP Enables the feature to wakeup USB if ID is toggled when USB is suspended. 22 1 read-write ENVBUSCHG_WKUP Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. 23 1 read-write FSDLL_RST_EN Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. 24 1 read-write RSVD1 Reserved. 25 2 read-only OTG_ID_VALUE Almost same as OTGID_STATUS in USBPHYx_STATUS Register 27 1 read-only HOST_FORCE_LS_SE0 Forces the next FS packet that is transmitted to have a EOP with LS timing 28 1 read-write UTMI_SUSPENDM Used by the PHY to indicate a powered-down state 29 1 read-only CLKGATE Gate UTMI Clocks 30 1 read-write SFTRST Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers 31 1 read-write CTRL_CLR USB PHY General Control Register 0x38 32 read-write 0xC0200000 0xFFFFFFFF ENOTG_ID_CHG_IRQ Enable OTG_ID_CHG_IRQ. 0 1 read-write ENHOSTDISCONDETECT For host mode, enables high-speed disconnect detector 1 1 read-write ENIRQHOSTDISCON Enables interrupt for detection of disconnection to Device when in high-speed host mode 2 1 read-write HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in high-speed mode 3 1 read-write ENDEVPLUGINDETECT For device mode, enables 200-KOhm pullups for detecting connectivity to the host. 4 1 read-write DEVPLUGIN_POLARITY For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in 5 1 read-write OTG_ID_CHG_IRQ OTG ID change interrupt. Indicates the value of ID pin changed. 6 1 read-write ENOTGIDDETECT Enables circuit to detect resistance of MiniAB ID pin. 7 1 read-write RESUMEIRQSTICKY Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it 8 1 read-write ENIRQRESUMEDETECT Enables interrupt for detection of a non-J state on the USB line 9 1 read-write RESUME_IRQ Indicates that the host is sending a wake-up after suspend 10 1 read-write ENIRQDEVPLUGIN Enables interrupt for the detection of connectivity to the USB line. 11 1 read-write DEVPLUGIN_IRQ Indicates that the device is connected 12 1 read-write DATA_ON_LRADC Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. 13 1 read-write ENUTMILEVEL2 Enables UTMI+ Level2. This should be enabled if needs to support LS device 14 1 read-write ENUTMILEVEL3 Enables UTMI+ Level3 15 1 read-write ENIRQWAKEUP Enables interrupt for the wakeup events. 16 1 read-write WAKEUP_IRQ Indicates that there is a wakeup event 17 1 read-write ENAUTO_PWRON_PLL Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended 18 1 read-write ENAUTOCLR_CLKGATE Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended 19 1 read-write ENAUTOCLR_PHY_PWD Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended 20 1 read-write ENDPDMCHG_WKUP Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended 21 1 read-write ENIDCHG_WKUP Enables the feature to wakeup USB if ID is toggled when USB is suspended. 22 1 read-write ENVBUSCHG_WKUP Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. 23 1 read-write FSDLL_RST_EN Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. 24 1 read-write RSVD1 Reserved. 25 2 read-only OTG_ID_VALUE Almost same as OTGID_STATUS in USBPHYx_STATUS Register 27 1 read-only HOST_FORCE_LS_SE0 Forces the next FS packet that is transmitted to have a EOP with LS timing 28 1 read-write UTMI_SUSPENDM Used by the PHY to indicate a powered-down state 29 1 read-only CLKGATE Gate UTMI Clocks 30 1 read-write SFTRST Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers 31 1 read-write CTRL_TOG USB PHY General Control Register 0x3C 32 read-write 0xC0200000 0xFFFFFFFF ENOTG_ID_CHG_IRQ Enable OTG_ID_CHG_IRQ. 0 1 read-write ENHOSTDISCONDETECT For host mode, enables high-speed disconnect detector 1 1 read-write ENIRQHOSTDISCON Enables interrupt for detection of disconnection to Device when in high-speed host mode 2 1 read-write HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in high-speed mode 3 1 read-write ENDEVPLUGINDETECT For device mode, enables 200-KOhm pullups for detecting connectivity to the host. 4 1 read-write DEVPLUGIN_POLARITY For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in 5 1 read-write OTG_ID_CHG_IRQ OTG ID change interrupt. Indicates the value of ID pin changed. 6 1 read-write ENOTGIDDETECT Enables circuit to detect resistance of MiniAB ID pin. 7 1 read-write RESUMEIRQSTICKY Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it 8 1 read-write ENIRQRESUMEDETECT Enables interrupt for detection of a non-J state on the USB line 9 1 read-write RESUME_IRQ Indicates that the host is sending a wake-up after suspend 10 1 read-write ENIRQDEVPLUGIN Enables interrupt for the detection of connectivity to the USB line. 11 1 read-write DEVPLUGIN_IRQ Indicates that the device is connected 12 1 read-write DATA_ON_LRADC Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. 13 1 read-write ENUTMILEVEL2 Enables UTMI+ Level2. This should be enabled if needs to support LS device 14 1 read-write ENUTMILEVEL3 Enables UTMI+ Level3 15 1 read-write ENIRQWAKEUP Enables interrupt for the wakeup events. 16 1 read-write WAKEUP_IRQ Indicates that there is a wakeup event 17 1 read-write ENAUTO_PWRON_PLL Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended 18 1 read-write ENAUTOCLR_CLKGATE Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended 19 1 read-write ENAUTOCLR_PHY_PWD Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended 20 1 read-write ENDPDMCHG_WKUP Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended 21 1 read-write ENIDCHG_WKUP Enables the feature to wakeup USB if ID is toggled when USB is suspended. 22 1 read-write ENVBUSCHG_WKUP Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. 23 1 read-write FSDLL_RST_EN Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. 24 1 read-write RSVD1 Reserved. 25 2 read-only OTG_ID_VALUE Almost same as OTGID_STATUS in USBPHYx_STATUS Register 27 1 read-only HOST_FORCE_LS_SE0 Forces the next FS packet that is transmitted to have a EOP with LS timing 28 1 read-write UTMI_SUSPENDM Used by the PHY to indicate a powered-down state 29 1 read-only CLKGATE Gate UTMI Clocks 30 1 read-write SFTRST Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers 31 1 read-write STATUS USB PHY Status Register 0x40 32 read-write 0 0xFFFFFFFF RSVD0 Reserved. 0 3 read-only HOSTDISCONDETECT_STATUS Indicates that the device has disconnected while in high-speed host mode. 3 1 read-only RSVD1 Reserved. 4 2 read-only DEVPLUGIN_STATUS Indicates that the device has been connected on the USB_DP and USB_DM lines. 6 1 read-only RSVD2 Reserved. 7 1 read-only OTGID_STATUS Indicates the results of ID pin on MiniAB plug 8 1 read-write RSVD3 Reserved. 9 1 read-only RESUME_STATUS Indicates that the host is sending a wake-up after suspend and has triggered an interrupt. 10 1 read-only RSVD4 Reserved. 11 21 read-only DEBUG USB PHY Debug Register 0x50 32 read-write 0x7F180000 0xFFFFFFFF OTGIDPIOLOCK Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value 0 1 read-write DEBUG_INTERFACE_HOLD Use holding registers to assist in timing for external UTMI interface. 1 1 read-write HSTPULLDOWN Set bit 3 to 1 to pull down 15-KOhm on USB_DP line 2 2 read-write ENHSTPULLDOWN Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown 4 2 read-write RSVD0 Reserved. 6 2 read-only TX2RXCOUNT Delay in between the end of transmit to the beginning of receive 8 4 read-write ENTX2RXCOUNT Set this bit to allow a countdown to transition in between TX and RX. 12 1 read-write RSVD1 Reserved. 13 3 read-only SQUELCHRESETCOUNT Delay in between the detection of squelch to the reset of high-speed RX. 16 5 read-write RSVD2 Reserved. 21 3 read-only ENSQUELCHRESET Set bit to allow squelch to reset high-speed receive. 24 1 read-write SQUELCHRESETLENGTH Duration of RESET in terms of the number of 480-MHz cycles. 25 4 read-write HOST_RESUME_DEBUG Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. 29 1 read-write CLKGATE Gate Test Clocks 30 1 read-write RSVD3 Reserved. 31 1 read-only DEBUG_SET USB PHY Debug Register 0x54 32 read-write 0x7F180000 0xFFFFFFFF OTGIDPIOLOCK Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value 0 1 read-write DEBUG_INTERFACE_HOLD Use holding registers to assist in timing for external UTMI interface. 1 1 read-write HSTPULLDOWN Set bit 3 to 1 to pull down 15-KOhm on USB_DP line 2 2 read-write ENHSTPULLDOWN Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown 4 2 read-write RSVD0 Reserved. 6 2 read-only TX2RXCOUNT Delay in between the end of transmit to the beginning of receive 8 4 read-write ENTX2RXCOUNT Set this bit to allow a countdown to transition in between TX and RX. 12 1 read-write RSVD1 Reserved. 13 3 read-only SQUELCHRESETCOUNT Delay in between the detection of squelch to the reset of high-speed RX. 16 5 read-write RSVD2 Reserved. 21 3 read-only ENSQUELCHRESET Set bit to allow squelch to reset high-speed receive. 24 1 read-write SQUELCHRESETLENGTH Duration of RESET in terms of the number of 480-MHz cycles. 25 4 read-write HOST_RESUME_DEBUG Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. 29 1 read-write CLKGATE Gate Test Clocks 30 1 read-write RSVD3 Reserved. 31 1 read-only DEBUG_CLR USB PHY Debug Register 0x58 32 read-write 0x7F180000 0xFFFFFFFF OTGIDPIOLOCK Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value 0 1 read-write DEBUG_INTERFACE_HOLD Use holding registers to assist in timing for external UTMI interface. 1 1 read-write HSTPULLDOWN Set bit 3 to 1 to pull down 15-KOhm on USB_DP line 2 2 read-write ENHSTPULLDOWN Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown 4 2 read-write RSVD0 Reserved. 6 2 read-only TX2RXCOUNT Delay in between the end of transmit to the beginning of receive 8 4 read-write ENTX2RXCOUNT Set this bit to allow a countdown to transition in between TX and RX. 12 1 read-write RSVD1 Reserved. 13 3 read-only SQUELCHRESETCOUNT Delay in between the detection of squelch to the reset of high-speed RX. 16 5 read-write RSVD2 Reserved. 21 3 read-only ENSQUELCHRESET Set bit to allow squelch to reset high-speed receive. 24 1 read-write SQUELCHRESETLENGTH Duration of RESET in terms of the number of 480-MHz cycles. 25 4 read-write HOST_RESUME_DEBUG Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. 29 1 read-write CLKGATE Gate Test Clocks 30 1 read-write RSVD3 Reserved. 31 1 read-only DEBUG_TOG USB PHY Debug Register 0x5C 32 read-write 0x7F180000 0xFFFFFFFF OTGIDPIOLOCK Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value 0 1 read-write DEBUG_INTERFACE_HOLD Use holding registers to assist in timing for external UTMI interface. 1 1 read-write HSTPULLDOWN Set bit 3 to 1 to pull down 15-KOhm on USB_DP line 2 2 read-write ENHSTPULLDOWN Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown 4 2 read-write RSVD0 Reserved. 6 2 read-only TX2RXCOUNT Delay in between the end of transmit to the beginning of receive 8 4 read-write ENTX2RXCOUNT Set this bit to allow a countdown to transition in between TX and RX. 12 1 read-write RSVD1 Reserved. 13 3 read-only SQUELCHRESETCOUNT Delay in between the detection of squelch to the reset of high-speed RX. 16 5 read-write RSVD2 Reserved. 21 3 read-only ENSQUELCHRESET Set bit to allow squelch to reset high-speed receive. 24 1 read-write SQUELCHRESETLENGTH Duration of RESET in terms of the number of 480-MHz cycles. 25 4 read-write HOST_RESUME_DEBUG Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. 29 1 read-write CLKGATE Gate Test Clocks 30 1 read-write RSVD3 Reserved. 31 1 read-only DEBUG0_STATUS UTMI Debug Status Register 0 0x60 32 read-only 0 0xFFFFFFFF LOOP_BACK_FAIL_COUNT Running count of the failed pseudo-random generator loopback 0 16 read-only UTMI_RXERROR_FAIL_COUNT Running count of the UTMI_RXERROR. 16 10 read-only SQUELCH_COUNT Running count of the squelch reset instead of normal end for HS RX. 26 6 read-only DEBUG1 UTMI Debug Status Register 1 0x70 32 read-write 0x1000 0xFFFFFFFF RSVD0 Reserved. Note: This bit should remain clear. 0 13 read-write ENTAILADJVD Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% 13 2 read-write RSVD1 Reserved. 15 17 read-only DEBUG1_SET UTMI Debug Status Register 1 0x74 32 read-write 0x1000 0xFFFFFFFF RSVD0 Reserved. Note: This bit should remain clear. 0 13 read-write ENTAILADJVD Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% 13 2 read-write RSVD1 Reserved. 15 17 read-only DEBUG1_CLR UTMI Debug Status Register 1 0x78 32 read-write 0x1000 0xFFFFFFFF RSVD0 Reserved. Note: This bit should remain clear. 0 13 read-write ENTAILADJVD Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% 13 2 read-write RSVD1 Reserved. 15 17 read-only DEBUG1_TOG UTMI Debug Status Register 1 0x7C 32 read-write 0x1000 0xFFFFFFFF RSVD0 Reserved. Note: This bit should remain clear. 0 13 read-write ENTAILADJVD Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% 13 2 read-write RSVD1 Reserved. 15 17 read-only VERSION UTMI RTL Version 0x80 32 read-only 0x4030000 0xFFFFFFFF STEP Fixed read-only value reflecting the stepping of the RTL version. 0 16 read-only MINOR Fixed read-only value reflecting the MINOR field of the RTL version. 16 8 read-only MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 24 8 read-only CSU CSU registers CSU CSU_ 0x400DC000 0 0x35C registers CSU 49 32 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 CSL%s Config security level register 0 32 read-write 0x330033 0xFFFFFFFF SUR_S2 Secure user read access control for the second slave 0 1 read-write SUR_S2_0 The secure user read access is disabled for the second slave. 0 SUR_S2_1 The secure user read access is enabled for the second slave. 0x1 SSR_S2 Secure supervisor read access control for the second slave 1 1 read-write SSR_S2_0 The secure supervisor read access is disabled for the second slave. 0 SSR_S2_1 The secure supervisor read access is enabled for the second slave. 0x1 NUR_S2 Non-secure user read access control for the second slave 2 1 read-write NUR_S2_0 The non-secure user read access is disabled for the second slave. 0 NUR_S2_1 The non-secure user read access is enabled for the second slave. 0x1 NSR_S2 Non-secure supervisor read access control for the second slave 3 1 read-write NSR_S2_0 The non-secure supervisor read access is disabled for the second slave. 0 NSR_S2_1 The non-secure supervisor read access is enabled for the second slave. 0x1 SUW_S2 Secure user write access control for the second slave 4 1 read-write SUW_S2_0 The secure user write access is disabled for the second slave. 0 SUW_S2_1 The secure user write access is enabled for the second slave. 0x1 SSW_S2 Secure supervisor write access control for the second slave 5 1 read-write SSW_S2_0 The secure supervisor write access is disabled for the second slave. 0 SSW_S2_1 The secure supervisor write access is enabled for the second slave. 0x1 NUW_S2 Non-secure user write access control for the second slave 6 1 read-write NUW_S2_0 The non-secure user write access is disabled for the second slave. 0 NUW_S2_1 The non-secure user write access is enabled for the second slave. 0x1 NSW_S2 Non-secure supervisor write access control for the second slave 7 1 read-write NSW_S2_0 The non-secure supervisor write access is disabled for the second slave. 0 NSW_S2_1 The non-secure supervisor write access is enabled for the second slave. 0x1 LOCK_S2 The lock bit corresponding to the second slave. It is written by the secure software. 8 1 read-write LOCK_S2_0 Not locked. Bits 7-0 can be written by the software. 0 LOCK_S2_1 Bits 7-0 are locked and cannot be written by the software 0x1 SUR_S1 Secure user read access control for the first slave 16 1 read-write SUR_S1_0 The secure user read access is disabled for the first slave. 0 SUR_S1_1 The secure user read access is enabled for the first slave. 0x1 SSR_S1 Secure supervisor read access control for the first slave 17 1 read-write SSR_S1_0 The secure supervisor read access is disabled for the first slave. 0 SSR_S1_1 The secure supervisor read access is enabled for the first slave. 0x1 NUR_S1 Non-secure user read access control for the first slave 18 1 read-write NUR_S1_0 The non-secure user read access is disabled for the first slave. 0 NUR_S1_1 The non-secure user read access is enabled for the first slave. 0x1 NSR_S1 Non-secure supervisor read access control for the first slave 19 1 read-write NSR_S1_0 The non-secure supervisor read access is disabled for the first slave. 0 NSR_S1_1 The non-secure supervisor read access is enabled for the first slave. 0x1 SUW_S1 Secure user write access control for the first slave 20 1 read-write SUW_S1_0 The secure user write access is disabled for the first slave. 0 SUW_S1_1 The secure user write access is enabled for the first slave. 0x1 SSW_S1 Secure supervisor write access control for the first slave 21 1 read-write SSW_S1_0 The secure supervisor write access is disabled for the first slave. 0 SSW_S1_1 The secure supervisor write access is enabled for the first slave. 0x1 NUW_S1 Non-secure user write access control for the first slave 22 1 read-write NUW_S1_0 The non-secure user write access is disabled for the first slave. 0 NUW_S1_1 The non-secure user write access is enabled for the first slave. 0x1 NSW_S1 Non-secure supervisor write access control for the first slave 23 1 read-write NSW_S1_0 The non-secure supervisor write access is disabled for the first slave. 0 NSW_S1_1 The non-secure supervisor write access is enabled for the first slave 0x1 LOCK_S1 The lock bit corresponding to the first slave. It is written by the secure software. 24 1 read-write LOCK_S1_0 Not locked. The bits 16-23 can be written by the software. 0 LOCK_S1_1 The bits 16-23 are locked and can't be written by the software. 0x1 HP0 HP0 register 0x200 32 read-write 0 0xFFFFFFFF HP_DMA Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the eDMA 2 1 read-write HP_DMA_0 The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0 HP_DMA_1 The HP register bit is routed to the csu_hprot1 output for the corresponding master. 0x1 L_DMA Lock bit set by the TZ software for the eDMA 3 1 read-write L_DMA_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_DMA_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HP_LCDIF Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the LCDIF 4 1 read-write HP_LCDIF_0 The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0 HP_LCDIF_1 The HP register bit is routed to the csu_hprot1 output for the corresponding master. 0x1 L_LCDIF Lock bit set by the TZ software for the LCDIF 5 1 read-write L_LCDIF_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_LCDIF_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HP_CSI Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the CSI 6 1 read-write HP_CSI_0 The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0 HP_CSI_1 The HP register bit is routed to the csu_hprot1 output for the corresponding master. 0x1 L_CSI Lock bit set by the TZ software for the CSI 7 1 read-write L_CSI_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_CSI_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HP_PXP Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the PXP 8 1 read-write HP_PXP_0 The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0 HP_PXP_1 The HP register bit is routed to the csu_hprot1 output for the corresponding master. 0x1 L_PXP Lock bit set by the TZ software for the PXP 9 1 read-write L_PXP_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_PXP_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HP_DCP Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the DCP 10 1 read-write HP_DCP_0 The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0 HP_DCP_1 The HP register bit is routed to the csu_hprot1 output for the corresponding master. 0x1 L_DCP Lock bit set by the TZ software for the DCP 11 1 read-write L_DCP_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_DCP_1 Lock-the adjacent (next lower) bit cannot be written by the software. 0x1 HP_ENET Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the ENET 14 1 read-write HP_ENET_0 The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0 HP_ENET_1 The HP register bit is routed to the csu_hprot1 output for the corresponding master. 0x1 L_ENET Lock bit set by the TZ software for the ENET 15 1 read-write L_ENET_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_ENET_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HP_USDHC1 Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC1 16 1 read-write HP_USDHC1_0 The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0 HP_USDHC1_1 The HP register bit is routed to the csu_hprot1 output for the corresponding master. 0x1 L_USDHC1 Lock bit set by the TZ software for the USDHC1 17 1 read-write L_USDHC1_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_USDHC1_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HP_USDHC2 Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC2 18 1 read-write HP_USDHC2_0 The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0 HP_USDHC2_1 The HP register bit is routed to the csu_hprot1 output for the corresponding master. 0x1 L_USDHC2 Lock bit set by the TZ software for the USDHC2 19 1 read-write L_USDHC2_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_USDHC2_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HP_TPSMP Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the TPSMP 20 1 read-write HP_TPSMP_0 The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0 HP_TPSMP_1 The HP register bit is routed to the csu_hprot1 output for the corresponding master. 0x1 L_TPSMP Lock bit set by the TZ software for the TPSMP 21 1 read-write L_TPSMP_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_TPSMP_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HP_USB Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USB 22 1 read-write HP_USB_0 The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0 HP_USB_1 The HP register bit is routed to the csu_hprot1 output for the corresponding master. 0x1 L_USB Lock bit set by the TZ software for the USB 23 1 read-write L_USB_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_USB_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 SA Secure access register 0x218 32 read-write 0 0xFFFFFFFF NSA_DMA Non-secure access policy indicator bit 2 1 read-write NSA_DMA_0 Secure access for the corresponding type-1 master 0 NSA_DMA_1 Non-secure access for the corresponding type-1 master 0x1 L_DMA Lock bit set by the TZ software for the eDMA 3 1 read-write L_DMA_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_DMA_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 NSA_LCDIF Non-secure access policy indicator bit 4 1 read-write NSA_LCDIF_0 Secure access for the corresponding type-1 master 0 NSA_LCDIF_1 Non-secure access for the corresponding type-1 master 0x1 L_LCDIF Lock bit set by the TZ software for the LCDIF 5 1 read-write L_LCDIF_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_LCDIF_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 NSA_CSI Non-secure access policy indicator bit 6 1 read-write NSA_CSI_0 Secure access for the corresponding type-1 master 0 NSA_CSI_1 Non-secure access for the corresponding type-1 master 0x1 L_CSI Lock bit set by the TZ software for the CSI 7 1 read-write L_CSI_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_CSI_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 NSA_PXP Non-Secure Access Policy indicator bit 8 1 read-write NSA_PXP_0 Secure access for the corresponding type-1 master 0 NSA_PXP_1 Non-secure access for the corresponding type-1 master 0x1 L_PXP Lock bit set by the TZ software for the PXP 9 1 read-write L_PXP_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_PXP_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 NSA_DCP Non-secure access policy indicator bit 10 1 read-write NSA_DCP_0 Secure access for the corresponding type-1 master 0 NSA_DCP_1 Non-secure access for the corresponding type-1 master 0x1 L_DCP Lock bit set by the TZ software for the DCP 11 1 read-write L_DCP_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_DCP_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 NSA_ENET Non-secure access policy indicator bit 14 1 read-write NSA_ENET_0 Secure access for the corresponding type-1 master 0 NSA_ENET_1 Non-secure access for the corresponding type-1 master 0x1 L_ENET Lock bit set by the TZ software for the ENET1 and ENET2 15 1 read-write L_ENET_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_ENET_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 NSA_USDHC1 Non-secure access policy indicator bit 16 1 read-write NSA_USDHC1_0 Secure access for the corresponding type-1 master 0 NSA_USDHC1_1 Non-secure access for the corresponding type-1 master 0x1 L_USDHC1 Lock bit set by the TZ software for the USDHC1 17 1 read-write L_USDHC1_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_USDHC1_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 NSA_USDHC2 Non-secure access policy indicator bit 18 1 read-write NSA_USDHC2_0 Secure access for the corresponding type-1 master 0 NSA_USDHC2_1 Non-secure access for the corresponding type-1 master 0x1 L_USDHC2 Lock bit set by the TZ software for the USDHC2 19 1 read-write L_USDHC2_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_USDHC2_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 NSA_TPSMP Non-secure access policy indicator bit 20 1 read-write NSA_TPSMP_0 Secure access for the corresponding type-1 master 0 NSA_TPSMP_1 Non-secure access for the corresponding type-1 master 0x1 L_TPSMP Lock bit set by the TZ software for the TPSMP 21 1 read-write L_TPSMP_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_TPSMP_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 NSA_USB Non-secure access policy indicator bit 22 1 read-write NSA_USB_0 Secure access for the corresponding type-1 master 0 NSA_USB_1 Non-secure access for the corresponding type-1 master 0x1 L_USB Lock bit set by the TZ software for the USB 23 1 read-write L_USB_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_USB_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HPCONTROL0 HPCONTROL0 register 0x358 32 read-write 0 0xFFFFFFFF HPC_DMA Indicates the privilege/user mode for the eDMA 2 1 read-write HPC_DMA_0 User mode for the corresponding master 0 HPC_DMA_1 Supervisor mode for the corresponding master 0x1 L_DMA Lock bit set by the TZ software for the eDMA 3 1 read-write L_DMA_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_DMA_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HPC_LCDIF Indicates the privilege/user mode for the LCDIF 4 1 read-write HPC_LCDIF_0 User mode for the corresponding master 0 HPC_LCDIF_1 Supervisor mode for the corresponding master 0x1 L_LCDIF Lock bit set by the TZ software for the LCDIF 5 1 read-write L_LCDIF_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_LCDIF_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HPC_CSI Indicates the privilege/user mode for the CSI 6 1 read-write HPC_CSI_0 User mode for the corresponding master 0 HPC_CSI_1 Supervisor mode for the corresponding master 0x1 L_CSI Lock bit set by the TZ software for the CSI 7 1 read-write L_CSI_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_CSI_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HPC_PXP Indicates the privilege/user mode for the PXP 8 1 read-write HPC_PXP_0 User mode for the corresponding master 0 HPC_PXP_1 Supervisor mode for the corresponding master 0x1 L_PXP Lock bit set by the TZ software for the PXP 9 1 read-write L_PXP_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_PXP_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HPC_DCP Indicates the privilege/user mode for the DCP 10 1 read-write HPC_DCP_0 User mode for the corresponding master 0 HPC_DCP_1 Supervisor mode for the corresponding master 0x1 L_DCP Lock bit set by the TZ software for the DCP 11 1 read-write L_DCP_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_DCP_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HPC_ENET Indicates the privilege/user mode for the ENET 14 1 read-write HPC_ENET_0 User mode for the corresponding master 0 HPC_ENET_1 Supervisor mode for the corresponding master 0x1 L_ENET Lock bit set by the TZ software for the ENET 15 1 read-write L_ENET_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_ENET_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HPC_USDHC1 Indicates the privilege/user mode for the USDHC1 16 1 read-write HPC_USDHC1_0 User mode for the corresponding master 0 HPC_USDHC1_1 Supervisor mode for the corresponding master 0x1 L_USDHC1 Lock bit set by the TZ software for the USDHC1 17 1 read-write L_USDHC1_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_USDHC1_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HPC_USDHC2 Indicates the privilege/user mode for the USDHC2 18 1 read-write HPC_USDHC2_0 User mode for the corresponding master 0 HPC_USDHC2_1 Supervisor mode for the corresponding master 0x1 L_USDHC2 Lock bit set by the TZ software for the USDHC2. 19 1 read-write L_USDHC2_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_USDHC2_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HPC_TPSMP Indicates the privilege/user mode for the TPSMP 20 1 read-write HPC_TPSMP_0 User mode for the corresponding master 0 HPC_TPSMP_1 Supervisor mode for the corresponding master 0x1 L_TPSMP Lock bit set by the TZ software for the TPSMP. 21 1 read-write L_TPSMP_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_TPSMP_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 HPC_USB Indicates the privilege/user mode for the USB 22 1 read-write HPC_USB_0 User mode for the corresponding master 0 HPC_USB_1 Supervisor mode for the corresponding master 0x1 L_USB Lock bit set by the TZ software for the USB. 23 1 read-write L_USB_0 No lock-the adjacent (next lower) bit can be written by the software. 0 L_USB_1 Lock-the adjacent (next lower) bit can't be written by the software. 0x1 USB USB USB USB_ 0x400E4000 0 0x1E0 registers USB_OTG1 25 ID Identification register 0 32 read-only 0xE4A1FA05 0xFFFFFFFF ID Configuration number 0 6 read-only NID Complement version of ID 8 6 read-only REVISION Revision number of the controller core. 16 8 read-only HWGENERAL Hardware General 0x4 32 read-only 0x35 0xFFFFFFFF PHYW Data width of the transciever connected to the controller core. PHYW bit reset value is 4 2 read-only PHYW_0 8 bit wide data bus Software non-programmable 0 PHYW_1 16 bit wide data bus Software non-programmable 0x1 PHYW_2 Reset to 8 bit wide data bus Software programmable 0x2 PHYW_3 Reset to 16 bit wide data bus Software programmable 0x3 PHYM Transciever type 6 3 read-only PHYM_0 UTMI/UMTI+ 0 PHYM_1 ULPI DDR 0x1 PHYM_2 ULPI 0x2 PHYM_3 Serial Only 0x3 PHYM_4 Software programmable - reset to UTMI/UTMI+ 0x4 PHYM_5 Software programmable - reset to ULPI DDR 0x5 PHYM_6 Software programmable - reset to ULPI 0x6 PHYM_7 Software programmable - reset to Serial 0x7 SM Serial interface mode capability 9 2 read-only SM_0 No Serial Engine, always use parallel signalling. 0 SM_1 Serial Engine present, always use serial signalling for FS/LS. 0x1 SM_2 Software programmable - Reset to use parallel signalling for FS/LS 0x2 SM_3 Software programmable - Reset to use serial signalling for FS/LS 0x3 HWHOST Host Hardware Parameters 0x8 32 read-only 0x10020001 0xFFFFFFFF HC Host Capable. Indicating whether host operation mode is supported or not. 0 1 read-only HC_0 Not supported 0 HC_1 Supported 0x1 NPORT The Nmber of downstream ports supported by the host controller is (NPORT+1) 1 3 read-only HWDEVICE Device Hardware Parameters 0xC 32 read-only 0x11 0xFFFFFFFF DC Device Capable. Indicating whether device operation mode is supported or not. 0 1 read-only DC_0 Not supported 0 DC_1 Supported 0x1 DEVEP Device Endpoint Number 1 5 read-only HWTXBUF TX Buffer Hardware Parameters 0x10 32 read-only 0x80080B08 0xFFFFFFFF TXBURST Default burst size for memory to TX buffer transfer 0 8 read-only TXCHANADD TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes 16 8 read-only HWRXBUF RX Buffer Hardware Parameters 0x14 32 read-only 0x808 0xFFFFFFFF RXBURST Default burst size for memory to RX buffer transfer 0 8 read-only RXADD Buffer total size for all receive endpoints is (2^RXADD) 8 8 read-only GPTIMER0LD General Purpose Timer #0 Load 0x80 32 read-write 0 0xFFFFFFFF GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' 0 24 read-write GPTIMER0CTRL General Purpose Timer #0 Controller 0x84 32 read-write 0 0xFFFFFFFF GPTCNT General Purpose Timer Counter. This field is the count value of the countdown timer. 0 24 read-write GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again 24 1 read-write GPTMODE_0 One Shot Mode 0 GPTMODE_1 Repeat Mode 0x1 GPTRST General Purpose Timer Reset 30 1 read-write GPTRST_0 No action 0 GPTRST_1 Load counter value from GPTLD bits in n_GPTIMER0LD 0x1 GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 31 1 read-write GPTRUN_0 Stop counting 0 GPTRUN_1 Run 0x1 GPTIMER1LD General Purpose Timer #1 Load 0x88 32 read-write 0 0xFFFFFFFF GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' 0 24 read-write GPTIMER1CTRL General Purpose Timer #1 Controller 0x8C 32 read-write 0 0xFFFFFFFF GPTCNT General Purpose Timer Counter. This field is the count value of the countdown timer. 0 24 read-write GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software 24 1 read-write GPTMODE_0 One Shot Mode 0 GPTMODE_1 Repeat Mode 0x1 GPTRST General Purpose Timer Reset 30 1 read-write GPTRST_0 No action 0 GPTRST_1 Load counter value from GPTLD bits in USB_n_GPTIMER0LD 0x1 GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 31 1 read-write GPTRUN_0 Stop counting 0 GPTRUN_1 Run 0x1 SBUSCFG System Bus Config 0x90 32 read-write 0x2 0xFFFFFFFF AHBBRST AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority) 0 3 read-write AHBBRST_0 Incremental burst of unspecified length only 0 AHBBRST_1 INCR4 burst, then single transfer 0x1 AHBBRST_2 INCR8 burst, INCR4 burst, then single transfer 0x2 AHBBRST_3 INCR16 burst, INCR8 burst, INCR4 burst, then single transfer 0x3 AHBBRST_5 INCR4 burst, then incremental burst of unspecified length 0x5 AHBBRST_6 INCR8 burst, INCR4 burst, then incremental burst of unspecified length 0x6 AHBBRST_7 INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length 0x7 CAPLENGTH Capability Registers Length 0x100 8 read-only 0x40 0xFF CAPLENGTH These bits are used as an offset to add to register base to find the beginning of the Operational Register 0 8 read-only HCIVERSION Host Controller Interface Version 0x102 16 read-only 0x100 0xFFFF HCIVERSION Host Controller Interface Version Number Default value is '10h', which means EHCI rev1.0. 0 16 read-only HCSPARAMS Host Controller Structural Parameters 0x104 32 read-only 0x10011 0xFFFFFFFF N_PORTS Number of downstream ports 0 4 read-only PPC Port Power Control This field indicates whether the host controller implementation includes port power control 4 1 read-only N_PCC Number of Ports per Companion Controller This field indicates the number of ports supported per internal Companion Controller 8 4 read-only N_CC Number of Companion Controller (N_CC) 12 4 read-only N_CC_0 There is no internal Companion Controller and port-ownership hand-off is not supported. 0 N_CC_1 There are internal companion controller(s) and port-ownership hand-offs is supported. 0x1 PI Port Indicators (P INDICATOR) This bit indicates whether the ports support port indicator control 16 1 read-only N_PTT Number of Ports per Transaction Translator (N_PTT) 20 4 read-only N_TT Number of Transaction Translators (N_TT) 24 4 read-only HCCPARAMS Host Controller Capability Parameters 0x108 32 read-only 0x6 0xFFFFFFFF ADC 64-bit Addressing Capability This bit is set '0b' in all controller core, no 64-bit addressing capability is supported 0 1 read-only PFL Programmable Frame List Flag If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller 1 1 read-only ASP Asynchronous Schedule Park Capability If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule 2 1 read-only IST Isochronous Scheduling Threshold 4 4 read-only EECP EHCI Extended Capabilities Pointer 8 8 read-only DCIVERSION Device Controller Interface Version 0x120 16 read-only 0x1 0xFFFF DCIVERSION Device Controller Interface Version Number Default value is '01h', which means rev0.1. 0 16 read-only DCCPARAMS Device Controller Capability Parameters 0x124 32 read-only 0x188 0xFFFFFFFF DEN Device Endpoint Number This field indicates the number of endpoints built into the device controller 0 5 read-only DC Device Capable When this bit is 1, this controller is capable of operating as a USB 2.0 device. 7 1 read-only HC Host Capable When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2 8 1 read-only USBCMD USB Command Register 0x140 32 read-write 0x80000 0xFFFFFFFF RS Run/Stop (RS) - Read/Write 0 1 read-write RST Controller Reset (RESET) - Read/Write 1 1 read-write FS_1 See description at bit 15 2 2 read-write PSE Periodic Schedule Enable- Read/Write 4 1 read-write PSE_0 Do not process the Periodic Schedule 0 PSE_1 Use the PERIODICLISTBASE register to access the Periodic Schedule. 0x1 ASE Asynchronous Schedule Enable - Read/Write 5 1 read-write ASE_0 Do not process the Asynchronous Schedule. 0 ASE_1 Use the ASYNCLISTADDR register to access the Asynchronous Schedule. 0x1 IAA Interrupt on Async Advance Doorbell - Read/Write 6 1 read-write ASP Asynchronous Schedule Park Mode Count - Read/Write 8 2 read-write ASPE Asynchronous Schedule Park Mode Enable - Read/Write 11 1 read-write SUTW Setup TripWire - Read/Write 13 1 read-write ATDTW Add dTD TripWire - Read/Write 14 1 read-write FS_2 Frame List Size - (Read/Write or Read Only) 15 1 read-write FS_2_0 1024 elements (4096 bytes) Default value 0 FS_2_1 512 elements (2048 bytes) 0x1 ITC Interrupt Threshold Control -Read/Write 16 8 read-write ITC_0 Immediate (no threshold) 0 ITC_1 1 micro-frame 0x1 ITC_2 2 micro-frames 0x2 ITC_4 4 micro-frames 0x4 ITC_8 8 micro-frames 0x8 ITC_16 16 micro-frames 0x10 ITC_32 32 micro-frames 0x20 ITC_64 64 micro-frames 0x40 USBSTS USB Status Register 0x144 32 read-write 0 0xFFFFFFFF UI USB Interrupt (USBINT) - R/WC 0 1 read-write UEI USB Error Interrupt (USBERRINT) - R/WC 1 1 read-write PCI Port Change Detect - R/WC 2 1 read-write FRI Frame List Rollover - R/WC 3 1 read-write SEI System Error- R/WC 4 1 read-write AAI Interrupt on Async Advance - R/WC 5 1 read-write URI USB Reset Received - R/WC 6 1 read-write SRI SOF Received - R/WC 7 1 read-write SLI DCSuspend - R/WC 8 1 read-write ULPII ULPI Interrupt - R/WC 10 1 read-write HCH HCHaIted - Read Only 12 1 read-write RCL Reclamation - Read Only 13 1 read-write PS Periodic Schedule Status - Read Only 14 1 read-write AS Asynchronous Schedule Status - Read Only 15 1 read-write NAKI NAK Interrupt Bit--RO 16 1 read-only TI0 General Purpose Timer Interrupt 0(GPTINT0)--R/WC 24 1 read-write TI1 General Purpose Timer Interrupt 1(GPTINT1)--R/WC 25 1 read-write USBINTR Interrupt Enable Register 0x148 32 read-write 0 0xFFFFFFFF UE USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt 0 1 read-write UEE USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt 1 1 read-write PCE Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt 2 1 read-write FRE Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt 3 1 read-write SEE System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt 4 1 read-write AAE Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt 5 1 read-write URE USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt 6 1 read-write SRE SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt 7 1 read-write SLE Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt 8 1 read-write ULPIE ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt 10 1 read-write NAKE NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt 16 1 read-write UAIE USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold 18 1 read-write UPIE USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold 19 1 read-write TIE0 General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt 24 1 read-write TIE1 General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt 25 1 read-write FRINDEX USB Frame Index 0x14C 32 read-write 0 0xFFFFFFFF FRINDEX Frame Index 0 14 read-write FRINDEX_0 (1024) 12 0 FRINDEX_1 (512) 11 0x1 FRINDEX_2 (256) 10 0x2 FRINDEX_3 (128) 9 0x3 FRINDEX_4 (64) 8 0x4 FRINDEX_5 (32) 7 0x5 FRINDEX_6 (16) 6 0x6 FRINDEX_7 (8) 5 0x7 DEVICEADDR Device Address DEVICEADDR_PERIODICLISTBASE 0x154 32 read-write 0 0xFFFFFFFF USBADRA Device Address Advance 24 1 read-write USBADR Device Address. These bits correspond to the USB device address 25 7 read-write PERIODICLISTBASE Frame List Base Address DEVICEADDR_PERIODICLISTBASE 0x154 32 read-write 0 0xFFFFFFFF BASEADR Base Address (Low) 12 20 read-write ASYNCLISTADDR Next Asynch. Address ASYNCLISTADDR_ENDPTLISTADDR 0x158 32 read-write 0 0xFFFFFFFF ASYBASE Link Pointer Low (LPL) 5 27 read-write ENDPTLISTADDR Endpoint List Address ASYNCLISTADDR_ENDPTLISTADDR 0x158 32 read-write 0 0xFFFFFFFF EPBASE Endpoint List Pointer(Low) 11 21 read-write BURSTSIZE Programmable Burst Size 0x160 32 read-write 0x808 0xFFFFFFFF RXPBURST Programmable RX Burst Size 0 8 read-write TXPBURST Programmable TX Burst Size 8 9 read-write TXFILLTUNING TX FIFO Fill Tuning 0x164 32 read-write 0 0xFFFFFFFF TXSCHOH Scheduler Overhead 0 8 read-write TXSCHHEALTH Scheduler Health Counter 8 5 read-write TXFIFOTHRES FIFO Burst Threshold 16 6 read-write ENDPTNAK Endpoint NAK 0x178 32 read-write 0 0xFFFFFFFF EPRN RX Endpoint NAK - R/WC 0 8 read-write EPTN TX Endpoint NAK - R/WC 16 8 read-write ENDPTNAKEN Endpoint NAK Enable 0x17C 32 read-write 0 0xFFFFFFFF EPRNE RX Endpoint NAK Enable - R/W 0 8 read-write EPTNE TX Endpoint NAK Enable - R/W 16 8 read-write CONFIGFLAG Configure Flag Register 0x180 32 read-only 0x1 0xFFFFFFFF CF Configure Flag Host software sets this bit as the last action in its process of configuring the Host Controller 0 1 read-only CF_0 Port routing control logic default-routes each port to an implementation dependent classic host controller. 0 CF_1 Port routing control logic default-routes all ports to this host controller. 0x1 PORTSC1 Port Status & Control 0x184 32 read-write 0x10000000 0xFFFFFFFF CCS Current Connect Status-Read Only 0 1 read-only CSC Connect Status Change-R/WC 1 1 read-write PE Port Enabled/Disabled-Read/Write 2 1 read-write PEC Port Enable/Disable Change-R/WC 3 1 read-write OCA Over-current Active-Read Only 4 1 read-only OCA_0 This port does not have an over-current condition. 0 OCA_1 This port currently has an over-current condition 0x1 OCC Over-current Change-R/WC 5 1 read-write FPR Force Port Resume -Read/Write 6 1 read-write SUSP Suspend - Read/Write or Read Only 7 1 read-write PR Port Reset - Read/Write or Read Only 8 1 read-write HSP High-Speed Port - Read Only 9 1 read-only LS Line Status-Read Only 10 2 read-write LS_0 SE0 0 LS_1 K-state 0x1 LS_2 J-state 0x2 LS_3 Undefined 0x3 PP Port Power (PP)-Read/Write or Read Only 12 1 read-write PO Port Owner-Read/Write 13 1 read-write PIC Port Indicator Control - Read/Write 14 2 read-write PIC_0 Port indicators are off 0 PIC_1 Amber 0x1 PIC_2 Green 0x2 PIC_3 Undefined 0x3 PTC Port Test Control - Read/Write 16 4 read-write PTC_0 TEST_MODE_DISABLE 0 PTC_1 J_STATE 0x1 PTC_2 K_STATE 0x2 PTC_3 SE0 (host) / NAK (device) 0x3 PTC_4 Packet 0x4 PTC_5 FORCE_ENABLE_HS 0x5 PTC_6 FORCE_ENABLE_FS 0x6 PTC_7 FORCE_ENABLE_LS 0x7 WKCN Wake on Connect Enable (WKCNNT_E) - Read/Write 20 1 read-write WKDC Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write 21 1 read-write WKOC Wake on Over-current Enable (WKOC_E) - Read/Write 22 1 read-write PHCD PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write 23 1 read-write PHCD_0 Enable PHY clock 0 PHCD_1 Disable PHY clock 0x1 PFSC Port Force Full Speed Connect - Read/Write 24 1 read-write PFSC_0 Normal operation 0 PFSC_1 Forced to full speed 0x1 PTS_2 See description at bits 31-30 25 1 read-write PSPD Port Speed - Read Only. This register field indicates the speed at which the port is operating. 26 2 read-write PSPD_0 Full Speed 0 PSPD_1 Low Speed 0x1 PSPD_2 High Speed 0x2 PSPD_3 Undefined 0x3 PTW Parallel Transceiver Width This bit has no effect if serial interface engine is used 28 1 read-write PTW_0 Select the 8-bit UTMI interface [60MHz] 0 PTW_1 Select the 16-bit UTMI interface [30MHz] 0x1 STS Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals 29 1 read-write PTS_1 All USB port interface modes are listed in this field description, but not all are supported 30 2 read-write OTGSC On-The-Go Status & control 0x1A4 32 read-write 0x1120 0xFFFFFFFF VD VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor. 0 1 read-write VC VBUS Charge - Read/Write 1 1 read-write OT OTG Termination - Read/Write 3 1 read-write DP Data Pulsing - Read/Write 4 1 read-write IDPU ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default] 5 1 read-write ID USB ID - Read Only. 0 = A device, 1 = B device 8 1 read-only AVV A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold. 9 1 read-only ASV A Session Valid - Read Only. Indicates VBus is above the A session valid threshold. 10 1 read-only BSV B Session Valid - Read Only. Indicates VBus is above the B session valid threshold. 11 1 read-only BSE B Session End - Read Only. Indicates VBus is below the B session end threshold. 12 1 read-only TOG_1MS 1 millisecond timer toggle - Read Only. This bit toggles once per millisecond. 13 1 read-only DPS Data Bus Pulsing Status - Read Only 14 1 read-only IDIS USB ID Interrupt Status - Read/Write 16 1 read-write AVVIS A VBus Valid Interrupt Status - Read/Write to Clear 17 1 read-write ASVIS A Session Valid Interrupt Status - Read/Write to Clear 18 1 read-write BSVIS B Session Valid Interrupt Status - Read/Write to Clear 19 1 read-write BSEIS B Session End Interrupt Status - Read/Write to Clear 20 1 read-write STATUS_1MS 1 millisecond timer Interrupt Status - Read/Write to Clear 21 1 read-write DPIS Data Pulse Interrupt Status - Read/Write to Clear 22 1 read-write IDIE USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt. 24 1 read-write AVVIE A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt. 25 1 read-write ASVIE A Session Valid Interrupt Enable - Read/Write 26 1 read-write BSVIE B Session Valid Interrupt Enable - Read/Write 27 1 read-write BSEIE B Session End Interrupt Enable - Read/Write. Setting this bit enables the B session end interrupt. 28 1 read-write EN_1MS 1 millisecond timer Interrupt Enable - Read/Write 29 1 read-write DPIE Data Pulse Interrupt Enable 30 1 read-write USBMODE USB Device Mode 0x1A8 32 read-write 0x5000 0xFFFFFFFF CM Controller Mode - R/WO 0 2 read-write CM_0 Idle [Default for combination host/device] 0 CM_2 Device Controller [Default for device only controller] 0x2 CM_3 Host Controller [Default for host only controller] 0x3 ES Endian Select - Read/Write 2 1 read-write ES_0 Little Endian [Default] 0 ES_1 Big Endian 0x1 SLOM Setup Lockout Mode 3 1 read-write SLOM_0 Setup Lockouts On (default); 0 SLOM_1 Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . 0x1 SDIS Stream Disable Mode 4 1 read-write ENDPTSETUPSTAT Endpoint Setup Status 0x1AC 32 read-write 0 0xFFFFFFFF ENDPTSETUPSTAT Setup Endpoint Status 0 16 read-write ENDPTPRIME Endpoint Prime 0x1B0 32 read-write 0 0xFFFFFFFF PERB Prime Endpoint Receive Buffer - R/WS 0 8 read-write PETB Prime Endpoint Transmit Buffer - R/WS 16 8 read-write ENDPTFLUSH Endpoint Flush 0x1B4 32 read-write 0 0xFFFFFFFF FERB Flush Endpoint Receive Buffer - R/WS 0 8 read-write FETB Flush Endpoint Transmit Buffer - R/WS 16 8 read-write ENDPTSTAT Endpoint Status 0x1B8 32 read-only 0 0xFFFFFFFF ERBR Endpoint Receive Buffer Ready -- Read Only 0 8 read-only ETBR Endpoint Transmit Buffer Ready -- Read Only 16 8 read-only ENDPTCOMPLETE Endpoint Complete 0x1BC 32 read-write 0 0xFFFFFFFF ERCE Endpoint Receive Complete Event - RW/C 0 8 read-write ETCE Endpoint Transmit Complete Event - R/WC 16 8 read-write ENDPTCTRL0 Endpoint Control0 0x1C0 32 read-write 0x800080 0xFFFFFFFF RXS RX Endpoint Stall - Read/Write 0 End Point OK 0 1 read-write RXT RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point. 2 2 read-write RXE RX Endpoint Enable 1 Enabled Endpoint0 is always enabled. 7 1 read-write TXS TX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host 16 1 read-write TXT TX Endpoint Type - Read/Write 00 - Control Endpoint0 is fixed as a Control End Point. 18 2 read-write TXE TX Endpoint Enable 1 Enabled Endpoint0 is always enabled. 23 1 read-write ENDPTCTRL1 Endpoint Control 1 0x1C4 32 read-write 0 0xFFFFFFFF RXS RX Endpoint Stall - Read/Write 0 End Point OK 0 1 read-write RXD RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero 1 1 read-write RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 2 2 read-write RXI RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero 5 1 read-write RXR RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device 6 1 read-write RXE RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 7 1 read-write TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared 16 1 read-write TXD TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 17 1 read-write TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 18 2 read-write TXI TX Data Toggle Inhibit 0 PID Sequencing Enabled 21 1 read-write TXR TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device 22 1 read-write TXE TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 23 1 read-write ENDPTCTRL2 Endpoint Control 2 0x1C8 32 read-write 0 0xFFFFFFFF RXS RX Endpoint Stall - Read/Write 0 End Point OK 0 1 read-write RXD RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero 1 1 read-write RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 2 2 read-write RXI RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero 5 1 read-write RXR RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device 6 1 read-write RXE RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 7 1 read-write TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared 16 1 read-write TXD TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 17 1 read-write TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 18 2 read-write TXI TX Data Toggle Inhibit 0 PID Sequencing Enabled 21 1 read-write TXR TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device 22 1 read-write TXE TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 23 1 read-write ENDPTCTRL3 Endpoint Control 3 0x1CC 32 read-write 0 0xFFFFFFFF RXS RX Endpoint Stall - Read/Write 0 End Point OK 0 1 read-write RXD RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero 1 1 read-write RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 2 2 read-write RXI RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero 5 1 read-write RXR RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device 6 1 read-write RXE RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 7 1 read-write TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared 16 1 read-write TXD TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 17 1 read-write TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 18 2 read-write TXI TX Data Toggle Inhibit 0 PID Sequencing Enabled 21 1 read-write TXR TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device 22 1 read-write TXE TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 23 1 read-write ENDPTCTRL4 Endpoint Control 4 0x1D0 32 read-write 0 0xFFFFFFFF RXS RX Endpoint Stall - Read/Write 0 End Point OK 0 1 read-write RXD RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero 1 1 read-write RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 2 2 read-write RXI RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero 5 1 read-write RXR RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device 6 1 read-write RXE RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 7 1 read-write TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared 16 1 read-write TXD TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 17 1 read-write TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 18 2 read-write TXI TX Data Toggle Inhibit 0 PID Sequencing Enabled 21 1 read-write TXR TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device 22 1 read-write TXE TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 23 1 read-write ENDPTCTRL5 Endpoint Control 5 0x1D4 32 read-write 0 0xFFFFFFFF RXS RX Endpoint Stall - Read/Write 0 End Point OK 0 1 read-write RXD RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero 1 1 read-write RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 2 2 read-write RXI RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero 5 1 read-write RXR RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device 6 1 read-write RXE RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 7 1 read-write TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared 16 1 read-write TXD TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 17 1 read-write TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 18 2 read-write TXI TX Data Toggle Inhibit 0 PID Sequencing Enabled 21 1 read-write TXR TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device 22 1 read-write TXE TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 23 1 read-write ENDPTCTRL6 Endpoint Control 6 0x1D8 32 read-write 0 0xFFFFFFFF RXS RX Endpoint Stall - Read/Write 0 End Point OK 0 1 read-write RXD RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero 1 1 read-write RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 2 2 read-write RXI RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero 5 1 read-write RXR RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device 6 1 read-write RXE RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 7 1 read-write TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared 16 1 read-write TXD TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 17 1 read-write TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 18 2 read-write TXI TX Data Toggle Inhibit 0 PID Sequencing Enabled 21 1 read-write TXR TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device 22 1 read-write TXE TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 23 1 read-write ENDPTCTRL7 Endpoint Control 7 0x1DC 32 read-write 0 0xFFFFFFFF RXS RX Endpoint Stall - Read/Write 0 End Point OK 0 1 read-write RXD RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero 1 1 read-write RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 2 2 read-write RXI RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero 5 1 read-write RXR RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device 6 1 read-write RXE RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 7 1 read-write TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared 16 1 read-write TXD TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 17 1 read-write TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt 18 2 read-write TXI TX Data Toggle Inhibit 0 PID Sequencing Enabled 21 1 read-write TXR TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device 22 1 read-write TXE TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured 23 1 read-write USBNC USB USB USBNC USBNC_ 0x400E4000 0 0x81C registers USB_OTG1_CTRL USB OTG1 Control Register 0x800 32 read-write 0x30001000 0xFFFFFFFF OVER_CUR_DIS Disable OTG1 Overcurrent Detection 7 1 read-write OVER_CUR_DIS_0 Enables overcurrent detection 0 OVER_CUR_DIS_1 Disables overcurrent detection 0x1 OVER_CUR_POL OTG1 Polarity of Overcurrent The polarity of OTG1 port overcurrent event 8 1 read-write OVER_CUR_POL_0 High active (high on this signal represents an overcurrent condition) 0 OVER_CUR_POL_1 Low active (low on this signal represents an overcurrent condition) 0x1 PWR_POL OTG1 Power Polarity This bit should be set according to PMIC Power Pin polarity. 9 1 read-write PWR_POL_0 PMIC Power Pin is Low active. 0 PWR_POL_1 PMIC Power Pin is High active. 0x1 WIE OTG1 Wake-up Interrupt Enable This bit enables or disables the OTG1 wake-up interrupt 10 1 read-write WIE_0 Interrupt Disabled 0 WIE_1 Interrupt Enabled 0x1 WKUP_SW_EN OTG1 Software Wake-up Enable 14 1 read-write WKUP_SW_EN_0 Disable 0 WKUP_SW_EN_1 Enable 0x1 WKUP_SW OTG1 Software Wake-up 15 1 read-write WKUP_SW_0 Inactive 0 WKUP_SW_1 Force wake-up 0x1 WKUP_ID_EN OTG1 Wake-up on ID change enable 16 1 read-write WKUP_ID_EN_0 Disable 0 WKUP_ID_EN_1 Enable 0x1 WKUP_VBUS_EN OTG1 wake-up on VBUS change enable 17 1 read-write WKUP_VBUS_EN_0 Disable 0 WKUP_VBUS_EN_1 Enable 0x1 WKUP_DPDM_EN Wake-up on DPDM change enable 29 1 read-write WKUP_DPDM_EN_0 DPDM changes wake-up to be disabled only when VBUS is 0. 0 WKUP_DPDM_EN_1 (Default) DPDM changes wake-up to be enabled, it is for device only. 0x1 WIR OTG1 Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTG1 port 31 1 read-only WIR_0 No wake-up interrupt request received 0 WIR_1 Wake-up Interrupt Request received 0x1 USB_OTG1_PHY_CTRL_0 OTG1 UTMI PHY Control 0 Register 0x818 32 read-write 0 0xFFFFFFFF UTMI_CLK_VLD Indicating whether OTG1 UTMI PHY clock is valid 31 1 read-write UTMI_CLK_VLD_0 Invalid 0 UTMI_CLK_VLD_1 Valid 0x1 DMA0 DMA DMA 0x400E8000 0 0x1200 registers DMA0 0 DMA1 1 DMA2 2 DMA3 3 DMA4 4 DMA5 5 DMA6 6 DMA7 7 DMA8 8 DMA9 9 DMA10 10 DMA11 11 DMA12 12 DMA13 13 DMA14 14 DMA15 15 DMA_ERROR 16 CR Control Register 0 32 read-write 0 0x80FFFFFF EDBG Enable Debug 1 1 read-write EDBG_0 When in debug mode, the DMA continues to operate. 0 EDBG_1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. 0x1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write ERCA_0 Fixed priority arbitration is used for channel selection . 0 ERCA_1 Round robin arbitration is used for channel selection . 0x1 HOE Halt On Error 4 1 read-write HOE_0 Normal operation 0 HOE_1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. 0x1 HALT Halt DMA Operations 5 1 read-write HALT_0 Normal operation 0 HALT_1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. 0x1 CLM Continuous Link Mode 6 1 read-write CLM_0 A minor loop channel link made to itself goes through channel arbitration before being activated again. 0 CLM_1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. 0x1 EMLM Enable Minor Loop Mapping 7 1 read-write EMLM_0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 0 EMLM_1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. 0x1 ECX Error Cancel Transfer 16 1 read-write ECX_0 Normal operation 0 ECX_1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. 0x1 CX Cancel Transfer 17 1 read-write CX_0 Normal operation 0 CX_1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. 0x1 ACTIVE DMA Active Status 31 1 read-only ACTIVE_0 eDMA is idle. 0 ACTIVE_1 eDMA is executing a channel. 0x1 ES Error Status Register 0x4 32 read-only 0 0xFFFFFFFF DBE Destination Bus Error 0 1 read-only DBE_0 No destination bus error 0 DBE_1 The last recorded error was a bus error on a destination write 0x1 SBE Source Bus Error 1 1 read-only SBE_0 No source bus error 0 SBE_1 The last recorded error was a bus error on a source read 0x1 SGE Scatter/Gather Configuration Error 2 1 read-only SGE_0 No scatter/gather configuration error 0 SGE_1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. 0x1 NCE NBYTES/CITER Configuration Error 3 1 read-only NCE_0 No NBYTES/CITER configuration error 0 NCE_1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] 0x1 DOE Destination Offset Error 4 1 read-only DOE_0 No destination offset configuration error 0 DOE_1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. 0x1 DAE Destination Address Error 5 1 read-only DAE_0 No destination address configuration error 0 DAE_1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. 0x1 SOE Source Offset Error 6 1 read-only SOE_0 No source offset configuration error 0 SOE_1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. 0x1 SAE Source Address Error 7 1 read-only SAE_0 No source address configuration error. 0 SAE_1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. 0x1 ERRCHN Error Channel Number or Canceled Channel Number 8 4 read-only CPE Channel Priority Error 14 1 read-only CPE_0 No channel priority error 0 CPE_1 The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. 0x1 ECX Transfer Canceled 16 1 read-only ECX_0 No canceled transfers 0 ECX_1 The last recorded entry was a canceled transfer by the error cancel transfer input 0x1 VLD VLD 31 1 read-only VLD_0 No ERR bits are set. 0 VLD_1 At least one ERR bit is set indicating a valid error exists that has not been cleared. 0x1 ERQ Enable Request Register 0xC 32 read-write 0 0xFFFFFFFF ERQ0 Enable DMA Request 0 0 1 read-write ERQ0_0 The DMA request signal for the corresponding channel is disabled 0 ERQ0_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ1 Enable DMA Request 1 1 1 read-write ERQ1_0 The DMA request signal for the corresponding channel is disabled 0 ERQ1_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ2 Enable DMA Request 2 2 1 read-write ERQ2_0 The DMA request signal for the corresponding channel is disabled 0 ERQ2_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ3 Enable DMA Request 3 3 1 read-write ERQ3_0 The DMA request signal for the corresponding channel is disabled 0 ERQ3_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ4 Enable DMA Request 4 4 1 read-write ERQ4_0 The DMA request signal for the corresponding channel is disabled 0 ERQ4_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ5 Enable DMA Request 5 5 1 read-write ERQ5_0 The DMA request signal for the corresponding channel is disabled 0 ERQ5_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ6 Enable DMA Request 6 6 1 read-write ERQ6_0 The DMA request signal for the corresponding channel is disabled 0 ERQ6_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ7 Enable DMA Request 7 7 1 read-write ERQ7_0 The DMA request signal for the corresponding channel is disabled 0 ERQ7_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ8 Enable DMA Request 8 8 1 read-write ERQ8_0 The DMA request signal for the corresponding channel is disabled 0 ERQ8_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ9 Enable DMA Request 9 9 1 read-write ERQ9_0 The DMA request signal for the corresponding channel is disabled 0 ERQ9_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ10 Enable DMA Request 10 10 1 read-write ERQ10_0 The DMA request signal for the corresponding channel is disabled 0 ERQ10_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ11 Enable DMA Request 11 11 1 read-write ERQ11_0 The DMA request signal for the corresponding channel is disabled 0 ERQ11_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ12 Enable DMA Request 12 12 1 read-write ERQ12_0 The DMA request signal for the corresponding channel is disabled 0 ERQ12_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ13 Enable DMA Request 13 13 1 read-write ERQ13_0 The DMA request signal for the corresponding channel is disabled 0 ERQ13_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ14 Enable DMA Request 14 14 1 read-write ERQ14_0 The DMA request signal for the corresponding channel is disabled 0 ERQ14_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ15 Enable DMA Request 15 15 1 read-write ERQ15_0 The DMA request signal for the corresponding channel is disabled 0 ERQ15_1 The DMA request signal for the corresponding channel is enabled 0x1 EEI Enable Error Interrupt Register 0x14 32 read-write 0 0xFFFFFFFF EEI0 Enable Error Interrupt 0 0 1 read-write EEI0_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI0_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI1 Enable Error Interrupt 1 1 1 read-write EEI1_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI1_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI2 Enable Error Interrupt 2 2 1 read-write EEI2_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI2_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI3 Enable Error Interrupt 3 3 1 read-write EEI3_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI3_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI4 Enable Error Interrupt 4 4 1 read-write EEI4_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI4_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI5 Enable Error Interrupt 5 5 1 read-write EEI5_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI5_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI6 Enable Error Interrupt 6 6 1 read-write EEI6_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI6_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI7 Enable Error Interrupt 7 7 1 read-write EEI7_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI7_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI8 Enable Error Interrupt 8 8 1 read-write EEI8_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI8_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI9 Enable Error Interrupt 9 9 1 read-write EEI9_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI9_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI10 Enable Error Interrupt 10 10 1 read-write EEI10_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI10_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI11 Enable Error Interrupt 11 11 1 read-write EEI11_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI11_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI12 Enable Error Interrupt 12 12 1 read-write EEI12_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI12_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI13 Enable Error Interrupt 13 13 1 read-write EEI13_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI13_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI14 Enable Error Interrupt 14 14 1 read-write EEI14_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI14_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI15 Enable Error Interrupt 15 15 1 read-write EEI15_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI15_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 CEEI Clear Enable Error Interrupt Register 0x18 8 read-write 0 0xFF CEEI Clear Enable Error Interrupt 0 4 read-write CAEE Clear All Enable Error Interrupts 6 1 read-write CAEE_0 Clear only the EEI bit specified in the CEEI field 0 CAEE_1 Clear all bits in EEI 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 SEEI Set Enable Error Interrupt Register 0x19 8 read-write 0 0xFF SEEI Set Enable Error Interrupt 0 4 read-write SAEE Sets All Enable Error Interrupts 6 1 read-write SAEE_0 Set only the EEI bit specified in the SEEI field. 0 SAEE_1 Sets all bits in EEI 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CERQ Clear Enable Request Register 0x1A 8 read-write 0 0xFF CERQ Clear Enable Request 0 4 read-write CAER Clear All Enable Requests 6 1 read-write CAER_0 Clear only the ERQ bit specified in the CERQ field 0 CAER_1 Clear all bits in ERQ 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 SERQ Set Enable Request Register 0x1B 8 read-write 0 0xFF SERQ Set Enable Request 0 4 read-write SAER Set All Enable Requests 6 1 read-write SAER_0 Set only the ERQ bit specified in the SERQ field 0 SAER_1 Set all bits in ERQ 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CDNE Clear DONE Status Bit Register 0x1C 8 read-write 0 0xFF CDNE Clear DONE Bit 0 4 read-write CADN Clears All DONE Bits 6 1 read-write CADN_0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field 0 CADN_1 Clears all bits in TCDn_CSR[DONE] 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 SSRT Set START Bit Register 0x1D 8 read-write 0 0xFF SSRT Set START Bit 0 4 read-write SAST Set All START Bits (activates all channels) 6 1 read-write SAST_0 Set only the TCDn_CSR[START] bit specified in the SSRT field 0 SAST_1 Set all bits in TCDn_CSR[START] 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CERR Clear Error Register 0x1E 8 read-write 0 0xFF CERR Clear Error Indicator 0 4 read-write CAEI Clear All Error Indicators 6 1 read-write CAEI_0 Clear only the ERR bit specified in the CERR field 0 CAEI_1 Clear all bits in ERR 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CINT Clear Interrupt Request Register 0x1F 8 read-write 0 0xFF CINT Clear Interrupt Request 0 4 read-write CAIR Clear All Interrupt Requests 6 1 read-write CAIR_0 Clear only the INT bit specified in the CINT field 0 CAIR_1 Clear all bits in INT 0x1 NOP No Op enable 7 1 read-write NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 INT Interrupt Request Register 0x24 32 read-write 0 0xFFFFFFFF INT0 Interrupt Request 0 0 1 read-write oneToClear INT0_0 The interrupt request for corresponding channel is cleared 0 INT0_1 The interrupt request for corresponding channel is active 0x1 INT1 Interrupt Request 1 1 1 read-write oneToClear INT1_0 The interrupt request for corresponding channel is cleared 0 INT1_1 The interrupt request for corresponding channel is active 0x1 INT2 Interrupt Request 2 2 1 read-write oneToClear INT2_0 The interrupt request for corresponding channel is cleared 0 INT2_1 The interrupt request for corresponding channel is active 0x1 INT3 Interrupt Request 3 3 1 read-write oneToClear INT3_0 The interrupt request for corresponding channel is cleared 0 INT3_1 The interrupt request for corresponding channel is active 0x1 INT4 Interrupt Request 4 4 1 read-write oneToClear INT4_0 The interrupt request for corresponding channel is cleared 0 INT4_1 The interrupt request for corresponding channel is active 0x1 INT5 Interrupt Request 5 5 1 read-write oneToClear INT5_0 The interrupt request for corresponding channel is cleared 0 INT5_1 The interrupt request for corresponding channel is active 0x1 INT6 Interrupt Request 6 6 1 read-write oneToClear INT6_0 The interrupt request for corresponding channel is cleared 0 INT6_1 The interrupt request for corresponding channel is active 0x1 INT7 Interrupt Request 7 7 1 read-write oneToClear INT7_0 The interrupt request for corresponding channel is cleared 0 INT7_1 The interrupt request for corresponding channel is active 0x1 INT8 Interrupt Request 8 8 1 read-write oneToClear INT8_0 The interrupt request for corresponding channel is cleared 0 INT8_1 The interrupt request for corresponding channel is active 0x1 INT9 Interrupt Request 9 9 1 read-write oneToClear INT9_0 The interrupt request for corresponding channel is cleared 0 INT9_1 The interrupt request for corresponding channel is active 0x1 INT10 Interrupt Request 10 10 1 read-write oneToClear INT10_0 The interrupt request for corresponding channel is cleared 0 INT10_1 The interrupt request for corresponding channel is active 0x1 INT11 Interrupt Request 11 11 1 read-write oneToClear INT11_0 The interrupt request for corresponding channel is cleared 0 INT11_1 The interrupt request for corresponding channel is active 0x1 INT12 Interrupt Request 12 12 1 read-write oneToClear INT12_0 The interrupt request for corresponding channel is cleared 0 INT12_1 The interrupt request for corresponding channel is active 0x1 INT13 Interrupt Request 13 13 1 read-write oneToClear INT13_0 The interrupt request for corresponding channel is cleared 0 INT13_1 The interrupt request for corresponding channel is active 0x1 INT14 Interrupt Request 14 14 1 read-write oneToClear INT14_0 The interrupt request for corresponding channel is cleared 0 INT14_1 The interrupt request for corresponding channel is active 0x1 INT15 Interrupt Request 15 15 1 read-write oneToClear INT15_0 The interrupt request for corresponding channel is cleared 0 INT15_1 The interrupt request for corresponding channel is active 0x1 ERR Error Register 0x2C 32 read-write 0 0xFFFFFFFF ERR0 Error In Channel 0 0 1 read-write oneToClear ERR0_0 An error in this channel has not occurred 0 ERR0_1 An error in this channel has occurred 0x1 ERR1 Error In Channel 1 1 1 read-write oneToClear ERR1_0 An error in this channel has not occurred 0 ERR1_1 An error in this channel has occurred 0x1 ERR2 Error In Channel 2 2 1 read-write oneToClear ERR2_0 An error in this channel has not occurred 0 ERR2_1 An error in this channel has occurred 0x1 ERR3 Error In Channel 3 3 1 read-write oneToClear ERR3_0 An error in this channel has not occurred 0 ERR3_1 An error in this channel has occurred 0x1 ERR4 Error In Channel 4 4 1 read-write oneToClear ERR4_0 An error in this channel has not occurred 0 ERR4_1 An error in this channel has occurred 0x1 ERR5 Error In Channel 5 5 1 read-write oneToClear ERR5_0 An error in this channel has not occurred 0 ERR5_1 An error in this channel has occurred 0x1 ERR6 Error In Channel 6 6 1 read-write oneToClear ERR6_0 An error in this channel has not occurred 0 ERR6_1 An error in this channel has occurred 0x1 ERR7 Error In Channel 7 7 1 read-write oneToClear ERR7_0 An error in this channel has not occurred 0 ERR7_1 An error in this channel has occurred 0x1 ERR8 Error In Channel 8 8 1 read-write oneToClear ERR8_0 An error in this channel has not occurred 0 ERR8_1 An error in this channel has occurred 0x1 ERR9 Error In Channel 9 9 1 read-write oneToClear ERR9_0 An error in this channel has not occurred 0 ERR9_1 An error in this channel has occurred 0x1 ERR10 Error In Channel 10 10 1 read-write oneToClear ERR10_0 An error in this channel has not occurred 0 ERR10_1 An error in this channel has occurred 0x1 ERR11 Error In Channel 11 11 1 read-write oneToClear ERR11_0 An error in this channel has not occurred 0 ERR11_1 An error in this channel has occurred 0x1 ERR12 Error In Channel 12 12 1 read-write oneToClear ERR12_0 An error in this channel has not occurred 0 ERR12_1 An error in this channel has occurred 0x1 ERR13 Error In Channel 13 13 1 read-write oneToClear ERR13_0 An error in this channel has not occurred 0 ERR13_1 An error in this channel has occurred 0x1 ERR14 Error In Channel 14 14 1 read-write oneToClear ERR14_0 An error in this channel has not occurred 0 ERR14_1 An error in this channel has occurred 0x1 ERR15 Error In Channel 15 15 1 read-write oneToClear ERR15_0 An error in this channel has not occurred 0 ERR15_1 An error in this channel has occurred 0x1 HRS Hardware Request Status Register 0x34 32 read-only 0 0xFFFFFFFF HRS0 Hardware Request Status Channel 0 0 1 read-only HRS0_0 A hardware service request for channel 0 is not present 0 HRS0_1 A hardware service request for channel 0 is present 0x1 HRS1 Hardware Request Status Channel 1 1 1 read-only HRS1_0 A hardware service request for channel 1 is not present 0 HRS1_1 A hardware service request for channel 1 is present 0x1 HRS2 Hardware Request Status Channel 2 2 1 read-only HRS2_0 A hardware service request for channel 2 is not present 0 HRS2_1 A hardware service request for channel 2 is present 0x1 HRS3 Hardware Request Status Channel 3 3 1 read-only HRS3_0 A hardware service request for channel 3 is not present 0 HRS3_1 A hardware service request for channel 3 is present 0x1 HRS4 Hardware Request Status Channel 4 4 1 read-only HRS4_0 A hardware service request for channel 4 is not present 0 HRS4_1 A hardware service request for channel 4 is present 0x1 HRS5 Hardware Request Status Channel 5 5 1 read-only HRS5_0 A hardware service request for channel 5 is not present 0 HRS5_1 A hardware service request for channel 5 is present 0x1 HRS6 Hardware Request Status Channel 6 6 1 read-only HRS6_0 A hardware service request for channel 6 is not present 0 HRS6_1 A hardware service request for channel 6 is present 0x1 HRS7 Hardware Request Status Channel 7 7 1 read-only HRS7_0 A hardware service request for channel 7 is not present 0 HRS7_1 A hardware service request for channel 7 is present 0x1 HRS8 Hardware Request Status Channel 8 8 1 read-only HRS8_0 A hardware service request for channel 8 is not present 0 HRS8_1 A hardware service request for channel 8 is present 0x1 HRS9 Hardware Request Status Channel 9 9 1 read-only HRS9_0 A hardware service request for channel 9 is not present 0 HRS9_1 A hardware service request for channel 9 is present 0x1 HRS10 Hardware Request Status Channel 10 10 1 read-only HRS10_0 A hardware service request for channel 10 is not present 0 HRS10_1 A hardware service request for channel 10 is present 0x1 HRS11 Hardware Request Status Channel 11 11 1 read-only HRS11_0 A hardware service request for channel 11 is not present 0 HRS11_1 A hardware service request for channel 11 is present 0x1 HRS12 Hardware Request Status Channel 12 12 1 read-only HRS12_0 A hardware service request for channel 12 is not present 0 HRS12_1 A hardware service request for channel 12 is present 0x1 HRS13 Hardware Request Status Channel 13 13 1 read-only HRS13_0 A hardware service request for channel 13 is not present 0 HRS13_1 A hardware service request for channel 13 is present 0x1 HRS14 Hardware Request Status Channel 14 14 1 read-only HRS14_0 A hardware service request for channel 14 is not present 0 HRS14_1 A hardware service request for channel 14 is present 0x1 HRS15 Hardware Request Status Channel 15 15 1 read-only HRS15_0 A hardware service request for channel 15 is not present 0 HRS15_1 A hardware service request for channel 15 is present 0x1 EARS Enable Asynchronous Request in Stop Register 0x44 32 read-write 0 0xFFFFFFFF EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write EDREQ_0_0 Disable asynchronous DMA request for channel 0. 0 EDREQ_0_1 Enable asynchronous DMA request for channel 0. 0x1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write EDREQ_1_0 Disable asynchronous DMA request for channel 1 0 EDREQ_1_1 Enable asynchronous DMA request for channel 1. 0x1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write EDREQ_2_0 Disable asynchronous DMA request for channel 2. 0 EDREQ_2_1 Enable asynchronous DMA request for channel 2. 0x1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write EDREQ_3_0 Disable asynchronous DMA request for channel 3. 0 EDREQ_3_1 Enable asynchronous DMA request for channel 3. 0x1 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4 4 1 read-write EDREQ_4_0 Disable asynchronous DMA request for channel 4. 0 EDREQ_4_1 Enable asynchronous DMA request for channel 4. 0x1 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 5 1 read-write EDREQ_5_0 Disable asynchronous DMA request for channel 5. 0 EDREQ_5_1 Enable asynchronous DMA request for channel 5. 0x1 EDREQ_6 Enable asynchronous DMA request in stop mode for channel 6 6 1 read-write EDREQ_6_0 Disable asynchronous DMA request for channel 6. 0 EDREQ_6_1 Enable asynchronous DMA request for channel 6. 0x1 EDREQ_7 Enable asynchronous DMA request in stop mode for channel 7 7 1 read-write EDREQ_7_0 Disable asynchronous DMA request for channel 7. 0 EDREQ_7_1 Enable asynchronous DMA request for channel 7. 0x1 EDREQ_8 Enable asynchronous DMA request in stop mode for channel 8 8 1 read-write EDREQ_8_0 Disable asynchronous DMA request for channel 8. 0 EDREQ_8_1 Enable asynchronous DMA request for channel 8. 0x1 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9 9 1 read-write EDREQ_9_0 Disable asynchronous DMA request for channel 9. 0 EDREQ_9_1 Enable asynchronous DMA request for channel 9. 0x1 EDREQ_10 Enable asynchronous DMA request in stop mode for channel 10 10 1 read-write EDREQ_10_0 Disable asynchronous DMA request for channel 10. 0 EDREQ_10_1 Enable asynchronous DMA request for channel 10. 0x1 EDREQ_11 Enable asynchronous DMA request in stop mode for channel 11 11 1 read-write EDREQ_11_0 Disable asynchronous DMA request for channel 11. 0 EDREQ_11_1 Enable asynchronous DMA request for channel 11. 0x1 EDREQ_12 Enable asynchronous DMA request in stop mode for channel 12 12 1 read-write EDREQ_12_0 Disable asynchronous DMA request for channel 12. 0 EDREQ_12_1 Enable asynchronous DMA request for channel 12. 0x1 EDREQ_13 Enable asynchronous DMA request in stop mode for channel 13 13 1 read-write EDREQ_13_0 Disable asynchronous DMA request for channel 13. 0 EDREQ_13_1 Enable asynchronous DMA request for channel 13. 0x1 EDREQ_14 Enable asynchronous DMA request in stop mode for channel 14 14 1 read-write EDREQ_14_0 Disable asynchronous DMA request for channel 14. 0 EDREQ_14_1 Enable asynchronous DMA request for channel 14. 0x1 EDREQ_15 Enable asynchronous DMA request in stop mode for channel 15 15 1 read-write EDREQ_15_0 Disable asynchronous DMA request for channel 15. 0 EDREQ_15_1 Enable asynchronous DMA request for channel 15. 0x1 DCHPRI3 Channel Priority Register 0x100 8 read-write 0x3 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI2 Channel Priority Register 0x101 8 read-write 0x2 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI1 Channel Priority Register 0x102 8 read-write 0x1 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI0 Channel Priority Register 0x103 8 read-write 0 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI7 Channel Priority Register 0x104 8 read-write 0x7 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI6 Channel Priority Register 0x105 8 read-write 0x6 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI5 Channel Priority Register 0x106 8 read-write 0x5 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI4 Channel Priority Register 0x107 8 read-write 0x4 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI11 Channel Priority Register 0x108 8 read-write 0xB 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI10 Channel Priority Register 0x109 8 read-write 0xA 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI9 Channel Priority Register 0x10A 8 read-write 0x9 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI8 Channel Priority Register 0x10B 8 read-write 0x8 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI15 Channel Priority Register 0x10C 8 read-write 0xF 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI14 Channel Priority Register 0x10D 8 read-write 0xE 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI13 Channel Priority Register 0x10E 8 read-write 0xD 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI12 Channel Priority Register 0x10F 8 read-write 0xC 0xFF CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 TCD0_SADDR TCD Source Address 0x1000 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD0_SOFF TCD Signed Source Address Offset 0x1004 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD0_ATTR TCD Transfer Attributes 0x1006 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD0_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD0_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD0_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1008 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD0_SLAST TCD Last Source Address Adjustment 0x100C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD0_DADDR TCD Destination Address 0x1010 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD0_DOFF TCD Signed Destination Address Offset 0x1014 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD0_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD0_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1016 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD0_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1018 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD0_CSR TCD Control and Status 0x101C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD0_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x101E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD0_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x101E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD1_SADDR TCD Source Address 0x1020 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD1_SOFF TCD Signed Source Address Offset 0x1024 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD1_ATTR TCD Transfer Attributes 0x1026 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD1_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1028 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD1_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1028 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD1_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1028 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD1_SLAST TCD Last Source Address Adjustment 0x102C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD1_DADDR TCD Destination Address 0x1030 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD1_DOFF TCD Signed Destination Address Offset 0x1034 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD1_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1036 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD1_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1036 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD1_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1038 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD1_CSR TCD Control and Status 0x103C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD1_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x103E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD1_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x103E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD2_SADDR TCD Source Address 0x1040 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD2_SOFF TCD Signed Source Address Offset 0x1044 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD2_ATTR TCD Transfer Attributes 0x1046 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD2_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1048 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD2_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1048 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD2_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1048 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD2_SLAST TCD Last Source Address Adjustment 0x104C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD2_DADDR TCD Destination Address 0x1050 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD2_DOFF TCD Signed Destination Address Offset 0x1054 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD2_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1056 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD2_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1056 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD2_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1058 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD2_CSR TCD Control and Status 0x105C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD2_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x105E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD2_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x105E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD3_SADDR TCD Source Address 0x1060 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD3_SOFF TCD Signed Source Address Offset 0x1064 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD3_ATTR TCD Transfer Attributes 0x1066 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD3_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1068 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD3_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1068 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD3_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1068 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD3_SLAST TCD Last Source Address Adjustment 0x106C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD3_DADDR TCD Destination Address 0x1070 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD3_DOFF TCD Signed Destination Address Offset 0x1074 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD3_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1076 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD3_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1076 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD3_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1078 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD3_CSR TCD Control and Status 0x107C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD3_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x107E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD3_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x107E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD4_SADDR TCD Source Address 0x1080 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD4_SOFF TCD Signed Source Address Offset 0x1084 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD4_ATTR TCD Transfer Attributes 0x1086 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD4_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1088 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD4_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1088 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD4_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1088 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD4_SLAST TCD Last Source Address Adjustment 0x108C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD4_DADDR TCD Destination Address 0x1090 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD4_DOFF TCD Signed Destination Address Offset 0x1094 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD4_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1096 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD4_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1096 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD4_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1098 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD4_CSR TCD Control and Status 0x109C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD4_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x109E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD4_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x109E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD5_SADDR TCD Source Address 0x10A0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD5_SOFF TCD Signed Source Address Offset 0x10A4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD5_ATTR TCD Transfer Attributes 0x10A6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD5_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x10A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD5_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x10A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD5_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x10A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD5_SLAST TCD Last Source Address Adjustment 0x10AC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD5_DADDR TCD Destination Address 0x10B0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD5_DOFF TCD Signed Destination Address Offset 0x10B4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD5_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x10B6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD5_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x10B6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD5_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10B8 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD5_CSR TCD Control and Status 0x10BC 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD5_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x10BE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD5_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x10BE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD6_SADDR TCD Source Address 0x10C0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD6_SOFF TCD Signed Source Address Offset 0x10C4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD6_ATTR TCD Transfer Attributes 0x10C6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD6_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x10C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD6_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x10C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD6_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x10C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD6_SLAST TCD Last Source Address Adjustment 0x10CC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD6_DADDR TCD Destination Address 0x10D0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD6_DOFF TCD Signed Destination Address Offset 0x10D4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD6_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x10D6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD6_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x10D6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD6_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10D8 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD6_CSR TCD Control and Status 0x10DC 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD6_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x10DE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD6_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x10DE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD7_SADDR TCD Source Address 0x10E0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD7_SOFF TCD Signed Source Address Offset 0x10E4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD7_ATTR TCD Transfer Attributes 0x10E6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD7_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x10E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD7_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x10E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD7_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x10E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD7_SLAST TCD Last Source Address Adjustment 0x10EC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD7_DADDR TCD Destination Address 0x10F0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD7_DOFF TCD Signed Destination Address Offset 0x10F4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD7_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x10F6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD7_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x10F6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD7_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10F8 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD7_CSR TCD Control and Status 0x10FC 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD7_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x10FE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD7_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x10FE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD8_SADDR TCD Source Address 0x1100 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD8_SOFF TCD Signed Source Address Offset 0x1104 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD8_ATTR TCD Transfer Attributes 0x1106 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD8_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1108 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD8_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1108 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD8_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1108 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD8_SLAST TCD Last Source Address Adjustment 0x110C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD8_DADDR TCD Destination Address 0x1110 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD8_DOFF TCD Signed Destination Address Offset 0x1114 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD8_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1116 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD8_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1116 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD8_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1118 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD8_CSR TCD Control and Status 0x111C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD8_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x111E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD8_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x111E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD9_SADDR TCD Source Address 0x1120 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD9_SOFF TCD Signed Source Address Offset 0x1124 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD9_ATTR TCD Transfer Attributes 0x1126 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD9_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1128 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD9_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1128 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD9_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1128 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD9_SLAST TCD Last Source Address Adjustment 0x112C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD9_DADDR TCD Destination Address 0x1130 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD9_DOFF TCD Signed Destination Address Offset 0x1134 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD9_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1136 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD9_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1136 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD9_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1138 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD9_CSR TCD Control and Status 0x113C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD9_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x113E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD9_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x113E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD10_SADDR TCD Source Address 0x1140 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD10_SOFF TCD Signed Source Address Offset 0x1144 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD10_ATTR TCD Transfer Attributes 0x1146 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD10_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1148 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD10_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1148 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD10_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1148 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD10_SLAST TCD Last Source Address Adjustment 0x114C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD10_DADDR TCD Destination Address 0x1150 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD10_DOFF TCD Signed Destination Address Offset 0x1154 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD10_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1156 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD10_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1156 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD10_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1158 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD10_CSR TCD Control and Status 0x115C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD10_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x115E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD10_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x115E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD11_SADDR TCD Source Address 0x1160 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD11_SOFF TCD Signed Source Address Offset 0x1164 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD11_ATTR TCD Transfer Attributes 0x1166 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD11_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1168 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD11_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1168 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD11_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1168 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD11_SLAST TCD Last Source Address Adjustment 0x116C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD11_DADDR TCD Destination Address 0x1170 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD11_DOFF TCD Signed Destination Address Offset 0x1174 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD11_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1176 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD11_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1176 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD11_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1178 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD11_CSR TCD Control and Status 0x117C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD11_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x117E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD11_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x117E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD12_SADDR TCD Source Address 0x1180 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD12_SOFF TCD Signed Source Address Offset 0x1184 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD12_ATTR TCD Transfer Attributes 0x1186 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD12_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1188 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD12_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1188 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD12_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1188 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD12_SLAST TCD Last Source Address Adjustment 0x118C 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD12_DADDR TCD Destination Address 0x1190 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD12_DOFF TCD Signed Destination Address Offset 0x1194 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD12_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1196 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD12_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1196 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD12_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1198 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD12_CSR TCD Control and Status 0x119C 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD12_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x119E 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD12_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x119E 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD13_SADDR TCD Source Address 0x11A0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD13_SOFF TCD Signed Source Address Offset 0x11A4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD13_ATTR TCD Transfer Attributes 0x11A6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD13_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x11A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD13_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x11A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD13_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x11A8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD13_SLAST TCD Last Source Address Adjustment 0x11AC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD13_DADDR TCD Destination Address 0x11B0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD13_DOFF TCD Signed Destination Address Offset 0x11B4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD13_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x11B6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD13_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x11B6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD13_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x11B8 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD13_CSR TCD Control and Status 0x11BC 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD13_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x11BE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD13_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x11BE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD14_SADDR TCD Source Address 0x11C0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD14_SOFF TCD Signed Source Address Offset 0x11C4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD14_ATTR TCD Transfer Attributes 0x11C6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD14_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x11C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD14_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x11C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD14_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x11C8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD14_SLAST TCD Last Source Address Adjustment 0x11CC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD14_DADDR TCD Destination Address 0x11D0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD14_DOFF TCD Signed Destination Address Offset 0x11D4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD14_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x11D6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD14_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x11D6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD14_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x11D8 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD14_CSR TCD Control and Status 0x11DC 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD14_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x11DE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD14_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x11DE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD15_SADDR TCD Source Address 0x11E0 32 read-write 0 0 SADDR Source Address 0 32 read-write TCD15_SOFF TCD Signed Source Address Offset 0x11E4 16 read-write 0 0 SOFF Source address signed offset 0 16 read-write TCD15_ATTR TCD Transfer Attributes 0x11E6 16 read-write 0 0 DSIZE Destination data transfer size 0 3 read-write DMOD Destination Address Modulo 3 5 read-write SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_3 64-bit 0x3 SSIZE_5 32-byte burst (4 beats of 64 bits) 0x5 SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 TCD15_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x11E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD15_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x11E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 30 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD15_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x11E8 32 read-write 0 0 NBYTES Minor Byte Transfer Count 0 10 read-write MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD15_SLAST TCD Last Source Address Adjustment 0x11EC 32 read-write 0 0 SLAST Last Source Address Adjustment 0 32 read-write TCD15_DADDR TCD Destination Address 0x11F0 32 read-write 0 0 DADDR Destination Address 0 32 read-write TCD15_DOFF TCD Signed Destination Address Offset 0x11F4 16 read-write 0 0 DOFF Destination Address Signed Offset 0 16 read-write TCD15_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x11F6 16 read-write 0 0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD15_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x11F6 16 read-write 0 0 CITER Current Major Iteration Count 0 9 read-write LINKCH Minor Loop Link Channel Number 9 4 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD15_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x11F8 32 read-write 0 0 DLASTSGA DLASTSGA 0 32 read-write TCD15_CSR TCD Control and Status 0x11FC 16 read-write 0 0 START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 DREQ Disable Request 3 1 read-write DREQ_0 The channel's ERQ bit is not affected. 0 DREQ_1 The channel's ERQ bit is cleared when the major loop is complete. 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 ACTIVE Channel Active 6 1 read-only DONE Channel Done 7 1 read-write MAJORLINKCH Major Loop Link Channel Number 8 4 read-write BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 TCD15_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x11FE 16 read-write 0 0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD15_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x11FE 16 read-write 0 0 BITER Starting major iteration count 0 9 read-write LINKCH Link Channel Number 9 4 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 DMAMUX DMAMUX DMAMUX 0x400EC000 0 0x40 registers 16 0x4 CHCFG[%s] Channel 0 Configuration Register 0 32 read-write 0 0xFFFFFFFF SOURCE DMA Channel Source (Slot Number) 0 7 read-write A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 DCP DCP register reference index DCP DCP_ 0x400F0000 0 0x434 registers DCP 50 DCP_VMI 51 CTRL DCP control register 0 0 32 read-write 0xF0800000 0xFFFFFFFF CHANNEL_INTERRUPT_ENABLE Per-channel interrupt enable bit 0 8 read-write CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 ENABLE_CONTEXT_SWITCHING Enable automatic context switching for the channels 21 1 read-write ENABLE_CONTEXT_CACHING The software must set this bit to enable the caching of contexts between the operations 22 1 read-write GATHER_RESIDUAL_WRITES The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations 23 1 read-write PRESENT_SHA Indicates whether the SHA1/SHA2 functions are present. 28 1 read-only Absent Absent 0 Present Present 0x1 PRESENT_CRYPTO Indicates whether the crypto (cipher/hash) functions are present. 29 1 read-only Absent Absent 0 Present Present 0x1 CLKGATE This bit must be set to zero for a normal operation 30 1 read-write SFTRST Set this bit to zero to enable a normal DCP operation 31 1 read-write CTRL_SET DCP control register 0 0x4 32 read-write 0xF0800000 0xFFFFFFFF CHANNEL_INTERRUPT_ENABLE Per-channel interrupt enable bit 0 8 read-write CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 ENABLE_CONTEXT_SWITCHING Enable automatic context switching for the channels 21 1 read-write ENABLE_CONTEXT_CACHING The software must set this bit to enable the caching of contexts between the operations 22 1 read-write GATHER_RESIDUAL_WRITES The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations 23 1 read-write PRESENT_SHA Indicates whether the SHA1/SHA2 functions are present. 28 1 read-only Absent Absent 0 Present Present 0x1 PRESENT_CRYPTO Indicates whether the crypto (cipher/hash) functions are present. 29 1 read-only Absent Absent 0 Present Present 0x1 CLKGATE This bit must be set to zero for a normal operation 30 1 read-write SFTRST Set this bit to zero to enable a normal DCP operation 31 1 read-write CTRL_CLR DCP control register 0 0x8 32 read-write 0xF0800000 0xFFFFFFFF CHANNEL_INTERRUPT_ENABLE Per-channel interrupt enable bit 0 8 read-write CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 ENABLE_CONTEXT_SWITCHING Enable automatic context switching for the channels 21 1 read-write ENABLE_CONTEXT_CACHING The software must set this bit to enable the caching of contexts between the operations 22 1 read-write GATHER_RESIDUAL_WRITES The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations 23 1 read-write PRESENT_SHA Indicates whether the SHA1/SHA2 functions are present. 28 1 read-only Absent Absent 0 Present Present 0x1 PRESENT_CRYPTO Indicates whether the crypto (cipher/hash) functions are present. 29 1 read-only Absent Absent 0 Present Present 0x1 CLKGATE This bit must be set to zero for a normal operation 30 1 read-write SFTRST Set this bit to zero to enable a normal DCP operation 31 1 read-write CTRL_TOG DCP control register 0 0xC 32 read-write 0xF0800000 0xFFFFFFFF CHANNEL_INTERRUPT_ENABLE Per-channel interrupt enable bit 0 8 read-write CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 ENABLE_CONTEXT_SWITCHING Enable automatic context switching for the channels 21 1 read-write ENABLE_CONTEXT_CACHING The software must set this bit to enable the caching of contexts between the operations 22 1 read-write GATHER_RESIDUAL_WRITES The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations 23 1 read-write PRESENT_SHA Indicates whether the SHA1/SHA2 functions are present. 28 1 read-only Absent Absent 0 Present Present 0x1 PRESENT_CRYPTO Indicates whether the crypto (cipher/hash) functions are present. 29 1 read-only Absent Absent 0 Present Present 0x1 CLKGATE This bit must be set to zero for a normal operation 30 1 read-write SFTRST Set this bit to zero to enable a normal DCP operation 31 1 read-write STAT DCP status register 0x10 32 read-write 0x10000000 0xFFFFFFFF IRQ Indicates which channels have pending interrupt requests 0 4 read-write READY_CHANNELS Indicates which channels are ready to proceed with a transfer (the active channel is also included) 16 8 read-only CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 CUR_CHANNEL Current (active) channel (encoded) 24 4 read-only None None 0 CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x3 CH3 CH3 0x4 OTP_KEY_READY When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. 28 1 read-only STAT_SET DCP status register 0x14 32 read-write 0x10000000 0xFFFFFFFF IRQ Indicates which channels have pending interrupt requests 0 4 read-write READY_CHANNELS Indicates which channels are ready to proceed with a transfer (the active channel is also included) 16 8 read-only CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 CUR_CHANNEL Current (active) channel (encoded) 24 4 read-only None None 0 CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x3 CH3 CH3 0x4 OTP_KEY_READY When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. 28 1 read-only STAT_CLR DCP status register 0x18 32 read-write 0x10000000 0xFFFFFFFF IRQ Indicates which channels have pending interrupt requests 0 4 read-write READY_CHANNELS Indicates which channels are ready to proceed with a transfer (the active channel is also included) 16 8 read-only CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 CUR_CHANNEL Current (active) channel (encoded) 24 4 read-only None None 0 CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x3 CH3 CH3 0x4 OTP_KEY_READY When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. 28 1 read-only STAT_TOG DCP status register 0x1C 32 read-write 0x10000000 0xFFFFFFFF IRQ Indicates which channels have pending interrupt requests 0 4 read-write READY_CHANNELS Indicates which channels are ready to proceed with a transfer (the active channel is also included) 16 8 read-only CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 CUR_CHANNEL Current (active) channel (encoded) 24 4 read-only None None 0 CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x3 CH3 CH3 0x4 OTP_KEY_READY When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. 28 1 read-only CHANNELCTRL DCP channel control register 0x20 32 read-write 0 0xFFFFFFFF ENABLE_CHANNEL Setting a bit in this field enables the DMA channel associated with it 0 8 read-write CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 HIGH_PRIORITY_CHANNEL Setting a bit in this field causes the corresponding channel to have high-priority arbitration 8 8 read-write CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 CH0_IRQ_MERGED Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt 16 1 read-write CHANNELCTRL_SET DCP channel control register 0x24 32 read-write 0 0xFFFFFFFF ENABLE_CHANNEL Setting a bit in this field enables the DMA channel associated with it 0 8 read-write CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 HIGH_PRIORITY_CHANNEL Setting a bit in this field causes the corresponding channel to have high-priority arbitration 8 8 read-write CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 CH0_IRQ_MERGED Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt 16 1 read-write CHANNELCTRL_CLR DCP channel control register 0x28 32 read-write 0 0xFFFFFFFF ENABLE_CHANNEL Setting a bit in this field enables the DMA channel associated with it 0 8 read-write CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 HIGH_PRIORITY_CHANNEL Setting a bit in this field causes the corresponding channel to have high-priority arbitration 8 8 read-write CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 CH0_IRQ_MERGED Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt 16 1 read-write CHANNELCTRL_TOG DCP channel control register 0x2C 32 read-write 0 0xFFFFFFFF ENABLE_CHANNEL Setting a bit in this field enables the DMA channel associated with it 0 8 read-write CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 HIGH_PRIORITY_CHANNEL Setting a bit in this field causes the corresponding channel to have high-priority arbitration 8 8 read-write CH0 CH0 0x1 CH1 CH1 0x2 CH2 CH2 0x4 CH3 CH3 0x8 CH0_IRQ_MERGED Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt 16 1 read-write CAPABILITY0 DCP capability 0 register 0x30 32 read-write 0x404 0xFFFFFFFF NUM_KEYS Encoded value indicating the number of key-storage locations implemented in the design 0 8 read-only NUM_CHANNELS Encoded value indicating the number of channels implemented in the design 8 4 read-only DISABLE_UNIQUE_KEY Write to a 1 to disable the per-device unique key 29 1 read-write DISABLE_DECRYPT Write to 1 to disable the decryption 31 1 read-write CAPABILITY1 DCP capability 1 register 0x40 32 read-only 0x70001 0xFFFFFFFF CIPHER_ALGORITHMS One-hot field indicating which cipher algorithms are available 0 16 read-only AES128 AES128 0x1 HASH_ALGORITHMS One-hot field indicating which hashing features are implemented in the hardware 16 16 read-only SHA1 SHA1 0x1 CRC32 CRC32 0x2 SHA256 SHA256 0x4 CONTEXT DCP context buffer pointer 0x50 32 read-write 0 0xFFFFFFFF ADDR Context pointer address 0 32 read-write KEY DCP key index 0x60 32 read-write 0 0xFFFFFFFF SUBWORD Key subword pointer 0 2 read-write INDEX Key index pointer. The valid indices are 0-[number_keys]. 4 2 read-write KEYDATA DCP key data 0x70 32 read-write 0 0xFFFFFFFF DATA Word 0 data for the key. This is the least-significant word. 0 32 read-write PACKET0 DCP work packet 0 status register 0x80 32 read-only 0 0xFFFFFFFF ADDR Next pointer register 0 32 read-only PACKET1 DCP work packet 1 status register 0x90 32 read-only 0 0xFFFFFFFF INTERRUPT Reflects whether the channel must issue an interrupt upon the completion of the packet. 0 1 read-only DECR_SEMAPHORE Reflects whether the channel's semaphore must be decremented at the end of the current operation 1 1 read-only CHAIN Reflects whether the next command pointer register must be loaded into the channel's current descriptor pointer 2 1 read-only CHAIN_CONTIGUOUS Reflects whether the next packet's address is located following this packet's payload. 3 1 read-only ENABLE_MEMCOPY Reflects whether the selected hashing function should be enabled for this operation. 4 1 read-only ENABLE_CIPHER Reflects whether the selected cipher function must be enabled for this operation. 5 1 read-only ENABLE_HASH Reflects whether the selected hashing function must be enabled for this operation. 6 1 read-only ENABLE_BLIT Reflects whether the DCP must perform a blit operation 7 1 read-only CIPHER_ENCRYPT When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption 8 1 read-only DECRYPT DECRYPT 0 ENCRYPT ENCRYPT 0x1 CIPHER_INIT Reflects whether the cipher block must load the initialization vector from the payload for this operation 9 1 read-only OTP_KEY Reflects whether a hardware-based key must be used 10 1 read-only PAYLOAD_KEY When set, it indicates the payload contains the key 11 1 read-only HASH_INIT Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers must be initialized before the operation 12 1 read-only HASH_TERM Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding must be applied by the hardware 13 1 read-only CHECK_HASH Reflects whether the calculated hash value must be compared to the hash provided in the payload. 14 1 read-only HASH_OUTPUT When the hashing is enabled, this bit controls whether the input or output data is hashed. 15 1 read-only INPUT INPUT 0 OUTPUT OUTPUT 0x1 CONSTANT_FILL When this bit is set (MEMCOPY and BLIT modes only), the DCP simply fills the destination buffer with the value found in the source address field 16 1 read-only TEST_SEMA_IRQ This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY! 17 1 read-only KEY_BYTESWAP Reflects whether the DCP engine swaps the key bytes (big-endian key). 18 1 read-only KEY_WORDSWAP Reflects whether the DCP engine swaps the key words (big-endian key). 19 1 read-only INPUT_BYTESWAP Reflects whether the DCP engine byteswaps the input data (big-endian data). 20 1 read-only INPUT_WORDSWAP Reflects whether the DCP engine wordswaps the input data (big-endian data). 21 1 read-only OUTPUT_BYTESWAP Reflects whether the DCP engine byteswaps the output data (big-endian data). 22 1 read-only OUTPUT_WORDSWAP Reflects whether the DCP engine wordswaps the output data (big-endian data). 23 1 read-only TAG Packet Tag 24 8 read-only PACKET2 DCP work packet 2 status register 0xA0 32 read-only 0 0xFFFFFFFF CIPHER_SELECT Cipher selection field 0 4 read-only AES128 AES128 0 CIPHER_MODE Cipher mode selection field. Reflects the mode of operation for the cipher operations. 4 4 read-only ECB ECB 0 CBC CBC 0x1 KEY_SELECT Key selection field 8 8 read-only KEY0 KEY0 0 KEY1 KEY1 0x1 KEY2 KEY2 0x2 KEY3 KEY3 0x3 UNIQUE_KEY UNIQUE_KEY 0xFE OTP_KEY OTP_KEY 0xFF HASH_SELECT Hash Selection Field 16 4 read-only SHA1 SHA1 0 CRC32 CRC32 0x1 SHA256 SHA256 0x2 CIPHER_CFG Cipher configuration bits. Optional configuration bits are required for the ciphers. 24 8 read-only PACKET3 DCP work packet 3 status register 0xB0 32 read-only 0 0xFFFFFFFF ADDR Source buffer address pointer 0 32 read-only PACKET4 DCP work packet 4 status register 0xC0 32 read-only 0 0xFFFFFFFF ADDR Destination buffer address pointer 0 32 read-only PACKET5 DCP work packet 5 status register 0xD0 32 read-only 0 0xFFFFFFFF COUNT Byte count register. This value is the working value and updates as the operation proceeds. 0 32 read-only PACKET6 DCP work packet 6 status register 0xE0 32 read-only 0 0xFFFFFFFF ADDR This regiser reflects the payload pointer for the current control packet. 0 32 read-only CH0CMDPTR DCP channel 0 command pointer address register 0x100 32 read-write 0 0xFFFFFFFF ADDR Pointer to the descriptor structure to be processed for channel 0. 0 32 read-write CH0SEMA DCP channel 0 semaphore register 0x110 32 read-write 0 0xFFFFFFFF INCREMENT The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected 0 8 read-write VALUE This read-only field shows the current (instantaneous) value of the semaphore counter. 16 8 read-only CH0STAT DCP channel 0 status register 0x120 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates the additional error codes for some of the error conditions 16 8 read-write NEXT_CHAIN_IS_0 Error signalled because the next pointer is 0x00000000 0x1 NO_CHAIN Error signalled because the semaphore is non-zero and neither chain bit is set 0x2 CONTEXT_ERROR Error signalled because an error is reported reading/writing the context buffer 0x3 PAYLOAD_ERROR Error signalled because an error is reported reading/writing the payload 0x4 INVALID_MODE Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) 0x5 TAG Indicates the tag from the last completed packet in the command structure 24 8 read-only CH0STAT_SET DCP channel 0 status register 0x124 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates the additional error codes for some of the error conditions 16 8 read-write NEXT_CHAIN_IS_0 Error signalled because the next pointer is 0x00000000 0x1 NO_CHAIN Error signalled because the semaphore is non-zero and neither chain bit is set 0x2 CONTEXT_ERROR Error signalled because an error is reported reading/writing the context buffer 0x3 PAYLOAD_ERROR Error signalled because an error is reported reading/writing the payload 0x4 INVALID_MODE Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) 0x5 TAG Indicates the tag from the last completed packet in the command structure 24 8 read-only CH0STAT_CLR DCP channel 0 status register 0x128 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates the additional error codes for some of the error conditions 16 8 read-write NEXT_CHAIN_IS_0 Error signalled because the next pointer is 0x00000000 0x1 NO_CHAIN Error signalled because the semaphore is non-zero and neither chain bit is set 0x2 CONTEXT_ERROR Error signalled because an error is reported reading/writing the context buffer 0x3 PAYLOAD_ERROR Error signalled because an error is reported reading/writing the payload 0x4 INVALID_MODE Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) 0x5 TAG Indicates the tag from the last completed packet in the command structure 24 8 read-only CH0STAT_TOG DCP channel 0 status register 0x12C 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates the additional error codes for some of the error conditions 16 8 read-write NEXT_CHAIN_IS_0 Error signalled because the next pointer is 0x00000000 0x1 NO_CHAIN Error signalled because the semaphore is non-zero and neither chain bit is set 0x2 CONTEXT_ERROR Error signalled because an error is reported reading/writing the context buffer 0x3 PAYLOAD_ERROR Error signalled because an error is reported reading/writing the payload 0x4 INVALID_MODE Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) 0x5 TAG Indicates the tag from the last completed packet in the command structure 24 8 read-only CH0OPTS DCP channel 0 options register 0x130 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH0OPTS_SET DCP channel 0 options register 0x134 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH0OPTS_CLR DCP channel 0 options register 0x138 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH0OPTS_TOG DCP channel 0 options register 0x13C 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH1CMDPTR DCP channel 1 command pointer address register 0x140 32 read-write 0 0xFFFFFFFF ADDR Pointer to the descriptor structure to be processed for channel 1. 0 32 read-write CH1SEMA DCP channel 1 semaphore register 0x150 32 read-write 0 0xFFFFFFFF INCREMENT The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and the DCP hardware substracts happening on the same clock are protected 0 8 read-write VALUE This read-only field shows the current (instantaneous) value of the semaphore counter. 16 8 read-only CH1STAT DCP channel 1 status register 0x160 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates the additional error codes for some of the error conditions. 16 8 read-write NEXT_CHAIN_IS_0 Error is signalled because the next pointer is 0x00000000. 0x1 NO_CHAIN Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. 0x2 CONTEXT_ERROR Error is signalled because an error was reported when reading/writing the context buffer. 0x3 PAYLOAD_ERROR Error is signalled because an error was reported when reading/writing the payload. 0x4 INVALID_MODE Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). 0x5 TAG Indicates the tag from the last completed packet in the command structure. 24 8 read-only CH1STAT_SET DCP channel 1 status register 0x164 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates the additional error codes for some of the error conditions. 16 8 read-write NEXT_CHAIN_IS_0 Error is signalled because the next pointer is 0x00000000. 0x1 NO_CHAIN Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. 0x2 CONTEXT_ERROR Error is signalled because an error was reported when reading/writing the context buffer. 0x3 PAYLOAD_ERROR Error is signalled because an error was reported when reading/writing the payload. 0x4 INVALID_MODE Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). 0x5 TAG Indicates the tag from the last completed packet in the command structure. 24 8 read-only CH1STAT_CLR DCP channel 1 status register 0x168 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates the additional error codes for some of the error conditions. 16 8 read-write NEXT_CHAIN_IS_0 Error is signalled because the next pointer is 0x00000000. 0x1 NO_CHAIN Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. 0x2 CONTEXT_ERROR Error is signalled because an error was reported when reading/writing the context buffer. 0x3 PAYLOAD_ERROR Error is signalled because an error was reported when reading/writing the payload. 0x4 INVALID_MODE Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). 0x5 TAG Indicates the tag from the last completed packet in the command structure. 24 8 read-only CH1STAT_TOG DCP channel 1 status register 0x16C 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates the additional error codes for some of the error conditions. 16 8 read-write NEXT_CHAIN_IS_0 Error is signalled because the next pointer is 0x00000000. 0x1 NO_CHAIN Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. 0x2 CONTEXT_ERROR Error is signalled because an error was reported when reading/writing the context buffer. 0x3 PAYLOAD_ERROR Error is signalled because an error was reported when reading/writing the payload. 0x4 INVALID_MODE Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). 0x5 TAG Indicates the tag from the last completed packet in the command structure. 24 8 read-only CH1OPTS DCP channel 1 options register 0x170 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH1OPTS_SET DCP channel 1 options register 0x174 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH1OPTS_CLR DCP channel 1 options register 0x178 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH1OPTS_TOG DCP channel 1 options register 0x17C 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH2CMDPTR DCP channel 2 command pointer address register 0x180 32 read-write 0 0xFFFFFFFF ADDR Pointer to the descriptor structure to be processed for channel 2. 0 32 read-write CH2SEMA DCP channel 2 semaphore register 0x190 32 read-write 0 0xFFFFFFFF INCREMENT The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected 0 8 read-write VALUE This read-only field shows the current (instantaneous) value of the semaphore counter. 16 8 read-only CH2STAT DCP channel 2 status register 0x1A0 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates additional error codes for some of the error conditions. 16 8 read-write NEXT_CHAIN_IS_0 Error is signalled because the next pointer is 0x00000000. 0x1 NO_CHAIN Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. 0x2 CONTEXT_ERROR Error is signalled because an error was reported while reading/writing the context buffer. 0x3 PAYLOAD_ERROR Error is signalled because an error was reported while reading/writing the payload. 0x4 INVALID_MODE Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). 0x5 TAG Indicates the tag from the last completed packet in the command structure. 24 8 read-only CH2STAT_SET DCP channel 2 status register 0x1A4 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates additional error codes for some of the error conditions. 16 8 read-write NEXT_CHAIN_IS_0 Error is signalled because the next pointer is 0x00000000. 0x1 NO_CHAIN Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. 0x2 CONTEXT_ERROR Error is signalled because an error was reported while reading/writing the context buffer. 0x3 PAYLOAD_ERROR Error is signalled because an error was reported while reading/writing the payload. 0x4 INVALID_MODE Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). 0x5 TAG Indicates the tag from the last completed packet in the command structure. 24 8 read-only CH2STAT_CLR DCP channel 2 status register 0x1A8 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates additional error codes for some of the error conditions. 16 8 read-write NEXT_CHAIN_IS_0 Error is signalled because the next pointer is 0x00000000. 0x1 NO_CHAIN Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. 0x2 CONTEXT_ERROR Error is signalled because an error was reported while reading/writing the context buffer. 0x3 PAYLOAD_ERROR Error is signalled because an error was reported while reading/writing the payload. 0x4 INVALID_MODE Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). 0x5 TAG Indicates the tag from the last completed packet in the command structure. 24 8 read-only CH2STAT_TOG DCP channel 2 status register 0x1AC 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates additional error codes for some of the error conditions. 16 8 read-write NEXT_CHAIN_IS_0 Error is signalled because the next pointer is 0x00000000. 0x1 NO_CHAIN Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. 0x2 CONTEXT_ERROR Error is signalled because an error was reported while reading/writing the context buffer. 0x3 PAYLOAD_ERROR Error is signalled because an error was reported while reading/writing the payload. 0x4 INVALID_MODE Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). 0x5 TAG Indicates the tag from the last completed packet in the command structure. 24 8 read-only CH2OPTS DCP channel 2 options register 0x1B0 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH2OPTS_SET DCP channel 2 options register 0x1B4 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH2OPTS_CLR DCP channel 2 options register 0x1B8 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH2OPTS_TOG DCP channel 2 options register 0x1BC 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH3CMDPTR DCP channel 3 command pointer address register 0x1C0 32 read-write 0 0xFFFFFFFF ADDR Pointer to the descriptor structure to be processed for channel 3. 0 32 read-write CH3SEMA DCP channel 3 semaphore register 0x1D0 32 read-write 0 0xFFFFFFFF INCREMENT The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected 0 8 read-write VALUE This read-only field shows the current (instantaneous) value of the semaphore counter. 16 8 read-only CH3STAT DCP channel 3 status register 0x1E0 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates additional error codes for some of the error conditions. 16 8 read-write NEXT_CHAIN_IS_0 Error is signalled because the next pointer is 0x00000000. 0x1 NO_CHAIN Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. 0x2 CONTEXT_ERROR Error is signalled because an error was reported while reading/writing the context buffer. 0x3 PAYLOAD_ERROR Error is signalled because an error was reported while reading/writing the payload. 0x4 INVALID_MODE Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). 0x5 TAG Indicates the tag from the last completed packet in the command structure. 24 8 read-only CH3STAT_SET DCP channel 3 status register 0x1E4 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates additional error codes for some of the error conditions. 16 8 read-write NEXT_CHAIN_IS_0 Error is signalled because the next pointer is 0x00000000. 0x1 NO_CHAIN Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. 0x2 CONTEXT_ERROR Error is signalled because an error was reported while reading/writing the context buffer. 0x3 PAYLOAD_ERROR Error is signalled because an error was reported while reading/writing the payload. 0x4 INVALID_MODE Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). 0x5 TAG Indicates the tag from the last completed packet in the command structure. 24 8 read-only CH3STAT_CLR DCP channel 3 status register 0x1E8 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates additional error codes for some of the error conditions. 16 8 read-write NEXT_CHAIN_IS_0 Error is signalled because the next pointer is 0x00000000. 0x1 NO_CHAIN Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. 0x2 CONTEXT_ERROR Error is signalled because an error was reported while reading/writing the context buffer. 0x3 PAYLOAD_ERROR Error is signalled because an error was reported while reading/writing the payload. 0x4 INVALID_MODE Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). 0x5 TAG Indicates the tag from the last completed packet in the command structure. 24 8 read-only CH3STAT_TOG DCP channel 3 status register 0x1EC 32 read-write 0 0xFFFFFFFF HASH_MISMATCH This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit 1 1 read-write ERROR_SETUP This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) 2 1 read-write ERROR_PACKET This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod 3 1 read-write ERROR_SRC This bit indicates that a bus error occurred when reading from the source buffer 4 1 read-write ERROR_DST This bit indicates that a bus error occurred when storing to the destination buffer 5 1 read-write ERROR_PAGEFAULT This bit indicates that a page fault occurred while converting a virtual address to a physical address 6 1 read-write ERROR_CODE Indicates additional error codes for some of the error conditions. 16 8 read-write NEXT_CHAIN_IS_0 Error is signalled because the next pointer is 0x00000000. 0x1 NO_CHAIN Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. 0x2 CONTEXT_ERROR Error is signalled because an error was reported while reading/writing the context buffer. 0x3 PAYLOAD_ERROR Error is signalled because an error was reported while reading/writing the payload. 0x4 INVALID_MODE Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). 0x5 TAG Indicates the tag from the last completed packet in the command structure. 24 8 read-only CH3OPTS DCP channel 3 options register 0x1F0 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH3OPTS_SET DCP channel 3 options register 0x1F4 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH3OPTS_CLR DCP channel 3 options register 0x1F8 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write CH3OPTS_TOG DCP channel 3 options register 0x1FC 32 read-write 0 0xFFFFFFFF RECOVERY_TIMER This field indicates the recovery time for the channel 0 16 read-write DBGSELECT DCP debug select register 0x400 32 read-write 0 0xFFFFFFFF INDEX Selects a value to read via the debug data register. 0 8 read-write CONTROL CONTROL 0x1 OTPKEY0 OTPKEY0 0x10 OTPKEY1 OTPKEY1 0x11 OTPKEY2 OTPKEY2 0x12 OTPKEY3 OTPKEY3 0x13 DBGDATA DCP debug data register 0x410 32 read-only 0 0xFFFFFFFF DATA Debug data 0 32 read-only PAGETABLE DCP page table register 0x420 32 read-write 0 0xFFFFFFFF ENABLE Page table enable control 0 1 read-write FLUSH Page table flush control. To flush the TLB, write this bit to 1 and then back to 0. 1 1 read-write BASE Page table base address 2 30 read-write VERSION DCP version register 0x430 32 read-only 0x2010000 0xFFFFFFFF STEP Fixed read-only value reflecting the stepping of the version of the design implementation. 0 16 read-only MINOR Fixed read-only value reflecting the MINOR version of the design implementation. 16 8 read-only MAJOR Fixed read-only value reflecting the MAJOR version of the design implementation. 24 8 read-only GPC GPC GPC GPC_ 0x400F4000 0 0x3C registers GPC 66 CNTR GPC Interface control register 0 32 read-write 0x520000 0xFFFFFFFF MEGA_PDN_REQ MEGA domain power down request 2 1 read-write MEGA_PDN_REQ_0 No Request 0 MEGA_PDN_REQ_1 Request power down sequence 0x1 MEGA_PUP_REQ MEGA domain power up request 3 1 read-write MEGA_PUP_REQ_0 No Request 0 MEGA_PUP_REQ_1 Request power up sequence 0x1 PDRAM0_PGE FlexRAM PDRAM0 Power Gate Enable 22 1 read-write PDRAM0_PGE_0 FlexRAM PDRAM0 domain will keep power even if the CPU core is powered down. 0 PDRAM0_PGE_1 FlexRAM PDRAM0 domain will be powered down when the CPU core is powered down.. 0x1 IMR1 IRQ masking register 1 0x8 32 read-write 0 0xFFFFFFFF IMR1 IRQ[31:0] masking bits: 1-irq masked, 0-irq is not masked 0 32 read-write IMR2 IRQ masking register 2 0xC 32 read-write 0 0xFFFFFFFF IMR2 IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked 0 32 read-write IMR3 IRQ masking register 3 0x10 32 read-write 0 0xFFFFFFFF IMR3 IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked 0 32 read-write IMR4 IRQ masking register 4 0x14 32 read-write 0 0xFFFFFFFF IMR4 IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked 0 32 read-write ISR1 IRQ status resister 1 0x18 32 read-only 0 0xFFFFFFFF ISR1 IRQ[31:0] status, read only 0 32 read-only ISR2 IRQ status resister 2 0x1C 32 read-only 0 0xFFFFFFFF ISR2 IRQ[63:32] status, read only 0 32 read-only ISR3 IRQ status resister 3 0x20 32 read-only 0 0xFFFFFFFF ISR3 IRQ[95:64] status, read only 0 32 read-only ISR4 IRQ status resister 4 0x24 32 read-only 0 0xFFFFFFFF ISR4 IRQ[127:96] status, read only 0 32 read-only IMR5 IRQ masking register 5 0x34 32 read-write 0 0xFFFFFFFF IMR5 IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked 0 32 read-write ISR5 IRQ status resister 5 0x38 32 read-only 0 0xFFFFFFFF ISR4 IRQ[159:128] status, read only 0 32 read-only PGC PGC GPC PGC PGC_ 0x400F4000 0 0x2B0 registers MEGA_CTRL PGC Mega Control Register 0x220 32 read-write 0 0xFFFFFFFF PCR Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up 0 1 read-write PCR_0 Do not switch off power even if pdn_req is asserted. 0 PCR_1 Switch off power when pdn_req is asserted. 0x1 MEGA_PUPSCR PGC Mega Power Up Sequence Control Register 0x224 32 read-write 0xF01 0xFFFFFFFF SW After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b) 0 6 read-write SW2ISO After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation 8 6 read-write MEGA_PDNSCR PGC Mega Pull Down Sequence Control Register 0x228 32 read-write 0x101 0xFFFFFFFF ISO After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation 0 6 read-write ISO2SW After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b) 8 6 read-write MEGA_SR PGC Mega Power Gating Controller Status Register 0x22C 32 read-write 0 0xFFFFFFFF PSR Power status 0 1 read-write PSR_0 The target subsystem was not powered down for the previous power-down request. 0 PSR_1 The target subsystem was powered down for the previous power-down request. 0x1 CPU_CTRL PGC CPU Control Register 0x2A0 32 read-write 0 0xFFFFFFFF PCR Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up 0 1 read-write PCR_0 Do not switch off power even if pdn_req is asserted. 0 PCR_1 Switch off power when pdn_req is asserted. 0x1 CPU_PUPSCR PGC CPU Power Up Sequence Control Register 0x2A4 32 read-write 0xF01 0xFFFFFFFF SW There are two different silicon revisions: 1 0 6 read-write SW2ISO There are two different silicon revisions: 1 8 6 read-write CPU_PDNSCR PGC CPU Pull Down Sequence Control Register 0x2A8 32 read-write 0x101 0xFFFFFFFF ISO After a power-down request (pdn_req assertion), the PGC waits a number of 32k clocks equal to the value of ISO before asserting isolation 0 6 read-write ISO2SW After asserting isolation, the PGC waits a number of 32k clocks equal to the value of ISO2SW before negating 8 6 read-write CPU_SR PGC CPU Power Gating Controller Status Register 0x2AC 32 read-write 0 0xFFFFFFFF PSR Power status 0 1 read-write PSR_0 The target subsystem was not powered down for the previous power-down request. 0 PSR_1 The target subsystem was powered down for the previous power-down request. 0x1 SRC SRC SRC SRC_ 0x400F8000 0 0x48 registers SRC 40 SCR SRC Control Register 0 32 read-write 0xA0480520 0xFFFFFFFF lockup_rst lockup reset enable bit 4 1 read-write lockup_rst_0 disabled 0 lockup_rst_1 enabled 0x1 mask_wdog_rst Mask wdog_rst_b source 7 4 read-write mask_wdog_rst_5 wdog_rst_b is masked 0x5 mask_wdog_rst_10 wdog_rst_b is not masked (default) 0xA core0_rst Software reset for core0 only 13 1 read-write core0_rst_0 do not assert core0 reset 0 core0_rst_1 assert core0 reset 0x1 core0_dbg_rst Software reset for core0 debug only 17 1 read-write core0_dbg_rst_0 do not assert core0 debug reset 0 core0_dbg_rst_1 assert core0 debug reset 0x1 dbg_rst_msk_pg Do not assert debug resets after power gating event of core 25 1 read-write dbg_rst_msk_pg_0 do not mask core debug resets (debug resets will be asserted after power gating event) 0 dbg_rst_msk_pg_1 mask core debug resets (debug resets won't be asserted after power gating event) 0x1 mask_wdog3_rst Mask wdog3_rst_b source 28 4 read-write mask_wdog3_rst_5 wdog3_rst_b is masked 0x5 mask_wdog3_rst_10 wdog3_rst_b is not masked 0xA SBMR1 SRC Boot Mode Register 1 0x4 32 read-only 0 0xFFFFFFFF BOOT_CFG1 Refer to fusemap. 0 8 read-only BOOT_CFG2 Refer to fusemap. 8 8 read-only BOOT_CFG3 Refer to fusemap. 16 8 read-only BOOT_CFG4 Refer to fusemap. 24 8 read-only SRSR SRC Reset Status Register 0x8 32 read-write 0x1 0xFFFFFFFF ipp_reset_b Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence) 0 1 read-write oneToClear ipp_reset_b_0 Reset is not a result of ipp_reset_b pin. 0 ipp_reset_b_1 Reset is a result of ipp_reset_b pin. 0x1 lockup Indicates a reset has been caused by CPU lockup. 1 1 read-write oneToClear lockup_0 Reset is not a result of the mentioned case. 0 lockup_1 Reset is a result of the mentioned case. 0x1 csu_reset_b Indicates whether the reset was the result of the csu_reset_b input. 2 1 read-write oneToClear csu_reset_b_0 Reset is not a result of the csu_reset_b event. 0 csu_reset_b_1 Reset is a result of the csu_reset_b event. 0x1 ipp_user_reset_b Indicates whether the reset was the result of the ipp_user_reset_b qualified reset. 3 1 read-write oneToClear ipp_user_reset_b_0 Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. 0 ipp_user_reset_b_1 Reset is a result of the ipp_user_reset_b qualified as COLD reset event. 0x1 wdog_rst_b IC Watchdog Time-out reset 4 1 read-write oneToClear wdog_rst_b_0 Reset is not a result of the watchdog time-out event. 0 wdog_rst_b_1 Reset is a result of the watchdog time-out event. 0x1 jtag_rst_b HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG. 5 1 read-write oneToClear jtag_rst_b_0 Reset is not a result of HIGH-Z reset from JTAG. 0 jtag_rst_b_1 Reset is a result of HIGH-Z reset from JTAG. 0x1 jtag_sw_rst JTAG software reset 6 1 read-write oneToClear jtag_sw_rst_0 Reset is not a result of the mentioned case. 0 jtag_sw_rst_1 Reset is not a result of the mentioned case. 0x1 wdog3_rst_b IC Watchdog3 Time-out reset 7 1 read-write oneToClear wdog3_rst_b_0 Reset is not a result of the watchdog3 time-out event. 0 wdog3_rst_b_1 Reset is a result of the watchdog3 time-out event. 0x1 tempsense_rst_b Temper Sensor software reset 8 1 read-write tempsense_rst_b_0 Reset is not a result of software reset from Temperature Sensor. 0 tempsense_rst_b_1 Reset is a result of software reset from Temperature Sensor. 0x1 SBMR2 SRC Boot Mode Register 2 0x1C 32 read-only 0 0xFFFFFFFF SEC_CONFIG SECONFIG[1] shows the state of the SECONFIG[1] fuse 0 2 read-only DIR_BT_DIS DIR_BT_DIS shows the state of the DIR_BT_DIS fuse 3 1 read-only BT_FUSE_SEL BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse 4 1 read-only BMOD BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B 24 2 read-only GPR1 SRC General Purpose Register 1 0x20 32 read-write 0 0xFFFFFFFF PERSISTENT_ENTRY0 Holds entry function for core0 for waking-up from low power mode 0 32 read-write GPR2 SRC General Purpose Register 2 0x24 32 read-write 0 0xFFFFFFFF PERSISTENT_ARG0 Holds argument of entry function for core0 for waking-up from low power mode 0 32 read-write GPR3 SRC General Purpose Register 3 0x28 32 read-write 0 0xFFFFFFFF GPR4 SRC General Purpose Register 4 0x2C 32 read-write 0 0xFFFFFFFF GPR5 SRC General Purpose Register 5 0x30 32 read-write 0 0xFFFFFFFF GPR6 SRC General Purpose Register 6 0x34 32 read-write 0 0xFFFFFFFF GPR7 SRC General Purpose Register 7 0x38 32 read-write 0 0xFFFFFFFF GPR8 SRC General Purpose Register 8 0x3C 32 read-write 0 0xFFFFFFFF GPR9 SRC General Purpose Register 9 0x40 32 read-only 0 0xFFFFFFFF GPR10 SRC General Purpose Register 10 0x44 32 read-write 0 0xFFFFFFFF PERSIST_REDUNDANT_BOOT This field identifies which image must be used - 0/1/2/3 26 2 read-write PERSIST_SECONDARY_BOOT This bit identifies which image must be used - primary and secondary 30 1 read-write CCM CCM CCM CCM_ 0x400FC000 0 0x8C registers CCM_1 42 CCM_2 43 CCR CCM Control Register 0 32 read-write 0x401107F 0xFFFFFFFF OSCNT Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for the dpll_ip to use and only then the gate in dpll_ip can be opened. 0 8 read-write COSC_EN On chip oscillator enable bit - this bit value is reflected on the output cosc_en 12 1 read-write COSC_EN_0 disable on chip oscillator 0 COSC_EN_1 enable on chip oscillator 0x1 REG_BYPASS_COUNT Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ 21 6 read-write REG_BYPASS_COUNT_0 no delay 0 REG_BYPASS_COUNT_1 1 CKIL clock period delay 0x1 REG_BYPASS_COUNT_63 63 CKIL clock periods delay 0x3F RBC_EN Enable for REG_BYPASS_COUNTER 27 1 read-write RBC_EN_0 REG_BYPASS_COUNTER disabled 0 RBC_EN_1 REG_BYPASS_COUNTER enabled. 0x1 CSR CCM Status Register 0x8 32 read-only 0x10 0xFFFFFFFF REF_EN_B Status of the value of CCM_REF_EN_B output of ccm 0 1 read-only REF_EN_B_0 value of CCM_REF_EN_B is '0' 0 REF_EN_B_1 value of CCM_REF_EN_B is '1' 0x1 CAMP2_READY Status indication of CAMP2. 3 1 read-only CAMP2_READY_0 CAMP2 is not ready. 0 CAMP2_READY_1 CAMP2 is ready. 0x1 COSC_READY Status indication of on board oscillator 5 1 read-only COSC_READY_0 on board oscillator is not ready. 0 COSC_READY_1 on board oscillator is ready. 0x1 CCSR CCM Clock Switcher Register 0xC 32 read-write 0 0xFFFFFFFF PLL3_SW_CLK_SEL Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes. 0 1 read-write PLL3_SW_CLK_SEL_0 pll3_main_clk 0 PLL3_SW_CLK_SEL_1 pll3 bypass clock 0x1 CBCDR CCM Bus Clock Divider Register 0x14 32 read-write 0x28000 0xFFFFFFFF IPG_PODF Divider for ipg podf. 8 2 read-write IPG_PODF_0 divide by 1 0 IPG_PODF_1 divide by 2 0x1 IPG_PODF_2 divide by 3 0x2 IPG_PODF_3 divide by 4 0x3 AHB_PODF Divider for AHB PODF 10 3 read-write AHB_PODF_0 divide by 1 0 AHB_PODF_1 divide by 2 0x1 AHB_PODF_2 divide by 3 0x2 AHB_PODF_3 divide by 4 0x3 AHB_PODF_4 divide by 5 0x4 AHB_PODF_5 divide by 6 0x5 AHB_PODF_6 divide by 7 0x6 AHB_PODF_7 divide by 8 0x7 PERIPH_CLK_SEL Selector for peripheral main clock 25 1 read-write PERIPH_CLK_SEL_0 derive clock selected by CCM_CBCMR[CORE_CLK_PRE_SEL] 0 PERIPH_CLK_SEL_1 derive clock selected by CCM_CBCMR[PERIPH_CLK2_SEL] 0x1 CBCMR CCM Bus Clock Multiplexer Register 0x18 32 read-write 0xC088020 0xFFFFFFFF LPSPI_CLK_SEL Selector for lpspi clock multiplexer 4 2 read-write LPSPI_CLK_SEL_0 derive clock from PLL3 PFD1 clk 0 LPSPI_CLK_SEL_1 derive clock from PLL3 PFD0 0x1 LPSPI_CLK_SEL_2 derive clock from PLL2 0x2 LPSPI_CLK_SEL_3 derive clock from PLL2 PFD2 0x3 PERIPH_CLK2_SEL Selector for peripheral clk2 clock multiplexer 12 2 read-write PERIPH_CLK2_SEL_0 derive clock from pll3_sw_clk 0 PERIPH_CLK2_SEL_1 derive clock from osc_clk 0x1 PERIPH_CLK2_SEL_2 derive clock from pll2_bypass_clk 0x2 TRACE_CLK_SEL Selector for Trace clock multiplexer 14 2 read-write TRACE_CLK_SEL_0 derive clock from PLL2 0 TRACE_CLK_SEL_1 derive clock from PLL2 PFD2 0x1 TRACE_CLK_SEL_2 derive clock from PLL2 PFD0 0x2 TRACE_CLK_SEL_3 derive clock from PLL2 PFD1 0x3 PRE_PERIPH_CLK_SEL Selector for pre_periph clock multiplexer 18 2 read-write PRE_PERIPH_CLK_SEL_0 derive clock from PLL2 0 PRE_PERIPH_CLK_SEL_1 derive clock from PLL3 PFD3 0x1 PRE_PERIPH_CLK_SEL_2 derive clock from PLL2 PFD3 0x2 PRE_PERIPH_CLK_SEL_3 derive clock from PLL6 0x3 LPSPI_PODF Divider for LPSPI. Divider should be updated when output clock is gated. 26 4 read-write LPSPI_PODF_0 divide by 1 0 LPSPI_PODF_1 divide by 2 0x1 LPSPI_PODF_2 divide by 3 0x2 LPSPI_PODF_3 divide by 4 0x3 LPSPI_PODF_4 divide by 5 0x4 LPSPI_PODF_5 divide by 6 0x5 LPSPI_PODF_6 divide by 7 0x6 LPSPI_PODF_7 divide by 8 0x7 LPSPI_PODF_8 divide by 9 0x8 LPSPI_PODF_9 divide by 10 0x9 LPSPI_PODF_10 divide by 11 0xA LPSPI_PODF_11 divide by 12 0xB LPSPI_PODF_12 divide by 13 0xC LPSPI_PODF_13 divide by 14 0xD LPSPI_PODF_14 divide by 15 0xE LPSPI_PODF_15 divide by 16 0xF CSCMR1 CCM Serial Clock Multiplexer Register 1 0x1C 32 read-write 0x80FC00 0xFFFFFFFF PERCLK_PODF Divider for perclk podf. 0 6 read-write DIVIDE_1 Divide by 1 0 DIVIDE_2 Divide by 2 0x1 DIVIDE_3 Divide by 3 0x2 DIVIDE_4 Divide by 4 0x3 DIVIDE_5 Divide by 5 0x4 DIVIDE_6 Divide by 6 0x5 DIVIDE_7 Divide by 7 0x6 DIVIDE_8 Divide by 8 0x7 DIVIDE_9 Divide by 9 0x8 DIVIDE_10 Divide by 10 0x9 DIVIDE_11 Divide by 11 0xA DIVIDE_12 Divide by 12 0xB DIVIDE_13 Divide by 13 0xC DIVIDE_14 Divide by 14 0xD DIVIDE_15 Divide by 15 0xE DIVIDE_16 Divide by 16 0xF DIVIDE_17 Divide by 17 0x10 DIVIDE_18 Divide by 18 0x11 DIVIDE_19 Divide by 19 0x12 DIVIDE_20 Divide by 20 0x13 DIVIDE_21 Divide by 21 0x14 DIVIDE_22 Divide by 22 0x15 DIVIDE_23 Divide by 23 0x16 DIVIDE_24 Divide by 24 0x17 DIVIDE_25 Divide by 25 0x18 DIVIDE_26 Divide by 26 0x19 DIVIDE_27 Divide by 27 0x1A DIVIDE_28 Divide by 28 0x1B DIVIDE_29 Divide by 29 0x1C DIVIDE_30 Divide by 30 0x1D DIVIDE_31 Divide by 31 0x1E DIVIDE_32 Divide by 32 0x1F DIVIDE_33 Divide by 33 0x20 DIVIDE_34 Divide by 34 0x21 DIVIDE_35 Divide by 35 0x22 DIVIDE_36 Divide by 36 0x23 DIVIDE_37 Divide by 37 0x24 DIVIDE_38 Divide by 38 0x25 DIVIDE_39 Divide by 39 0x26 DIVIDE_40 Divide by 40 0x27 DIVIDE_41 Divide by 41 0x28 DIVIDE_42 Divide by 42 0x29 DIVIDE_43 Divide by 43 0x2A DIVIDE_44 Divide by 44 0x2B DIVIDE_45 Divide by 45 0x2C DIVIDE_46 Divide by 46 0x2D DIVIDE_47 Divide by 47 0x2E DIVIDE_48 Divide by 48 0x2F DIVIDE_49 Divide by 49 0x30 DIVIDE_50 Divide by 50 0x31 DIVIDE_51 Divide by 51 0x32 DIVIDE_52 Divide by 52 0x33 DIVIDE_53 Divide by 53 0x34 DIVIDE_54 Divide by 54 0x35 DIVIDE_55 Divide by 55 0x36 DIVIDE_56 Divide by 56 0x37 DIVIDE_57 Divide by 57 0x38 DIVIDE_58 Divide by 58 0x39 DIVIDE_59 Divide by 59 0x3A DIVIDE_60 Divide by 60 0x3B DIVIDE_61 Divide by 61 0x3C DIVIDE_62 Divide by 62 0x3D DIVIDE_63 Divide by 63 0x3E DIVIDE_64 Divide by 64 0x3F PERCLK_CLK_SEL Selector for the perclk clock multiplexor 6 1 read-write PERCLK_CLK_SEL_0 derive clock from ipg clk root 0 PERCLK_CLK_SEL_1 derive clock from osc_clk 0x1 SAI1_CLK_SEL Selector for sai1 clock multiplexer 10 2 read-write SAI1_CLK_SEL_0 derive clock from PLL3 PFD2 0 SAI1_CLK_SEL_1 derive from pll3_sw_clk 0x1 SAI1_CLK_SEL_2 derive clock from PLL4 0x2 SAI3_CLK_SEL Selector for sai3 clock multiplexer 14 2 read-write SAI3_CLK_SEL_0 derive clock from PLL3 PFD2 0 SAI3_CLK_SEL_1 derive from pll3_sw_clk 0x1 SAI3_CLK_SEL_2 derive clock from PLL4 0x2 FLEXSPI_PODF Divider for flexspi clock root. 23 3 read-write FLEXSPI_PODF_0 divide by 1 0 FLEXSPI_PODF_1 divide by 2 0x1 FLEXSPI_PODF_2 divide by 3 0x2 FLEXSPI_PODF_3 divide by 4 0x3 FLEXSPI_PODF_4 divide by 5 0x4 FLEXSPI_PODF_5 divide by 6 0x5 FLEXSPI_PODF_6 divide by 7 0x6 FLEXSPI_PODF_7 divide by 8 0x7 FLEXSPI_CLK_SEL Selector for flexspi clock multiplexer 29 2 read-write FLEXSPI_CLK_SEL_0 derive clock from PLL2 0 FLEXSPI_CLK_SEL_1 derive clock from pll3_sw_clk 0x1 FLEXSPI_CLK_SEL_2 derive clock from PLL2 PFD2 0x2 FLEXSPI_CLK_SEL_3 derive clock from PLL3 PFD0 0x3 FLEXSPI_CLK_SRC Select for source of flexspi_clk_root 31 1 read-write FLEXSPI_CLK_SRC_0 derive clock selected by CCM_CSCMR1[FLEXSPI_CLK_SEL] 0 FLEXSPI_CLK_SRC_1 derive clock selected by CCM_CBCMR[PERIPH_CLK2_ SEL] 0x1 CSCMR2 CCM Serial Clock Multiplexer Register 2 0x20 32 read-write 0x180000 0xFFFFFFFF FLEXIO1_CLK_SEL Selector for flexio1 clock multiplexer 19 2 read-write FLEXIO1_CLK_SEL_0 derive clock from PLL4 divided clock 0 FLEXIO1_CLK_SEL_1 derive clock from PLL3 PFD2 clock 0x1 FLEXIO1_CLK_SEL_2 derive from PLL2 0x2 FLEXIO1_CLK_SEL_3 derive clock from pll3_sw_clk 0x3 ADC_ACLK_PODF Divider for ADC alt_clk, as the list below (other values reserved). 27 4 read-write ADC_ACLK_PODF_7 pll3_sw_clk / 8 0x7 ADC_ACLK_PODF_11 pll3_sw_clk / 12 0xB ADC_ACLK_PODF_15 pll3_sw_clk / 16 0xF ADC_ACLK_EN Enable ADC alt_clk, so that ADC alt_clk can be driven be divided pll3_sw_clk. 31 1 read-write ADC_ACLK_EN_0 ADC alt_clk source is disabled 0 ADC_ACLK_EN_1 ADC alt_clk source is enabled 0x1 CSCDR1 CCM Serial Clock Divider Register 1 0x24 32 read-write 0x6000000 0xFFFFFFFF UART_CLK_PODF Divider for uart clock podf. 0 6 read-write DIVIDE_1 Divide by 1 0 DIVIDE_2 Divide by 2 0x1 DIVIDE_3 Divide by 3 0x2 DIVIDE_4 Divide by 4 0x3 DIVIDE_5 Divide by 5 0x4 DIVIDE_6 Divide by 6 0x5 DIVIDE_7 Divide by 7 0x6 DIVIDE_8 Divide by 8 0x7 DIVIDE_9 Divide by 9 0x8 DIVIDE_10 Divide by 10 0x9 DIVIDE_11 Divide by 11 0xA DIVIDE_12 Divide by 12 0xB DIVIDE_13 Divide by 13 0xC DIVIDE_14 Divide by 14 0xD DIVIDE_15 Divide by 15 0xE DIVIDE_16 Divide by 16 0xF DIVIDE_17 Divide by 17 0x10 DIVIDE_18 Divide by 18 0x11 DIVIDE_19 Divide by 19 0x12 DIVIDE_20 Divide by 20 0x13 DIVIDE_21 Divide by 21 0x14 DIVIDE_22 Divide by 22 0x15 DIVIDE_23 Divide by 23 0x16 DIVIDE_24 Divide by 24 0x17 DIVIDE_25 Divide by 25 0x18 DIVIDE_26 Divide by 26 0x19 DIVIDE_27 Divide by 27 0x1A DIVIDE_28 Divide by 28 0x1B DIVIDE_29 Divide by 29 0x1C DIVIDE_30 Divide by 30 0x1D DIVIDE_31 Divide by 31 0x1E DIVIDE_32 Divide by 32 0x1F DIVIDE_33 Divide by 33 0x20 DIVIDE_34 Divide by 34 0x21 DIVIDE_35 Divide by 35 0x22 DIVIDE_36 Divide by 36 0x23 DIVIDE_37 Divide by 37 0x24 DIVIDE_38 Divide by 38 0x25 DIVIDE_39 Divide by 39 0x26 DIVIDE_40 Divide by 40 0x27 DIVIDE_41 Divide by 41 0x28 DIVIDE_42 Divide by 42 0x29 DIVIDE_43 Divide by 43 0x2A DIVIDE_44 Divide by 44 0x2B DIVIDE_45 Divide by 45 0x2C DIVIDE_46 Divide by 46 0x2D DIVIDE_47 Divide by 47 0x2E DIVIDE_48 Divide by 48 0x2F DIVIDE_49 Divide by 49 0x30 DIVIDE_50 Divide by 50 0x31 DIVIDE_51 Divide by 51 0x32 DIVIDE_52 Divide by 52 0x33 DIVIDE_53 Divide by 53 0x34 DIVIDE_54 Divide by 54 0x35 DIVIDE_55 Divide by 55 0x36 DIVIDE_56 Divide by 56 0x37 DIVIDE_57 Divide by 57 0x38 DIVIDE_58 Divide by 58 0x39 DIVIDE_59 Divide by 59 0x3A DIVIDE_60 Divide by 60 0x3B DIVIDE_61 Divide by 61 0x3C DIVIDE_62 Divide by 62 0x3D DIVIDE_63 Divide by 63 0x3E DIVIDE_64 Divide by 64 0x3F UART_CLK_SEL Selector for the UART clock multiplexor 6 2 read-write UART_CLK_SEL_0 derive clock from pll3_80m 0 UART_CLK_SEL_1 derive clock from osc_clk 0x1 UART_CLK_SEL_2 derive clock from per_clk_root 0x2 TRACE_PODF Divider for trace clock. Divider should be updated when output clock is gated. 25 4 read-write TRACE_PODF_0 divide by 1 0 TRACE_PODF_1 divide by 2 0x1 TRACE_PODF_2 divide by 3 0x2 TRACE_PODF_3 divide by 4 0x3 TRACE_PODF_4 divide by 5 0x4 TRACE_PODF_5 divide by 6 0x5 TRACE_PODF_6 divide by 7 0x6 TRACE_PODF_7 divide by 8 0x7 TRACE_PODF_8 divide by 9 0x8 TRACE_PODF_9 divide by 10 0x9 TRACE_PODF_10 divide by 11 0xA TRACE_PODF_11 divide by 12 0xB TRACE_PODF_12 divide by 13 0xC TRACE_PODF_13 divide by 14 0xD TRACE_PODF_14 divide by 15 0xE TRACE_PODF_15 divide by 16 0xF CS1CDR CCM Clock Divider Register 0x28 32 read-write 0xEC102C1 0xFFFFFFFF SAI1_CLK_PODF Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. 0 6 read-write DIVIDE_1 Divide by 1 0 DIVIDE_2 Divide by 2 0x1 DIVIDE_3 Divide by 3 0x2 DIVIDE_4 Divide by 4 0x3 DIVIDE_5 Divide by 5 0x4 DIVIDE_6 Divide by 6 0x5 DIVIDE_7 Divide by 7 0x6 DIVIDE_8 Divide by 8 0x7 DIVIDE_9 Divide by 9 0x8 DIVIDE_10 Divide by 10 0x9 DIVIDE_11 Divide by 11 0xA DIVIDE_12 Divide by 12 0xB DIVIDE_13 Divide by 13 0xC DIVIDE_14 Divide by 14 0xD DIVIDE_15 Divide by 15 0xE DIVIDE_16 Divide by 16 0xF DIVIDE_17 Divide by 17 0x10 DIVIDE_18 Divide by 18 0x11 DIVIDE_19 Divide by 19 0x12 DIVIDE_20 Divide by 20 0x13 DIVIDE_21 Divide by 21 0x14 DIVIDE_22 Divide by 22 0x15 DIVIDE_23 Divide by 23 0x16 DIVIDE_24 Divide by 24 0x17 DIVIDE_25 Divide by 25 0x18 DIVIDE_26 Divide by 26 0x19 DIVIDE_27 Divide by 27 0x1A DIVIDE_28 Divide by 28 0x1B DIVIDE_29 Divide by 29 0x1C DIVIDE_30 Divide by 30 0x1D DIVIDE_31 Divide by 31 0x1E DIVIDE_32 Divide by 32 0x1F DIVIDE_33 Divide by 33 0x20 DIVIDE_34 Divide by 34 0x21 DIVIDE_35 Divide by 35 0x22 DIVIDE_36 Divide by 36 0x23 DIVIDE_37 Divide by 37 0x24 DIVIDE_38 Divide by 38 0x25 DIVIDE_39 Divide by 39 0x26 DIVIDE_40 Divide by 40 0x27 DIVIDE_41 Divide by 41 0x28 DIVIDE_42 Divide by 42 0x29 DIVIDE_43 Divide by 43 0x2A DIVIDE_44 Divide by 44 0x2B DIVIDE_45 Divide by 45 0x2C DIVIDE_46 Divide by 46 0x2D DIVIDE_47 Divide by 47 0x2E DIVIDE_48 Divide by 48 0x2F DIVIDE_49 Divide by 49 0x30 DIVIDE_50 Divide by 50 0x31 DIVIDE_51 Divide by 51 0x32 DIVIDE_52 Divide by 52 0x33 DIVIDE_53 Divide by 53 0x34 DIVIDE_54 Divide by 54 0x35 DIVIDE_55 Divide by 55 0x36 DIVIDE_56 Divide by 56 0x37 DIVIDE_57 Divide by 57 0x38 DIVIDE_58 Divide by 58 0x39 DIVIDE_59 Divide by 59 0x3A DIVIDE_60 Divide by 60 0x3B DIVIDE_61 Divide by 61 0x3C DIVIDE_62 Divide by 62 0x3D DIVIDE_63 Divide by 63 0x3E DIVIDE_64 Divide by 64 0x3F SAI1_CLK_PRED Divider for sai1 clock pred. 6 3 read-write SAI1_CLK_PRED_0 divide by 1 0 SAI1_CLK_PRED_1 divide by 2 0x1 SAI1_CLK_PRED_2 divide by 3 0x2 SAI1_CLK_PRED_3 divide by 4 0x3 SAI1_CLK_PRED_4 divide by 5 0x4 SAI1_CLK_PRED_5 divide by 6 0x5 SAI1_CLK_PRED_6 divide by 7 0x6 SAI1_CLK_PRED_7 divide by 8 0x7 FLEXIO1_CLK_PRED Divider for flexio1 clock. 9 3 read-write FLEXIO1_CLK_PRED_0 divide by 1 0 FLEXIO1_CLK_PRED_1 divide by 2 0x1 FLEXIO1_CLK_PRED_2 divide by 3 0x2 FLEXIO1_CLK_PRED_3 divide by 4 0x3 FLEXIO1_CLK_PRED_4 divide by 5 0x4 FLEXIO1_CLK_PRED_5 divide by 6 0x5 FLEXIO1_CLK_PRED_6 divide by 7 0x6 FLEXIO1_CLK_PRED_7 divide by 8 0x7 SAI3_CLK_PODF Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. 16 6 read-write DIVIDE_1 Divide by 1 0 DIVIDE_2 Divide by 2 0x1 DIVIDE_3 Divide by 3 0x2 DIVIDE_4 Divide by 4 0x3 DIVIDE_5 Divide by 5 0x4 DIVIDE_6 Divide by 6 0x5 DIVIDE_7 Divide by 7 0x6 DIVIDE_8 Divide by 8 0x7 DIVIDE_9 Divide by 9 0x8 DIVIDE_10 Divide by 10 0x9 DIVIDE_11 Divide by 11 0xA DIVIDE_12 Divide by 12 0xB DIVIDE_13 Divide by 13 0xC DIVIDE_14 Divide by 14 0xD DIVIDE_15 Divide by 15 0xE DIVIDE_16 Divide by 16 0xF DIVIDE_17 Divide by 17 0x10 DIVIDE_18 Divide by 18 0x11 DIVIDE_19 Divide by 19 0x12 DIVIDE_20 Divide by 20 0x13 DIVIDE_21 Divide by 21 0x14 DIVIDE_22 Divide by 22 0x15 DIVIDE_23 Divide by 23 0x16 DIVIDE_24 Divide by 24 0x17 DIVIDE_25 Divide by 25 0x18 DIVIDE_26 Divide by 26 0x19 DIVIDE_27 Divide by 27 0x1A DIVIDE_28 Divide by 28 0x1B DIVIDE_29 Divide by 29 0x1C DIVIDE_30 Divide by 30 0x1D DIVIDE_31 Divide by 31 0x1E DIVIDE_32 Divide by 32 0x1F DIVIDE_33 Divide by 33 0x20 DIVIDE_34 Divide by 34 0x21 DIVIDE_35 Divide by 35 0x22 DIVIDE_36 Divide by 36 0x23 DIVIDE_37 Divide by 37 0x24 DIVIDE_38 Divide by 38 0x25 DIVIDE_39 Divide by 39 0x26 DIVIDE_40 Divide by 40 0x27 DIVIDE_41 Divide by 41 0x28 DIVIDE_42 Divide by 42 0x29 DIVIDE_43 Divide by 43 0x2A DIVIDE_44 Divide by 44 0x2B DIVIDE_45 Divide by 45 0x2C DIVIDE_46 Divide by 46 0x2D DIVIDE_47 Divide by 47 0x2E DIVIDE_48 Divide by 48 0x2F DIVIDE_49 Divide by 49 0x30 DIVIDE_50 Divide by 50 0x31 DIVIDE_51 Divide by 51 0x32 DIVIDE_52 Divide by 52 0x33 DIVIDE_53 Divide by 53 0x34 DIVIDE_54 Divide by 54 0x35 DIVIDE_55 Divide by 55 0x36 DIVIDE_56 Divide by 56 0x37 DIVIDE_57 Divide by 57 0x38 DIVIDE_58 Divide by 58 0x39 DIVIDE_59 Divide by 59 0x3A DIVIDE_60 Divide by 60 0x3B DIVIDE_61 Divide by 61 0x3C DIVIDE_62 Divide by 62 0x3D DIVIDE_63 Divide by 63 0x3E DIVIDE_64 Divide by 64 0x3F SAI3_CLK_PRED Divider for sai3 clock pred. 22 3 read-write SAI3_CLK_PRED_0 divide by 1 0 SAI3_CLK_PRED_1 divide by 2 0x1 SAI3_CLK_PRED_2 divide by 3 0x2 SAI3_CLK_PRED_3 divide by 4 0x3 SAI3_CLK_PRED_4 divide by 5 0x4 SAI3_CLK_PRED_5 divide by 6 0x5 SAI3_CLK_PRED_6 divide by 7 0x6 SAI3_CLK_PRED_7 divide by 8 0x7 FLEXIO1_CLK_PODF Divider for flexio1 clock. Divider should be updated when output clock is gated. 25 4 read-write DIVIDE_1 Divide by 1 0 DIVIDE_2 Divide by 2 0x1 DIVIDE_3 Divide by 3 0x2 DIVIDE_4 Divide by 4 0x3 DIVIDE_5 Divide by 5 0x4 DIVIDE_6 Divide by 6 0x5 DIVIDE_7 Divide by 7 0x6 DIVIDE_8 Divide by 8 0x7 DIVIDE_9 Divide by 9 0x8 DIVIDE_10 Divide by 10 0x9 DIVIDE_11 Divide by 11 0xA DIVIDE_12 Divide by 12 0xB DIVIDE_13 Divide by 13 0xC DIVIDE_14 Divide by 14 0xD DIVIDE_15 Divide by 15 0xE DIVIDE_16 Divide by 16 0xF CDCDR CCM D1 Clock Divider Register 0x30 32 read-write 0x3F00000 0xFFFFFFFF SPDIF0_CLK_SEL Selector for spdif0 clock multiplexer 20 2 read-write SPDIF0_CLK_SEL_0 derive clock from PLL4 0 SPDIF0_CLK_SEL_1 derive clock from PLL3 PFD2 0x1 SPDIF0_CLK_SEL_3 derive clock from pll3_sw_clk 0x3 SPDIF0_CLK_PODF Divider for spdif0 clock podf. Divider should be updated when output clock is gated. 22 3 read-write DIVIDE_1 Divide by 1 0 DIVIDE_2 Divide by 2 0x1 DIVIDE_3 Divide by 3 0x2 DIVIDE_4 Divide by 4 0x3 DIVIDE_5 Divide by 5 0x4 DIVIDE_6 Divide by 6 0x5 DIVIDE_7 Divide by 7 0x6 DIVIDE_8 Divide by 8 0x7 SPDIF0_CLK_PRED Divider for spdif0 clock pred. Divider should be updated when output clock is gated. 25 3 read-write DIVIDE_1 Divide by 1 0 DIVIDE_2 Divide by 2 0x1 DIVIDE_3 Divide by 3 0x2 DIVIDE_4 Divide by 4 0x3 DIVIDE_5 Divide by 5 0x4 DIVIDE_6 Divide by 6 0x5 DIVIDE_7 Divide by 7 0x6 DIVIDE_8 Divide by 8 0x7 CSCDR2 CCM Serial Clock Divider Register 2 0x38 32 read-write 0x39000 0xFFFFFFFF LPI2C_CLK_SEL Selector for the LPI2C clock multiplexor 18 1 read-write LPI2C_CLK_SEL_0 derive clock from pll3_60m 0 LPI2C_CLK_SEL_1 derive clock from osc_clk 0x1 LPI2C_CLK_PODF Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. 19 6 read-write DIVIDE_1 Divide by 1 0 DIVIDE_2 Divide by 2 0x1 DIVIDE_3 Divide by 3 0x2 DIVIDE_4 Divide by 4 0x3 DIVIDE_5 Divide by 5 0x4 DIVIDE_6 Divide by 6 0x5 DIVIDE_7 Divide by 7 0x6 DIVIDE_8 Divide by 8 0x7 DIVIDE_9 Divide by 9 0x8 DIVIDE_10 Divide by 10 0x9 DIVIDE_11 Divide by 11 0xA DIVIDE_12 Divide by 12 0xB DIVIDE_13 Divide by 13 0xC DIVIDE_14 Divide by 14 0xD DIVIDE_15 Divide by 15 0xE DIVIDE_16 Divide by 16 0xF DIVIDE_17 Divide by 17 0x10 DIVIDE_18 Divide by 18 0x11 DIVIDE_19 Divide by 19 0x12 DIVIDE_20 Divide by 20 0x13 DIVIDE_21 Divide by 21 0x14 DIVIDE_22 Divide by 22 0x15 DIVIDE_23 Divide by 23 0x16 DIVIDE_24 Divide by 24 0x17 DIVIDE_25 Divide by 25 0x18 DIVIDE_26 Divide by 26 0x19 DIVIDE_27 Divide by 27 0x1A DIVIDE_28 Divide by 28 0x1B DIVIDE_29 Divide by 29 0x1C DIVIDE_30 Divide by 30 0x1D DIVIDE_31 Divide by 31 0x1E DIVIDE_32 Divide by 32 0x1F DIVIDE_33 Divide by 33 0x20 DIVIDE_34 Divide by 34 0x21 DIVIDE_35 Divide by 35 0x22 DIVIDE_36 Divide by 36 0x23 DIVIDE_37 Divide by 37 0x24 DIVIDE_38 Divide by 38 0x25 DIVIDE_39 Divide by 39 0x26 DIVIDE_40 Divide by 40 0x27 DIVIDE_41 Divide by 41 0x28 DIVIDE_42 Divide by 42 0x29 DIVIDE_43 Divide by 43 0x2A DIVIDE_44 Divide by 44 0x2B DIVIDE_45 Divide by 45 0x2C DIVIDE_46 Divide by 46 0x2D DIVIDE_47 Divide by 47 0x2E DIVIDE_48 Divide by 48 0x2F DIVIDE_49 Divide by 49 0x30 DIVIDE_50 Divide by 50 0x31 DIVIDE_51 Divide by 51 0x32 DIVIDE_52 Divide by 52 0x33 DIVIDE_53 Divide by 53 0x34 DIVIDE_54 Divide by 54 0x35 DIVIDE_55 Divide by 55 0x36 DIVIDE_56 Divide by 56 0x37 DIVIDE_57 Divide by 57 0x38 DIVIDE_58 Divide by 58 0x39 DIVIDE_59 Divide by 59 0x3A DIVIDE_60 Divide by 60 0x3B DIVIDE_61 Divide by 61 0x3C DIVIDE_62 Divide by 62 0x3D DIVIDE_63 Divide by 63 0x3E DIVIDE_64 Divide by 64 0x3F CDHIPR CCM Divider Handshake In-Process Register 0x48 32 read-only 0 0xFFFFFFFF AHB_PODF_BUSY Busy indicator for ahb_podf. 1 1 read-only AHB_PODF_BUSY_0 divider is not busy and its value represents the actual division. 0 AHB_PODF_BUSY_1 divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied. 0x1 FLEXSPI_PODF_BUSY Busy indicator for flexspi_podf. 3 1 read-only FLEXSPI_PODF_BUSY_0 divider is not busy and its value represents the actual division. 0 FLEXSPI_PODF_BUSY_1 divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the flexspi_podf will be applied. 0x1 PERCLK_PODF_BUSY Busy indicator for perclk_podf. 4 1 read-only PERCLK_PODF_BUSY_0 divider is not busy and its value represents the actual division. 0 PERCLK_PODF_BUSY_1 divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the perclk_podf will be applied. 0x1 PERIPH_CLK_SEL_BUSY Busy indicator for periph_clk_sel mux control. 5 1 read-only PERIPH_CLK_SEL_BUSY_0 mux is not busy and its value represents the actual division. 0 PERIPH_CLK_SEL_BUSY_1 mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied. 0x1 CLPCR CCM Low Power Control Register 0x54 32 read-write 0x79 0xFFFFFFFF LPM Setting the low power mode that system will enter on next assertion of dsm_request signal. 0 2 read-write LPM_0 Remain in run mode 0 LPM_1 Transfer to wait mode 0x1 LPM_2 Transfer to stop mode 0x2 ARM_CLK_DIS_ON_LPM Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode 5 1 read-write ARM_CLK_DIS_ON_LPM_0 ARM clock enabled on wait mode. 0 ARM_CLK_DIS_ON_LPM_1 ARM clock disabled on wait mode. . 0x1 SBYOS Standby clock oscillator bit 6 1 read-write SBYOS_0 On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') 0 SBYOS_1 On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process. 0x1 DIS_REF_OSC dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i 7 1 read-write DIS_REF_OSC_0 external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. 0 DIS_REF_OSC_1 external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' 0x1 VSTBY Voltage standby request bit 8 1 read-write VSTBY_0 Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') 0 VSTBY_1 Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). 0x1 STBY_COUNT Standby counter definition 9 2 read-write STBY_COUNT_0 CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles 0 STBY_COUNT_1 CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles 0x1 STBY_COUNT_2 CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles 0x2 STBY_COUNT_3 CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles 0x3 COSC_PWRDOWN In run mode, software can manually control powering down of on chip oscillator, i 11 1 read-write COSC_PWRDOWN_0 On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. 0 COSC_PWRDOWN_1 On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. 0x1 MASK_CORE0_WFI Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request 22 1 read-write MASK_CORE0_WFI_0 WFI of core0 is not masked 0 MASK_CORE0_WFI_1 WFI of core0 is masked 0x1 MASK_SCU_IDLE Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request 26 1 read-write MASK_SCU_IDLE_0 SCU IDLE is not masked 0 MASK_SCU_IDLE_1 SCU IDLE is masked 0x1 MASK_L2CC_IDLE Mask L2CC IDLE for entering low power mode 27 1 read-write MASK_L2CC_IDLE_0 L2CC IDLE is not masked 0 MASK_L2CC_IDLE_1 L2CC IDLE is masked 0x1 CISR CCM Interrupt Status Register 0x58 32 read-write 0 0xFFFFFFFF LRF_PLL CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs 0 1 read-write oneToClear LRF_PLL_0 interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs 0 LRF_PLL_1 interrupt generated due to lock ready of all enabled and not bypaseed PLLs 0x1 COSC_READY CCM interrupt request 2 generated due to on board oscillator ready, i 6 1 read-write oneToClear COSC_READY_0 interrupt is not generated due to on board oscillator ready 0 COSC_READY_1 interrupt generated due to on board oscillator ready 0x1 FLEXSPI_PODF_LOADED CCM interrupt request 1 generated due to frequency change of flexspi_podf 16 1 read-write oneToClear FLEXSPI_PODF_LOADED_0 interrupt is not generated due to frequency change of flexspi_podf 0 FLEXSPI_PODF_LOADED_1 interrupt generated due to frequency change of flexspi_podf 0x1 PERCLK_PODF_LOADED CCM interrupt request 1 generated due to frequency change of perclk_podf 18 1 read-write oneToClear PERCLK_PODF_LOADED_0 interrupt is not generated due to frequency change of perclk_podf 0 PERCLK_PODF_LOADED_1 interrupt generated due to frequency change of perclk_podf 0x1 AHB_PODF_LOADED CCM interrupt request 1 generated due to frequency change of ahb_podf 20 1 read-write oneToClear AHB_PODF_LOADED_0 interrupt is not generated due to frequency change of ahb_podf 0 AHB_PODF_LOADED_1 interrupt generated due to frequency change of ahb_podf 0x1 PERIPH_CLK_SEL_LOADED CCM interrupt request 1 generated due to update of periph_clk_sel. 22 1 read-write oneToClear PERIPH_CLK_SEL_LOADED_0 interrupt is not generated due to update of periph_clk_sel. 0 PERIPH_CLK_SEL_LOADED_1 interrupt generated due to update of periph_clk_sel. 0x1 CIMR CCM Interrupt Mask Register 0x5C 32 read-write 0xFFFFFFFF 0xFFFFFFFF MASK_LRF_PLL mask interrupt generation due to lrf of PLLs 0 1 read-write MASK_LRF_PLL_0 don't mask interrupt due to lrf of PLLs - interrupt will be created 0 MASK_LRF_PLL_1 mask interrupt due to lrf of PLLs 0x1 MASK_COSC_READY mask interrupt generation due to on board oscillator ready 6 1 read-write MASK_COSC_READY_0 don't mask interrupt due to on board oscillator ready - interrupt will be created 0 MASK_COSC_READY_1 mask interrupt due to on board oscillator ready 0x1 MASK_FLEXSPI_PODF_LOADED mask interrupt generation due to update of flexspi_podf 16 1 read-write MASK_FLEXSPI_PODF_LOADED_0 don't mask interrupt due to update of flexspi_podf 0 MASK_FLEXSPI_PODF_LOADED_1 mask interrupt due to update of flexspi_podf 0x1 MASK_PERCLK_PODF_LOADED mask interrupt generation due to update of perclk_podf 18 1 read-write MASK_PERCLK_PODF_LOADED_0 don't mask interrupt due to update of perclk_podf 0 MASK_PERCLK_PODF_LOADED_1 mask interrupt due to update of perclk_podf 0x1 MASK_AHB_PODF_LOADED mask interrupt generation due to frequency change of ahb_podf 20 1 read-write MASK_AHB_PODF_LOADED_0 don't mask interrupt due to frequency change of ahb_podf - interrupt will be created 0 MASK_AHB_PODF_LOADED_1 mask interrupt due to frequency change of ahb_podf 0x1 MASK_PERIPH_CLK_SEL_LOADED mask interrupt generation due to update of periph_clk_sel. 22 1 read-write MASK_PERIPH_CLK_SEL_LOADED_0 don't mask interrupt due to update of periph_clk_sel - interrupt will be created 0 MASK_PERIPH_CLK_SEL_LOADED_1 mask interrupt due to update of periph_clk_sel 0x1 CCOSR CCM Clock Output Source Register 0x60 32 read-write 0xA0001 0xFFFFFFFF CLKO1_SEL Selection of the clock to be generated on CCM_CLKO1 0 4 read-write CLKO1_SEL_0 pll3_sw_clk (divided by 2) 0 CLKO1_SEL_1 PLL2 (divided by 2) 0x1 CLKO1_SEL_2 ENET PLL (divided by 2) 0x2 CLKO1_SEL_11 core_clk_root 0xB CLKO1_SEL_12 ipg_clk_root 0xC CLKO1_SEL_13 perclk_root 0xD CLKO1_SEL_15 pll4_main_clk 0xF CLKO1_DIV Setting the divider of CCM_CLKO1 4 3 read-write CLKO1_DIV_0 divide by 1 0 CLKO1_DIV_1 divide by 2 0x1 CLKO1_DIV_2 divide by 3 0x2 CLKO1_DIV_3 divide by 4 0x3 CLKO1_DIV_4 divide by 5 0x4 CLKO1_DIV_5 divide by 6 0x5 CLKO1_DIV_6 divide by 7 0x6 CLKO1_DIV_7 divide by 8 0x7 CLKO1_EN Enable of CCM_CLKO1 clock 7 1 read-write CLKO1_EN_0 CCM_CLKO1 disabled. 0 CLKO1_EN_1 CCM_CLKO1 enabled. 0x1 CLK_OUT_SEL CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks 8 1 read-write CLK_OUT_SEL_0 CCM_CLKO1 output drives CCM_CLKO1 clock 0 CLK_OUT_SEL_1 CCM_CLKO1 output drives CCM_CLKO2 clock 0x1 CLKO2_SEL Selection of the clock to be generated on CCM_CLKO2 16 5 read-write CLKO2_SEL_6 lpi2c_clk_root 0x6 CLKO2_SEL_14 osc_clk 0xE CLKO2_SEL_16 lpspi_clk_root 0x10 CLKO2_SEL_18 sai1_clk_root 0x12 CLKO2_SEL_20 sai3_clk_root 0x14 CLKO2_SEL_22 trace_clk_root 0x16 CLKO2_SEL_27 flexspi_clk_root 0x1B CLKO2_SEL_28 uart_clk_root 0x1C CLKO2_SEL_29 spdif0_clk_root 0x1D CLKO2_DIV Setting the divider of CCM_CLKO2 21 3 read-write CLKO2_DIV_0 divide by 1 0 CLKO2_DIV_1 divide by 2 0x1 CLKO2_DIV_2 divide by 3 0x2 CLKO2_DIV_3 divide by 4 0x3 CLKO2_DIV_4 divide by 5 0x4 CLKO2_DIV_5 divide by 6 0x5 CLKO2_DIV_6 divide by 7 0x6 CLKO2_DIV_7 divide by 8 0x7 CLKO2_EN Enable of CCM_CLKO2 clock 24 1 read-write CLKO2_EN_0 CCM_CLKO2 disabled. 0 CLKO2_EN_1 CCM_CLKO2 enabled. 0x1 CGPR CCM General Purpose Register 0x64 32 read-write 0xC000 0xFFFFFFFF PMIC_DELAY_SCALER Defines clock dividion of clock for stby_count (pmic delay counter) 0 1 read-write PMIC_DELAY_SCALER_0 clock is not divided 0 PMIC_DELAY_SCALER_1 clock is divided /8 0x1 EFUSE_PROG_SUPPLY_GATE Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing 4 1 read-write EFUSE_PROG_SUPPLY_GATE_0 fuse programing supply voltage is gated off to the efuse module 0 EFUSE_PROG_SUPPLY_GATE_1 allow fuse programing. 0x1 SYS_MEM_DS_CTRL System memory DS control 14 2 read-write SYS_MEM_DS_CTRL_0 Disable memory DS mode always 0 SYS_MEM_DS_CTRL_1 Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled 0x1 SYS_MEM_DS_CTRL_2 enable memory (outside ARM platform) DS mode when system is in STOP mode #1x FPL Fast PLL enable. 16 1 read-write FPL_0 Engage PLL enable default way. 0 FPL_1 Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. 0x1 INT_MEM_CLK_LPM Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal 17 1 read-write INT_MEM_CLK_LPM_0 Disable the clock to the ARM platform memories when entering Low Power Mode 0 INT_MEM_CLK_LPM_1 Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating) 0x1 CCGR0 CCM Clock Gating Register 0 0x68 32 read-write 0xFFFFFFFF 0xFFFFFFFF CG0 aips_tz1 clocks (aips_tz1_clk_enable) 0 2 read-write CG1 aips_tz2 clocks (aips_tz2_clk_enable) 2 2 read-write CG2 mqs clock ( mqs_hmclk_clock_enable) 4 2 read-write CG3 flexspi_exsc clock (flexspi_exsc_clk_enable) 6 2 read-write CG4 sim_m_clk_r_clk_enable 8 2 read-write CG5 dcp clock (dcp_clk_enable) 10 2 read-write CG6 lpuart3 clock (lpuart3_clk_enable) 12 2 read-write CG7 Reserved 14 2 read-write CG8 Reserved 16 2 read-write CG9 Reserved 18 2 read-write CG10 Reserved 20 2 read-write CG11 trace clock (trace_clk_enable) 22 2 read-write CG12 gpt2 bus clocks (gpt2_bus_clk_enable) 24 2 read-write CG13 gpt2 serial clocks (gpt2_serial_clk_enable) 26 2 read-write CG14 lpuart2 clock (lpuart2_clk_enable) 28 2 read-write CG15 gpio2_clocks (gpio2_clk_enable) 30 2 read-write CCGR1 CCM Clock Gating Register 1 0x6C 32 read-write 0xFFFFFFFF 0xFFFFFFFF CG0 lpspi1 clocks (lpspi1_clk_enable) 0 2 read-write CG1 lpspi2 clocks (lpspi2_clk_enable) 2 2 read-write CG2 Reserved 4 2 read-write CG3 Reserved 6 2 read-write CG4 Reserved 8 2 read-write CG5 Reserved 10 2 read-write CG6 pit clocks (pit_clk_enable) 12 2 read-write CG7 Reserved 14 2 read-write CG8 adc1 clock (adc1_clk_enable) 16 2 read-write CG9 Reserved 18 2 read-write CG10 gpt1 bus clock (gpt_clk_enable) 20 2 read-write CG11 gpt1 serial clock (gpt_serial_clk_enable) 22 2 read-write CG12 lpuart4 clock (lpuart4_clk_enable) 24 2 read-write CG13 gpio1 clock (gpio1_clk_enable) 26 2 read-write CG14 csu clock (csu_clk_enable) 28 2 read-write CG15 gpio5 clock (gpio5_clk_enable) 30 2 read-write CCGR2 CCM Clock Gating Register 2 0x70 32 read-write 0xFFFFFFFF 0xFFFFFFFF CG0 ocram_exsc clock (ocram_exsc_clk_enable) 0 2 read-write CG1 Reserved 2 2 read-write CG2 iomuxc_snvs clock (iomuxc_snvs_clk_enable) 4 2 read-write CG3 lpi2c1 clock (lpi2c1_clk_enable) 6 2 read-write CG4 lpi2c2 clock (lpi2c2_clk_enable) 8 2 read-write CG5 Reserved 10 2 read-write CG6 OCOTP_CTRL clock (iim_clk_enable) 12 2 read-write CG7 Reserved 14 2 read-write CG8 Reserved 16 2 read-write CG9 Reserved 18 2 read-write CG10 Reserved 20 2 read-write CG11 xbar1 clock (xbar1_clk_enable) 22 2 read-write CG12 Reserved 24 2 read-write CG13 Reserved 26 2 read-write CG14 Reserved 28 2 read-write CG15 Reserved 30 2 read-write CCGR3 CCM Clock Gating Register 3 0x74 32 read-write 0xFFFFFFFF 0xFFFFFFFF CG0 Reserved 0 2 read-write CG1 Reserved 2 2 read-write CG2 Reserved 4 2 read-write CG3 Reserved 6 2 read-write CG4 aoi1 clock (aoi1_clk_enable) 8 2 read-write CG5 Reserved 10 2 read-write CG6 Reserved 12 2 read-write CG7 ewm clocks (ewm_clk_enable) 14 2 read-write CG8 wdog1 clock (wdog1_clk_enable) 16 2 read-write CG9 flexram clock (flexram_clk_enable) 18 2 read-write CG10 Reserved 20 2 read-write CG11 Reserved 22 2 read-write CG12 Reserved 24 2 read-write CG13 Reserved 26 2 read-write CG14 The OCRAM clock cannot be turned off when the CM cache is running on this device. 28 2 read-write CG15 iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable) 30 2 read-write CCGR4 CCM Clock Gating Register 4 0x78 32 read-write 0xFFFFFFFF 0xFFFFFFFF CG0 sim_m7_clk_r_enable 0 2 read-write CG1 iomuxc clock (iomuxc_clk_enable) 2 2 read-write CG2 iomuxc gpr clock (iomuxc_gpr_clk_enable) 4 2 read-write CG3 Reserved 6 2 read-write CG4 sim_m7 clock (sim_m7_clk_enable) 8 2 read-write CG5 Reserved 10 2 read-write CG6 sim_m clocks (sim_m_clk_enable) 12 2 read-write CG7 sim_ems clocks (sim_ems_clk_enable) 14 2 read-write CG8 pwm1 clocks (pwm1_clk_enable) 16 2 read-write CG9 Reserved 18 2 read-write CG10 Reserved 20 2 read-write CG11 Reserved 22 2 read-write CG12 Reserved 24 2 read-write CG13 Reserved 26 2 read-write CG14 Reserved 28 2 read-write CG15 dma_ps clocks (dma_ps_clk_enable) 30 2 read-write CCGR5 CCM Clock Gating Register 5 0x7C 32 read-write 0xFFFFFFFF 0xFFFFFFFF CG0 rom clock (rom_clk_enable) 0 2 read-write CG1 flexio1 clock (flexio1_clk_enable) 2 2 read-write CG2 wdog3 clock (wdog3_clk_enable) 4 2 read-write CG3 dma clock (dma_clk_enable) 6 2 read-write CG4 kpp clock (kpp_clk_enable) 8 2 read-write CG5 wdog2 clock (wdog2_clk_enable) 10 2 read-write CG6 Reserved 12 2 read-write CG7 spdif clock (spdif_clk_enable) 14 2 read-write CG8 Reserved 16 2 read-write CG9 sai1 clock (sai1_clk_enable) 18 2 read-write CG10 Reserved 20 2 read-write CG11 sai3 clock (sai3_clk_enable) 22 2 read-write CG12 lpuart1 clock (lpuart1_clk_enable) 24 2 read-write CG13 Reserved 26 2 read-write CG14 snvs_hp clock (snvs_hp_clk_enable) 28 2 read-write CG15 snvs_lp clock (snvs_lp_clk_enable) 30 2 read-write CCGR6 CCM Clock Gating Register 6 0x80 32 read-write 0xFFFFFFFF 0xFFFFFFFF CG0 usboh3 clock (usboh3_clk_enable) 0 2 read-write CG1 Reserved 2 2 read-write CG2 Reserved 4 2 read-write CG3 dcdc clocks (dcdc_clk_enable) 6 2 read-write CG4 Reserved 8 2 read-write CG5 flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared 10 2 read-write CG6 trng clock (trng_clk_enable) 12 2 read-write CG7 Reserved 14 2 read-write CG8 Reserved 16 2 read-write CG9 Reserved 18 2 read-write CG10 sim_per clock (sim_per_clk_enable) 20 2 read-write CG11 anadig clocks (anadig_clk_enable) 22 2 read-write CG12 Reserved 24 2 read-write CG13 Reserved 26 2 read-write CG14 Reserved 28 2 read-write CG15 Reserved 30 2 read-write CMEOR CCM Module Enable Overide Register 0x88 32 read-write 0xFFFFFFFF 0xFFFFFFFF MOD_EN_OV_GPT Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk' 5 1 read-write MOD_EN_OV_GPT_0 don't override module enable signal 0 MOD_EN_OV_GPT_1 override module enable signal 0x1 MOD_EN_OV_PIT Overide clock enable signal from PIT - clock will not be gated based on PIT's signal 'ipg_enable_clk' 6 1 read-write MOD_EN_OV_PIT_0 don't override module enable signal 0 MOD_EN_OV_PIT_1 override module enable signal 0x1 MOD_EN_OV_TRNG Overide clock enable signal from TRNG 9 1 read-write MOD_EN_OV_TRNG_0 don't override module enable signal 0 MOD_EN_OV_TRNG_1 override module enable signal 0x1 ROMC ROMC ROMC ROMC_ 0x40180000 0 0x20C registers 8 0x4 7,6,5,4,3,2,1,0 ROMPATCH%sD ROMC Data Registers 0xD4 32 read-write 0 0xFFFFFFFF DATAX Data Fix Registers - Stores the data used for 1-word data fix operations 0 32 read-write ROMPATCHCNTL ROMC Control Register 0xF4 32 read-write 0x8400000 0xFFFFFFFF DATAFIX Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for code patch routine 0 8 read-write DATAFIX_0 Address comparator triggers a opcode patch 0 DATAFIX_1 Address comparator triggers a data fix 0x1 DIS ROMC Disable -- This bit, when set, disables all ROMC operations 29 1 read-write DIS_0 Does not affect any ROMC functions (default) 0 DIS_1 Disable all ROMC functions: data fixing, and opcode patching 0x1 ROMPATCHENH ROMC Enable Register High 0xF8 32 read-only 0 0xFFFFFFFF ROMPATCHENL ROMC Enable Register Low 0xFC 32 read-write 0 0xFFFFFFFF ENABLE Enable Address Comparator - This bit enables the corresponding address comparator to trigger an event 0 16 read-write ENABLE_0 Address comparator disabled 0 ENABLE_1 Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address 0x1 16 0x4 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 ROMPATCH%sA ROMC Address Registers 0x100 32 read-write 0 0xFFFFFFFF THUMBX THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch 0 1 read-write THUMBX_0 Arm patch 0 THUMBX_1 THUMB patch (ignore if data fix) 0x1 ADDRX Address Comparator Registers - Indicates the memory address to be watched 1 22 read-write ROMPATCHSR ROMC Status Register 0x208 32 read-write 0 0xFFFFFFFF SOURCE ROMC Source Number - Binary encoding of the number of the address comparator which has an address match in the most recent patch event on ROMC AHB 0 6 read-only SOURCE_0 Address Comparator 0 matched 0 SOURCE_1 Address Comparator 1 matched 0x1 SOURCE_15 Address Comparator 15 matched 0xF SW ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address comparator matches occurred 17 1 read-write oneToClear SW_0 no event or comparator collisions 0 SW_1 a collision has occurred 0x1 LPUART1 LPUART LPUART LPUART 0x40184000 0 0x30 registers LPUART1 20 VERID Version ID Register 0 32 read-only 0x4010003 0xFFFFFFFF FEATURE Feature Identification Number 0 16 read-only FEATURE_1 Standard feature set. 0x1 FEATURE_3 Standard feature set with MODEM/IrDA support. 0x3 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x202 0xFFFFFFFF TXFIFO Transmit FIFO Size 0 8 read-only RXFIFO Receive FIFO Size 8 8 read-only GLOBAL LPUART Global Register 0x8 32 read-write 0 0xFFFFFFFF RST Software Reset 1 1 read-write RST_0 Module is not reset. 0 RST_1 Module is reset. 0x1 PINCFG LPUART Pin Configuration Register 0xC 32 read-write 0 0xFFFFFFFF TRGSEL Trigger Select 0 2 read-write TRGSEL_0 Input trigger is disabled. 0 TRGSEL_1 Input trigger is used instead of RXD pin input. 0x1 TRGSEL_2 Input trigger is used instead of CTS_B pin input. 0x2 TRGSEL_3 Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. 0x3 BAUD LPUART Baud Rate Register 0x10 32 read-write 0xF000004 0xFFFFFFFF SBR Baud Rate Modulo Divisor. 0 13 read-write SBNS Stop Bit Number Select 13 1 read-write SBNS_0 One stop bit. 0 SBNS_1 Two stop bits. 0x1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write RXEDGIE_0 Hardware interrupts from STAT[RXEDGIF] are disabled. 0 RXEDGIE_1 Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. 0x1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write LBKDIE_0 Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). 0 LBKDIE_1 Hardware interrupt requested when STAT[LBKDIF] flag is 1. 0x1 RESYNCDIS Resynchronization Disable 16 1 read-write RESYNCDIS_0 Resynchronization during received data word is supported 0 RESYNCDIS_1 Resynchronization during received data word is disabled 0x1 BOTHEDGE Both Edge Sampling 17 1 read-write BOTHEDGE_0 Receiver samples input data using the rising edge of the baud rate clock. 0 BOTHEDGE_1 Receiver samples input data using the rising and falling edge of the baud rate clock. 0x1 MATCFG Match Configuration 18 2 read-write MATCFG_0 Address Match Wakeup 0 MATCFG_1 Idle Match Wakeup 0x1 MATCFG_2 Match On and Match Off 0x2 MATCFG_3 Enables RWU on Data Match and Match On/Off for transmitter CTS input 0x3 RIDMAE Receiver Idle DMA Enable 20 1 read-write RIDMAE_0 DMA request disabled. 0 RIDMAE_1 DMA request enabled. 0x1 RDMAE Receiver Full DMA Enable 21 1 read-write RDMAE_0 DMA request disabled. 0 RDMAE_1 DMA request enabled. 0x1 TDMAE Transmitter DMA Enable 23 1 read-write TDMAE_0 DMA request disabled. 0 TDMAE_1 DMA request enabled. 0x1 OSR Oversampling Ratio 24 5 read-write OSR_0 Writing 0 to this field will result in an oversampling ratio of 16 0 OSR_3 Oversampling ratio of 4, requires BOTHEDGE to be set. 0x3 OSR_4 Oversampling ratio of 5, requires BOTHEDGE to be set. 0x4 OSR_5 Oversampling ratio of 6, requires BOTHEDGE to be set. 0x5 OSR_6 Oversampling ratio of 7, requires BOTHEDGE to be set. 0x6 OSR_7 Oversampling ratio of 8. 0x7 OSR_8 Oversampling ratio of 9. 0x8 OSR_9 Oversampling ratio of 10. 0x9 OSR_10 Oversampling ratio of 11. 0xA OSR_11 Oversampling ratio of 12. 0xB OSR_12 Oversampling ratio of 13. 0xC OSR_13 Oversampling ratio of 14. 0xD OSR_14 Oversampling ratio of 15. 0xE OSR_15 Oversampling ratio of 16. 0xF OSR_16 Oversampling ratio of 17. 0x10 OSR_17 Oversampling ratio of 18. 0x11 OSR_18 Oversampling ratio of 19. 0x12 OSR_19 Oversampling ratio of 20. 0x13 OSR_20 Oversampling ratio of 21. 0x14 OSR_21 Oversampling ratio of 22. 0x15 OSR_22 Oversampling ratio of 23. 0x16 OSR_23 Oversampling ratio of 24. 0x17 OSR_24 Oversampling ratio of 25. 0x18 OSR_25 Oversampling ratio of 26. 0x19 OSR_26 Oversampling ratio of 27. 0x1A OSR_27 Oversampling ratio of 28. 0x1B OSR_28 Oversampling ratio of 29. 0x1C OSR_29 Oversampling ratio of 30. 0x1D OSR_30 Oversampling ratio of 31. 0x1E OSR_31 Oversampling ratio of 32. 0x1F M10 10-bit Mode select 29 1 read-write M10_0 Receiver and transmitter use 7-bit to 9-bit data characters. 0 M10_1 Receiver and transmitter use 10-bit data characters. 0x1 MAEN2 Match Address Mode Enable 2 30 1 read-write MAEN2_0 Normal operation. 0 MAEN2_1 Enables automatic address matching or data matching mode for MATCH[MA2]. 0x1 MAEN1 Match Address Mode Enable 1 31 1 read-write MAEN1_0 Normal operation. 0 MAEN1_1 Enables automatic address matching or data matching mode for MATCH[MA1]. 0x1 STAT LPUART Status Register 0x14 32 read-write 0xC00000 0xFFFFFFFF MA2F Match 2 Flag 14 1 read-write oneToClear MA2F_0 Received data is not equal to MA2 0 MA2F_1 Received data is equal to MA2 0x1 MA1F Match 1 Flag 15 1 read-write oneToClear MA1F_0 Received data is not equal to MA1 0 MA1F_1 Received data is equal to MA1 0x1 PF Parity Error Flag 16 1 read-write oneToClear PF_0 No parity error. 0 PF_1 Parity error. 0x1 FE Framing Error Flag 17 1 read-write oneToClear FE_0 No framing error detected. This does not guarantee the framing is correct. 0 FE_1 Framing error. 0x1 NF Noise Flag 18 1 read-write oneToClear NF_0 No noise detected. 0 NF_1 Noise detected in the received character in the DATA register. 0x1 OR Receiver Overrun Flag 19 1 read-write oneToClear OR_0 No overrun. 0 OR_1 Receive overrun (new LPUART data lost). 0x1 IDLE Idle Line Flag 20 1 read-write oneToClear IDLE_0 No idle line detected. 0 IDLE_1 Idle line was detected. 0x1 RDRF Receive Data Register Full Flag 21 1 read-only RDRF_0 Receive data buffer empty. 0 RDRF_1 Receive data buffer full. 0x1 TC Transmission Complete Flag 22 1 read-only TC_0 Transmitter active (sending data, a preamble, or a break). 0 TC_1 Transmitter idle (transmission activity complete). 0x1 TDRE Transmit Data Register Empty Flag 23 1 read-only TDRE_0 Transmit data buffer full. 0 TDRE_1 Transmit data buffer empty. 0x1 RAF Receiver Active Flag 24 1 read-only RAF_0 LPUART receiver idle waiting for a start bit. 0 RAF_1 LPUART receiver active (RXD input not idle). 0x1 LBKDE LIN Break Detection Enable 25 1 read-write LBKDE_0 LIN break detect is disabled, normal break character can be detected. 0 LBKDE_1 LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). 0x1 BRK13 Break Character Generation Length 26 1 read-write BRK13_0 Break character is transmitted with length of 9 to 13 bit times. 0 BRK13_1 Break character is transmitted with length of 12 to 15 bit times. 0x1 RWUID Receive Wake Up Idle Detect 27 1 read-write RWUID_0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. 0 RWUID_1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. 0x1 RXINV Receive Data Inversion 28 1 read-write RXINV_0 Receive data not inverted. 0 RXINV_1 Receive data inverted. 0x1 MSBF MSB First 29 1 read-write MSBF_0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. 0 MSBF_1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. 0x1 RXEDGIF RXD Pin Active Edge Interrupt Flag 30 1 read-write oneToClear RXEDGIF_0 No active edge on the receive pin has occurred. 0 RXEDGIF_1 An active edge on the receive pin has occurred. 0x1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write oneToClear LBKDIF_0 No LIN break character has been detected. 0 LBKDIF_1 LIN break character has been detected. 0x1 CTRL LPUART Control Register 0x18 32 read-write 0 0xFFFFFFFF PT Parity Type 0 1 read-write PT_0 Even parity. 0 PT_1 Odd parity. 0x1 PE Parity Enable 1 1 read-write PE_0 No hardware parity generation or checking. 0 PE_1 Parity enabled. 0x1 ILT Idle Line Type Select 2 1 read-write ILT_0 Idle character bit count starts after start bit. 0 ILT_1 Idle character bit count starts after stop bit. 0x1 WAKE Receiver Wakeup Method Select 3 1 read-write WAKE_0 Configures RWU for idle-line wakeup. 0 WAKE_1 Configures RWU with address-mark wakeup. 0x1 M 9-Bit or 8-Bit Mode Select 4 1 read-write M_0 Receiver and transmitter use 8-bit data characters. 0 M_1 Receiver and transmitter use 9-bit data characters. 0x1 RSRC Receiver Source Select 5 1 read-write RSRC_0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. 0 RSRC_1 Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. 0x1 DOZEEN Doze Enable 6 1 read-write DOZEEN_0 LPUART is enabled in Doze mode. 0 DOZEEN_1 LPUART is disabled in Doze mode. 0x1 LOOPS Loop Mode Select 7 1 read-write LOOPS_0 Normal operation - RXD and TXD use separate pins. 0 LOOPS_1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). 0x1 IDLECFG Idle Configuration 8 3 read-write IDLECFG_0 1 idle character 0 IDLECFG_1 2 idle characters 0x1 IDLECFG_2 4 idle characters 0x2 IDLECFG_3 8 idle characters 0x3 IDLECFG_4 16 idle characters 0x4 IDLECFG_5 32 idle characters 0x5 IDLECFG_6 64 idle characters 0x6 IDLECFG_7 128 idle characters 0x7 M7 7-Bit Mode Select 11 1 read-write M7_0 Receiver and transmitter use 8-bit to 10-bit data characters. 0 M7_1 Receiver and transmitter use 7-bit data characters. 0x1 MA2IE Match 2 Interrupt Enable 14 1 read-write MA2IE_0 MA2F interrupt disabled 0 MA2IE_1 MA2F interrupt enabled 0x1 MA1IE Match 1 Interrupt Enable 15 1 read-write MA1IE_0 MA1F interrupt disabled 0 MA1IE_1 MA1F interrupt enabled 0x1 SBK Send Break 16 1 read-write SBK_0 Normal transmitter operation. 0 SBK_1 Queue break character(s) to be sent. 0x1 RWU Receiver Wakeup Control 17 1 read-write RWU_0 Normal receiver operation. 0 RWU_1 LPUART receiver in standby waiting for wakeup condition. 0x1 RE Receiver Enable 18 1 read-write RE_0 Receiver disabled. 0 RE_1 Receiver enabled. 0x1 TE Transmitter Enable 19 1 read-write TE_0 Transmitter disabled. 0 TE_1 Transmitter enabled. 0x1 ILIE Idle Line Interrupt Enable 20 1 read-write ILIE_0 Hardware interrupts from IDLE disabled; use polling. 0 ILIE_1 Hardware interrupt requested when IDLE flag is 1. 0x1 RIE Receiver Interrupt Enable 21 1 read-write RIE_0 Hardware interrupts from RDRF disabled; use polling. 0 RIE_1 Hardware interrupt requested when RDRF flag is 1. 0x1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write TCIE_0 Hardware interrupts from TC disabled; use polling. 0 TCIE_1 Hardware interrupt requested when TC flag is 1. 0x1 TIE Transmit Interrupt Enable 23 1 read-write TIE_0 Hardware interrupts from TDRE disabled; use polling. 0 TIE_1 Hardware interrupt requested when TDRE flag is 1. 0x1 PEIE Parity Error Interrupt Enable 24 1 read-write PEIE_0 PF interrupts disabled; use polling). 0 PEIE_1 Hardware interrupt requested when PF is set. 0x1 FEIE Framing Error Interrupt Enable 25 1 read-write FEIE_0 FE interrupts disabled; use polling. 0 FEIE_1 Hardware interrupt requested when FE is set. 0x1 NEIE Noise Error Interrupt Enable 26 1 read-write NEIE_0 NF interrupts disabled; use polling. 0 NEIE_1 Hardware interrupt requested when NF is set. 0x1 ORIE Overrun Interrupt Enable 27 1 read-write ORIE_0 OR interrupts disabled; use polling. 0 ORIE_1 Hardware interrupt requested when OR is set. 0x1 TXINV Transmit Data Inversion 28 1 read-write TXINV_0 Transmit data not inverted. 0 TXINV_1 Transmit data inverted. 0x1 TXDIR TXD Pin Direction in Single-Wire Mode 29 1 read-write TXDIR_0 TXD pin is an input in single-wire mode. 0 TXDIR_1 TXD pin is an output in single-wire mode. 0x1 R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write DATA LPUART Data Register 0x1C 32 read-write 0x1000 0xFFFFFFFF R0T0 R0T0 0 1 read-write R1T1 R1T1 1 1 read-write R2T2 R2T2 2 1 read-write R3T3 R3T3 3 1 read-write R4T4 R4T4 4 1 read-write R5T5 R5T5 5 1 read-write R6T6 R6T6 6 1 read-write R7T7 R7T7 7 1 read-write R8T8 R8T8 8 1 read-write R9T9 R9T9 9 1 read-write IDLINE Idle Line 11 1 read-only IDLINE_0 Receiver was not idle before receiving this character. 0 IDLINE_1 Receiver was idle before receiving this character. 0x1 RXEMPT Receive Buffer Empty 12 1 read-only RXEMPT_0 Receive buffer contains valid data. 0 RXEMPT_1 Receive buffer is empty, data returned on read is not valid. 0x1 FRETSC Frame Error / Transmit Special Character 13 1 read-write FRETSC_0 The dataword was received without a frame error on read, or transmit a normal character on write. 0 FRETSC_1 The dataword was received with a frame error, or transmit an idle or break character on transmit. 0x1 PARITYE PARITYE 14 1 read-only PARITYE_0 The dataword was received without a parity error. 0 PARITYE_1 The dataword was received with a parity error. 0x1 NOISY NOISY 15 1 read-only NOISY_0 The dataword was received without noise. 0 NOISY_1 The data was received with noise. 0x1 MATCH LPUART Match Address Register 0x20 32 read-write 0 0xFFFFFFFF MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x24 32 read-write 0 0xFFFFFFFF TXCTSE Transmitter clear-to-send enable 0 1 read-write TXCTSE_0 CTS has no effect on the transmitter. 0 TXCTSE_1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. 0x1 TXRTSE Transmitter request-to-send enable 1 1 read-write TXRTSE_0 The transmitter has no effect on RTS. 0 TXRTSE_1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. 0x1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write TXRTSPOL_0 Transmitter RTS is active low. 0 TXRTSPOL_1 Transmitter RTS is active high. 0x1 RXRTSE Receiver request-to-send enable 3 1 read-write RXRTSE_0 The receiver has no effect on RTS. 0 RXRTSE_1 RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. 0x1 TXCTSC Transmit CTS Configuration 4 1 read-write TXCTSC_0 CTS input is sampled at the start of each character. 0 TXCTSC_1 CTS input is sampled when the transmitter is idle. 0x1 TXCTSSRC Transmit CTS Source 5 1 read-write TXCTSSRC_0 CTS input is the CTS_B pin. 0 TXCTSSRC_1 CTS input is the inverted Receiver Match result. 0x1 RTSWATER Receive RTS Configuration 8 2 read-write TNP Transmitter narrow pulse 16 2 read-write TNP_0 1/OSR. 0 TNP_1 2/OSR. 0x1 TNP_2 3/OSR. 0x2 TNP_3 4/OSR. 0x3 IREN Infrared enable 18 1 read-write IREN_0 IR disabled. 0 IREN_1 IR enabled. 0x1 FIFO LPUART FIFO Register 0x28 32 read-write 0xC00011 0xFFFFFFFF RXFIFOSIZE Receive FIFO Buffer Depth 0 3 read-only RXFIFOSIZE_0 Receive FIFO/Buffer depth = 1 dataword. 0 RXFIFOSIZE_1 Receive FIFO/Buffer depth = 4 datawords. 0x1 RXFIFOSIZE_2 Receive FIFO/Buffer depth = 8 datawords. 0x2 RXFIFOSIZE_3 Receive FIFO/Buffer depth = 16 datawords. 0x3 RXFIFOSIZE_4 Receive FIFO/Buffer depth = 32 datawords. 0x4 RXFIFOSIZE_5 Receive FIFO/Buffer depth = 64 datawords. 0x5 RXFIFOSIZE_6 Receive FIFO/Buffer depth = 128 datawords. 0x6 RXFIFOSIZE_7 Receive FIFO/Buffer depth = 256 datawords. 0x7 RXFE Receive FIFO Enable 3 1 read-write RXFE_0 Receive FIFO is not enabled. Buffer is depth 1. 0 RXFE_1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. 0x1 TXFIFOSIZE Transmit FIFO Buffer Depth 4 3 read-only TXFIFOSIZE_0 Transmit FIFO/Buffer depth = 1 dataword. 0 TXFIFOSIZE_1 Transmit FIFO/Buffer depth = 4 datawords. 0x1 TXFIFOSIZE_2 Transmit FIFO/Buffer depth = 8 datawords. 0x2 TXFIFOSIZE_3 Transmit FIFO/Buffer depth = 16 datawords. 0x3 TXFIFOSIZE_4 Transmit FIFO/Buffer depth = 32 datawords. 0x4 TXFIFOSIZE_5 Transmit FIFO/Buffer depth = 64 datawords. 0x5 TXFIFOSIZE_6 Transmit FIFO/Buffer depth = 128 datawords. 0x6 TXFIFOSIZE_7 Transmit FIFO/Buffer depth = 256 datawords 0x7 TXFE Transmit FIFO Enable 7 1 read-write TXFE_0 Transmit FIFO is not enabled. Buffer is depth 1. 0 TXFE_1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. 0x1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write RXUFE_0 RXUF flag does not generate an interrupt to the host. 0 RXUFE_1 RXUF flag generates an interrupt to the host. 0x1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write TXOFE_0 TXOF flag does not generate an interrupt to the host. 0 TXOFE_1 TXOF flag generates an interrupt to the host. 0x1 RXIDEN Receiver Idle Empty Enable 10 3 read-write RXIDEN_0 Disable RDRF assertion due to partially filled FIFO when receiver is idle. 0 RXIDEN_1 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 0x1 RXIDEN_2 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 0x2 RXIDEN_3 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 0x3 RXIDEN_4 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 0x4 RXIDEN_5 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 0x5 RXIDEN_6 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 0x6 RXIDEN_7 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. 0x7 RXFLUSH Receive FIFO/Buffer Flush 14 1 read-write RXFLUSH_0 No flush operation occurs. 0 RXFLUSH_1 All data in the receive FIFO/buffer is cleared out. 0x1 TXFLUSH Transmit FIFO/Buffer Flush 15 1 read-write TXFLUSH_0 No flush operation occurs. 0 TXFLUSH_1 All data in the transmit FIFO/Buffer is cleared out. 0x1 RXUF Receiver Buffer Underflow Flag 16 1 read-write oneToClear RXUF_0 No receive buffer underflow has occurred since the last time the flag was cleared. 0 RXUF_1 At least one receive buffer underflow has occurred since the last time the flag was cleared. 0x1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write oneToClear TXOF_0 No transmit buffer overflow has occurred since the last time the flag was cleared. 0 TXOF_1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. 0x1 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only RXEMPT_0 Receive buffer is not empty. 0 RXEMPT_1 Receive buffer is empty. 0x1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only TXEMPT_0 Transmit buffer is not empty. 0 TXEMPT_1 Transmit buffer is empty. 0x1 WATER LPUART Watermark Register 0x2C 32 read-write 0 0xFFFFFFFF TXWATER Transmit Watermark 0 2 read-write TXCOUNT Transmit Counter 8 3 read-only RXWATER Receive Watermark 16 2 read-write RXCOUNT Receive Counter 24 3 read-only LPUART2 LPUART LPUART 0x40188000 0 0x30 registers LPUART2 21 LPUART3 LPUART LPUART 0x4018C000 0 0x30 registers LPUART3 22 LPUART4 LPUART LPUART 0x40190000 0 0x30 registers LPUART4 23 LPSPI1 LPSPI LPSPI LPSPI 0x40194000 0 0x78 registers LPSPI1 32 VERID Version ID Register 0 32 read-only 0x1020004 0xFFFFFFFF FEATURE Module Identification Number 0 16 read-only FEATURE_4 Standard feature set supporting a 32-bit shift register. 0x4 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x40404 0xFFFFFFFF TXFIFO Transmit FIFO Size 0 8 read-only RXFIFO Receive FIFO Size 8 8 read-only PCSNUM PCS Number 16 8 read-only CR Control Register 0x10 32 read-write 0 0xFFFFFFFF MEN Module Enable 0 1 read-write MEN_0 Module is disabled 0 MEN_1 Module is enabled 0x1 RST Software Reset 1 1 read-write RST_0 Module is not reset 0 RST_1 Module is reset 0x1 DOZEN Doze Mode Enable 2 1 read-write DOZEN_0 LPSPI module is enabled in Doze mode 0 DOZEN_1 LPSPI module is disabled in Doze mode 0x1 DBGEN Debug Enable 3 1 read-write DBGEN_0 LPSPI module is disabled in debug mode 0 DBGEN_1 LPSPI module is enabled in debug mode 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit FIFO is reset 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive FIFO is reset 0x1 SR Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data not requested 0 TDF_1 Transmit data is requested 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive Data is not ready 0 RDF_1 Receive data is ready 0x1 WCF Word Complete Flag 8 1 read-write oneToClear WCF_0 Transfer of a received word has not yet completed 0 WCF_1 Transfer of a received word has completed 0x1 FCF Frame Complete Flag 9 1 read-write oneToClear FCF_0 Frame transfer has not completed 0 FCF_1 Frame transfer has completed 0x1 TCF Transfer Complete Flag 10 1 read-write oneToClear TCF_0 All transfers have not completed 0 TCF_1 All transfers have completed 0x1 TEF Transmit Error Flag 11 1 read-write oneToClear TEF_0 Transmit FIFO underrun has not occurred 0 TEF_1 Transmit FIFO underrun has occurred 0x1 REF Receive Error Flag 12 1 read-write oneToClear REF_0 Receive FIFO has not overflowed 0 REF_1 Receive FIFO has overflowed 0x1 DMF Data Match Flag 13 1 read-write oneToClear DMF_0 Have not received matching data 0 DMF_1 Have received matching data 0x1 MBF Module Busy Flag 24 1 read-only MBF_0 LPSPI is idle 0 MBF_1 LPSPI is busy 0x1 IER Interrupt Enable Register 0x18 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 WCIE Word Complete Interrupt Enable 8 1 read-write WCIE_0 Disabled 0 WCIE_1 Enabled 0x1 FCIE Frame Complete Interrupt Enable 9 1 read-write FCIE_0 Disabled 0 FCIE_1 Enabled 0x1 TCIE Transfer Complete Interrupt Enable 10 1 read-write TCIE_0 Disabled 0 TCIE_1 Enabled 0x1 TEIE Transmit Error Interrupt Enable 11 1 read-write TEIE_0 Disabled 0 TEIE_1 Enabled 0x1 REIE Receive Error Interrupt Enable 12 1 read-write REIE_0 Disabled 0 REIE_1 Enabled 0x1 DMIE Data Match Interrupt Enable 13 1 read-write DMIE_0 Disabled 0 DMIE_1 Enabled 0x1 DER DMA Enable Register 0x1C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 CFGR0 Configuration Register 0 0x20 32 read-write 0 0xFFFFFFFF HREN Host Request Enable 0 1 read-write HREN_0 Host request is disabled 0 HREN_1 Host request is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write HRPOL_0 Active low 0 HRPOL_1 Active high 0x1 HRSEL Host Request Select 2 1 read-write HRSEL_0 Host request input is the LPSPI_HREQ pin 0 HRSEL_1 Host request input is the input trigger 0x1 CIRFIFO Circular FIFO Enable 8 1 read-write CIRFIFO_0 Circular FIFO is disabled 0 CIRFIFO_1 Circular FIFO is enabled 0x1 RDMO Receive Data Match Only 9 1 read-write RDMO_0 Received data is stored in the receive FIFO as in normal operations 0 RDMO_1 Received data is discarded unless the Data Match Flag (DMF) is set 0x1 CFGR1 Configuration Register 1 0x24 32 read-write 0 0xFFFFFFFF MASTER Master Mode 0 1 read-write MASTER_0 Slave mode 0 MASTER_1 Master mode 0x1 SAMPLE Sample Point 1 1 read-write SAMPLE_0 Input data is sampled on SCK edge 0 SAMPLE_1 Input data is sampled on delayed SCK edge 0x1 AUTOPCS Automatic PCS 2 1 read-write AUTOPCS_0 Automatic PCS generation is disabled 0 AUTOPCS_1 Automatic PCS generation is enabled 0x1 NOSTALL No Stall 3 1 read-write NOSTALL_0 Transfers will stall when the transmit FIFO is empty or the receive FIFO is full 0 NOSTALL_1 Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur 0x1 PCSPOL Peripheral Chip Select Polarity 8 4 read-write PCSPOL_0 The Peripheral Chip Select pin PCSx is active low 0 PCSPOL_1 The Peripheral Chip Select pin PCSx is active high 0x1 MATCFG Match Configuration 16 3 read-write MATCFG_0 Match is disabled 0 MATCFG_2 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) 0x2 MATCFG_3 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) 0x3 MATCFG_4 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] 0x4 MATCFG_5 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] 0x5 MATCFG_6 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] 0x6 MATCFG_7 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] 0x7 PINCFG Pin Configuration 24 2 read-write PINCFG_0 SIN is used for input data and SOUT is used for output data 0 PINCFG_1 SIN is used for both input and output data 0x1 PINCFG_2 SOUT is used for both input and output data 0x2 PINCFG_3 SOUT is used for input data and SIN is used for output data 0x3 OUTCFG Output Config 26 1 read-write OUTCFG_0 Output data retains last value when chip select is negated 0 OUTCFG_1 Output data is tristated when chip select is negated 0x1 PCSCFG Peripheral Chip Select Configuration 27 1 read-write PCSCFG_0 PCS[3:2] are enabled 0 PCSCFG_1 PCS[3:2] are disabled 0x1 DMR0 Data Match Register 0 0x30 32 read-write 0 0xFFFFFFFF MATCH0 Match 0 Value 0 32 read-write DMR1 Data Match Register 1 0x34 32 read-write 0 0xFFFFFFFF MATCH1 Match 1 Value 0 32 read-write CCR Clock Configuration Register 0x40 32 read-write 0 0xFFFFFFFF SCKDIV SCK Divider 0 8 read-write DBT Delay Between Transfers 8 8 read-write PCSSCK PCS-to-SCK Delay 16 8 read-write SCKPCS SCK-to-PCS Delay 24 8 read-write FCR FIFO Control Register 0x58 32 read-write 0 0xFFFFFFFF TXWATER Transmit FIFO Watermark 0 4 read-write RXWATER Receive FIFO Watermark 16 4 read-write FSR FIFO Status Register 0x5C 32 read-only 0 0xFFFFFFFF TXCOUNT Transmit FIFO Count 0 5 read-only RXCOUNT Receive FIFO Count 16 5 read-only TCR Transmit Command Register 0x60 32 read-write 0x1F 0xFFFFFFFF FRAMESZ Frame Size 0 12 read-write WIDTH Transfer Width 16 2 read-write WIDTH_0 1 bit transfer 0 WIDTH_1 2 bit transfer 0x1 WIDTH_2 4 bit transfer 0x2 TXMSK Transmit Data Mask 18 1 read-write TXMSK_0 Normal transfer 0 TXMSK_1 Mask transmit data 0x1 RXMSK Receive Data Mask 19 1 read-write RXMSK_0 Normal transfer 0 RXMSK_1 Receive data is masked 0x1 CONTC Continuing Command 20 1 read-write CONTC_0 Command word for start of new transfer 0 CONTC_1 Command word for continuing transfer 0x1 CONT Continuous Transfer 21 1 read-write CONT_0 Continuous transfer is disabled 0 CONT_1 Continuous transfer is enabled 0x1 BYSW Byte Swap 22 1 read-write BYSW_0 Byte swap is disabled 0 BYSW_1 Byte swap is enabled 0x1 LSBF LSB First 23 1 read-write LSBF_0 Data is transferred MSB first 0 LSBF_1 Data is transferred LSB first 0x1 PCS Peripheral Chip Select 24 2 read-write PCS_0 Transfer using LPSPI_PCS[0] 0 PCS_1 Transfer using LPSPI_PCS[1] 0x1 PCS_2 Transfer using LPSPI_PCS[2] 0x2 PCS_3 Transfer using LPSPI_PCS[3] 0x3 PRESCALE Prescaler Value 27 3 read-write PRESCALE_0 Divide by 1 0 PRESCALE_1 Divide by 2 0x1 PRESCALE_2 Divide by 4 0x2 PRESCALE_3 Divide by 8 0x3 PRESCALE_4 Divide by 16 0x4 PRESCALE_5 Divide by 32 0x5 PRESCALE_6 Divide by 64 0x6 PRESCALE_7 Divide by 128 0x7 CPHA Clock Phase 30 1 read-write CPHA_0 Data is captured on the leading edge of SCK and changed on the following edge of SCK 0 CPHA_1 Data is changed on the leading edge of SCK and captured on the following edge of SCK 0x1 CPOL Clock Polarity 31 1 read-write CPOL_0 The inactive state value of SCK is low 0 CPOL_1 The inactive state value of SCK is high 0x1 TDR Transmit Data Register 0x64 32 write-only 0 0xFFFFFFFF DATA Transmit Data 0 32 write-only RSR Receive Status Register 0x70 32 read-only 0x2 0xFFFFFFFF SOF Start Of Frame 0 1 read-only SOF_0 Subsequent data word received after LPSPI_PCS assertion 0 SOF_1 First data word received after LPSPI_PCS assertion 0x1 RXEMPTY RX FIFO Empty 1 1 read-only RXEMPTY_0 RX FIFO is not empty 0 RXEMPTY_1 RX FIFO is empty 0x1 RDR Receive Data Register 0x74 32 read-only 0 0xFFFFFFFF DATA Receive Data 0 32 read-only LPSPI2 LPSPI LPSPI 0x40198000 0 0x78 registers LPSPI2 33 LPI2C1 LPI2C LPI2C LPI2C 0x401A4000 0 0x174 registers LPI2C1 28 VERID Version ID Register 0 32 read-only 0x1000003 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only FEATURE_2 Master only, with standard feature set 0x2 FEATURE_3 Master and slave, with standard feature set 0x3 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x202 0xFFFFFFFF MTXFIFO Master Transmit FIFO Size 0 4 read-only MRXFIFO Master Receive FIFO Size 8 4 read-only MCR Master Control Register 0x10 32 read-write 0 0xFFFFFFFF MEN Master Enable 0 1 read-write MEN_0 Master logic is disabled 0 MEN_1 Master logic is enabled 0x1 RST Software Reset 1 1 read-write RST_0 Master logic is not reset 0 RST_1 Master logic is reset 0x1 DOZEN Doze mode enable 2 1 read-write DOZEN_0 Master is enabled in Doze mode 0 DOZEN_1 Master is disabled in Doze mode 0x1 DBGEN Debug Enable 3 1 read-write DBGEN_0 Master is disabled in debug mode 0 DBGEN_1 Master is enabled in debug mode 0x1 RTF Reset Transmit FIFO 8 1 read-write RTF_0 No effect 0 RTF_1 Transmit FIFO is reset 0x1 RRF Reset Receive FIFO 9 1 read-write RRF_0 No effect 0 RRF_1 Receive FIFO is reset 0x1 MSR Master Status Register 0x14 32 read-write 0x1 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data is not requested 0 TDF_1 Transmit data is requested 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive Data is not ready 0 RDF_1 Receive data is ready 0x1 EPF End Packet Flag 8 1 read-write oneToClear EPF_0 Master has not generated a STOP or Repeated START condition 0 EPF_1 Master has generated a STOP or Repeated START condition 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear SDF_0 Master has not generated a STOP condition 0 SDF_1 Master has generated a STOP condition 0x1 NDF NACK Detect Flag 10 1 read-write oneToClear NDF_0 Unexpected NACK was not detected 0 NDF_1 Unexpected NACK was detected 0x1 ALF Arbitration Lost Flag 11 1 read-write oneToClear ALF_0 Master has not lost arbitration 0 ALF_1 Master has lost arbitration 0x1 FEF FIFO Error Flag 12 1 read-write oneToClear FEF_0 No error 0 FEF_1 Master sending or receiving data without a START condition 0x1 PLTF Pin Low Timeout Flag 13 1 read-write oneToClear PLTF_0 Pin low timeout has not occurred or is disabled 0 PLTF_1 Pin low timeout has occurred 0x1 DMF Data Match Flag 14 1 read-write oneToClear DMF_0 Have not received matching data 0 DMF_1 Have received matching data 0x1 MBF Master Busy Flag 24 1 read-only MBF_0 I2C Master is idle 0 MBF_1 I2C Master is busy 0x1 BBF Bus Busy Flag 25 1 read-only BBF_0 I2C Bus is idle 0 BBF_1 I2C Bus is busy 0x1 MIER Master Interrupt Enable Register 0x18 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 EPIE End Packet Interrupt Enable 8 1 read-write EPIE_0 Disabled 0 EPIE_1 Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write SDIE_0 Disabled 0 SDIE_1 Enabled 0x1 NDIE NACK Detect Interrupt Enable 10 1 read-write NDIE_0 Disabled 0 NDIE_1 Enabled 0x1 ALIE Arbitration Lost Interrupt Enable 11 1 read-write ALIE_0 Disabled 0 ALIE_1 Enabled 0x1 FEIE FIFO Error Interrupt Enable 12 1 read-write FEIE_0 Enabled 0 FEIE_1 Disabled 0x1 PLTIE Pin Low Timeout Interrupt Enable 13 1 read-write PLTIE_0 Disabled 0 PLTIE_1 Enabled 0x1 DMIE Data Match Interrupt Enable 14 1 read-write DMIE_0 Disabled 0 DMIE_1 Enabled 0x1 MDER Master DMA Enable Register 0x1C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 MCFGR0 Master Configuration Register 0 0x20 32 read-write 0 0xFFFFFFFF HREN Host Request Enable 0 1 read-write HREN_0 Host request input is disabled 0 HREN_1 Host request input is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write HRPOL_0 Active low 0 HRPOL_1 Active high 0x1 HRSEL Host Request Select 2 1 read-write HRSEL_0 Host request input is pin HREQ 0 HRSEL_1 Host request input is input trigger 0x1 CIRFIFO Circular FIFO Enable 8 1 read-write CIRFIFO_0 Circular FIFO is disabled 0 CIRFIFO_1 Circular FIFO is enabled 0x1 RDMO Receive Data Match Only 9 1 read-write RDMO_0 Received data is stored in the receive FIFO 0 RDMO_1 Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set 0x1 MCFGR1 Master Configuration Register 1 0x24 32 read-write 0 0xFFFFFFFF PRESCALE Prescaler 0 3 read-write PRESCALE_0 Divide by 1 0 PRESCALE_1 Divide by 2 0x1 PRESCALE_2 Divide by 4 0x2 PRESCALE_3 Divide by 8 0x3 PRESCALE_4 Divide by 16 0x4 PRESCALE_5 Divide by 32 0x5 PRESCALE_6 Divide by 64 0x6 PRESCALE_7 Divide by 128 0x7 AUTOSTOP Automatic STOP Generation 8 1 read-write AUTOSTOP_0 No effect 0 AUTOSTOP_1 STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy 0x1 IGNACK IGNACK 9 1 read-write IGNACK_0 LPI2C Master will receive ACK and NACK normally 0 IGNACK_1 LPI2C Master will treat a received NACK as if it (NACK) was an ACK 0x1 TIMECFG Timeout Configuration 10 1 read-write TIMECFG_0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout 0 TIMECFG_1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout 0x1 MATCFG Match Configuration 16 3 read-write MATCFG_0 Match is disabled 0 MATCFG_2 Match is enabled (1st data word equals MATCH0 OR MATCH1) 0x2 MATCFG_3 Match is enabled (any data word equals MATCH0 OR MATCH1) 0x3 MATCFG_4 Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) 0x4 MATCFG_5 Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) 0x5 MATCFG_6 Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) 0x6 MATCFG_7 Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) 0x7 PINCFG Pin Configuration 24 3 read-write PINCFG_0 2-pin open drain mode 0 PINCFG_1 2-pin output only mode (ultra-fast mode) 0x1 PINCFG_2 2-pin push-pull mode 0x2 PINCFG_3 4-pin push-pull mode 0x3 PINCFG_4 2-pin open drain mode with separate LPI2C slave 0x4 PINCFG_5 2-pin output only mode (ultra-fast mode) with separate LPI2C slave 0x5 PINCFG_6 2-pin push-pull mode with separate LPI2C slave 0x6 PINCFG_7 4-pin push-pull mode (inverted outputs) 0x7 MCFGR2 Master Configuration Register 2 0x28 32 read-write 0 0xFFFFFFFF BUSIDLE Bus Idle Timeout 0 12 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write MCFGR3 Master Configuration Register 3 0x2C 32 read-write 0 0xFFFFFFFF PINLOW Pin Low Timeout 8 12 read-write MDMR Master Data Match Register 0x40 32 read-write 0 0xFFFFFFFF MATCH0 Match 0 Value 0 8 read-write MATCH1 Match 1 Value 16 8 read-write MCCR0 Master Clock Configuration Register 0 0x48 32 read-write 0 0xFFFFFFFF CLKLO Clock Low Period 0 6 read-write CLKHI Clock High Period 8 6 read-write SETHOLD Setup Hold Delay 16 6 read-write DATAVD Data Valid Delay 24 6 read-write MCCR1 Master Clock Configuration Register 1 0x50 32 read-write 0 0xFFFFFFFF CLKLO Clock Low Period 0 6 read-write CLKHI Clock High Period 8 6 read-write SETHOLD Setup Hold Delay 16 6 read-write DATAVD Data Valid Delay 24 6 read-write MFCR Master FIFO Control Register 0x58 32 read-write 0 0xFFFFFFFF TXWATER Transmit FIFO Watermark 0 2 read-write RXWATER Receive FIFO Watermark 16 2 read-write MFSR Master FIFO Status Register 0x5C 32 read-only 0 0xFFFFFFFF TXCOUNT Transmit FIFO Count 0 3 read-only RXCOUNT Receive FIFO Count 16 3 read-only MTDR Master Transmit Data Register 0x60 32 read-write 0 0xFFFFFFFF DATA Transmit Data 0 8 write-only CMD Command Data 8 3 write-only CMD_0 Transmit DATA[7:0] 0 CMD_1 Receive (DATA[7:0] + 1) bytes 0x1 CMD_2 Generate STOP condition 0x2 CMD_3 Receive and discard (DATA[7:0] + 1) bytes 0x3 CMD_4 Generate (repeated) START and transmit address in DATA[7:0] 0x4 CMD_5 Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. 0x5 CMD_6 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode 0x6 CMD_7 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. 0x7 MRDR Master Receive Data Register 0x70 32 read-only 0x4000 0xFFFFFFFF DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only RXEMPTY_0 Receive FIFO is not empty 0 RXEMPTY_1 Receive FIFO is empty 0x1 SCR Slave Control Register 0x110 32 read-write 0 0xFFFFFFFF SEN Slave Enable 0 1 read-write SEN_0 I2C Slave mode is disabled 0 SEN_1 I2C Slave mode is enabled 0x1 RST Software Reset 1 1 read-write RST_0 Slave mode logic is not reset 0 RST_1 Slave mode logic is reset 0x1 FILTEN Filter Enable 4 1 read-write FILTEN_0 Disable digital filter and output delay counter for slave mode 0 FILTEN_1 Enable digital filter and output delay counter for slave mode 0x1 FILTDZ Filter Doze Enable 5 1 read-write FILTDZ_0 Filter remains enabled in Doze mode 0 FILTDZ_1 Filter is disabled in Doze mode 0x1 RTF Reset Transmit FIFO 8 1 read-write RTF_0 No effect 0 RTF_1 Transmit Data Register is now empty 0x1 RRF Reset Receive FIFO 9 1 read-write RRF_0 No effect 0 RRF_1 Receive Data Register is now empty 0x1 SSR Slave Status Register 0x114 32 read-write 0 0xFFFFFFFF TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data not requested 0 TDF_1 Transmit data is requested 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive data is not ready 0 RDF_1 Receive data is ready 0x1 AVF Address Valid Flag 2 1 read-only AVF_0 Address Status Register is not valid 0 AVF_1 Address Status Register is valid 0x1 TAF Transmit ACK Flag 3 1 read-only TAF_0 Transmit ACK/NACK is not required 0 TAF_1 Transmit ACK/NACK is required 0x1 RSF Repeated Start Flag 8 1 read-write oneToClear RSF_0 Slave has not detected a Repeated START condition 0 RSF_1 Slave has detected a Repeated START condition 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear SDF_0 Slave has not detected a STOP condition 0 SDF_1 Slave has detected a STOP condition 0x1 BEF Bit Error Flag 10 1 read-write oneToClear BEF_0 Slave has not detected a bit error 0 BEF_1 Slave has detected a bit error 0x1 FEF FIFO Error Flag 11 1 read-write oneToClear FEF_0 FIFO underflow or overflow was not detected 0 FEF_1 FIFO underflow or overflow was detected 0x1 AM0F Address Match 0 Flag 12 1 read-only AM0F_0 Have not received an ADDR0 matching address 0 AM0F_1 Have received an ADDR0 matching address 0x1 AM1F Address Match 1 Flag 13 1 read-only AM1F_0 Have not received an ADDR1 or ADDR0/ADDR1 range matching address 0 AM1F_1 Have received an ADDR1 or ADDR0/ADDR1 range matching address 0x1 GCF General Call Flag 14 1 read-only GCF_0 Slave has not detected the General Call Address or the General Call Address is disabled 0 GCF_1 Slave has detected the General Call Address 0x1 SARF SMBus Alert Response Flag 15 1 read-only SARF_0 SMBus Alert Response is disabled or not detected 0 SARF_1 SMBus Alert Response is enabled and detected 0x1 SBF Slave Busy Flag 24 1 read-only SBF_0 I2C Slave is idle 0 SBF_1 I2C Slave is busy 0x1 BBF Bus Busy Flag 25 1 read-only BBF_0 I2C Bus is idle 0 BBF_1 I2C Bus is busy 0x1 SIER Slave Interrupt Enable Register 0x118 32 read-write 0 0xFFFFFFFF TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 AVIE Address Valid Interrupt Enable 2 1 read-write AVIE_0 Disabled 0 AVIE_1 Enabled 0x1 TAIE Transmit ACK Interrupt Enable 3 1 read-write TAIE_0 Disabled 0 TAIE_1 Enabled 0x1 RSIE Repeated Start Interrupt Enable 8 1 read-write RSIE_0 Disabled 0 RSIE_1 Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write SDIE_0 Disabled 0 SDIE_1 Enabled 0x1 BEIE Bit Error Interrupt Enable 10 1 read-write BEIE_0 Disabled 0 BEIE_1 Enabled 0x1 FEIE FIFO Error Interrupt Enable 11 1 read-write FEIE_0 Disabled 0 FEIE_1 Enabled 0x1 AM0IE Address Match 0 Interrupt Enable 12 1 read-write AM0IE_0 Enabled 0 AM0IE_1 Disabled 0x1 AM1F Address Match 1 Interrupt Enable 13 1 read-write AM1F_0 Disabled 0 AM1F_1 Enabled 0x1 GCIE General Call Interrupt Enable 14 1 read-write GCIE_0 Disabled 0 GCIE_1 Enabled 0x1 SARIE SMBus Alert Response Interrupt Enable 15 1 read-write SARIE_0 Disabled 0 SARIE_1 Enabled 0x1 SDER Slave DMA Enable Register 0x11C 32 read-write 0 0xFFFFFFFF TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 AVDE Address Valid DMA Enable 2 1 read-write AVDE_0 DMA request is disabled 0 AVDE_1 DMA request is enabled 0x1 SCFGR1 Slave Configuration Register 1 0x124 32 read-write 0 0xFFFFFFFF ADRSTALL Address SCL Stall 0 1 read-write ADRSTALL_0 Clock stretching is disabled 0 ADRSTALL_1 Clock stretching is enabled 0x1 RXSTALL RX SCL Stall 1 1 read-write RXSTALL_0 Clock stretching is disabled 0 RXSTALL_1 Clock stretching is enabled 0x1 TXDSTALL TX Data SCL Stall 2 1 read-write TXDSTALL_0 Clock stretching is disabled 0 TXDSTALL_1 Clock stretching is enabled 0x1 ACKSTALL ACK SCL Stall 3 1 read-write ACKSTALL_0 Clock stretching is disabled 0 ACKSTALL_1 Clock stretching is enabled 0x1 GCEN General Call Enable 8 1 read-write GCEN_0 General Call address is disabled 0 GCEN_1 General Call address is enabled 0x1 SAEN SMBus Alert Enable 9 1 read-write SAEN_0 Disables match on SMBus Alert 0 SAEN_1 Enables match on SMBus Alert 0x1 TXCFG Transmit Flag Configuration 10 1 read-write TXCFG_0 Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty 0 TXCFG_1 Transmit Data Flag will assert whenever the Transmit Data register is empty 0x1 RXCFG Receive Data Configuration 11 1 read-write RXCFG_0 Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). 0 RXCFG_1 Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). 0x1 IGNACK Ignore NACK 12 1 read-write IGNACK_0 Slave will end transfer when NACK is detected 0 IGNACK_1 Slave will not end transfer when NACK detected 0x1 HSMEN High Speed Mode Enable 13 1 read-write HSMEN_0 Disables detection of HS-mode master code 0 HSMEN_1 Enables detection of HS-mode master code 0x1 ADDRCFG Address Configuration 16 3 read-write ADDRCFG_0 Address match 0 (7-bit) 0 ADDRCFG_1 Address match 0 (10-bit) 0x1 ADDRCFG_2 Address match 0 (7-bit) or Address match 1 (7-bit) 0x2 ADDRCFG_3 Address match 0 (10-bit) or Address match 1 (10-bit) 0x3 ADDRCFG_4 Address match 0 (7-bit) or Address match 1 (10-bit) 0x4 ADDRCFG_5 Address match 0 (10-bit) or Address match 1 (7-bit) 0x5 ADDRCFG_6 From Address match 0 (7-bit) to Address match 1 (7-bit) 0x6 ADDRCFG_7 From Address match 0 (10-bit) to Address match 1 (10-bit) 0x7 SCFGR2 Slave Configuration Register 2 0x128 32 read-write 0 0xFFFFFFFF CLKHOLD Clock Hold Time 0 4 read-write DATAVD Data Valid Delay 8 6 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write SAMR Slave Address Match Register 0x140 32 read-write 0 0xFFFFFFFF ADDR0 Address 0 Value 1 10 read-write ADDR1 Address 1 Value 17 10 read-write SASR Slave Address Status Register 0x150 32 read-only 0x4000 0xFFFFFFFF RADDR Received Address 0 11 read-only ANV Address Not Valid 14 1 read-only ANV_0 Received Address (RADDR) is valid 0 ANV_1 Received Address (RADDR) is not valid 0x1 STAR Slave Transmit ACK Register 0x154 32 read-write 0 0xFFFFFFFF TXNACK Transmit NACK 0 1 read-write TXNACK_0 Write a Transmit ACK for each received word 0 TXNACK_1 Write a Transmit NACK for each received word 0x1 STDR Slave Transmit Data Register 0x160 32 read-write 0 0xFFFFFFFF DATA Transmit Data 0 8 write-only SRDR Slave Receive Data Register 0x170 32 read-only 0x4000 0xFFFFFFFF DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only RXEMPTY_0 The Receive Data Register is not empty 0 RXEMPTY_1 The Receive Data Register is empty 0x1 SOF Start Of Frame 15 1 read-only SOF_0 Indicates this is not the first data word since a (repeated) START or STOP condition 0 SOF_1 Indicates this is the first data word since a (repeated) START or STOP condition 0x1 LPI2C2 LPI2C LPI2C 0x401A8000 0 0x174 registers LPI2C2 29 FLEXIO1 FLEXIO FLEXIO 0x401AC000 0 0x7A0 registers FLEXIO1 68 VERID Version ID Register 0 32 read-only 0x1010001 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only FEATURE_0 Standard features implemented. 0 FEATURE_1 Supports state, logic and parallel modes. 0x1 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x2200808 0xFFFFFFFF SHIFTER Shifter Number 0 8 read-only TIMER Timer Number 8 8 read-only PIN Pin Number 16 8 read-only TRIGGER Trigger Number 24 8 read-only CTRL FlexIO Control Register 0x8 32 read-write 0 0xFFFFFFFF FLEXEN FlexIO Enable 0 1 read-write FLEXEN_0 FlexIO module is disabled. 0 FLEXEN_1 FlexIO module is enabled. 0x1 SWRST Software Reset 1 1 read-write SWRST_0 Software reset is disabled 0 SWRST_1 Software reset is enabled, all FlexIO registers except the Control Register are reset. 0x1 FASTACC Fast Access 2 1 read-write FASTACC_0 Configures for normal register accesses to FlexIO 0 FASTACC_1 Configures for fast register accesses to FlexIO 0x1 DBGE Debug Enable 30 1 read-write DBGE_0 FlexIO is disabled in debug modes. 0 DBGE_1 FlexIO is enabled in debug modes 0x1 DOZEN Doze Enable 31 1 read-write DOZEN_0 FlexIO enabled in Doze modes. 0 DOZEN_1 FlexIO disabled in Doze modes. 0x1 PIN Pin State Register 0xC 32 read-only 0 0xFFFFFFFF PDI Pin Data Input 0 32 read-only SHIFTSTAT Shifter Status Register 0x10 32 read-write 0 0xFFFFFFFF SSF Shifter Status Flag 0 8 read-write oneToClear SHIFTERR Shifter Error Register 0x14 32 read-write 0 0xFFFFFFFF SEF Shifter Error Flags 0 8 read-write oneToClear TIMSTAT Timer Status Register 0x18 32 read-write 0 0xFFFFFFFF TSF Timer Status Flags 0 8 read-write oneToClear SHIFTSIEN Shifter Status Interrupt Enable 0x20 32 read-write 0 0xFFFFFFFF SSIE Shifter Status Interrupt Enable 0 8 read-write SHIFTEIEN Shifter Error Interrupt Enable 0x24 32 read-write 0 0xFFFFFFFF SEIE Shifter Error Interrupt Enable 0 8 read-write TIMIEN Timer Interrupt Enable Register 0x28 32 read-write 0 0xFFFFFFFF TEIE Timer Status Interrupt Enable 0 8 read-write SHIFTSDEN Shifter Status DMA Enable 0x30 32 read-write 0 0xFFFFFFFF SSDE Shifter Status DMA Enable 0 8 read-write SHIFTSTATE Shifter State Register 0x40 32 read-write 0 0xFFFFFFFF STATE Current State Pointer 0 3 read-write 8 0x4 SHIFTCTL[%s] Shifter Control N Register 0x80 32 read-write 0 0xFFFFFFFF SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 State mode. SHIFTBUF contents are used for storing programmable state attributes. 0x6 SMOD_7 Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. 0x7 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write 8 0x4 SHIFTCFG[%s] Shifter Configuration N Register 0x100 32 read-write 0 0xFFFFFFFF SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write 8 0x4 SHIFTBUF[%s] Shifter Buffer N Register 0x200 32 read-write 0 0xFFFFFFFF SHIFTBUF Shift Buffer 0 32 read-write 8 0x4 SHIFTBUFBIS[%s] Shifter Buffer N Bit Swapped Register 0x280 32 read-write 0 0xFFFFFFFF SHIFTBUFBIS Shift Buffer 0 32 read-write 8 0x4 SHIFTBUFBYS[%s] Shifter Buffer N Byte Swapped Register 0x300 32 read-write 0 0xFFFFFFFF SHIFTBUFBYS Shift Buffer 0 32 read-write 8 0x4 SHIFTBUFBBS[%s] Shifter Buffer N Bit Byte Swapped Register 0x380 32 read-write 0 0xFFFFFFFF SHIFTBUFBBS Shift Buffer 0 32 read-write 8 0x4 TIMCTL[%s] Timer Control N Register 0x400 32 read-write 0 0xFFFFFFFF TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write 8 0x4 TIMCFG[%s] Timer Configuration N Register 0x480 32 read-write 0 0xFFFFFFFF TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 8 0x4 TIMCMP[%s] Timer Compare N Register 0x500 32 read-write 0 0xFFFFFFFF CMP Timer Compare Value 0 16 read-write 8 0x4 SHIFTBUFNBS[%s] Shifter Buffer N Nibble Byte Swapped Register 0x680 32 read-write 0 0xFFFFFFFF SHIFTBUFNBS Shift Buffer 0 32 read-write 8 0x4 SHIFTBUFHWS[%s] Shifter Buffer N Half Word Swapped Register 0x700 32 read-write 0 0xFFFFFFFF SHIFTBUFHWS Shift Buffer 0 32 read-write 8 0x4 SHIFTBUFNIS[%s] Shifter Buffer N Nibble Swapped Register 0x780 32 read-write 0 0xFFFFFFFF SHIFTBUFNIS Shift Buffer 0 32 read-write GPIO1 GPIO GPIO GPIO 0x401B8000 0 0x90 registers GPIO1_Combined_0_15 70 GPIO1_Combined_16_31 71 DR GPIO data register 0 32 read-write 0 0xFFFFFFFF DR DR 0 32 read-write GDIR GPIO direction register 0x4 32 read-write 0 0xFFFFFFFF GDIR GDIR 0 32 read-write PSR GPIO pad status register 0x8 32 read-only 0 0xFFFFFFFF PSR PSR 0 32 read-only ICR1 GPIO interrupt configuration register1 0xC 32 read-write 0 0xFFFFFFFF ICR0 ICR0 0 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR1 ICR1 2 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR2 ICR2 4 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR3 ICR3 6 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR4 ICR4 8 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR5 ICR5 10 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR6 ICR6 12 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR7 ICR7 14 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR8 ICR8 16 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR9 ICR9 18 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR10 ICR10 20 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR11 ICR11 22 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR12 ICR12 24 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR13 ICR13 26 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR14 ICR14 28 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR15 ICR15 30 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR2 GPIO interrupt configuration register2 0x10 32 read-write 0 0xFFFFFFFF ICR16 ICR16 0 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR17 ICR17 2 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR18 ICR18 4 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR19 ICR19 6 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR20 ICR20 8 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR21 ICR21 10 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR22 ICR22 12 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR23 ICR23 14 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR24 ICR24 16 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR25 ICR25 18 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR26 ICR26 20 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR27 ICR27 22 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR28 ICR28 24 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR29 ICR29 26 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR30 ICR30 28 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 ICR31 ICR31 30 2 read-write LOW_LEVEL Interrupt n is low-level sensitive. 0 HIGH_LEVEL Interrupt n is high-level sensitive. 0x1 RISING_EDGE Interrupt n is rising-edge sensitive. 0x2 FALLING_EDGE Interrupt n is falling-edge sensitive. 0x3 IMR GPIO interrupt mask register 0x14 32 read-write 0 0xFFFFFFFF IMR IMR 0 32 read-write ISR GPIO interrupt status register 0x18 32 read-write 0 0xFFFFFFFF ISR ISR 0 32 read-write oneToClear EDGE_SEL GPIO edge select register 0x1C 32 read-write 0 0xFFFFFFFF GPIO_EDGE_SEL GPIO_EDGE_SEL 0 32 read-write DR_SET GPIO data register SET 0x84 32 write-only 0 0xFFFFFFFF DR_SET DR_SET 0 32 write-only DR_CLEAR GPIO data register CLEAR 0x88 32 write-only 0 0xFFFFFFFF DR_CLEAR DR_CLEAR 0 32 write-only DR_TOGGLE GPIO data register TOGGLE 0x8C 32 write-only 0 0xFFFFFFFF DR_TOGGLE DR_TOGGLE 0 32 write-only GPIO5 GPIO GPIO 0x400C0000 0 0x90 registers GPIO5_Combined_0_15 73 GPIO2 GPIO GPIO 0x42000000 0 0x90 registers GPIO2_Combined_0_15 72 PWM1 PWM PWM 0x401CC000 0 0x196 registers PWM1_0 34 PWM1_1 35 PWM1_2 36 PWM1_3 37 PWM1_FAULT 38 SM0CNT Counter Register 0 16 read-only 0 0xFFFF CNT Counter Register Bits 0 16 read-only SM0INIT Initial Count Register 0x2 16 read-write 0 0xFFFF INIT Initial Count Register Bits 0 16 read-write SM0CTRL2 Control 2 Register 0x4 16 read-write 0 0xFFFF CLK_SEL Clock Source Select 0 2 read-write CLK_SEL_0 The IPBus clock is used as the clock for the local prescaler and counter. 0 CLK_SEL_1 EXT_CLK is used as the clock for the local prescaler and counter. 0x1 CLK_SEL_2 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. 0x2 RELOAD_SEL Reload Source Select 2 1 read-write RELOAD_SEL_0 The local RELOAD signal is used to reload registers. 0 RELOAD_SEL_1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. 0x1 FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write FORCE_SEL_0 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. 0 FORCE_SEL_1 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. 0x1 FORCE_SEL_2 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. 0x2 FORCE_SEL_3 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0x3 FORCE_SEL_4 The local sync signal from this submodule is used to force updates. 0x4 FORCE_SEL_5 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0x5 FORCE_SEL_6 The external force signal, EXT_FORCE, from outside the PWM module causes updates. 0x6 FORCE_SEL_7 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. 0x7 FORCE Force Initialization 6 1 read-write FRCEN FRCEN 7 1 read-write FRCEN_0 Initialization from a FORCE_OUT is disabled. 0 FRCEN_1 Initialization from a FORCE_OUT is enabled. 0x1 INIT_SEL Initialization Control Select 8 2 read-write INIT_SEL_0 Local sync (PWM_X) causes initialization. 0 INIT_SEL_1 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. 0x1 INIT_SEL_2 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. 0x2 INIT_SEL_3 EXT_SYNC causes initialization. 0x3 PWMX_INIT PWM_X Initial Value 10 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWM23_INIT PWM23 Initial Value 12 1 read-write INDEP Independent or Complementary Pair Operation 13 1 read-write INDEP_0 PWM_A and PWM_B form a complementary PWM pair. 0 INDEP_1 PWM_A and PWM_B outputs are independent PWMs. 0x1 WAITEN WAIT Enable 14 1 read-write DBGEN Debug Enable 15 1 read-write SM0CTRL Control Register 0x6 16 read-write 0x400 0xFFFF DBLEN Double Switching Enable 0 1 read-write DBLEN_0 Double switching disabled. 0 DBLEN_1 Double switching enabled. 0x1 DBLX PWMX Double Switching Enable 1 1 read-write DBLX_0 PWMX double pulse disabled. 0 DBLX_1 PWMX double pulse enabled. 0x1 LDMOD Load Mode Select 2 1 read-write LDMOD_0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 0 LDMOD_1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. 0x1 SPLIT Split the DBLPWM signal to PWMA and PWMB 3 1 read-write SPLIT_0 DBLPWM is not split. PWMA and PWMB each have double pulses. 0 SPLIT_1 DBLPWM is split to PWMA and PWMB. 0x1 PRSC Prescaler 4 3 read-write PRSC_0 PWM clock frequency = fclk 0 PRSC_1 PWM clock frequency = fclk/2 0x1 PRSC_2 PWM clock frequency = fclk/4 0x2 PRSC_3 PWM clock frequency = fclk/8 0x3 PRSC_4 PWM clock frequency = fclk/16 0x4 PRSC_5 PWM clock frequency = fclk/32 0x5 PRSC_6 PWM clock frequency = fclk/64 0x6 PRSC_7 PWM clock frequency = fclk/128 0x7 COMPMODE Compare Mode 7 1 read-write COMPMODE_0 The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 0 COMPMODE_1 The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. 0x1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write FULL_0 Full-cycle reloads disabled. 0 FULL_1 Full-cycle reloads enabled. 0x1 HALF Half Cycle Reload 11 1 read-write HALF_0 Half-cycle reloads disabled. 0 HALF_1 Half-cycle reloads enabled. 0x1 LDFQ Load Frequency 12 4 read-write LDFQ_0 Every PWM opportunity 0 LDFQ_1 Every 2 PWM opportunities 0x1 LDFQ_2 Every 3 PWM opportunities 0x2 LDFQ_3 Every 4 PWM opportunities 0x3 LDFQ_4 Every 5 PWM opportunities 0x4 LDFQ_5 Every 6 PWM opportunities 0x5 LDFQ_6 Every 7 PWM opportunities 0x6 LDFQ_7 Every 8 PWM opportunities 0x7 LDFQ_8 Every 9 PWM opportunities 0x8 LDFQ_9 Every 10 PWM opportunities 0x9 LDFQ_10 Every 11 PWM opportunities 0xA LDFQ_11 Every 12 PWM opportunities 0xB LDFQ_12 Every 13 PWM opportunities 0xC LDFQ_13 Every 14 PWM opportunities 0xD LDFQ_14 Every 15 PWM opportunities 0xE LDFQ_15 Every 16 PWM opportunities 0xF SM0VAL0 Value Register 0 0xA 16 read-write 0 0xFFFF VAL0 Value Register 0 0 16 read-write SM0FRACVAL1 Fractional Value Register 1 0xC 16 read-write 0 0xFFFF FRACVAL1 Fractional Value 1 Register 11 5 read-write SM0VAL1 Value Register 1 0xE 16 read-write 0 0xFFFF VAL1 Value Register 1 0 16 read-write SM0FRACVAL2 Fractional Value Register 2 0x10 16 read-write 0 0xFFFF FRACVAL2 Fractional Value 2 11 5 read-write SM0VAL2 Value Register 2 0x12 16 read-write 0 0xFFFF VAL2 Value Register 2 0 16 read-write SM0FRACVAL3 Fractional Value Register 3 0x14 16 read-write 0 0xFFFF FRACVAL3 Fractional Value 3 11 5 read-write SM0VAL3 Value Register 3 0x16 16 read-write 0 0xFFFF VAL3 Value Register 3 0 16 read-write SM0FRACVAL4 Fractional Value Register 4 0x18 16 read-write 0 0xFFFF FRACVAL4 Fractional Value 4 11 5 read-write SM0VAL4 Value Register 4 0x1A 16 read-write 0 0xFFFF VAL4 Value Register 4 0 16 read-write SM0FRACVAL5 Fractional Value Register 5 0x1C 16 read-write 0 0xFFFF FRACVAL5 Fractional Value 5 11 5 read-write SM0VAL5 Value Register 5 0x1E 16 read-write 0 0xFFFF VAL5 Value Register 5 0 16 read-write SM0FRCTRL Fractional Control Register 0x20 16 read-write 0 0xFFFF FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write FRAC1_EN_0 Disable fractional cycle length for the PWM period. 0 FRAC1_EN_1 Enable fractional cycle length for the PWM period. 0x1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write FRAC23_EN_0 Disable fractional cycle placement for PWM_A. 0 FRAC23_EN_1 Enable fractional cycle placement for PWM_A. 0x1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write FRAC45_EN_0 Disable fractional cycle placement for PWM_B. 0 FRAC45_EN_1 Enable fractional cycle placement for PWM_B. 0x1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write FRAC_PU_0 Turn off fractional delay logic. 0 FRAC_PU_1 Power up fractional delay logic. 0x1 TEST Test Status Bit 15 1 read-only SM0OCTRL Output Control Register 0x22 16 read-write 0 0xFFFF PWMXFS PWM_X Fault State 0 2 read-write PWMXFS_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 PWMXFS_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 PWMXFS_2 Output is tristated. 0x2 PWMXFS_3 Output is tristated. 0x3 PWMBFS PWM_B Fault State 2 2 read-write PWMBFS_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 PWMBFS_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 PWMBFS_2 Output is tristated. 0x2 PWMBFS_3 Output is tristated. 0x3 PWMAFS PWM_A Fault State 4 2 read-write PWMAFS_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 PWMAFS_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 PWMAFS_2 Output is tristated. 0x2 PWMAFS_3 Output is tristated. 0x3 POLX PWM_X Output Polarity 8 1 read-write POLX_0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. 0 POLX_1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. 0x1 POLB PWM_B Output Polarity 9 1 read-write POLB_0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. 0 POLB_1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. 0x1 POLA PWM_A Output Polarity 10 1 read-write POLA_0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. 0 POLA_1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. 0x1 PWMX_IN PWM_X Input 13 1 read-only PWMB_IN PWM_B Input 14 1 read-only PWMA_IN PWM_A Input 15 1 read-only SM0STS Status Register 0x24 16 read-write 0 0xFFFF CMPF Compare Flags 0 6 read-write oneToClear CMPF_0 No compare event has occurred for a particular VALx value. 0 CMPF_1 A compare event has occurred for a particular VALx value. 0x1 CFX0 Capture Flag X0 6 1 read-write oneToClear CFX1 Capture Flag X1 7 1 read-write oneToClear CFB0 Capture Flag B0 8 1 read-write oneToClear CFB1 Capture Flag B1 9 1 read-write oneToClear CFA0 Capture Flag A0 10 1 read-write oneToClear CFA1 Capture Flag A1 11 1 read-write oneToClear RF Reload Flag 12 1 read-write oneToClear RF_0 No new reload cycle since last STS[RF] clearing 0 RF_1 New reload cycle since last STS[RF] clearing 0x1 REF Reload Error Flag 13 1 read-write oneToClear REF_0 No reload error occurred. 0 REF_1 Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. 0x1 RUF Registers Updated Flag 14 1 read-only RUF_0 No register update has occurred since last reload. 0 RUF_1 At least one of the double buffered registers has been updated since the last reload. 0x1 SM0INTEN Interrupt Enable Register 0x26 16 read-write 0 0xFFFF CMPIE Compare Interrupt Enables 0 6 read-write CMPIE_0 The corresponding STS[CMPF] bit will not cause an interrupt request. 0 CMPIE_1 The corresponding STS[CMPF] bit will cause an interrupt request. 0x1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write CX0IE_0 Interrupt request disabled for STS[CFX0]. 0 CX0IE_1 Interrupt request enabled for STS[CFX0]. 0x1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write CX1IE_0 Interrupt request disabled for STS[CFX1]. 0 CX1IE_1 Interrupt request enabled for STS[CFX1]. 0x1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write CB0IE_0 Interrupt request disabled for STS[CFB0]. 0 CB0IE_1 Interrupt request enabled for STS[CFB0]. 0x1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write CB1IE_0 Interrupt request disabled for STS[CFB1]. 0 CB1IE_1 Interrupt request enabled for STS[CFB1]. 0x1 CA0IE Capture A 0 Interrupt Enable 10 1 read-write CA0IE_0 Interrupt request disabled for STS[CFA0]. 0 CA0IE_1 Interrupt request enabled for STS[CFA0]. 0x1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write CA1IE_0 Interrupt request disabled for STS[CFA1]. 0 CA1IE_1 Interrupt request enabled for STS[CFA1]. 0x1 RIE Reload Interrupt Enable 12 1 read-write RIE_0 STS[RF] CPU interrupt requests disabled 0 RIE_1 STS[RF] CPU interrupt requests enabled 0x1 REIE Reload Error Interrupt Enable 13 1 read-write REIE_0 STS[REF] CPU interrupt requests disabled 0 REIE_1 STS[REF] CPU interrupt requests enabled 0x1 SM0DMAEN DMA Enable Register 0x28 16 read-write 0 0xFFFF CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write CAPTDE_0 Read DMA requests disabled. 0 CAPTDE_1 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. 0x1 CAPTDE_2 A local sync (VAL1 matches counter) sets the read DMA request. 0x2 CAPTDE_3 A local reload (STS[RF] being set) sets the read DMA request. 0x3 FAND FIFO Watermark AND Control 8 1 read-write FAND_0 Selected FIFO watermarks are OR'ed together. 0 FAND_1 Selected FIFO watermarks are AND'ed together. 0x1 VALDE Value Registers DMA Enable 9 1 read-write VALDE_0 DMA write requests disabled 0 VALDE_1 DMA write requests for the VALx and FRACVALx registers enabled 0x1 SM0TCTRL Output Trigger Control Register 0x2A 16 read-write 0 0xFFFF OUT_TRIG_EN Output Trigger Enables 0 6 read-write OUT_TRIG_EN_0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. 0 OUT_TRIG_EN_1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. 0x1 TRGFRQ Trigger frequency 12 1 read-write TRGFRQ_0 Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 0 TRGFRQ_1 Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 0x1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write PWBOT1_0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. 0 PWBOT1_1 Route the PWMB output to the PWM_OUT_TRIG1 port. 0x1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write PWAOT0_0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. 0 PWAOT0_1 Route the PWMA output to the PWM_OUT_TRIG0 port. 0x1 SM0DISMAP0 Fault Disable Mapping Register 0 0x2C 16 read-write 0xFFFF 0xFFFF DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SM0DISMAP1 Fault Disable Mapping Register 1 0x2E 16 read-write 0xFFFF 0xFFFF DIS1A PWM_A Fault Disable Mask 1 0 4 read-write DIS1B PWM_B Fault Disable Mask 1 4 4 read-write DIS1X PWM_X Fault Disable Mask 1 8 4 read-write SM0DTCNT0 Deadtime Count Register 0 0x30 16 read-write 0x7FF 0xFFFF DTCNT0 DTCNT0 0 16 read-write SM0DTCNT1 Deadtime Count Register 1 0x32 16 read-write 0x7FF 0xFFFF DTCNT1 DTCNT1 0 16 read-write SM0CAPTCTRLA Capture Control A Register 0x34 16 read-write 0 0xFFFF ARMA Arm A 0 1 read-write ARMA_0 Input capture operation is disabled. 0 ARMA_1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. 0x1 ONESHOTA One Shot Mode A 1 1 read-write ONESHOTA_0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0 ONESHOTA_1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. 0x1 EDGA0 Edge A 0 2 2 read-write EDGA0_0 Disabled 0 EDGA0_1 Capture falling edges 0x1 EDGA0_2 Capture rising edges 0x2 EDGA0_3 Capture any edge 0x3 EDGA1 Edge A 1 4 2 read-write EDGA1_0 Disabled 0 EDGA1_1 Capture falling edges 0x1 EDGA1_2 Capture rising edges 0x2 EDGA1_3 Capture any edge 0x3 INP_SELA Input Select A 6 1 read-write INP_SELA_0 Raw PWM_A input signal selected as source. 0 INP_SELA_1 Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. 0x1 EDGCNTA_EN Edge Counter A Enable 7 1 read-write EDGCNTA_EN_0 Edge counter disabled and held in reset 0 EDGCNTA_EN_1 Edge counter enabled 0x1 CFAWM Capture A FIFOs Water Mark 8 2 read-write CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only SM0CAPTCOMPA Capture Compare A Register 0x36 16 read-write 0 0xFFFF EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SM0CAPTCTRLB Capture Control B Register 0x38 16 read-write 0 0xFFFF ARMB Arm B 0 1 read-write ARMB_0 Input capture operation is disabled. 0 ARMB_1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. 0x1 ONESHOTB One Shot Mode B 1 1 read-write ONESHOTB_0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0 ONESHOTB_1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. 0x1 EDGB0 Edge B 0 2 2 read-write EDGB0_0 Disabled 0 EDGB0_1 Capture falling edges 0x1 EDGB0_2 Capture rising edges 0x2 EDGB0_3 Capture any edge 0x3 EDGB1 Edge B 1 4 2 read-write EDGB1_0 Disabled 0 EDGB1_1 Capture falling edges 0x1 EDGB1_2 Capture rising edges 0x2 EDGB1_3 Capture any edge 0x3 INP_SELB Input Select B 6 1 read-write INP_SELB_0 Raw PWM_B input signal selected as source. 0 INP_SELB_1 Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. 0x1 EDGCNTB_EN Edge Counter B Enable 7 1 read-write EDGCNTB_EN_0 Edge counter disabled and held in reset 0 EDGCNTB_EN_1 Edge counter enabled 0x1 CFBWM Capture B FIFOs Water Mark 8 2 read-write CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only SM0CAPTCOMPB Capture Compare B Register 0x3A 16 read-write 0 0xFFFF EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SM0CAPTCTRLX Capture Control X Register 0x3C 16 read-write 0 0xFFFF ARMX Arm X 0 1 read-write ARMX_0 Input capture operation is disabled. 0 ARMX_1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. 0x1 ONESHOTX One Shot Mode Aux 1 1 read-write ONESHOTX_0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0 ONESHOTX_1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. 0x1 EDGX0 Edge X 0 2 2 read-write EDGX0_0 Disabled 0 EDGX0_1 Capture falling edges 0x1 EDGX0_2 Capture rising edges 0x2 EDGX0_3 Capture any edge 0x3 EDGX1 Edge X 1 4 2 read-write EDGX1_0 Disabled 0 EDGX1_1 Capture falling edges 0x1 EDGX1_2 Capture rising edges 0x2 EDGX1_3 Capture any edge 0x3 INP_SELX Input Select X 6 1 read-write INP_SELX_0 Raw PWM_X input signal selected as source. 0 INP_SELX_1 Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. 0x1 EDGCNTX_EN Edge Counter X Enable 7 1 read-write EDGCNTX_EN_0 Edge counter disabled and held in reset 0 EDGCNTX_EN_1 Edge counter enabled 0x1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only SM0CAPTCOMPX Capture Compare X Register 0x3E 16 read-write 0 0xFFFF EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SM0CVAL0 Capture Value 0 Register 0x40 16 read-only 0 0xFFFF CAPTVAL0 CAPTVAL0 0 16 read-only SM0CVAL0CYC Capture Value 0 Cycle Register 0x42 16 read-only 0 0xFFFF CVAL0CYC CVAL0CYC 0 4 read-only SM0CVAL1 Capture Value 1 Register 0x44 16 read-only 0 0xFFFF CAPTVAL1 CAPTVAL1 0 16 read-only SM0CVAL1CYC Capture Value 1 Cycle Register 0x46 16 read-only 0 0xFFFF CVAL1CYC CVAL1CYC 0 4 read-only SM0CVAL2 Capture Value 2 Register 0x48 16 read-only 0 0xFFFF CAPTVAL2 CAPTVAL2 0 16 read-only SM0CVAL2CYC Capture Value 2 Cycle Register 0x4A 16 read-only 0 0xFFFF CVAL2CYC CVAL2CYC 0 4 read-only SM0CVAL3 Capture Value 3 Register 0x4C 16 read-only 0 0xFFFF CAPTVAL3 CAPTVAL3 0 16 read-only SM0CVAL3CYC Capture Value 3 Cycle Register 0x4E 16 read-only 0 0xFFFF CVAL3CYC CVAL3CYC 0 4 read-only SM0CVAL4 Capture Value 4 Register 0x50 16 read-only 0 0xFFFF CAPTVAL4 CAPTVAL4 0 16 read-only SM0CVAL4CYC Capture Value 4 Cycle Register 0x52 16 read-only 0 0xFFFF CVAL4CYC CVAL4CYC 0 4 read-only SM0CVAL5 Capture Value 5 Register 0x54 16 read-only 0 0xFFFF CAPTVAL5 CAPTVAL5 0 16 read-only SM0CVAL5CYC Capture Value 5 Cycle Register 0x56 16 read-only 0 0xFFFF CVAL5CYC CVAL5CYC 0 4 read-only SM0PHASEDLY Phase Delay Register 0x58 16 read-write 0 0xFFFF PHASEDLY Initial Count Register Bits 0 16 read-write SM1CNT Counter Register 0x60 16 read-only 0 0xFFFF CNT Counter Register Bits 0 16 read-only SM1INIT Initial Count Register 0x62 16 read-write 0 0xFFFF INIT Initial Count Register Bits 0 16 read-write SM1CTRL2 Control 2 Register 0x64 16 read-write 0 0xFFFF CLK_SEL Clock Source Select 0 2 read-write CLK_SEL_0 The IPBus clock is used as the clock for the local prescaler and counter. 0 CLK_SEL_1 EXT_CLK is used as the clock for the local prescaler and counter. 0x1 CLK_SEL_2 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. 0x2 RELOAD_SEL Reload Source Select 2 1 read-write RELOAD_SEL_0 The local RELOAD signal is used to reload registers. 0 RELOAD_SEL_1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. 0x1 FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write FORCE_SEL_0 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. 0 FORCE_SEL_1 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. 0x1 FORCE_SEL_2 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. 0x2 FORCE_SEL_3 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0x3 FORCE_SEL_4 The local sync signal from this submodule is used to force updates. 0x4 FORCE_SEL_5 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0x5 FORCE_SEL_6 The external force signal, EXT_FORCE, from outside the PWM module causes updates. 0x6 FORCE_SEL_7 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. 0x7 FORCE Force Initialization 6 1 read-write FRCEN FRCEN 7 1 read-write FRCEN_0 Initialization from a FORCE_OUT is disabled. 0 FRCEN_1 Initialization from a FORCE_OUT is enabled. 0x1 INIT_SEL Initialization Control Select 8 2 read-write INIT_SEL_0 Local sync (PWM_X) causes initialization. 0 INIT_SEL_1 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. 0x1 INIT_SEL_2 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. 0x2 INIT_SEL_3 EXT_SYNC causes initialization. 0x3 PWMX_INIT PWM_X Initial Value 10 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWM23_INIT PWM23 Initial Value 12 1 read-write INDEP Independent or Complementary Pair Operation 13 1 read-write INDEP_0 PWM_A and PWM_B form a complementary PWM pair. 0 INDEP_1 PWM_A and PWM_B outputs are independent PWMs. 0x1 WAITEN WAIT Enable 14 1 read-write DBGEN Debug Enable 15 1 read-write SM1CTRL Control Register 0x66 16 read-write 0x400 0xFFFF DBLEN Double Switching Enable 0 1 read-write DBLEN_0 Double switching disabled. 0 DBLEN_1 Double switching enabled. 0x1 DBLX PWMX Double Switching Enable 1 1 read-write DBLX_0 PWMX double pulse disabled. 0 DBLX_1 PWMX double pulse enabled. 0x1 LDMOD Load Mode Select 2 1 read-write LDMOD_0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 0 LDMOD_1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. 0x1 SPLIT Split the DBLPWM signal to PWMA and PWMB 3 1 read-write SPLIT_0 DBLPWM is not split. PWMA and PWMB each have double pulses. 0 SPLIT_1 DBLPWM is split to PWMA and PWMB. 0x1 PRSC Prescaler 4 3 read-write PRSC_0 PWM clock frequency = fclk 0 PRSC_1 PWM clock frequency = fclk/2 0x1 PRSC_2 PWM clock frequency = fclk/4 0x2 PRSC_3 PWM clock frequency = fclk/8 0x3 PRSC_4 PWM clock frequency = fclk/16 0x4 PRSC_5 PWM clock frequency = fclk/32 0x5 PRSC_6 PWM clock frequency = fclk/64 0x6 PRSC_7 PWM clock frequency = fclk/128 0x7 COMPMODE Compare Mode 7 1 read-write COMPMODE_0 The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 0 COMPMODE_1 The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. 0x1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write FULL_0 Full-cycle reloads disabled. 0 FULL_1 Full-cycle reloads enabled. 0x1 HALF Half Cycle Reload 11 1 read-write HALF_0 Half-cycle reloads disabled. 0 HALF_1 Half-cycle reloads enabled. 0x1 LDFQ Load Frequency 12 4 read-write LDFQ_0 Every PWM opportunity 0 LDFQ_1 Every 2 PWM opportunities 0x1 LDFQ_2 Every 3 PWM opportunities 0x2 LDFQ_3 Every 4 PWM opportunities 0x3 LDFQ_4 Every 5 PWM opportunities 0x4 LDFQ_5 Every 6 PWM opportunities 0x5 LDFQ_6 Every 7 PWM opportunities 0x6 LDFQ_7 Every 8 PWM opportunities 0x7 LDFQ_8 Every 9 PWM opportunities 0x8 LDFQ_9 Every 10 PWM opportunities 0x9 LDFQ_10 Every 11 PWM opportunities 0xA LDFQ_11 Every 12 PWM opportunities 0xB LDFQ_12 Every 13 PWM opportunities 0xC LDFQ_13 Every 14 PWM opportunities 0xD LDFQ_14 Every 15 PWM opportunities 0xE LDFQ_15 Every 16 PWM opportunities 0xF SM1VAL0 Value Register 0 0x6A 16 read-write 0 0xFFFF VAL0 Value Register 0 0 16 read-write SM1FRACVAL1 Fractional Value Register 1 0x6C 16 read-write 0 0xFFFF FRACVAL1 Fractional Value 1 Register 11 5 read-write SM1VAL1 Value Register 1 0x6E 16 read-write 0 0xFFFF VAL1 Value Register 1 0 16 read-write SM1FRACVAL2 Fractional Value Register 2 0x70 16 read-write 0 0xFFFF FRACVAL2 Fractional Value 2 11 5 read-write SM1VAL2 Value Register 2 0x72 16 read-write 0 0xFFFF VAL2 Value Register 2 0 16 read-write SM1FRACVAL3 Fractional Value Register 3 0x74 16 read-write 0 0xFFFF FRACVAL3 Fractional Value 3 11 5 read-write SM1VAL3 Value Register 3 0x76 16 read-write 0 0xFFFF VAL3 Value Register 3 0 16 read-write SM1FRACVAL4 Fractional Value Register 4 0x78 16 read-write 0 0xFFFF FRACVAL4 Fractional Value 4 11 5 read-write SM1VAL4 Value Register 4 0x7A 16 read-write 0 0xFFFF VAL4 Value Register 4 0 16 read-write SM1FRACVAL5 Fractional Value Register 5 0x7C 16 read-write 0 0xFFFF FRACVAL5 Fractional Value 5 11 5 read-write SM1VAL5 Value Register 5 0x7E 16 read-write 0 0xFFFF VAL5 Value Register 5 0 16 read-write SM1FRCTRL Fractional Control Register 0x80 16 read-write 0 0xFFFF FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write FRAC1_EN_0 Disable fractional cycle length for the PWM period. 0 FRAC1_EN_1 Enable fractional cycle length for the PWM period. 0x1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write FRAC23_EN_0 Disable fractional cycle placement for PWM_A. 0 FRAC23_EN_1 Enable fractional cycle placement for PWM_A. 0x1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write FRAC45_EN_0 Disable fractional cycle placement for PWM_B. 0 FRAC45_EN_1 Enable fractional cycle placement for PWM_B. 0x1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write FRAC_PU_0 Turn off fractional delay logic. 0 FRAC_PU_1 Power up fractional delay logic. 0x1 TEST Test Status Bit 15 1 read-only SM1OCTRL Output Control Register 0x82 16 read-write 0 0xFFFF PWMXFS PWM_X Fault State 0 2 read-write PWMXFS_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 PWMXFS_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 PWMXFS_2 Output is tristated. 0x2 PWMXFS_3 Output is tristated. 0x3 PWMBFS PWM_B Fault State 2 2 read-write PWMBFS_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 PWMBFS_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 PWMBFS_2 Output is tristated. 0x2 PWMBFS_3 Output is tristated. 0x3 PWMAFS PWM_A Fault State 4 2 read-write PWMAFS_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 PWMAFS_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 PWMAFS_2 Output is tristated. 0x2 PWMAFS_3 Output is tristated. 0x3 POLX PWM_X Output Polarity 8 1 read-write POLX_0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. 0 POLX_1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. 0x1 POLB PWM_B Output Polarity 9 1 read-write POLB_0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. 0 POLB_1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. 0x1 POLA PWM_A Output Polarity 10 1 read-write POLA_0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. 0 POLA_1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. 0x1 PWMX_IN PWM_X Input 13 1 read-only PWMB_IN PWM_B Input 14 1 read-only PWMA_IN PWM_A Input 15 1 read-only SM1STS Status Register 0x84 16 read-write 0 0xFFFF CMPF Compare Flags 0 6 read-write oneToClear CMPF_0 No compare event has occurred for a particular VALx value. 0 CMPF_1 A compare event has occurred for a particular VALx value. 0x1 CFX0 Capture Flag X0 6 1 read-write oneToClear CFX1 Capture Flag X1 7 1 read-write oneToClear CFB0 Capture Flag B0 8 1 read-write oneToClear CFB1 Capture Flag B1 9 1 read-write oneToClear CFA0 Capture Flag A0 10 1 read-write oneToClear CFA1 Capture Flag A1 11 1 read-write oneToClear RF Reload Flag 12 1 read-write oneToClear RF_0 No new reload cycle since last STS[RF] clearing 0 RF_1 New reload cycle since last STS[RF] clearing 0x1 REF Reload Error Flag 13 1 read-write oneToClear REF_0 No reload error occurred. 0 REF_1 Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. 0x1 RUF Registers Updated Flag 14 1 read-only RUF_0 No register update has occurred since last reload. 0 RUF_1 At least one of the double buffered registers has been updated since the last reload. 0x1 SM1INTEN Interrupt Enable Register 0x86 16 read-write 0 0xFFFF CMPIE Compare Interrupt Enables 0 6 read-write CMPIE_0 The corresponding STS[CMPF] bit will not cause an interrupt request. 0 CMPIE_1 The corresponding STS[CMPF] bit will cause an interrupt request. 0x1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write CX0IE_0 Interrupt request disabled for STS[CFX0]. 0 CX0IE_1 Interrupt request enabled for STS[CFX0]. 0x1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write CX1IE_0 Interrupt request disabled for STS[CFX1]. 0 CX1IE_1 Interrupt request enabled for STS[CFX1]. 0x1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write CB0IE_0 Interrupt request disabled for STS[CFB0]. 0 CB0IE_1 Interrupt request enabled for STS[CFB0]. 0x1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write CB1IE_0 Interrupt request disabled for STS[CFB1]. 0 CB1IE_1 Interrupt request enabled for STS[CFB1]. 0x1 CA0IE Capture A 0 Interrupt Enable 10 1 read-write CA0IE_0 Interrupt request disabled for STS[CFA0]. 0 CA0IE_1 Interrupt request enabled for STS[CFA0]. 0x1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write CA1IE_0 Interrupt request disabled for STS[CFA1]. 0 CA1IE_1 Interrupt request enabled for STS[CFA1]. 0x1 RIE Reload Interrupt Enable 12 1 read-write RIE_0 STS[RF] CPU interrupt requests disabled 0 RIE_1 STS[RF] CPU interrupt requests enabled 0x1 REIE Reload Error Interrupt Enable 13 1 read-write REIE_0 STS[REF] CPU interrupt requests disabled 0 REIE_1 STS[REF] CPU interrupt requests enabled 0x1 SM1DMAEN DMA Enable Register 0x88 16 read-write 0 0xFFFF CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write CAPTDE_0 Read DMA requests disabled. 0 CAPTDE_1 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. 0x1 CAPTDE_2 A local sync (VAL1 matches counter) sets the read DMA request. 0x2 CAPTDE_3 A local reload (STS[RF] being set) sets the read DMA request. 0x3 FAND FIFO Watermark AND Control 8 1 read-write FAND_0 Selected FIFO watermarks are OR'ed together. 0 FAND_1 Selected FIFO watermarks are AND'ed together. 0x1 VALDE Value Registers DMA Enable 9 1 read-write VALDE_0 DMA write requests disabled 0 VALDE_1 DMA write requests for the VALx and FRACVALx registers enabled 0x1 SM1TCTRL Output Trigger Control Register 0x8A 16 read-write 0 0xFFFF OUT_TRIG_EN Output Trigger Enables 0 6 read-write OUT_TRIG_EN_0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. 0 OUT_TRIG_EN_1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. 0x1 TRGFRQ Trigger frequency 12 1 read-write TRGFRQ_0 Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 0 TRGFRQ_1 Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 0x1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write PWBOT1_0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. 0 PWBOT1_1 Route the PWMB output to the PWM_OUT_TRIG1 port. 0x1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write PWAOT0_0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. 0 PWAOT0_1 Route the PWMA output to the PWM_OUT_TRIG0 port. 0x1 SM1DISMAP0 Fault Disable Mapping Register 0 0x8C 16 read-write 0xFFFF 0xFFFF DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SM1DISMAP1 Fault Disable Mapping Register 1 0x8E 16 read-write 0xFFFF 0xFFFF DIS1A PWM_A Fault Disable Mask 1 0 4 read-write DIS1B PWM_B Fault Disable Mask 1 4 4 read-write DIS1X PWM_X Fault Disable Mask 1 8 4 read-write SM1DTCNT0 Deadtime Count Register 0 0x90 16 read-write 0x7FF 0xFFFF DTCNT0 DTCNT0 0 16 read-write SM1DTCNT1 Deadtime Count Register 1 0x92 16 read-write 0x7FF 0xFFFF DTCNT1 DTCNT1 0 16 read-write SM1CAPTCTRLA Capture Control A Register 0x94 16 read-write 0 0xFFFF ARMA Arm A 0 1 read-write ARMA_0 Input capture operation is disabled. 0 ARMA_1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. 0x1 ONESHOTA One Shot Mode A 1 1 read-write ONESHOTA_0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0 ONESHOTA_1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. 0x1 EDGA0 Edge A 0 2 2 read-write EDGA0_0 Disabled 0 EDGA0_1 Capture falling edges 0x1 EDGA0_2 Capture rising edges 0x2 EDGA0_3 Capture any edge 0x3 EDGA1 Edge A 1 4 2 read-write EDGA1_0 Disabled 0 EDGA1_1 Capture falling edges 0x1 EDGA1_2 Capture rising edges 0x2 EDGA1_3 Capture any edge 0x3 INP_SELA Input Select A 6 1 read-write INP_SELA_0 Raw PWM_A input signal selected as source. 0 INP_SELA_1 Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. 0x1 EDGCNTA_EN Edge Counter A Enable 7 1 read-write EDGCNTA_EN_0 Edge counter disabled and held in reset 0 EDGCNTA_EN_1 Edge counter enabled 0x1 CFAWM Capture A FIFOs Water Mark 8 2 read-write CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only SM1CAPTCOMPA Capture Compare A Register 0x96 16 read-write 0 0xFFFF EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SM1CAPTCTRLB Capture Control B Register 0x98 16 read-write 0 0xFFFF ARMB Arm B 0 1 read-write ARMB_0 Input capture operation is disabled. 0 ARMB_1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. 0x1 ONESHOTB One Shot Mode B 1 1 read-write ONESHOTB_0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0 ONESHOTB_1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. 0x1 EDGB0 Edge B 0 2 2 read-write EDGB0_0 Disabled 0 EDGB0_1 Capture falling edges 0x1 EDGB0_2 Capture rising edges 0x2 EDGB0_3 Capture any edge 0x3 EDGB1 Edge B 1 4 2 read-write EDGB1_0 Disabled 0 EDGB1_1 Capture falling edges 0x1 EDGB1_2 Capture rising edges 0x2 EDGB1_3 Capture any edge 0x3 INP_SELB Input Select B 6 1 read-write INP_SELB_0 Raw PWM_B input signal selected as source. 0 INP_SELB_1 Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. 0x1 EDGCNTB_EN Edge Counter B Enable 7 1 read-write EDGCNTB_EN_0 Edge counter disabled and held in reset 0 EDGCNTB_EN_1 Edge counter enabled 0x1 CFBWM Capture B FIFOs Water Mark 8 2 read-write CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only SM1CAPTCOMPB Capture Compare B Register 0x9A 16 read-write 0 0xFFFF EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SM1CAPTCTRLX Capture Control X Register 0x9C 16 read-write 0 0xFFFF ARMX Arm X 0 1 read-write ARMX_0 Input capture operation is disabled. 0 ARMX_1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. 0x1 ONESHOTX One Shot Mode Aux 1 1 read-write ONESHOTX_0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0 ONESHOTX_1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. 0x1 EDGX0 Edge X 0 2 2 read-write EDGX0_0 Disabled 0 EDGX0_1 Capture falling edges 0x1 EDGX0_2 Capture rising edges 0x2 EDGX0_3 Capture any edge 0x3 EDGX1 Edge X 1 4 2 read-write EDGX1_0 Disabled 0 EDGX1_1 Capture falling edges 0x1 EDGX1_2 Capture rising edges 0x2 EDGX1_3 Capture any edge 0x3 INP_SELX Input Select X 6 1 read-write INP_SELX_0 Raw PWM_X input signal selected as source. 0 INP_SELX_1 Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. 0x1 EDGCNTX_EN Edge Counter X Enable 7 1 read-write EDGCNTX_EN_0 Edge counter disabled and held in reset 0 EDGCNTX_EN_1 Edge counter enabled 0x1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only SM1CAPTCOMPX Capture Compare X Register 0x9E 16 read-write 0 0xFFFF EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SM1CVAL0 Capture Value 0 Register 0xA0 16 read-only 0 0xFFFF CAPTVAL0 CAPTVAL0 0 16 read-only SM1CVAL0CYC Capture Value 0 Cycle Register 0xA2 16 read-only 0 0xFFFF CVAL0CYC CVAL0CYC 0 4 read-only SM1CVAL1 Capture Value 1 Register 0xA4 16 read-only 0 0xFFFF CAPTVAL1 CAPTVAL1 0 16 read-only SM1CVAL1CYC Capture Value 1 Cycle Register 0xA6 16 read-only 0 0xFFFF CVAL1CYC CVAL1CYC 0 4 read-only SM1CVAL2 Capture Value 2 Register 0xA8 16 read-only 0 0xFFFF CAPTVAL2 CAPTVAL2 0 16 read-only SM1CVAL2CYC Capture Value 2 Cycle Register 0xAA 16 read-only 0 0xFFFF CVAL2CYC CVAL2CYC 0 4 read-only SM1CVAL3 Capture Value 3 Register 0xAC 16 read-only 0 0xFFFF CAPTVAL3 CAPTVAL3 0 16 read-only SM1CVAL3CYC Capture Value 3 Cycle Register 0xAE 16 read-only 0 0xFFFF CVAL3CYC CVAL3CYC 0 4 read-only SM1CVAL4 Capture Value 4 Register 0xB0 16 read-only 0 0xFFFF CAPTVAL4 CAPTVAL4 0 16 read-only SM1CVAL4CYC Capture Value 4 Cycle Register 0xB2 16 read-only 0 0xFFFF CVAL4CYC CVAL4CYC 0 4 read-only SM1CVAL5 Capture Value 5 Register 0xB4 16 read-only 0 0xFFFF CAPTVAL5 CAPTVAL5 0 16 read-only SM1CVAL5CYC Capture Value 5 Cycle Register 0xB6 16 read-only 0 0xFFFF CVAL5CYC CVAL5CYC 0 4 read-only SM1PHASEDLY Phase Delay Register 0xB8 16 read-write 0 0xFFFF PHASEDLY Initial Count Register Bits 0 16 read-write SM2CNT Counter Register 0xC0 16 read-only 0 0xFFFF CNT Counter Register Bits 0 16 read-only SM2INIT Initial Count Register 0xC2 16 read-write 0 0xFFFF INIT Initial Count Register Bits 0 16 read-write SM2CTRL2 Control 2 Register 0xC4 16 read-write 0 0xFFFF CLK_SEL Clock Source Select 0 2 read-write CLK_SEL_0 The IPBus clock is used as the clock for the local prescaler and counter. 0 CLK_SEL_1 EXT_CLK is used as the clock for the local prescaler and counter. 0x1 CLK_SEL_2 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. 0x2 RELOAD_SEL Reload Source Select 2 1 read-write RELOAD_SEL_0 The local RELOAD signal is used to reload registers. 0 RELOAD_SEL_1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. 0x1 FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write FORCE_SEL_0 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. 0 FORCE_SEL_1 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. 0x1 FORCE_SEL_2 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. 0x2 FORCE_SEL_3 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0x3 FORCE_SEL_4 The local sync signal from this submodule is used to force updates. 0x4 FORCE_SEL_5 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0x5 FORCE_SEL_6 The external force signal, EXT_FORCE, from outside the PWM module causes updates. 0x6 FORCE_SEL_7 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. 0x7 FORCE Force Initialization 6 1 read-write FRCEN FRCEN 7 1 read-write FRCEN_0 Initialization from a FORCE_OUT is disabled. 0 FRCEN_1 Initialization from a FORCE_OUT is enabled. 0x1 INIT_SEL Initialization Control Select 8 2 read-write INIT_SEL_0 Local sync (PWM_X) causes initialization. 0 INIT_SEL_1 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. 0x1 INIT_SEL_2 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. 0x2 INIT_SEL_3 EXT_SYNC causes initialization. 0x3 PWMX_INIT PWM_X Initial Value 10 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWM23_INIT PWM23 Initial Value 12 1 read-write INDEP Independent or Complementary Pair Operation 13 1 read-write INDEP_0 PWM_A and PWM_B form a complementary PWM pair. 0 INDEP_1 PWM_A and PWM_B outputs are independent PWMs. 0x1 WAITEN WAIT Enable 14 1 read-write DBGEN Debug Enable 15 1 read-write SM2CTRL Control Register 0xC6 16 read-write 0x400 0xFFFF DBLEN Double Switching Enable 0 1 read-write DBLEN_0 Double switching disabled. 0 DBLEN_1 Double switching enabled. 0x1 DBLX PWMX Double Switching Enable 1 1 read-write DBLX_0 PWMX double pulse disabled. 0 DBLX_1 PWMX double pulse enabled. 0x1 LDMOD Load Mode Select 2 1 read-write LDMOD_0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 0 LDMOD_1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. 0x1 SPLIT Split the DBLPWM signal to PWMA and PWMB 3 1 read-write SPLIT_0 DBLPWM is not split. PWMA and PWMB each have double pulses. 0 SPLIT_1 DBLPWM is split to PWMA and PWMB. 0x1 PRSC Prescaler 4 3 read-write PRSC_0 PWM clock frequency = fclk 0 PRSC_1 PWM clock frequency = fclk/2 0x1 PRSC_2 PWM clock frequency = fclk/4 0x2 PRSC_3 PWM clock frequency = fclk/8 0x3 PRSC_4 PWM clock frequency = fclk/16 0x4 PRSC_5 PWM clock frequency = fclk/32 0x5 PRSC_6 PWM clock frequency = fclk/64 0x6 PRSC_7 PWM clock frequency = fclk/128 0x7 COMPMODE Compare Mode 7 1 read-write COMPMODE_0 The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 0 COMPMODE_1 The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. 0x1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write FULL_0 Full-cycle reloads disabled. 0 FULL_1 Full-cycle reloads enabled. 0x1 HALF Half Cycle Reload 11 1 read-write HALF_0 Half-cycle reloads disabled. 0 HALF_1 Half-cycle reloads enabled. 0x1 LDFQ Load Frequency 12 4 read-write LDFQ_0 Every PWM opportunity 0 LDFQ_1 Every 2 PWM opportunities 0x1 LDFQ_2 Every 3 PWM opportunities 0x2 LDFQ_3 Every 4 PWM opportunities 0x3 LDFQ_4 Every 5 PWM opportunities 0x4 LDFQ_5 Every 6 PWM opportunities 0x5 LDFQ_6 Every 7 PWM opportunities 0x6 LDFQ_7 Every 8 PWM opportunities 0x7 LDFQ_8 Every 9 PWM opportunities 0x8 LDFQ_9 Every 10 PWM opportunities 0x9 LDFQ_10 Every 11 PWM opportunities 0xA LDFQ_11 Every 12 PWM opportunities 0xB LDFQ_12 Every 13 PWM opportunities 0xC LDFQ_13 Every 14 PWM opportunities 0xD LDFQ_14 Every 15 PWM opportunities 0xE LDFQ_15 Every 16 PWM opportunities 0xF SM2VAL0 Value Register 0 0xCA 16 read-write 0 0xFFFF VAL0 Value Register 0 0 16 read-write SM2FRACVAL1 Fractional Value Register 1 0xCC 16 read-write 0 0xFFFF FRACVAL1 Fractional Value 1 Register 11 5 read-write SM2VAL1 Value Register 1 0xCE 16 read-write 0 0xFFFF VAL1 Value Register 1 0 16 read-write SM2FRACVAL2 Fractional Value Register 2 0xD0 16 read-write 0 0xFFFF FRACVAL2 Fractional Value 2 11 5 read-write SM2VAL2 Value Register 2 0xD2 16 read-write 0 0xFFFF VAL2 Value Register 2 0 16 read-write SM2FRACVAL3 Fractional Value Register 3 0xD4 16 read-write 0 0xFFFF FRACVAL3 Fractional Value 3 11 5 read-write SM2VAL3 Value Register 3 0xD6 16 read-write 0 0xFFFF VAL3 Value Register 3 0 16 read-write SM2FRACVAL4 Fractional Value Register 4 0xD8 16 read-write 0 0xFFFF FRACVAL4 Fractional Value 4 11 5 read-write SM2VAL4 Value Register 4 0xDA 16 read-write 0 0xFFFF VAL4 Value Register 4 0 16 read-write SM2FRACVAL5 Fractional Value Register 5 0xDC 16 read-write 0 0xFFFF FRACVAL5 Fractional Value 5 11 5 read-write SM2VAL5 Value Register 5 0xDE 16 read-write 0 0xFFFF VAL5 Value Register 5 0 16 read-write SM2FRCTRL Fractional Control Register 0xE0 16 read-write 0 0xFFFF FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write FRAC1_EN_0 Disable fractional cycle length for the PWM period. 0 FRAC1_EN_1 Enable fractional cycle length for the PWM period. 0x1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write FRAC23_EN_0 Disable fractional cycle placement for PWM_A. 0 FRAC23_EN_1 Enable fractional cycle placement for PWM_A. 0x1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write FRAC45_EN_0 Disable fractional cycle placement for PWM_B. 0 FRAC45_EN_1 Enable fractional cycle placement for PWM_B. 0x1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write FRAC_PU_0 Turn off fractional delay logic. 0 FRAC_PU_1 Power up fractional delay logic. 0x1 TEST Test Status Bit 15 1 read-only SM2OCTRL Output Control Register 0xE2 16 read-write 0 0xFFFF PWMXFS PWM_X Fault State 0 2 read-write PWMXFS_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 PWMXFS_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 PWMXFS_2 Output is tristated. 0x2 PWMXFS_3 Output is tristated. 0x3 PWMBFS PWM_B Fault State 2 2 read-write PWMBFS_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 PWMBFS_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 PWMBFS_2 Output is tristated. 0x2 PWMBFS_3 Output is tristated. 0x3 PWMAFS PWM_A Fault State 4 2 read-write PWMAFS_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 PWMAFS_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 PWMAFS_2 Output is tristated. 0x2 PWMAFS_3 Output is tristated. 0x3 POLX PWM_X Output Polarity 8 1 read-write POLX_0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. 0 POLX_1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. 0x1 POLB PWM_B Output Polarity 9 1 read-write POLB_0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. 0 POLB_1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. 0x1 POLA PWM_A Output Polarity 10 1 read-write POLA_0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. 0 POLA_1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. 0x1 PWMX_IN PWM_X Input 13 1 read-only PWMB_IN PWM_B Input 14 1 read-only PWMA_IN PWM_A Input 15 1 read-only SM2STS Status Register 0xE4 16 read-write 0 0xFFFF CMPF Compare Flags 0 6 read-write oneToClear CMPF_0 No compare event has occurred for a particular VALx value. 0 CMPF_1 A compare event has occurred for a particular VALx value. 0x1 CFX0 Capture Flag X0 6 1 read-write oneToClear CFX1 Capture Flag X1 7 1 read-write oneToClear CFB0 Capture Flag B0 8 1 read-write oneToClear CFB1 Capture Flag B1 9 1 read-write oneToClear CFA0 Capture Flag A0 10 1 read-write oneToClear CFA1 Capture Flag A1 11 1 read-write oneToClear RF Reload Flag 12 1 read-write oneToClear RF_0 No new reload cycle since last STS[RF] clearing 0 RF_1 New reload cycle since last STS[RF] clearing 0x1 REF Reload Error Flag 13 1 read-write oneToClear REF_0 No reload error occurred. 0 REF_1 Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. 0x1 RUF Registers Updated Flag 14 1 read-only RUF_0 No register update has occurred since last reload. 0 RUF_1 At least one of the double buffered registers has been updated since the last reload. 0x1 SM2INTEN Interrupt Enable Register 0xE6 16 read-write 0 0xFFFF CMPIE Compare Interrupt Enables 0 6 read-write CMPIE_0 The corresponding STS[CMPF] bit will not cause an interrupt request. 0 CMPIE_1 The corresponding STS[CMPF] bit will cause an interrupt request. 0x1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write CX0IE_0 Interrupt request disabled for STS[CFX0]. 0 CX0IE_1 Interrupt request enabled for STS[CFX0]. 0x1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write CX1IE_0 Interrupt request disabled for STS[CFX1]. 0 CX1IE_1 Interrupt request enabled for STS[CFX1]. 0x1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write CB0IE_0 Interrupt request disabled for STS[CFB0]. 0 CB0IE_1 Interrupt request enabled for STS[CFB0]. 0x1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write CB1IE_0 Interrupt request disabled for STS[CFB1]. 0 CB1IE_1 Interrupt request enabled for STS[CFB1]. 0x1 CA0IE Capture A 0 Interrupt Enable 10 1 read-write CA0IE_0 Interrupt request disabled for STS[CFA0]. 0 CA0IE_1 Interrupt request enabled for STS[CFA0]. 0x1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write CA1IE_0 Interrupt request disabled for STS[CFA1]. 0 CA1IE_1 Interrupt request enabled for STS[CFA1]. 0x1 RIE Reload Interrupt Enable 12 1 read-write RIE_0 STS[RF] CPU interrupt requests disabled 0 RIE_1 STS[RF] CPU interrupt requests enabled 0x1 REIE Reload Error Interrupt Enable 13 1 read-write REIE_0 STS[REF] CPU interrupt requests disabled 0 REIE_1 STS[REF] CPU interrupt requests enabled 0x1 SM2DMAEN DMA Enable Register 0xE8 16 read-write 0 0xFFFF CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write CAPTDE_0 Read DMA requests disabled. 0 CAPTDE_1 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. 0x1 CAPTDE_2 A local sync (VAL1 matches counter) sets the read DMA request. 0x2 CAPTDE_3 A local reload (STS[RF] being set) sets the read DMA request. 0x3 FAND FIFO Watermark AND Control 8 1 read-write FAND_0 Selected FIFO watermarks are OR'ed together. 0 FAND_1 Selected FIFO watermarks are AND'ed together. 0x1 VALDE Value Registers DMA Enable 9 1 read-write VALDE_0 DMA write requests disabled 0 VALDE_1 DMA write requests for the VALx and FRACVALx registers enabled 0x1 SM2TCTRL Output Trigger Control Register 0xEA 16 read-write 0 0xFFFF OUT_TRIG_EN Output Trigger Enables 0 6 read-write OUT_TRIG_EN_0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. 0 OUT_TRIG_EN_1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. 0x1 TRGFRQ Trigger frequency 12 1 read-write TRGFRQ_0 Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 0 TRGFRQ_1 Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 0x1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write PWBOT1_0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. 0 PWBOT1_1 Route the PWMB output to the PWM_OUT_TRIG1 port. 0x1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write PWAOT0_0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. 0 PWAOT0_1 Route the PWMA output to the PWM_OUT_TRIG0 port. 0x1 SM2DISMAP0 Fault Disable Mapping Register 0 0xEC 16 read-write 0xFFFF 0xFFFF DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SM2DISMAP1 Fault Disable Mapping Register 1 0xEE 16 read-write 0xFFFF 0xFFFF DIS1A PWM_A Fault Disable Mask 1 0 4 read-write DIS1B PWM_B Fault Disable Mask 1 4 4 read-write DIS1X PWM_X Fault Disable Mask 1 8 4 read-write SM2DTCNT0 Deadtime Count Register 0 0xF0 16 read-write 0x7FF 0xFFFF DTCNT0 DTCNT0 0 16 read-write SM2DTCNT1 Deadtime Count Register 1 0xF2 16 read-write 0x7FF 0xFFFF DTCNT1 DTCNT1 0 16 read-write SM2CAPTCTRLA Capture Control A Register 0xF4 16 read-write 0 0xFFFF ARMA Arm A 0 1 read-write ARMA_0 Input capture operation is disabled. 0 ARMA_1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. 0x1 ONESHOTA One Shot Mode A 1 1 read-write ONESHOTA_0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0 ONESHOTA_1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. 0x1 EDGA0 Edge A 0 2 2 read-write EDGA0_0 Disabled 0 EDGA0_1 Capture falling edges 0x1 EDGA0_2 Capture rising edges 0x2 EDGA0_3 Capture any edge 0x3 EDGA1 Edge A 1 4 2 read-write EDGA1_0 Disabled 0 EDGA1_1 Capture falling edges 0x1 EDGA1_2 Capture rising edges 0x2 EDGA1_3 Capture any edge 0x3 INP_SELA Input Select A 6 1 read-write INP_SELA_0 Raw PWM_A input signal selected as source. 0 INP_SELA_1 Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. 0x1 EDGCNTA_EN Edge Counter A Enable 7 1 read-write EDGCNTA_EN_0 Edge counter disabled and held in reset 0 EDGCNTA_EN_1 Edge counter enabled 0x1 CFAWM Capture A FIFOs Water Mark 8 2 read-write CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only SM2CAPTCOMPA Capture Compare A Register 0xF6 16 read-write 0 0xFFFF EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SM2CAPTCTRLB Capture Control B Register 0xF8 16 read-write 0 0xFFFF ARMB Arm B 0 1 read-write ARMB_0 Input capture operation is disabled. 0 ARMB_1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. 0x1 ONESHOTB One Shot Mode B 1 1 read-write ONESHOTB_0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0 ONESHOTB_1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. 0x1 EDGB0 Edge B 0 2 2 read-write EDGB0_0 Disabled 0 EDGB0_1 Capture falling edges 0x1 EDGB0_2 Capture rising edges 0x2 EDGB0_3 Capture any edge 0x3 EDGB1 Edge B 1 4 2 read-write EDGB1_0 Disabled 0 EDGB1_1 Capture falling edges 0x1 EDGB1_2 Capture rising edges 0x2 EDGB1_3 Capture any edge 0x3 INP_SELB Input Select B 6 1 read-write INP_SELB_0 Raw PWM_B input signal selected as source. 0 INP_SELB_1 Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. 0x1 EDGCNTB_EN Edge Counter B Enable 7 1 read-write EDGCNTB_EN_0 Edge counter disabled and held in reset 0 EDGCNTB_EN_1 Edge counter enabled 0x1 CFBWM Capture B FIFOs Water Mark 8 2 read-write CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only SM2CAPTCOMPB Capture Compare B Register 0xFA 16 read-write 0 0xFFFF EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SM2CAPTCTRLX Capture Control X Register 0xFC 16 read-write 0 0xFFFF ARMX Arm X 0 1 read-write ARMX_0 Input capture operation is disabled. 0 ARMX_1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. 0x1 ONESHOTX One Shot Mode Aux 1 1 read-write ONESHOTX_0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0 ONESHOTX_1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. 0x1 EDGX0 Edge X 0 2 2 read-write EDGX0_0 Disabled 0 EDGX0_1 Capture falling edges 0x1 EDGX0_2 Capture rising edges 0x2 EDGX0_3 Capture any edge 0x3 EDGX1 Edge X 1 4 2 read-write EDGX1_0 Disabled 0 EDGX1_1 Capture falling edges 0x1 EDGX1_2 Capture rising edges 0x2 EDGX1_3 Capture any edge 0x3 INP_SELX Input Select X 6 1 read-write INP_SELX_0 Raw PWM_X input signal selected as source. 0 INP_SELX_1 Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. 0x1 EDGCNTX_EN Edge Counter X Enable 7 1 read-write EDGCNTX_EN_0 Edge counter disabled and held in reset 0 EDGCNTX_EN_1 Edge counter enabled 0x1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only SM2CAPTCOMPX Capture Compare X Register 0xFE 16 read-write 0 0xFFFF EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SM2CVAL0 Capture Value 0 Register 0x100 16 read-only 0 0xFFFF CAPTVAL0 CAPTVAL0 0 16 read-only SM2CVAL0CYC Capture Value 0 Cycle Register 0x102 16 read-only 0 0xFFFF CVAL0CYC CVAL0CYC 0 4 read-only SM2CVAL1 Capture Value 1 Register 0x104 16 read-only 0 0xFFFF CAPTVAL1 CAPTVAL1 0 16 read-only SM2CVAL1CYC Capture Value 1 Cycle Register 0x106 16 read-only 0 0xFFFF CVAL1CYC CVAL1CYC 0 4 read-only SM2CVAL2 Capture Value 2 Register 0x108 16 read-only 0 0xFFFF CAPTVAL2 CAPTVAL2 0 16 read-only SM2CVAL2CYC Capture Value 2 Cycle Register 0x10A 16 read-only 0 0xFFFF CVAL2CYC CVAL2CYC 0 4 read-only SM2CVAL3 Capture Value 3 Register 0x10C 16 read-only 0 0xFFFF CAPTVAL3 CAPTVAL3 0 16 read-only SM2CVAL3CYC Capture Value 3 Cycle Register 0x10E 16 read-only 0 0xFFFF CVAL3CYC CVAL3CYC 0 4 read-only SM2CVAL4 Capture Value 4 Register 0x110 16 read-only 0 0xFFFF CAPTVAL4 CAPTVAL4 0 16 read-only SM2CVAL4CYC Capture Value 4 Cycle Register 0x112 16 read-only 0 0xFFFF CVAL4CYC CVAL4CYC 0 4 read-only SM2CVAL5 Capture Value 5 Register 0x114 16 read-only 0 0xFFFF CAPTVAL5 CAPTVAL5 0 16 read-only SM2CVAL5CYC Capture Value 5 Cycle Register 0x116 16 read-only 0 0xFFFF CVAL5CYC CVAL5CYC 0 4 read-only SM2PHASEDLY Phase Delay Register 0x118 16 read-write 0 0xFFFF PHASEDLY Initial Count Register Bits 0 16 read-write SM3CNT Counter Register 0x120 16 read-only 0 0xFFFF CNT Counter Register Bits 0 16 read-only SM3INIT Initial Count Register 0x122 16 read-write 0 0xFFFF INIT Initial Count Register Bits 0 16 read-write SM3CTRL2 Control 2 Register 0x124 16 read-write 0 0xFFFF CLK_SEL Clock Source Select 0 2 read-write CLK_SEL_0 The IPBus clock is used as the clock for the local prescaler and counter. 0 CLK_SEL_1 EXT_CLK is used as the clock for the local prescaler and counter. 0x1 CLK_SEL_2 Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. 0x2 RELOAD_SEL Reload Source Select 2 1 read-write RELOAD_SEL_0 The local RELOAD signal is used to reload registers. 0 RELOAD_SEL_1 The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. 0x1 FORCE_SEL This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 3 3 read-write FORCE_SEL_0 The local force signal, CTRL2[FORCE], from this submodule is used to force updates. 0 FORCE_SEL_1 The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. 0x1 FORCE_SEL_2 The local reload signal from this submodule is used to force updates without regard to the state of LDOK. 0x2 FORCE_SEL_3 The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0x3 FORCE_SEL_4 The local sync signal from this submodule is used to force updates. 0x4 FORCE_SEL_5 The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0x5 FORCE_SEL_6 The external force signal, EXT_FORCE, from outside the PWM module causes updates. 0x6 FORCE_SEL_7 The external sync signal, EXT_SYNC, from outside the PWM module causes updates. 0x7 FORCE Force Initialization 6 1 read-write FRCEN FRCEN 7 1 read-write FRCEN_0 Initialization from a FORCE_OUT is disabled. 0 FRCEN_1 Initialization from a FORCE_OUT is enabled. 0x1 INIT_SEL Initialization Control Select 8 2 read-write INIT_SEL_0 Local sync (PWM_X) causes initialization. 0 INIT_SEL_1 Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. 0x1 INIT_SEL_2 Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. 0x2 INIT_SEL_3 EXT_SYNC causes initialization. 0x3 PWMX_INIT PWM_X Initial Value 10 1 read-write PWM45_INIT PWM45 Initial Value 11 1 read-write PWM23_INIT PWM23 Initial Value 12 1 read-write INDEP Independent or Complementary Pair Operation 13 1 read-write INDEP_0 PWM_A and PWM_B form a complementary PWM pair. 0 INDEP_1 PWM_A and PWM_B outputs are independent PWMs. 0x1 WAITEN WAIT Enable 14 1 read-write DBGEN Debug Enable 15 1 read-write SM3CTRL Control Register 0x126 16 read-write 0x400 0xFFFF DBLEN Double Switching Enable 0 1 read-write DBLEN_0 Double switching disabled. 0 DBLEN_1 Double switching enabled. 0x1 DBLX PWMX Double Switching Enable 1 1 read-write DBLX_0 PWMX double pulse disabled. 0 DBLX_1 PWMX double pulse enabled. 0x1 LDMOD Load Mode Select 2 1 read-write LDMOD_0 Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 0 LDMOD_1 Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. 0x1 SPLIT Split the DBLPWM signal to PWMA and PWMB 3 1 read-write SPLIT_0 DBLPWM is not split. PWMA and PWMB each have double pulses. 0 SPLIT_1 DBLPWM is split to PWMA and PWMB. 0x1 PRSC Prescaler 4 3 read-write PRSC_0 PWM clock frequency = fclk 0 PRSC_1 PWM clock frequency = fclk/2 0x1 PRSC_2 PWM clock frequency = fclk/4 0x2 PRSC_3 PWM clock frequency = fclk/8 0x3 PRSC_4 PWM clock frequency = fclk/16 0x4 PRSC_5 PWM clock frequency = fclk/32 0x5 PRSC_6 PWM clock frequency = fclk/64 0x6 PRSC_7 PWM clock frequency = fclk/128 0x7 COMPMODE Compare Mode 7 1 read-write COMPMODE_0 The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 0 COMPMODE_1 The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. 0x1 DT Deadtime 8 2 read-only FULL Full Cycle Reload 10 1 read-write FULL_0 Full-cycle reloads disabled. 0 FULL_1 Full-cycle reloads enabled. 0x1 HALF Half Cycle Reload 11 1 read-write HALF_0 Half-cycle reloads disabled. 0 HALF_1 Half-cycle reloads enabled. 0x1 LDFQ Load Frequency 12 4 read-write LDFQ_0 Every PWM opportunity 0 LDFQ_1 Every 2 PWM opportunities 0x1 LDFQ_2 Every 3 PWM opportunities 0x2 LDFQ_3 Every 4 PWM opportunities 0x3 LDFQ_4 Every 5 PWM opportunities 0x4 LDFQ_5 Every 6 PWM opportunities 0x5 LDFQ_6 Every 7 PWM opportunities 0x6 LDFQ_7 Every 8 PWM opportunities 0x7 LDFQ_8 Every 9 PWM opportunities 0x8 LDFQ_9 Every 10 PWM opportunities 0x9 LDFQ_10 Every 11 PWM opportunities 0xA LDFQ_11 Every 12 PWM opportunities 0xB LDFQ_12 Every 13 PWM opportunities 0xC LDFQ_13 Every 14 PWM opportunities 0xD LDFQ_14 Every 15 PWM opportunities 0xE LDFQ_15 Every 16 PWM opportunities 0xF SM3VAL0 Value Register 0 0x12A 16 read-write 0 0xFFFF VAL0 Value Register 0 0 16 read-write SM3FRACVAL1 Fractional Value Register 1 0x12C 16 read-write 0 0xFFFF FRACVAL1 Fractional Value 1 Register 11 5 read-write SM3VAL1 Value Register 1 0x12E 16 read-write 0 0xFFFF VAL1 Value Register 1 0 16 read-write SM3FRACVAL2 Fractional Value Register 2 0x130 16 read-write 0 0xFFFF FRACVAL2 Fractional Value 2 11 5 read-write SM3VAL2 Value Register 2 0x132 16 read-write 0 0xFFFF VAL2 Value Register 2 0 16 read-write SM3FRACVAL3 Fractional Value Register 3 0x134 16 read-write 0 0xFFFF FRACVAL3 Fractional Value 3 11 5 read-write SM3VAL3 Value Register 3 0x136 16 read-write 0 0xFFFF VAL3 Value Register 3 0 16 read-write SM3FRACVAL4 Fractional Value Register 4 0x138 16 read-write 0 0xFFFF FRACVAL4 Fractional Value 4 11 5 read-write SM3VAL4 Value Register 4 0x13A 16 read-write 0 0xFFFF VAL4 Value Register 4 0 16 read-write SM3FRACVAL5 Fractional Value Register 5 0x13C 16 read-write 0 0xFFFF FRACVAL5 Fractional Value 5 11 5 read-write SM3VAL5 Value Register 5 0x13E 16 read-write 0 0xFFFF VAL5 Value Register 5 0 16 read-write SM3FRCTRL Fractional Control Register 0x140 16 read-write 0 0xFFFF FRAC1_EN Fractional Cycle PWM Period Enable 1 1 read-write FRAC1_EN_0 Disable fractional cycle length for the PWM period. 0 FRAC1_EN_1 Enable fractional cycle length for the PWM period. 0x1 FRAC23_EN Fractional Cycle Placement Enable for PWM_A 2 1 read-write FRAC23_EN_0 Disable fractional cycle placement for PWM_A. 0 FRAC23_EN_1 Enable fractional cycle placement for PWM_A. 0x1 FRAC45_EN Fractional Cycle Placement Enable for PWM_B 4 1 read-write FRAC45_EN_0 Disable fractional cycle placement for PWM_B. 0 FRAC45_EN_1 Enable fractional cycle placement for PWM_B. 0x1 FRAC_PU Fractional Delay Circuit Power Up 8 1 read-write FRAC_PU_0 Turn off fractional delay logic. 0 FRAC_PU_1 Power up fractional delay logic. 0x1 TEST Test Status Bit 15 1 read-only SM3OCTRL Output Control Register 0x142 16 read-write 0 0xFFFF PWMXFS PWM_X Fault State 0 2 read-write PWMXFS_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 PWMXFS_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 PWMXFS_2 Output is tristated. 0x2 PWMXFS_3 Output is tristated. 0x3 PWMBFS PWM_B Fault State 2 2 read-write PWMBFS_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 PWMBFS_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 PWMBFS_2 Output is tristated. 0x2 PWMBFS_3 Output is tristated. 0x3 PWMAFS PWM_A Fault State 4 2 read-write PWMAFS_0 Output is forced to logic 0 state prior to consideration of output polarity control. 0 PWMAFS_1 Output is forced to logic 1 state prior to consideration of output polarity control. 0x1 PWMAFS_2 Output is tristated. 0x2 PWMAFS_3 Output is tristated. 0x3 POLX PWM_X Output Polarity 8 1 read-write POLX_0 PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. 0 POLX_1 PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. 0x1 POLB PWM_B Output Polarity 9 1 read-write POLB_0 PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. 0 POLB_1 PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. 0x1 POLA PWM_A Output Polarity 10 1 read-write POLA_0 PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. 0 POLA_1 PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. 0x1 PWMX_IN PWM_X Input 13 1 read-only PWMB_IN PWM_B Input 14 1 read-only PWMA_IN PWM_A Input 15 1 read-only SM3STS Status Register 0x144 16 read-write 0 0xFFFF CMPF Compare Flags 0 6 read-write oneToClear CMPF_0 No compare event has occurred for a particular VALx value. 0 CMPF_1 A compare event has occurred for a particular VALx value. 0x1 CFX0 Capture Flag X0 6 1 read-write oneToClear CFX1 Capture Flag X1 7 1 read-write oneToClear CFB0 Capture Flag B0 8 1 read-write oneToClear CFB1 Capture Flag B1 9 1 read-write oneToClear CFA0 Capture Flag A0 10 1 read-write oneToClear CFA1 Capture Flag A1 11 1 read-write oneToClear RF Reload Flag 12 1 read-write oneToClear RF_0 No new reload cycle since last STS[RF] clearing 0 RF_1 New reload cycle since last STS[RF] clearing 0x1 REF Reload Error Flag 13 1 read-write oneToClear REF_0 No reload error occurred. 0 REF_1 Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. 0x1 RUF Registers Updated Flag 14 1 read-only RUF_0 No register update has occurred since last reload. 0 RUF_1 At least one of the double buffered registers has been updated since the last reload. 0x1 SM3INTEN Interrupt Enable Register 0x146 16 read-write 0 0xFFFF CMPIE Compare Interrupt Enables 0 6 read-write CMPIE_0 The corresponding STS[CMPF] bit will not cause an interrupt request. 0 CMPIE_1 The corresponding STS[CMPF] bit will cause an interrupt request. 0x1 CX0IE Capture X 0 Interrupt Enable 6 1 read-write CX0IE_0 Interrupt request disabled for STS[CFX0]. 0 CX0IE_1 Interrupt request enabled for STS[CFX0]. 0x1 CX1IE Capture X 1 Interrupt Enable 7 1 read-write CX1IE_0 Interrupt request disabled for STS[CFX1]. 0 CX1IE_1 Interrupt request enabled for STS[CFX1]. 0x1 CB0IE Capture B 0 Interrupt Enable 8 1 read-write CB0IE_0 Interrupt request disabled for STS[CFB0]. 0 CB0IE_1 Interrupt request enabled for STS[CFB0]. 0x1 CB1IE Capture B 1 Interrupt Enable 9 1 read-write CB1IE_0 Interrupt request disabled for STS[CFB1]. 0 CB1IE_1 Interrupt request enabled for STS[CFB1]. 0x1 CA0IE Capture A 0 Interrupt Enable 10 1 read-write CA0IE_0 Interrupt request disabled for STS[CFA0]. 0 CA0IE_1 Interrupt request enabled for STS[CFA0]. 0x1 CA1IE Capture A 1 Interrupt Enable 11 1 read-write CA1IE_0 Interrupt request disabled for STS[CFA1]. 0 CA1IE_1 Interrupt request enabled for STS[CFA1]. 0x1 RIE Reload Interrupt Enable 12 1 read-write RIE_0 STS[RF] CPU interrupt requests disabled 0 RIE_1 STS[RF] CPU interrupt requests enabled 0x1 REIE Reload Error Interrupt Enable 13 1 read-write REIE_0 STS[REF] CPU interrupt requests disabled 0 REIE_1 STS[REF] CPU interrupt requests enabled 0x1 SM3DMAEN DMA Enable Register 0x148 16 read-write 0 0xFFFF CX0DE Capture X0 FIFO DMA Enable 0 1 read-write CX1DE Capture X1 FIFO DMA Enable 1 1 read-write CB0DE Capture B0 FIFO DMA Enable 2 1 read-write CB1DE Capture B1 FIFO DMA Enable 3 1 read-write CA0DE Capture A0 FIFO DMA Enable 4 1 read-write CA1DE Capture A1 FIFO DMA Enable 5 1 read-write CAPTDE Capture DMA Enable Source Select 6 2 read-write CAPTDE_0 Read DMA requests disabled. 0 CAPTDE_1 Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. 0x1 CAPTDE_2 A local sync (VAL1 matches counter) sets the read DMA request. 0x2 CAPTDE_3 A local reload (STS[RF] being set) sets the read DMA request. 0x3 FAND FIFO Watermark AND Control 8 1 read-write FAND_0 Selected FIFO watermarks are OR'ed together. 0 FAND_1 Selected FIFO watermarks are AND'ed together. 0x1 VALDE Value Registers DMA Enable 9 1 read-write VALDE_0 DMA write requests disabled 0 VALDE_1 DMA write requests for the VALx and FRACVALx registers enabled 0x1 SM3TCTRL Output Trigger Control Register 0x14A 16 read-write 0 0xFFFF OUT_TRIG_EN Output Trigger Enables 0 6 read-write OUT_TRIG_EN_0 PWM_OUT_TRIGx will not set when the counter value matches the VALx value. 0 OUT_TRIG_EN_1 PWM_OUT_TRIGx will set when the counter value matches the VALx value. 0x1 TRGFRQ Trigger frequency 12 1 read-write TRGFRQ_0 Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 0 TRGFRQ_1 Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 0x1 PWBOT1 Output Trigger 1 Source Select 14 1 read-write PWBOT1_0 Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. 0 PWBOT1_1 Route the PWMB output to the PWM_OUT_TRIG1 port. 0x1 PWAOT0 Output Trigger 0 Source Select 15 1 read-write PWAOT0_0 Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. 0 PWAOT0_1 Route the PWMA output to the PWM_OUT_TRIG0 port. 0x1 SM3DISMAP0 Fault Disable Mapping Register 0 0x14C 16 read-write 0xFFFF 0xFFFF DIS0A PWM_A Fault Disable Mask 0 0 4 read-write DIS0B PWM_B Fault Disable Mask 0 4 4 read-write DIS0X PWM_X Fault Disable Mask 0 8 4 read-write SM3DISMAP1 Fault Disable Mapping Register 1 0x14E 16 read-write 0xFFFF 0xFFFF DIS1A PWM_A Fault Disable Mask 1 0 4 read-write DIS1B PWM_B Fault Disable Mask 1 4 4 read-write DIS1X PWM_X Fault Disable Mask 1 8 4 read-write SM3DTCNT0 Deadtime Count Register 0 0x150 16 read-write 0x7FF 0xFFFF DTCNT0 DTCNT0 0 16 read-write SM3DTCNT1 Deadtime Count Register 1 0x152 16 read-write 0x7FF 0xFFFF DTCNT1 DTCNT1 0 16 read-write SM3CAPTCTRLA Capture Control A Register 0x154 16 read-write 0 0xFFFF ARMA Arm A 0 1 read-write ARMA_0 Input capture operation is disabled. 0 ARMA_1 Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. 0x1 ONESHOTA One Shot Mode A 1 1 read-write ONESHOTA_0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0 ONESHOTA_1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. 0x1 EDGA0 Edge A 0 2 2 read-write EDGA0_0 Disabled 0 EDGA0_1 Capture falling edges 0x1 EDGA0_2 Capture rising edges 0x2 EDGA0_3 Capture any edge 0x3 EDGA1 Edge A 1 4 2 read-write EDGA1_0 Disabled 0 EDGA1_1 Capture falling edges 0x1 EDGA1_2 Capture rising edges 0x2 EDGA1_3 Capture any edge 0x3 INP_SELA Input Select A 6 1 read-write INP_SELA_0 Raw PWM_A input signal selected as source. 0 INP_SELA_1 Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. 0x1 EDGCNTA_EN Edge Counter A Enable 7 1 read-write EDGCNTA_EN_0 Edge counter disabled and held in reset 0 EDGCNTA_EN_1 Edge counter enabled 0x1 CFAWM Capture A FIFOs Water Mark 8 2 read-write CA0CNT Capture A0 FIFO Word Count 10 3 read-only CA1CNT Capture A1 FIFO Word Count 13 3 read-only SM3CAPTCOMPA Capture Compare A Register 0x156 16 read-write 0 0xFFFF EDGCMPA Edge Compare A 0 8 read-write EDGCNTA Edge Counter A 8 8 read-only SM3CAPTCTRLB Capture Control B Register 0x158 16 read-write 0 0xFFFF ARMB Arm B 0 1 read-write ARMB_0 Input capture operation is disabled. 0 ARMB_1 Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. 0x1 ONESHOTB One Shot Mode B 1 1 read-write ONESHOTB_0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0 ONESHOTB_1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. 0x1 EDGB0 Edge B 0 2 2 read-write EDGB0_0 Disabled 0 EDGB0_1 Capture falling edges 0x1 EDGB0_2 Capture rising edges 0x2 EDGB0_3 Capture any edge 0x3 EDGB1 Edge B 1 4 2 read-write EDGB1_0 Disabled 0 EDGB1_1 Capture falling edges 0x1 EDGB1_2 Capture rising edges 0x2 EDGB1_3 Capture any edge 0x3 INP_SELB Input Select B 6 1 read-write INP_SELB_0 Raw PWM_B input signal selected as source. 0 INP_SELB_1 Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. 0x1 EDGCNTB_EN Edge Counter B Enable 7 1 read-write EDGCNTB_EN_0 Edge counter disabled and held in reset 0 EDGCNTB_EN_1 Edge counter enabled 0x1 CFBWM Capture B FIFOs Water Mark 8 2 read-write CB0CNT Capture B0 FIFO Word Count 10 3 read-only CB1CNT Capture B1 FIFO Word Count 13 3 read-only SM3CAPTCOMPB Capture Compare B Register 0x15A 16 read-write 0 0xFFFF EDGCMPB Edge Compare B 0 8 read-write EDGCNTB Edge Counter B 8 8 read-only SM3CAPTCTRLX Capture Control X Register 0x15C 16 read-write 0 0xFFFF ARMX Arm X 0 1 read-write ARMX_0 Input capture operation is disabled. 0 ARMX_1 Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. 0x1 ONESHOTX One Shot Mode Aux 1 1 read-write ONESHOTX_0 Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0 ONESHOTX_1 One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. 0x1 EDGX0 Edge X 0 2 2 read-write EDGX0_0 Disabled 0 EDGX0_1 Capture falling edges 0x1 EDGX0_2 Capture rising edges 0x2 EDGX0_3 Capture any edge 0x3 EDGX1 Edge X 1 4 2 read-write EDGX1_0 Disabled 0 EDGX1_1 Capture falling edges 0x1 EDGX1_2 Capture rising edges 0x2 EDGX1_3 Capture any edge 0x3 INP_SELX Input Select X 6 1 read-write INP_SELX_0 Raw PWM_X input signal selected as source. 0 INP_SELX_1 Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. 0x1 EDGCNTX_EN Edge Counter X Enable 7 1 read-write EDGCNTX_EN_0 Edge counter disabled and held in reset 0 EDGCNTX_EN_1 Edge counter enabled 0x1 CFXWM Capture X FIFOs Water Mark 8 2 read-write CX0CNT Capture X0 FIFO Word Count 10 3 read-only CX1CNT Capture X1 FIFO Word Count 13 3 read-only SM3CAPTCOMPX Capture Compare X Register 0x15E 16 read-write 0 0xFFFF EDGCMPX Edge Compare X 0 8 read-write EDGCNTX Edge Counter X 8 8 read-only SM3CVAL0 Capture Value 0 Register 0x160 16 read-only 0 0xFFFF CAPTVAL0 CAPTVAL0 0 16 read-only SM3CVAL0CYC Capture Value 0 Cycle Register 0x162 16 read-only 0 0xFFFF CVAL0CYC CVAL0CYC 0 4 read-only SM3CVAL1 Capture Value 1 Register 0x164 16 read-only 0 0xFFFF CAPTVAL1 CAPTVAL1 0 16 read-only SM3CVAL1CYC Capture Value 1 Cycle Register 0x166 16 read-only 0 0xFFFF CVAL1CYC CVAL1CYC 0 4 read-only SM3CVAL2 Capture Value 2 Register 0x168 16 read-only 0 0xFFFF CAPTVAL2 CAPTVAL2 0 16 read-only SM3CVAL2CYC Capture Value 2 Cycle Register 0x16A 16 read-only 0 0xFFFF CVAL2CYC CVAL2CYC 0 4 read-only SM3CVAL3 Capture Value 3 Register 0x16C 16 read-only 0 0xFFFF CAPTVAL3 CAPTVAL3 0 16 read-only SM3CVAL3CYC Capture Value 3 Cycle Register 0x16E 16 read-only 0 0xFFFF CVAL3CYC CVAL3CYC 0 4 read-only SM3CVAL4 Capture Value 4 Register 0x170 16 read-only 0 0xFFFF CAPTVAL4 CAPTVAL4 0 16 read-only SM3CVAL4CYC Capture Value 4 Cycle Register 0x172 16 read-only 0 0xFFFF CVAL4CYC CVAL4CYC 0 4 read-only SM3CVAL5 Capture Value 5 Register 0x174 16 read-only 0 0xFFFF CAPTVAL5 CAPTVAL5 0 16 read-only SM3CVAL5CYC Capture Value 5 Cycle Register 0x176 16 read-only 0 0xFFFF CVAL5CYC CVAL5CYC 0 4 read-only SM3PHASEDLY Phase Delay Register 0x178 16 read-write 0 0xFFFF PHASEDLY Initial Count Register Bits 0 16 read-write OUTEN Output Enable Register 0x180 16 read-write 0 0xFFFF PWMX_EN PWM_X Output Enables 0 4 read-write PWMX_EN_0 PWM_X output disabled. 0 PWMX_EN_1 PWM_X output enabled. 0x1 PWMB_EN PWM_B Output Enables 4 4 read-write PWMB_EN_0 PWM_B output disabled. 0 PWMB_EN_1 PWM_B output enabled. 0x1 PWMA_EN PWM_A Output Enables 8 4 read-write PWMA_EN_0 PWM_A output disabled. 0 PWMA_EN_1 PWM_A output enabled. 0x1 MASK Mask Register 0x182 16 read-write 0 0xFFFF MASKX PWM_X Masks 0 4 read-write MASKX_0 PWM_X output normal. 0 MASKX_1 PWM_X output masked. 0x1 MASKB PWM_B Masks 4 4 read-write MASKB_0 PWM_B output normal. 0 MASKB_1 PWM_B output masked. 0x1 MASKA PWM_A Masks 8 4 read-write MASKA_0 PWM_A output normal. 0 MASKA_1 PWM_A output masked. 0x1 UPDATE_MASK Update Mask Bits Immediately 12 4 write-only UPDATE_MASK_0 Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. 0 UPDATE_MASK_1 Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. 0x1 SWCOUT Software Controlled Output Register 0x184 16 read-write 0 0xFFFF SM0OUT45 Submodule 0 Software Controlled Output 45 0 1 read-write SM0OUT45_0 A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. 0 SM0OUT45_1 A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. 0x1 SM0OUT23 Submodule 0 Software Controlled Output 23 1 1 read-write SM0OUT23_0 A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. 0 SM0OUT23_1 A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. 0x1 SM1OUT45 Submodule 1 Software Controlled Output 45 2 1 read-write SM1OUT45_0 A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. 0 SM1OUT45_1 A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. 0x1 SM1OUT23 Submodule 1 Software Controlled Output 23 3 1 read-write SM1OUT23_0 A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. 0 SM1OUT23_1 A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. 0x1 SM2OUT45 Submodule 2 Software Controlled Output 45 4 1 read-write SM2OUT45_0 A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. 0 SM2OUT45_1 A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. 0x1 SM2OUT23 Submodule 2 Software Controlled Output 23 5 1 read-write SM2OUT23_0 A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. 0 SM2OUT23_1 A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. 0x1 SM3OUT45 Submodule 3 Software Controlled Output 45 6 1 read-write SM3OUT45_0 A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. 0 SM3OUT45_1 A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. 0x1 SM3OUT23 Submodule 3 Software Controlled Output 23 7 1 read-write SM3OUT23_0 A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. 0 SM3OUT23_1 A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. 0x1 DTSRCSEL PWM Source Select Register 0x186 16 read-write 0 0xFFFF SM0SEL45 Submodule 0 PWM45 Control Select 0 2 read-write SM0SEL45_0 Generated SM0PWM45 signal is used by the deadtime logic. 0 SM0SEL45_1 Inverted generated SM0PWM45 signal is used by the deadtime logic. 0x1 SM0SEL45_2 SWCOUT[SM0OUT45] is used by the deadtime logic. 0x2 SM0SEL45_3 PWM0_EXTB signal is used by the deadtime logic. 0x3 SM0SEL23 Submodule 0 PWM23 Control Select 2 2 read-write SM0SEL23_0 Generated SM0PWM23 signal is used by the deadtime logic. 0 SM0SEL23_1 Inverted generated SM0PWM23 signal is used by the deadtime logic. 0x1 SM0SEL23_2 SWCOUT[SM0OUT23] is used by the deadtime logic. 0x2 SM0SEL23_3 PWM0_EXTA signal is used by the deadtime logic. 0x3 SM1SEL45 Submodule 1 PWM45 Control Select 4 2 read-write SM1SEL45_0 Generated SM1PWM45 signal is used by the deadtime logic. 0 SM1SEL45_1 Inverted generated SM1PWM45 signal is used by the deadtime logic. 0x1 SM1SEL45_2 SWCOUT[SM1OUT45] is used by the deadtime logic. 0x2 SM1SEL45_3 PWM1_EXTB signal is used by the deadtime logic. 0x3 SM1SEL23 Submodule 1 PWM23 Control Select 6 2 read-write SM1SEL23_0 Generated SM1PWM23 signal is used by the deadtime logic. 0 SM1SEL23_1 Inverted generated SM1PWM23 signal is used by the deadtime logic. 0x1 SM1SEL23_2 SWCOUT[SM1OUT23] is used by the deadtime logic. 0x2 SM1SEL23_3 PWM1_EXTA signal is used by the deadtime logic. 0x3 SM2SEL45 Submodule 2 PWM45 Control Select 8 2 read-write SM2SEL45_0 Generated SM2PWM45 signal is used by the deadtime logic. 0 SM2SEL45_1 Inverted generated SM2PWM45 signal is used by the deadtime logic. 0x1 SM2SEL45_2 SWCOUT[SM2OUT45] is used by the deadtime logic. 0x2 SM2SEL45_3 PWM2_EXTB signal is used by the deadtime logic. 0x3 SM2SEL23 Submodule 2 PWM23 Control Select 10 2 read-write SM2SEL23_0 Generated SM2PWM23 signal is used by the deadtime logic. 0 SM2SEL23_1 Inverted generated SM2PWM23 signal is used by the deadtime logic. 0x1 SM2SEL23_2 SWCOUT[SM2OUT23] is used by the deadtime logic. 0x2 SM2SEL23_3 PWM2_EXTA signal is used by the deadtime logic. 0x3 SM3SEL45 Submodule 3 PWM45 Control Select 12 2 read-write SM3SEL45_0 Generated SM3PWM45 signal is used by the deadtime logic. 0 SM3SEL45_1 Inverted generated SM3PWM45 signal is used by the deadtime logic. 0x1 SM3SEL45_2 SWCOUT[SM3OUT45] is used by the deadtime logic. 0x2 SM3SEL45_3 PWM3_EXTB signal is used by the deadtime logic. 0x3 SM3SEL23 Submodule 3 PWM23 Control Select 14 2 read-write SM3SEL23_0 Generated SM3PWM23 signal is used by the deadtime logic. 0 SM3SEL23_1 Inverted generated SM3PWM23 signal is used by the deadtime logic. 0x1 SM3SEL23_2 SWCOUT[SM3OUT23] is used by the deadtime logic. 0x2 SM3SEL23_3 PWM3_EXTA signal is used by the deadtime logic. 0x3 MCTRL Master Control Register 0x188 16 read-write 0 0xFFFF LDOK Load Okay 0 4 read-write LDOK_0 Do not load new values. 0 LDOK_1 Load prescaler, modulus, and PWM values of the corresponding submodule. 0x1 CLDOK Clear Load Okay 4 4 read-write RUN Run 8 4 read-write RUN_0 PWM generator is disabled in the corresponding submodule. 0 RUN_1 PWM generator is enabled in the corresponding submodule. 0x1 IPOL Current Polarity 12 4 read-write IPOL_0 PWM23 is used to generate complementary PWM pair in the corresponding submodule. 0 IPOL_1 PWM45 is used to generate complementary PWM pair in the corresponding submodule. 0x1 MCTRL2 Master Control 2 Register 0x18A 16 read-write 0 0xFFFF MONPLL Monitor PLL State 0 2 read-write MONPLL_0 Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. 0 MONPLL_1 Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. 0x1 MONPLL_2 Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. 0x2 MONPLL_3 Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset. 0x3 FCTRL0 Fault Control Register 0x18C 16 read-write 0 0xFFFF FIE Fault Interrupt Enables 0 4 read-write FIE_0 FAULTx CPU interrupt requests disabled. 0 FIE_1 FAULTx CPU interrupt requests enabled. 0x1 FSAFE Fault Safety Mode 4 4 read-write FSAFE_0 Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is setm then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). 0 FSAFE_1 Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. 0x1 FAUTO Automatic Fault Clearing 8 4 read-write FAUTO_0 Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the states of FSTS[FHALF] and FSTS[FFULL]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL[FSAFE]. 0 FAUTO_1 Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. 0x1 FLVL Fault Level 12 4 read-write FLVL_0 A logic 0 on the fault input indicates a fault condition. 0 FLVL_1 A logic 1 on the fault input indicates a fault condition. 0x1 FSTS0 Fault Status Register 0x18E 16 read-write 0 0xFFFF FFLAG Fault Flags 0 4 read-write FFLAG_0 No fault on the FAULTx pin. 0 FFLAG_1 Fault on the FAULTx pin. 0x1 FFULL Full Cycle 4 4 read-write FFULL_0 PWM outputs are not re-enabled at the start of a full cycle 0 FFULL_1 PWM outputs are re-enabled at the start of a full cycle 0x1 FFPIN Filtered Fault Pins 8 4 read-only FHALF Half Cycle Fault Recovery 12 4 read-write FHALF_0 PWM outputs are not re-enabled at the start of a half cycle. 0 FHALF_1 PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). 0x1 FFILT0 Fault Filter Register 0x190 16 read-write 0 0xFFFF FILT_PER Fault Filter Period 0 8 read-write FILT_CNT Fault Filter Count 8 3 read-write GSTR Fault Glitch Stretch Enable 15 1 read-write GSTR_0 Fault input glitch stretching is disabled. 0 GSTR_1 Input fault signals will be stretched to at least 2 IPBus clock cycles. 0x1 FTST0 Fault Test Register 0x192 16 read-write 0 0xFFFF FTEST Fault Test 0 1 read-write FTEST_0 No fault 0 FTEST_1 Cause a simulated fault 0x1 FCTRL20 Fault Control 2 Register 0x194 16 read-write 0 0xFFFF NOCOMB No Combinational Path From Fault Input To PWM Output 0 4 read-write NOCOMB_0 There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. 0 NOCOMB_1 The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. 0x1 SPDIF SPDIF SPDIF SPDIF_ 0x401DC000 0 0x54 registers SPDIF 60 SCR SPDIF Configuration Register 0 32 read-write 0x400 0xFFFFFFFF USrc_Sel no description available 0 2 read-write USrc_Sel_0 No embedded U channel 0 USrc_Sel_1 U channel from SPDIF receive block (CD mode) 0x1 USrc_Sel_3 U channel from on chip transmitter 0x3 TxSel no description available 2 3 read-write TxSel_0 Off and output 0 0 TxSel_1 Feed-through SPDIFIN 0x1 TxSel_5 Tx Normal operation 0x5 ValCtrl no description available 5 1 read-write ValCtrl_0 Outgoing Validity always set 0 ValCtrl_1 Outgoing Validity always clear 0x1 DMA_TX_En DMA Transmit Request Enable (Tx FIFO empty) 8 1 read-write DMA_Rx_En DMA Receive Request Enable (RX FIFO full) 9 1 read-write TxFIFO_Ctrl no description available 10 2 read-write TxFIFO_Ctrl_0 Send out digital zero on SPDIF Tx 0 TxFIFO_Ctrl_1 Tx Normal operation 0x1 TxFIFO_Ctrl_2 Reset to 1 sample remaining 0x2 soft_reset When write 1 to this bit, it will cause SPDIF software reset 12 1 read-write LOW_POWER When write 1 to this bit, it will cause SPDIF enter low-power mode 13 1 read-write TxFIFOEmpty_Sel no description available 15 2 read-write TxFIFOEmpty_Sel_0 Empty interrupt if 0 sample in Tx left and right FIFOs 0 TxFIFOEmpty_Sel_1 Empty interrupt if at most 4 sample in Tx left and right FIFOs 0x1 TxFIFOEmpty_Sel_2 Empty interrupt if at most 8 sample in Tx left and right FIFOs 0x2 TxFIFOEmpty_Sel_3 Empty interrupt if at most 12 sample in Tx left and right FIFOs 0x3 TxAutoSync no description available 17 1 read-write TxAutoSync_0 Tx FIFO auto sync off 0 TxAutoSync_1 Tx FIFO auto sync on 0x1 RxAutoSync no description available 18 1 read-write RxAutoSync_0 Rx FIFO auto sync off 0 RxAutoSync_1 RxFIFO auto sync on 0x1 RxFIFOFull_Sel no description available 19 2 read-write RxFIFOFull_Sel_0 Full interrupt if at least 1 sample in Rx left and right FIFOs 0 RxFIFOFull_Sel_1 Full interrupt if at least 4 sample in Rx left and right FIFOs 0x1 RxFIFOFull_Sel_2 Full interrupt if at least 8 sample in Rx left and right FIFOs 0x2 RxFIFOFull_Sel_3 Full interrupt if at least 16 sample in Rx left and right FIFO 0x3 RxFIFO_Rst no description available 21 1 read-write RxFIFO_Rst_0 Normal operation 0 RxFIFO_Rst_1 Reset register to 1 sample remaining 0x1 RxFIFO_Off_On no description available 22 1 read-write RxFIFO_Off_On_0 SPDIF Rx FIFO is on 0 RxFIFO_Off_On_1 SPDIF Rx FIFO is off. Does not accept data from interface 0x1 RxFIFO_Ctrl no description available 23 1 read-write RxFIFO_Ctrl_0 Normal operation 0 RxFIFO_Ctrl_1 Always read zero from Rx data register 0x1 SRCD CDText Control Register 0x4 32 read-write 0 0xFFFFFFFF USyncMode no description available 1 1 read-write USyncMode_0 Non-CD data 0 USyncMode_1 CD user channel subcode 0x1 SRPC PhaseConfig Register 0x8 32 read-write 0 0xFFFFFFFF GainSel Gain selection: 3 3 read-write GainSel_0 24*(2**10) 0 GainSel_1 16*(2**10) 0x1 GainSel_2 12*(2**10) 0x2 GainSel_3 8*(2**10) 0x3 GainSel_4 6*(2**10) 0x4 GainSel_5 4*(2**10) 0x5 GainSel_6 3*(2**10) 0x6 LOCK LOCK bit to show that the internal DPLL is locked, read only 6 1 read-only ClkSrc_Sel Clock source selection, all other settings not shown are reserved: 7 4 read-write ClkSrc_Sel_0 if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) 0 ClkSrc_Sel_1 if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) 0x1 ClkSrc_Sel_3 if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK 0x3 ClkSrc_Sel_5 REF_CLK_32K (XTALOSC) 0x5 ClkSrc_Sel_6 tx_clk (SPDIF0_CLK_ROOT) 0x6 ClkSrc_Sel_8 SPDIF_EXT_CLK 0x8 SIE InterruptEn Register 0xC 32 read-write 0 0xFFFFFFFF RxFIFOFul SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. 0 1 read-write TxEm SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. 1 1 read-write LockLoss SPDIF receiver loss of lock 2 1 read-write RxFIFOResyn Rx FIFO resync 3 1 read-write RxFIFOUnOv Rx FIFO underrun/overrun 4 1 read-write UQErr U/Q Channel framing error 5 1 read-write UQSync U/Q Channel sync found 6 1 read-write QRxOv Q Channel receive register overrun 7 1 read-write QRxFul Q Channel receive register full, can't be cleared with reg 8 1 read-write URxOv U Channel receive register overrun 9 1 read-write URxFul U Channel receive register full, can't be cleared with reg 10 1 read-write BitErr SPDIF receiver found parity bit error 14 1 read-write SymErr SPDIF receiver found illegal symbol 15 1 read-write ValNoGood SPDIF validity flag no good 16 1 read-write CNew SPDIF receive change in value of control channel 17 1 read-write TxResyn SPDIF Tx FIFO resync 18 1 read-write TxUnOv SPDIF Tx FIFO under/overrun 19 1 read-write Lock SPDIF receiver's DPLL is locked 20 1 read-write SIC InterruptClear Register SIC_SIS 0x10 32 read-write 0 0xFFFFFFFF LockLoss SPDIF receiver loss of lock 2 1 write-only RxFIFOResyn Rx FIFO resync 3 1 write-only RxFIFOUnOv Rx FIFO underrun/overrun 4 1 write-only UQErr U/Q Channel framing error 5 1 write-only UQSync U/Q Channel sync found 6 1 write-only QRxOv Q Channel receive register overrun 7 1 write-only URxOv U Channel receive register overrun 9 1 write-only BitErr SPDIF receiver found parity bit error 14 1 write-only SymErr SPDIF receiver found illegal symbol 15 1 write-only ValNoGood SPDIF validity flag no good 16 1 write-only CNew SPDIF receive change in value of control channel 17 1 write-only TxResyn SPDIF Tx FIFO resync 18 1 write-only TxUnOv SPDIF Tx FIFO under/overrun 19 1 write-only Lock SPDIF receiver's DPLL is locked 20 1 write-only SIS InterruptStat Register SIC_SIS 0x10 32 read-only 0x2 0xFFFFFFFF RxFIFOFul SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. 0 1 read-only TxEm SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. 1 1 read-only LockLoss SPDIF receiver loss of lock 2 1 read-only RxFIFOResyn Rx FIFO resync 3 1 read-only RxFIFOUnOv Rx FIFO underrun/overrun 4 1 read-only UQErr U/Q Channel framing error 5 1 read-only UQSync U/Q Channel sync found 6 1 read-only QRxOv Q Channel receive register overrun 7 1 read-only QRxFul Q Channel receive register full, can't be cleared with reg 8 1 read-only URxOv U Channel receive register overrun 9 1 read-only URxFul U Channel receive register full, can't be cleared with reg 10 1 read-only BitErr SPDIF receiver found parity bit error 14 1 read-only SymErr SPDIF receiver found illegal symbol 15 1 read-only ValNoGood SPDIF validity flag no good 16 1 read-only CNew SPDIF receive change in value of control channel 17 1 read-only TxResyn SPDIF Tx FIFO resync 18 1 read-only TxUnOv SPDIF Tx FIFO under/overrun 19 1 read-only Lock SPDIF receiver's DPLL is locked 20 1 read-only SRL SPDIFRxLeft Register 0x14 32 read-only 0 0xFFFFFFFF RxDataLeft Processor receive SPDIF data left 0 24 read-only SRR SPDIFRxRight Register 0x18 32 read-only 0 0xFFFFFFFF RxDataRight Processor receive SPDIF data right 0 24 read-only SRCSH SPDIFRxCChannel_h Register 0x1C 32 read-only 0 0xFFFFFFFF RxCChannel_h SPDIF receive C channel register, contains first 24 bits of C channel without interpretation 0 24 read-only SRCSL SPDIFRxCChannel_l Register 0x20 32 read-only 0 0xFFFFFFFF RxCChannel_l SPDIF receive C channel register, contains next 24 bits of C channel without interpretation 0 24 read-only SRU UchannelRx Register 0x24 32 read-only 0 0xFFFFFFFF RxUChannel SPDIF receive U channel register, contains next 3 U channel bytes 0 24 read-only SRQ QchannelRx Register 0x28 32 read-only 0 0xFFFFFFFF RxQChannel SPDIF receive Q channel register, contains next 3 Q channel bytes 0 24 read-only STL SPDIFTxLeft Register 0x2C 32 read-write 0 0xFFFFFFFF TxDataLeft SPDIF transmit left channel data. It is write-only, and always returns zeros when read 0 24 write-only STR SPDIFTxRight Register 0x30 32 read-write 0 0xFFFFFFFF TxDataRight SPDIF transmit right channel data. It is write-only, and always returns zeros when read 0 24 write-only STCSCH SPDIFTxCChannelCons_h Register 0x34 32 read-write 0 0xFFFFFFFF TxCChannelCons_h SPDIF transmit Cons 0 24 read-write STCSCL SPDIFTxCChannelCons_l Register 0x38 32 read-write 0 0xFFFFFFFF TxCChannelCons_l SPDIF transmit Cons 0 24 read-write SRFM FreqMeas Register 0x44 32 read-only 0 0xFFFFFFFF FreqMeas Frequency measurement data 0 24 read-only STC SPDIFTxClk Register 0x50 32 read-write 0x20F00 0xFFFFFFFF TxClk_DF Divider factor (1-128) 0 7 read-write TxClk_DF_0 divider factor is 1 0 TxClk_DF_1 divider factor is 2 0x1 TxClk_DF_127 divider factor is 128 0x7F tx_all_clk_en Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1. 7 1 read-write tx_all_clk_en_0 disable transfer clock. 0 tx_all_clk_en_1 enable transfer clock. 0x1 TxClk_Source no description available 8 3 read-write TxClk_Source_0 XTALOSC input (XTALOSC clock) 0 TxClk_Source_1 tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) 0x1 TxClk_Source_2 tx_clk1 (from SAI1) 0x2 TxClk_Source_3 tx_clk2 SPDIF_EXT_CLK, from pads 0x3 TxClk_Source_4 tx_clk3 (from SAI2) 0x4 TxClk_Source_5 ipg_clk input (frequency divided) 0x5 TxClk_Source_6 tx_clk4 (from SAI3) 0x6 SYSCLK_DF system clock divider factor, 2~512. 11 9 read-write SYSCLK_DF_0 no clock signal 0 SYSCLK_DF_1 divider factor is 2 0x1 SYSCLK_DF_511 divider factor is 512 0x1FF SAI1 I2S I2S I2S 0x401E0000 0 0xE4 registers SAI1 56 VERID Version ID Register 0 32 read-only 0x3000000 0xFFFFFFFF FEATURE Feature Specification Number 0 16 read-only FEATURE_0 Standard feature set. 0 MINOR Minor Version Number 16 8 read-only MAJOR Major Version Number 24 8 read-only PARAM Parameter Register 0x4 32 read-only 0x50502 0xFFFFFFFF DATALINE Number of Datalines 0 4 read-only FIFO FIFO Size 8 4 read-only FRAME Frame Size 16 4 read-only TCSR SAI Transmit Control Register 0x8 32 read-write 0 0xFFFFFFFF FRDE FIFO Request DMA Enable 0 1 read-write FRDE_0 Disables the DMA request. 0 FRDE_1 Enables the DMA request. 0x1 FWDE FIFO Warning DMA Enable 1 1 read-write FWDE_0 Disables the DMA request. 0 FWDE_1 Enables the DMA request. 0x1 FRIE FIFO Request Interrupt Enable 8 1 read-write FRIE_0 Disables the interrupt. 0 FRIE_1 Enables the interrupt. 0x1 FWIE FIFO Warning Interrupt Enable 9 1 read-write FWIE_0 Disables the interrupt. 0 FWIE_1 Enables the interrupt. 0x1 FEIE FIFO Error Interrupt Enable 10 1 read-write FEIE_0 Disables the interrupt. 0 FEIE_1 Enables the interrupt. 0x1 SEIE Sync Error Interrupt Enable 11 1 read-write SEIE_0 Disables interrupt. 0 SEIE_1 Enables interrupt. 0x1 WSIE Word Start Interrupt Enable 12 1 read-write WSIE_0 Disables interrupt. 0 WSIE_1 Enables interrupt. 0x1 FRF FIFO Request Flag 16 1 read-only FRF_0 Transmit FIFO watermark has not been reached. 0 FRF_1 Transmit FIFO watermark has been reached. 0x1 FWF FIFO Warning Flag 17 1 read-only FWF_0 No enabled transmit FIFO is empty. 0 FWF_1 Enabled transmit FIFO is empty. 0x1 FEF FIFO Error Flag 18 1 read-write oneToClear FEF_0 Transmit underrun not detected. 0 FEF_1 Transmit underrun detected. 0x1 SEF Sync Error Flag 19 1 read-write oneToClear SEF_0 Sync error not detected. 0 SEF_1 Frame sync error detected. 0x1 WSF Word Start Flag 20 1 read-write oneToClear WSF_0 Start of word not detected. 0 WSF_1 Start of word detected. 0x1 SR Software Reset 24 1 read-write SR_0 No effect. 0 SR_1 Software reset. 0x1 FR FIFO Reset 25 1 read-write FR_0 No effect. 0 FR_1 FIFO reset. 0x1 BCE Bit Clock Enable 28 1 read-write BCE_0 Transmit bit clock is disabled. 0 BCE_1 Transmit bit clock is enabled. 0x1 DBGE Debug Enable 29 1 read-write DBGE_0 Transmitter is disabled in Debug mode, after completing the current frame. 0 DBGE_1 Transmitter is enabled in Debug mode. 0x1 STOPE Stop Enable 30 1 read-write STOPE_0 Transmitter disabled in Stop mode. 0 STOPE_1 Transmitter enabled in Stop mode. 0x1 TE Transmitter Enable 31 1 read-write TE_0 Transmitter is disabled. 0 TE_1 Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. 0x1 TCR1 SAI Transmit Configuration 1 Register 0xC 32 read-write 0 0xFFFFFFFF TFW Transmit FIFO Watermark 0 5 read-write TCR2 SAI Transmit Configuration 2 Register 0x10 32 read-write 0 0xFFFFFFFF DIV Bit Clock Divide 0 8 read-write BCD Bit Clock Direction 24 1 read-write BCD_0 Bit clock is generated externally in Slave mode. 0 BCD_1 Bit clock is generated internally in Master mode. 0x1 BCP Bit Clock Polarity 25 1 read-write BCP_0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0 BCP_1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. 0x1 MSEL MCLK Select 26 2 read-write MSEL_0 Bus Clock selected. 0 MSEL_1 Master Clock (MCLK) 1 option selected. 0x1 MSEL_2 Master Clock (MCLK) 2 option selected. 0x2 MSEL_3 Master Clock (MCLK) 3 option selected. 0x3 BCI Bit Clock Input 28 1 read-write BCI_0 No effect. 0 BCI_1 Internal logic is clocked as if bit clock was externally generated. 0x1 BCS Bit Clock Swap 29 1 read-write BCS_0 Use the normal bit clock source. 0 BCS_1 Swap the bit clock source. 0x1 SYNC Synchronous Mode 30 2 read-write SYNC_0 Asynchronous mode. 0 SYNC_1 Synchronous with receiver. 0x1 TCR3 SAI Transmit Configuration 3 Register 0x14 32 read-write 0 0xFFFFFFFF WDFL Word Flag Configuration 0 5 read-write TCE Transmit Channel Enable 16 2 read-write CFR Channel FIFO Reset 24 2 read-write TCR4 SAI Transmit Configuration 4 Register 0x18 32 read-write 0 0xFFFFFFFF FSD Frame Sync Direction 0 1 read-write FSD_0 Frame sync is generated externally in Slave mode. 0 FSD_1 Frame sync is generated internally in Master mode. 0x1 FSP Frame Sync Polarity 1 1 read-write FSP_0 Frame sync is active high. 0 FSP_1 Frame sync is active low. 0x1 ONDEM On Demand Mode 2 1 read-write ONDEM_0 Internal frame sync is generated continuously. 0 ONDEM_1 Internal frame sync is generated when the FIFO warning flag is clear. 0x1 FSE Frame Sync Early 3 1 read-write FSE_0 Frame sync asserts with the first bit of the frame. 0 FSE_1 Frame sync asserts one bit before the first bit of the frame. 0x1 MF MSB First 4 1 read-write MF_0 LSB is transmitted first. 0 MF_1 MSB is transmitted first. 0x1 CHMOD Channel Mode 5 1 read-write CHMOD_0 TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. 0 CHMOD_1 Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. 0x1 SYWD Sync Width 8 5 read-write FRSZ Frame size 16 5 read-write FPACK FIFO Packing Mode 24 2 read-write FPACK_0 FIFO packing is disabled 0 FPACK_2 8-bit FIFO packing is enabled 0x2 FPACK_3 16-bit FIFO packing is enabled 0x3 FCOMB FIFO Combine Mode 26 2 read-write FCOMB_0 FIFO combine mode disabled. 0 FCOMB_1 FIFO combine mode enabled on FIFO reads (from transmit shift registers). 0x1 FCOMB_2 FIFO combine mode enabled on FIFO writes (by software). 0x2 FCOMB_3 FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). 0x3 FCONT FIFO Continue on Error 28 1 read-write FCONT_0 On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0 FCONT_1 On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. 0x1 TCR5 SAI Transmit Configuration 5 Register 0x1C 32 read-write 0 0xFFFFFFFF FBT First Bit Shifted 8 5 read-write W0W Word 0 Width 16 5 read-write WNW Word N Width 24 5 read-write 2 0x4 TDR[%s] SAI Transmit Data Register 0x20 32 read-write 0 0xFFFFFFFF TDR Transmit Data Register 0 32 read-write 2 0x4 TFR[%s] SAI Transmit FIFO Register 0x40 32 read-only 0 0xFFFFFFFF RFP Read FIFO Pointer 0 6 read-only WFP Write FIFO Pointer 16 6 read-only WCP Write Channel Pointer 31 1 read-only WCP_0 No effect. 0 WCP_1 FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. 0x1 TMR SAI Transmit Mask Register 0x60 32 read-write 0 0xFFFFFFFF TWM Transmit Word Mask 0 32 read-write TWM_0 Word N is enabled. 0 TWM_1 Word N is masked. The transmit data pins are tri-stated or drive zero when masked. 0x1 RCSR SAI Receive Control Register 0x88 32 read-write 0 0xFFFFFFFF FRDE FIFO Request DMA Enable 0 1 read-write FRDE_0 Disables the DMA request. 0 FRDE_1 Enables the DMA request. 0x1 FWDE FIFO Warning DMA Enable 1 1 read-write FWDE_0 Disables the DMA request. 0 FWDE_1 Enables the DMA request. 0x1 FRIE FIFO Request Interrupt Enable 8 1 read-write FRIE_0 Disables the interrupt. 0 FRIE_1 Enables the interrupt. 0x1 FWIE FIFO Warning Interrupt Enable 9 1 read-write FWIE_0 Disables the interrupt. 0 FWIE_1 Enables the interrupt. 0x1 FEIE FIFO Error Interrupt Enable 10 1 read-write FEIE_0 Disables the interrupt. 0 FEIE_1 Enables the interrupt. 0x1 SEIE Sync Error Interrupt Enable 11 1 read-write SEIE_0 Disables interrupt. 0 SEIE_1 Enables interrupt. 0x1 WSIE Word Start Interrupt Enable 12 1 read-write WSIE_0 Disables interrupt. 0 WSIE_1 Enables interrupt. 0x1 FRF FIFO Request Flag 16 1 read-only FRF_0 Receive FIFO watermark not reached. 0 FRF_1 Receive FIFO watermark has been reached. 0x1 FWF FIFO Warning Flag 17 1 read-only FWF_0 No enabled receive FIFO is full. 0 FWF_1 Enabled receive FIFO is full. 0x1 FEF FIFO Error Flag 18 1 read-write oneToClear FEF_0 Receive overflow not detected. 0 FEF_1 Receive overflow detected. 0x1 SEF Sync Error Flag 19 1 read-write oneToClear SEF_0 Sync error not detected. 0 SEF_1 Frame sync error detected. 0x1 WSF Word Start Flag 20 1 read-write oneToClear WSF_0 Start of word not detected. 0 WSF_1 Start of word detected. 0x1 SR Software Reset 24 1 read-write SR_0 No effect. 0 SR_1 Software reset. 0x1 FR FIFO Reset 25 1 read-write FR_0 No effect. 0 FR_1 FIFO reset. 0x1 BCE Bit Clock Enable 28 1 read-write BCE_0 Receive bit clock is disabled. 0 BCE_1 Receive bit clock is enabled. 0x1 DBGE Debug Enable 29 1 read-write DBGE_0 Receiver is disabled in Debug mode, after completing the current frame. 0 DBGE_1 Receiver is enabled in Debug mode. 0x1 STOPE Stop Enable 30 1 read-write STOPE_0 Receiver disabled in Stop mode. 0 STOPE_1 Receiver enabled in Stop mode. 0x1 RE Receiver Enable 31 1 read-write RE_0 Receiver is disabled. 0 RE_1 Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. 0x1 RCR1 SAI Receive Configuration 1 Register 0x8C 32 read-write 0 0xFFFFFFFF RFW Receive FIFO Watermark 0 5 read-write RCR2 SAI Receive Configuration 2 Register 0x90 32 read-write 0 0xFFFFFFFF DIV Bit Clock Divide 0 8 read-write BCD Bit Clock Direction 24 1 read-write BCD_0 Bit clock is generated externally in Slave mode. 0 BCD_1 Bit clock is generated internally in Master mode. 0x1 BCP Bit Clock Polarity 25 1 read-write BCP_0 Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0 BCP_1 Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. 0x1 MSEL MCLK Select 26 2 read-write MSEL_0 Bus Clock selected. 0 MSEL_1 Master Clock (MCLK) 1 option selected. 0x1 MSEL_2 Master Clock (MCLK) 2 option selected. 0x2 MSEL_3 Master Clock (MCLK) 3 option selected. 0x3 BCI Bit Clock Input 28 1 read-write BCI_0 No effect. 0 BCI_1 Internal logic is clocked as if bit clock was externally generated. 0x1 BCS Bit Clock Swap 29 1 read-write BCS_0 Use the normal bit clock source. 0 BCS_1 Swap the bit clock source. 0x1 SYNC Synchronous Mode 30 2 read-write SYNC_0 Asynchronous mode. 0 SYNC_1 Synchronous with transmitter. 0x1 RCR3 SAI Receive Configuration 3 Register 0x94 32 read-write 0 0xFFFFFFFF WDFL Word Flag Configuration 0 5 read-write RCE Receive Channel Enable 16 2 read-write CFR Channel FIFO Reset 24 2 read-write RCR4 SAI Receive Configuration 4 Register 0x98 32 read-write 0 0xFFFFFFFF FSD Frame Sync Direction 0 1 read-write FSD_0 Frame Sync is generated externally in Slave mode. 0 FSD_1 Frame Sync is generated internally in Master mode. 0x1 FSP Frame Sync Polarity 1 1 read-write FSP_0 Frame sync is active high. 0 FSP_1 Frame sync is active low. 0x1 ONDEM On Demand Mode 2 1 read-write ONDEM_0 Internal frame sync is generated continuously. 0 ONDEM_1 Internal frame sync is generated when the FIFO warning flag is clear. 0x1 FSE Frame Sync Early 3 1 read-write FSE_0 Frame sync asserts with the first bit of the frame. 0 FSE_1 Frame sync asserts one bit before the first bit of the frame. 0x1 MF MSB First 4 1 read-write MF_0 LSB is received first. 0 MF_1 MSB is received first. 0x1 SYWD Sync Width 8 5 read-write FRSZ Frame Size 16 5 read-write FPACK FIFO Packing Mode 24 2 read-write FPACK_0 FIFO packing is disabled 0 FPACK_2 8-bit FIFO packing is enabled 0x2 FPACK_3 16-bit FIFO packing is enabled 0x3 FCOMB FIFO Combine Mode 26 2 read-write FCOMB_0 FIFO combine mode disabled. 0 FCOMB_1 FIFO combine mode enabled on FIFO writes (from receive shift registers). 0x1 FCOMB_2 FIFO combine mode enabled on FIFO reads (by software). 0x2 FCOMB_3 FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). 0x3 FCONT FIFO Continue on Error 28 1 read-write FCONT_0 On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0 FCONT_1 On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. 0x1 RCR5 SAI Receive Configuration 5 Register 0x9C 32 read-write 0 0xFFFFFFFF FBT First Bit Shifted 8 5 read-write W0W Word 0 Width 16 5 read-write WNW Word N Width 24 5 read-write 2 0x4 RDR[%s] SAI Receive Data Register 0xA0 32 read-only 0 0xFFFFFFFF RDR Receive Data Register 0 32 read-only 2 0x4 RFR[%s] SAI Receive FIFO Register 0xC0 32 read-only 0 0xFFFFFFFF RFP Read FIFO Pointer 0 6 read-only RCP Receive Channel Pointer 15 1 read-only RCP_0 No effect. 0 RCP_1 FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. 0x1 WFP Write FIFO Pointer 16 6 read-only RMR SAI Receive Mask Register 0xE0 32 read-write 0 0xFFFFFFFF RWM Receive Word Mask 0 32 read-write RWM_0 Word N is enabled. 0 RWM_1 Word N is masked. 0x1 SAI3 I2S I2S 0x401E8000 0 0xE4 registers SAI3_RX 58 SAI3_TX 59 GPT1 GPT GPT GPT1_ GPT 0x401EC000 0 0x28 registers GPT1 30 CR GPT Control Register 0 32 read-write 0 0xFFFFFFFF EN GPT Enable 0 1 read-write EN_0 GPT is disabled. 0 EN_1 GPT is enabled. 0x1 ENMOD GPT Enable mode 1 1 read-write ENMOD_0 GPT counter will retain its value when it is disabled. 0 ENMOD_1 GPT counter value is reset to 0 when it is disabled. 0x1 DBGEN GPT debug mode enable 2 1 read-write DBGEN_0 GPT is disabled in debug mode. 0 DBGEN_1 GPT is enabled in debug mode. 0x1 WAITEN GPT Wait Mode enable 3 1 read-write WAITEN_0 GPT is disabled in wait mode. 0 WAITEN_1 GPT is enabled in wait mode. 0x1 DOZEEN GPT Doze Mode Enable 4 1 read-write DOZEEN_0 GPT is disabled in doze mode. 0 DOZEEN_1 GPT is enabled in doze mode. 0x1 STOPEN GPT Stop Mode enable 5 1 read-write STOPEN_0 GPT is disabled in Stop mode. 0 STOPEN_1 GPT is enabled in Stop mode. 0x1 CLKSRC Clock Source select 6 3 read-write CLKSRC_0 No clock 0 CLKSRC_1 Peripheral Clock (ipg_clk) 0x1 CLKSRC_2 High Frequency Reference Clock (ipg_clk_highfreq) 0x2 CLKSRC_3 External Clock 0x3 CLKSRC_4 Low Frequency Reference Clock (ipg_clk_32k) 0x4 CLKSRC_5 Crystal oscillator as Reference Clock (ipg_clk_24M) 0x5 FRR Free-Run or Restart mode 9 1 read-write FRR_0 Restart mode 0 FRR_1 Free-Run mode 0x1 EN_24M Enable 24 MHz clock input from crystal 10 1 read-write EN_24M_0 24M clock disabled 0 EN_24M_1 24M clock enabled 0x1 SWR Software reset 15 1 read-write SWR_0 GPT is not in reset state 0 SWR_1 GPT is in reset state 0x1 IM1 See IM2 16 2 read-write IM2 IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event 18 2 read-write IM2_0 capture disabled 0 IM2_1 capture on rising edge only 0x1 IM2_2 capture on falling edge only 0x2 IM2_3 capture on both edges 0x3 OM1 See OM3 20 3 read-write OM2 See OM3 23 3 read-write OM3 OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode 26 3 read-write OM3_0 Output disconnected. No response on pin. 0 OM3_1 Toggle output pin 0x1 OM3_2 Clear output pin 0x2 OM3_3 Set output pin 0x3 OM3_4 Generate an active low pulse (that is one input clock wide) on the output pin. #1xx FO1 See F03 29 1 read-write FO2 See F03 30 1 read-write FO3 FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register) 31 1 read-write FO3_0 Writing a 0 has no effect. 0 FO3_1 Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. 0x1 PR GPT Prescaler Register 0x4 32 read-write 0 0xFFFFFFFF PRESCALER Prescaler bits 0 12 read-write PRESCALER_0 Divide by 1 0 PRESCALER_1 Divide by 2 0x1 PRESCALER_4095 Divide by 4096 0xFFF PRESCALER24M Prescaler bits 12 4 read-write PRESCALER24M_0 Divide by 1 0 PRESCALER24M_1 Divide by 2 0x1 PRESCALER24M_15 Divide by 16 0xF SR GPT Status Register 0x8 32 read-write 0 0xFFFFFFFF OF1 See OF3 0 1 read-write oneToClear OF2 See OF3 1 1 read-write oneToClear OF3 OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n 2 1 read-write oneToClear OF3_0 Compare event has not occurred. 0 OF3_1 Compare event has occurred. 0x1 IF1 See IF2 3 1 read-write oneToClear IF2 IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n 4 1 read-write oneToClear IF2_0 Capture event has not occurred. 0 IF2_1 Capture event has occurred. 0x1 ROV Rollover Flag 5 1 read-write oneToClear ROV_0 Rollover has not occurred. 0 ROV_1 Rollover has occurred. 0x1 IR GPT Interrupt Register 0xC 32 read-write 0 0xFFFFFFFF OF1IE See OF3IE 0 1 read-write OF2IE See OF3IE 1 1 read-write OF3IE OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt 2 1 read-write OF3IE_0 Output Compare Channel n interrupt is disabled. 0 OF3IE_1 Output Compare Channel n interrupt is enabled. 0x1 IF1IE See IF2IE 3 1 read-write IF2IE IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable 4 1 read-write IF2IE_0 IF2IE Input Capture n Interrupt Enable is disabled. 0 IF2IE_1 IF2IE Input Capture n Interrupt Enable is enabled. 0x1 ROVIE Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt. 5 1 read-write ROVIE_0 Rollover interrupt is disabled. 0 ROVIE_1 Rollover interrupt enabled. 0x1 OCR1 GPT Output Compare Register 1 0x10 32 read-write 0xFFFFFFFF 0xFFFFFFFF COMP Compare Value 0 32 read-write OCR2 GPT Output Compare Register 2 0x14 32 read-write 0xFFFFFFFF 0xFFFFFFFF COMP Compare Value 0 32 read-write OCR3 GPT Output Compare Register 3 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF COMP Compare Value 0 32 read-write ICR1 GPT Input Capture Register 1 0x1C 32 read-only 0 0xFFFFFFFF CAPT Capture Value 0 32 read-only ICR2 GPT Input Capture Register 2 0x20 32 read-only 0 0xFFFFFFFF CAPT Capture Value 0 32 read-only CNT GPT Counter Register 0x24 32 read-only 0 0xFFFFFFFF COUNT Counter Value. The COUNT bits show the current count value of the GPT counter. 0 32 read-only GPT2 GPT GPT GPT2_ 0x401F0000 0 0x28 registers GPT2 31 OCOTP no description available OCOTP 0x401F4000 0 0x6F4 registers HW_OCOTP_CTRL OTP Controller Control Register 0 32 read-write 0 0xFFFFFFFF ADDR OTP write and read access address register 0 6 read-write BUSY OTP controller status bit 8 1 read-only ERROR Set by the controller when an access to a locked region(OTP or shadow register) is requested 9 1 read-write RELOAD_SHADOWS Set to force re-loading the shadow registers (HW/SW capability and LOCK) 10 1 read-write WR_UNLOCK Write 0x3E77 to enable OTP write accesses 16 16 read-write HW_OCOTP_CTRL_SET OTP Controller Control Register 0x4 32 read-write 0 0xFFFFFFFF ADDR OTP write and read access address register 0 6 read-write oneToSet BUSY OTP controller status bit 8 1 read-only oneToSet ERROR Set by the controller when an access to a locked region(OTP or shadow register) is requested 9 1 read-write oneToSet RELOAD_SHADOWS Set to force re-loading the shadow registers (HW/SW capability and LOCK) 10 1 read-write oneToSet WR_UNLOCK Write 0x3E77 to enable OTP write accesses 16 16 read-write oneToSet HW_OCOTP_CTRL_CLR OTP Controller Control Register 0x8 32 read-write 0 0xFFFFFFFF ADDR OTP write and read access address register 0 6 read-write oneToClear BUSY OTP controller status bit 8 1 read-only oneToClear ERROR Set by the controller when an access to a locked region(OTP or shadow register) is requested 9 1 read-write oneToClear RELOAD_SHADOWS Set to force re-loading the shadow registers (HW/SW capability and LOCK) 10 1 read-write oneToClear WR_UNLOCK Write 0x3E77 to enable OTP write accesses 16 16 read-write oneToClear HW_OCOTP_CTRL_TOG OTP Controller Control Register 0xC 32 read-write 0 0xFFFFFFFF ADDR OTP write and read access address register 0 6 read-write oneToToggle BUSY OTP controller status bit 8 1 read-only oneToToggle ERROR Set by the controller when an access to a locked region(OTP or shadow register) is requested 9 1 read-write oneToToggle RELOAD_SHADOWS Set to force re-loading the shadow registers (HW/SW capability and LOCK) 10 1 read-write oneToToggle WR_UNLOCK Write 0x3E77 to enable OTP write accesses 16 16 read-write oneToToggle HW_OCOTP_TIMING OTP Controller Timing Register 0x10 32 read-write 0x60D9755 0xFFFFFFFF STROBE_PROG This count value specifies the strobe period in one time write OTP 0 12 read-write RELAX This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd 12 4 read-write STROBE_READ This count value specifies the strobe period in one time read OTP 16 6 read-write WAIT This count value specifies time interval between auto read and write access in one time program 22 6 read-write HW_OCOTP_DATA OTP Controller Write Data Register 0x20 32 read-write 0 0xFFFFFFFF DATA Used to initiate a write to OTP 0 32 read-write HW_OCOTP_READ_CTRL OTP Controller Write Data Register 0x30 32 read-write 0 0xFFFFFFFF READ_FUSE Used to initiate a read to OTP 0 1 read-write HW_OCOTP_READ_FUSE_DATA OTP Controller Read Data Register 0x40 32 read-write 0 0xFFFFFFFF DATA The data read from OTP 0 32 read-write HW_OCOTP_SW_STICKY Sticky bit Register 0x50 32 read-write 0 0xFFFFFFFF SRK_REVOKE_LOCK Shadow register write and OTP write lock for SRK_REVOKE region 1 1 read-write FIELD_RETURN_LOCK Shadow register write and OTP write lock for FIELD_RETURN region 2 1 read-write HW_OCOTP_SCS Software Controllable Signals Register 0x60 32 read-write 0 0xFFFFFFFF HAB_JDE HAB JTAG Debug Enable 0 1 read-write SPARE Unallocated read/write bits for implementation specific software use. 1 30 read-write LOCK When set, all of the bits in this register are locked and can not be changed through SW programming 31 1 read-write HW_OCOTP_SCS_SET Software Controllable Signals Register 0x64 32 read-write 0 0xFFFFFFFF HAB_JDE HAB JTAG Debug Enable 0 1 read-write oneToSet SPARE Unallocated read/write bits for implementation specific software use. 1 30 read-write oneToSet LOCK When set, all of the bits in this register are locked and can not be changed through SW programming 31 1 read-write oneToSet HW_OCOTP_SCS_CLR Software Controllable Signals Register 0x68 32 read-write 0 0xFFFFFFFF HAB_JDE HAB JTAG Debug Enable 0 1 read-write oneToClear SPARE Unallocated read/write bits for implementation specific software use. 1 30 read-write oneToClear LOCK When set, all of the bits in this register are locked and can not be changed through SW programming 31 1 read-write oneToClear HW_OCOTP_SCS_TOG Software Controllable Signals Register 0x6C 32 read-write 0 0xFFFFFFFF HAB_JDE HAB JTAG Debug Enable 0 1 read-write oneToToggle SPARE Unallocated read/write bits for implementation specific software use. 1 30 read-write oneToToggle LOCK When set, all of the bits in this register are locked and can not be changed through SW programming 31 1 read-write oneToToggle HW_OCOTP_VERSION OTP Controller Version Register 0x90 32 read-only 0x6000000 0xFFFFFFFF STEP Fixed read-only value reflecting the stepping of the RTL version. 0 16 read-only MINOR Fixed read-only value reflecting the MINOR field of the RTL version. 16 8 read-only MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 24 8 read-only HW_OCOTP_TIMING2 OTP Controller Timing Register 2 0x100 32 read-write 0x1C30092 0xFFFFFFFF RELAX_PROG This count value specifies the strobe period in one time write OTP 0 12 read-write RELAX_READ This count value specifies the strobe period in one time read OTP 16 6 read-write RELAX1 This count value specifies time interval between auto read and write access in one time program 22 8 read-write HW_OCOTP_LOCK Value of OTP Bank0 Word0 (Lock controls) 0x400 32 read-write 0 0xFFFFFFFF TESTER Status of shadow register and OTP write lock for tester region 0 2 read-only BOOT_CFG Status of shadow register and OTP write lock for boot_cfg region 2 2 read-only MEM_TRIM Status of shadow register and OTP write lock for mem_trim region 4 2 read-only SJC_RESP Status of shadow register read and write, OTP read and write lock for sjc_resp region 6 1 read-only MAC_ADDR Status of shadow register and OTP write lock for mac_addr region 8 2 read-only GP1 Status of shadow register and OTP write lock for gp1 region 10 2 read-only GP2 Status of shadow register and OTP write lock for gp2 region 12 2 read-only OTPMK_MSB Status of shadow register read and write, OTP read and write lock for otpmk region (MSB) 15 1 read-only SW_GP1 Status of shadow register and OTP write lock for sw_gp1 region 16 1 read-only OTPMK_LSB Status of shadow register read and write, OTP read and write lock for otpmk region (LSB) 17 1 read-only ANALOG Status of shadow register and OTP write lock for analog region 18 2 read-only OTPMK_CRC Status of shadow register and OTP write lock for otpmk_crc region 20 1 read-only SW_GP2_LOCK Status of shadow register and OTP write lock for sw_gp2 region 21 1 read-only MISC_CONF Status of shadow register and OTP write lock for misc_conf region 22 1 read-only SW_GP2_RLOCK Status of shadow register and OTP read lock for sw_gp2 region 23 1 read-only GP3 Status of shadow register and OTP write lock for gp3 region 26 2 read-only FIELD_RETURN Reserved 28 4 read-write HW_OCOTP_CFG0 Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) 0x410 32 read-write 0 0xFFFFFFFF BITS This register contains 32 bits of the Unique ID and SJC_CHALLENGE field 0 32 read-write HW_OCOTP_CFG1 Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) 0x420 32 read-write 0 0xFFFFFFFF BITS This register contains 32 bits of the Unique ID and SJC_CHALLENGE field 0 32 read-write HW_OCOTP_CFG2 Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) 0x430 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 0, word 3 (ADDR = 0x03) 0 32 read-write HW_OCOTP_CFG3 Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) 0x440 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 0, word 4 (ADDR = 0x04) 0 32 read-write HW_OCOTP_CFG4 Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) 0x450 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 0, word 5 (ADDR = 0x05) 0 32 read-write HW_OCOTP_CFG5 Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) 0x460 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 0, word 6 (ADDR = 0x06) 0 32 read-write HW_OCOTP_CFG6 Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) 0x470 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 0, word 7 (ADDR = 0x07) 0 32 read-write HW_OCOTP_MEM0 Value of OTP Bank1 Word0 (Memory Related Info.) 0x480 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP bank 1, word 0 (ADDR = 0x08) 0 32 read-write HW_OCOTP_MEM1 Value of OTP Bank1 Word1 (Memory Related Info.) 0x490 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP bank 1, word 1 (ADDR = 0x09) 0 32 read-write HW_OCOTP_MEM2 Value of OTP Bank1 Word2 (Memory Related Info.) 0x4A0 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP bank 1, word 2 (ADDR = 0x0A) 0 32 read-write HW_OCOTP_MEM3 Value of OTP Bank1 Word3 (Memory Related Info.) 0x4B0 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP bank 1, word 3 (ADDR = 0x0B) 0 32 read-write HW_OCOTP_MEM4 Value of OTP Bank1 Word4 (Memory Related Info.) 0x4C0 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP bank 1, word 4 (ADDR = 0x0C) 0 32 read-write HW_OCOTP_ANA0 Value of OTP Bank1 Word5 (Analog Info.) 0x4D0 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP bank 1, word 5 (ADDR = 0x0D) 0 32 read-write HW_OCOTP_ANA1 Value of OTP Bank1 Word6 (Analog Info.) 0x4E0 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP bank 1, word 6 (ADDR = 0x0E) 0 32 read-write HW_OCOTP_ANA2 Value of OTP Bank1 Word7 (Analog Info.) 0x4F0 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP bank 1, word 7 (ADDR = 0x0F) 0 32 read-write HW_OCOTP_SRK0 Shadow Register for OTP Bank3 Word0 (SRK Hash) 0x580 32 read-write 0 0xFFFFFFFF BITS Shadow register for the hash of the Super Root Key word0 (Copy of OTP Bank 3, word 0 (ADDR = 0x1C)) 0 32 read-write HW_OCOTP_SRK1 Shadow Register for OTP Bank3 Word1 (SRK Hash) 0x590 32 read-write 0 0xFFFFFFFF BITS Shadow register for the hash of the Super Root Key word1 (Copy of OTP Bank 3, word 1 (ADDR = 0x1D)) 0 32 read-write HW_OCOTP_SRK2 Shadow Register for OTP Bank3 Word2 (SRK Hash) 0x5A0 32 read-write 0 0xFFFFFFFF BITS Shadow register for the hash of the Super Root Key word2 (Copy of OTP Bank 3, word 2 (ADDR = 0x1E)) 0 32 read-write HW_OCOTP_SRK3 Shadow Register for OTP Bank3 Word3 (SRK Hash) 0x5B0 32 read-write 0 0xFFFFFFFF BITS Shadow register for the hash of the Super Root Key word3 (Copy of OTP Bank 3, word 3 (ADDR = 0x1F)) 0 32 read-write HW_OCOTP_SRK4 Shadow Register for OTP Bank3 Word4 (SRK Hash) 0x5C0 32 read-write 0 0xFFFFFFFF BITS Shadow register for the hash of the Super Root Key word4 (Copy of OTP Bank 3, word 4 (ADDR = 0x20)) 0 32 read-write HW_OCOTP_SRK5 Shadow Register for OTP Bank3 Word5 (SRK Hash) 0x5D0 32 read-write 0 0xFFFFFFFF BITS Shadow register for the hash of the Super Root Key word5 (Copy of OTP Bank 3, word 5 (ADDR = 0x21)) 0 32 read-write HW_OCOTP_SRK6 Shadow Register for OTP Bank3 Word6 (SRK Hash) 0x5E0 32 read-write 0 0xFFFFFFFF BITS Shadow register for the hash of the Super Root Key word6 (Copy of OTP Bank 3, word 6 (ADDR = 0x22)) 0 32 read-write HW_OCOTP_SRK7 Shadow Register for OTP Bank3 Word7 (SRK Hash) 0x5F0 32 read-write 0 0xFFFFFFFF BITS Shadow register for the hash of the Super Root Key word7 (Copy of OTP Bank 3, word 7 (ADDR = 0x23)) 0 32 read-write HW_OCOTP_SJC_RESP0 Value of OTP Bank4 Word0 (Secure JTAG Response Field) 0x600 32 read-write 0 0xFFFFFFFF BITS Shadow register for the SJC_RESP Key word0 (Copy of OTP Bank 4, word 0 (ADDR = 0x20)) 0 32 read-write HW_OCOTP_SJC_RESP1 Value of OTP Bank4 Word1 (Secure JTAG Response Field) 0x610 32 read-write 0 0xFFFFFFFF BITS Shadow register for the SJC_RESP Key word1 (Copy of OTP Bank 4, word 1 (ADDR = 0x21)) 0 32 read-write HW_OCOTP_MAC0 Value of OTP Bank4 Word2 (MAC Address) 0x620 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 4, word 2 (ADDR = 0x22). 0 32 read-write HW_OCOTP_MAC1 Value of OTP Bank4 Word3 (MAC Address) 0x630 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 4, word 3 (ADDR = 0x23). 0 32 read-write HW_OCOTP_GP3 Value of OTP Bank4 Word4 (MAC Address) 0x640 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 4, word 4 (ADDR = 0x24). 0 32 read-write HW_OCOTP_GP1 Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) 0x660 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 4, word 6 (ADDR = 0x26). 0 32 read-write HW_OCOTP_GP2 Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) 0x670 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 4, word 7 (ADDR = 0x27). 0 32 read-write HW_OCOTP_SW_GP1 Value of OTP Bank5 Word0 (SW GP1) 0x680 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 5, word 0 (ADDR = 0x28). 0 32 read-write HW_OCOTP_SW_GP20 Value of OTP Bank5 Word1 (SW GP2) 0x690 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 5, word 1 (ADDR = 0x29). 0 32 read-write HW_OCOTP_SW_GP21 Value of OTP Bank5 Word2 (SW GP2) 0x6A0 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 5, word 2 (ADDR = 0x2a). 0 32 read-write HW_OCOTP_SW_GP22 Value of OTP Bank5 Word3 (SW GP2) 0x6B0 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 5, word 3 (ADDR = 0x2b). 0 32 read-write HW_OCOTP_SW_GP23 Value of OTP Bank5 Word4 (SW GP2) 0x6C0 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 5, word 4 (ADDR = 0x2c). 0 32 read-write HW_OCOTP_MISC_CONF0 Value of OTP Bank5 Word5 (Misc Conf) 0x6D0 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 5, word 5 (ADDR = 0x2d). 0 32 read-write HW_OCOTP_MISC_CONF1 Value of OTP Bank5 Word6 (Misc Conf) 0x6E0 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 5, word 6 (ADDR = 0x2e). 0 32 read-write HW_OCOTP_SRK_REVOKE Value of OTP Bank5 Word7 (SRK Revoke) 0x6F0 32 read-write 0 0xFFFFFFFF BITS Reflects value of OTP Bank 5, word 7 (ADDR = 0x2f). 0 32 read-write IOMUXC IOMUXC IOMUXC IOMUXC_ 0x401F8000 0 0x224 registers SW_MUX_CTL_PAD_GPIO_AD_14 SW_MUX_CTL_PAD_GPIO_AD_14 SW MUX Control Register 0x10 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPI2C1_SCL of instance: LPI2C1 0 ALT1 Select mux mode: ALT1 mux port: LPUART3_CTS_B of instance: LPUART3 0x1 ALT2 Select mux mode: ALT2 mux port: KPP_COL00 of instance: KPP 0x2 ALT3 Select mux mode: ALT3 mux port: LPUART4_CTS_B of instance: LPUART4 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO26 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO28 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: REF_CLK_24M of instance: XTAL OSC 0x6 ALT7 Select mux mode: ALT7 mux port: XBAR1_INOUT02 of instance: XBAR1 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_14 0x1 SW_MUX_CTL_PAD_GPIO_AD_13 SW_MUX_CTL_PAD_GPIO_AD_13 SW MUX Control Register 0x14 32 read-write 0x7 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPI2C1_SDA of instance: LPI2C1 0 ALT1 Select mux mode: ALT1 mux port: LPUART3_RTS_B of instance: LPUART3 0x1 ALT2 Select mux mode: ALT2 mux port: KPP_ROW00 of instance: KPP 0x2 ALT3 Select mux mode: ALT3 mux port: LPUART4_RTS_B of instance: LPUART4 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO25 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO27 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: NMI_GLUE_NMI of instance: NMI_GLUE 0x6 ALT7 Select mux mode: ALT7 mux port: JTAG_TMS of instance: JTAG 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_13 0x1 SW_MUX_CTL_PAD_GPIO_AD_12 SW_MUX_CTL_PAD_GPIO_AD_12 SW MUX Control Register 0x18 32 read-write 0x7 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPSPI2_SCK of instance: LPSPI2 0 ALT1 Select mux mode: ALT1 mux port: FLEXPWM1_PWM0_X of instance: FLEXPWM1 0x1 ALT2 Select mux mode: ALT2 mux port: KPP_COL01 of instance: KPP 0x2 ALT3 Select mux mode: ALT3 mux port: PIT_TRIGGER01 of instance: PIT 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO24 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO26 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: USB_OTG1_PWR of instance: USB 0x6 ALT7 Select mux mode: ALT7 mux port: JTAG_TCK of instance: JTAG 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_12 0x1 SW_MUX_CTL_PAD_GPIO_AD_11 SW_MUX_CTL_PAD_GPIO_AD_11 SW MUX Control Register 0x1C 32 read-write 0x7 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPSPI2_PCS0 of instance: LPSPI2 0 ALT1 Select mux mode: ALT1 mux port: FLEXPWM1_PWM1_X of instance: FLEXPWM1 0x1 ALT2 Select mux mode: ALT2 mux port: KPP_ROW01 of instance: KPP 0x2 ALT3 Select mux mode: ALT3 mux port: PIT_TRIGGER02 of instance: PIT 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO23 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO25 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: WDOG1_B of instance: WDOG1 0x6 ALT7 Select mux mode: ALT7 mux port: JTAG_MOD of instance: JTAG 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_11 0x1 SW_MUX_CTL_PAD_GPIO_AD_10 SW_MUX_CTL_PAD_GPIO_AD_10 SW MUX Control Register 0x20 32 read-write 0x7 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPSPI2_SDO of instance: LPSPI2 0 ALT1 Select mux mode: ALT1 mux port: FLEXPWM1_PWM2_X of instance: FLEXPWM1 0x1 ALT2 Select mux mode: ALT2 mux port: KPP_COL02 of instance: KPP 0x2 ALT3 Select mux mode: ALT3 mux port: PIT_TRIGGER03 of instance: PIT 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO22 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO24 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: OTG1_ID of instance: anatop 0x6 ALT7 Select mux mode: ALT7 mux port: JTAG_TDI of instance: JTAG 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_10 0x1 SW_MUX_CTL_PAD_GPIO_AD_09 SW_MUX_CTL_PAD_GPIO_AD_09 SW MUX Control Register 0x24 32 read-write 0x7 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPSPI2_SDI of instance: LPSPI2 0 ALT1 Select mux mode: ALT1 mux port: FLEXPWM1_PWM3_X of instance: FLEXPWM1 0x1 ALT2 Select mux mode: ALT2 mux port: KPP_ROW02 of instance: KPP 0x2 ALT3 Select mux mode: ALT3 mux port: ARM_TRACE_SWO of instance: cm7_mxrt 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO21 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO23 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: REF_32K_OUT of instance: anatop 0x6 ALT7 Select mux mode: ALT7 mux port: JTAG_TDO of instance: JTAG 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_09 0x1 SW_MUX_CTL_PAD_GPIO_AD_08 SW_MUX_CTL_PAD_GPIO_AD_08 SW MUX Control Register 0x28 32 read-write 0x7 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPI2C2_SCL of instance: LPI2C2 0 ALT1 Select mux mode: ALT1 mux port: LPUART3_TXD of instance: LPUART3 0x1 ALT2 Select mux mode: ALT2 mux port: ARM_CM7_TXEV of instance: cm7_mxrt 0x2 ALT3 Select mux mode: ALT3 mux port: LPUART2_CTS_B of instance: LPUART2 0x3 ALT4 Select mux mode: ALT4 mux port: GPT2_COMPARE3 of instance: GPT2 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO22 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: EWM_OUT_B of instance: EWM 0x6 ALT7 Select mux mode: ALT7 mux port: JTAG_TRSTB of instance: JTAG 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_08 0x1 SW_MUX_CTL_PAD_GPIO_AD_07 SW_MUX_CTL_PAD_GPIO_AD_07 SW MUX Control Register 0x2C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPI2C2_SDA of instance: LPI2C2 0 ALT1 Select mux mode: ALT1 mux port: LPUART3_RXD of instance: LPUART3 0x1 ALT2 Select mux mode: ALT2 mux port: ARM_CM7_RXEV of instance: cm7_mxrt 0x2 ALT3 Select mux mode: ALT3 mux port: LPUART2_RTS_B of instance: LPUART2 0x3 ALT4 Select mux mode: ALT4 mux port: GPT2_CAPTURE2 of instance: GPT2 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO21 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: OCOTP_FUSE_LATCHED of instance: OCOTP 0x6 ALT7 Select mux mode: ALT7 mux port: XBAR1_INOUT03 of instance: XBAR1 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_07 0x1 SW_MUX_CTL_PAD_GPIO_AD_06 SW_MUX_CTL_PAD_GPIO_AD_06 SW MUX Control Register 0x30 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPSPI1_SCK of instance: LPSPI1 0 ALT1 Select mux mode: ALT1 mux port: PIT_TRIGGER00 of instance: PIT 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_A of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: KPP_COL01 of instance: KPP 0x3 ALT4 Select mux mode: ALT4 mux port: GPT2_COMPARE2 of instance: GPT2 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO20 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: LPI2C1_HREQ of instance: LPI2C1 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_06 0x1 SW_MUX_CTL_PAD_GPIO_AD_05 SW_MUX_CTL_PAD_GPIO_AD_05 SW MUX Control Register 0x34 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPSPI1_PCS0 of instance: LPSPI1 0 ALT1 Select mux mode: ALT1 mux port: PIT_TRIGGER01 of instance: PIT 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_B of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: KPP_ROW01 of instance: KPP 0x3 ALT4 Select mux mode: ALT4 mux port: GPT2_CAPTURE1 of instance: GPT2 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO19 of instance: GPIOMUX 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_05 0x1 SW_MUX_CTL_PAD_GPIO_AD_04 SW_MUX_CTL_PAD_GPIO_AD_04 SW MUX Control Register 0x38 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPSPI1_SDO of instance: LPSPI1 0 ALT1 Select mux mode: ALT1 mux port: PIT_TRIGGER02 of instance: PIT 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM2_A of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: KPP_COL02 of instance: KPP 0x3 ALT4 Select mux mode: ALT4 mux port: GPT2_COMPARE1 of instance: GPT2 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO18 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: SNVS_HP_VIO_5_CTL of instance: snvs_hp 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_04 0x1 SW_MUX_CTL_PAD_GPIO_AD_03 SW_MUX_CTL_PAD_GPIO_AD_03 SW MUX Control Register 0x3C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPSPI1_SDI of instance: LPSPI1 0 ALT1 Select mux mode: ALT1 mux port: PIT_TRIGGER03 of instance: PIT 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM2_B of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: KPP_ROW02 of instance: KPP 0x3 ALT4 Select mux mode: ALT4 mux port: GPT2_CLK of instance: GPT2 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO17 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: SNVS_HP_VIO_5_B of instance: snvs_hp 0x6 ALT7 Select mux mode: ALT7 mux port: JTAG_DE_B of instance: JTAG 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_03 0x1 SW_MUX_CTL_PAD_GPIO_AD_02 SW_MUX_CTL_PAD_GPIO_AD_02 SW MUX Control Register 0x40 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPUART4_TXD of instance: LPUART4 0 ALT1 Select mux mode: ALT1 mux port: LPSPI1_PCS1 of instance: LPSPI1 0x1 ALT2 Select mux mode: ALT2 mux port: WDOG2_B of instance: WDOG2 0x2 ALT3 Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: LPI2C2 0x3 ALT4 Select mux mode: ALT4 mux port: MQS_RIGHT of instance: MQS 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO16 of instance: GPIOMUX 0x5 ALT7 Select mux mode: ALT7 mux port: ARM_CM7_TRACE_CLK of instance: cm7_mxrt 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_02 0x1 SW_MUX_CTL_PAD_GPIO_AD_01 SW_MUX_CTL_PAD_GPIO_AD_01 SW MUX Control Register 0x44 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPUART4_RXD of instance: LPUART4 0 ALT1 Select mux mode: ALT1 mux port: LPSPI2_PCS1 of instance: LPSPI2 0x1 ALT2 Select mux mode: ALT2 mux port: WDOG1_ANY of instance: WDOG1 0x2 ALT3 Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: LPI2C2 0x3 ALT4 Select mux mode: ALT4 mux port: MQS_LEFT of instance: MQS 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO15 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: USB_OTG1_OC of instance: USB 0x6 ALT7 Select mux mode: ALT7 mux port: ARM_CM7_TRACE_SWO of instance: cm7_mxrt 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_01 0x1 SW_MUX_CTL_PAD_GPIO_AD_00 SW_MUX_CTL_PAD_GPIO_AD_00 SW MUX Control Register 0x48 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPUART2_TXD of instance: LPUART2 0 ALT1 Select mux mode: ALT1 mux port: LPSPI1_PCS2 of instance: LPSPI1 0x1 ALT2 Select mux mode: ALT2 mux port: KPP_COL03 of instance: KPP 0x2 ALT3 Select mux mode: ALT3 mux port: USB_OTG1_PWR of instance: USB 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO20 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO14 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: NMI_GLUE_NMI of instance: NMI_GLUE 0x6 ALT7 Select mux mode: ALT7 mux port: ARM_CM7_TRACE00 of instance: cm7_mxrt 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_AD_00 0x1 SW_MUX_CTL_PAD_GPIO_SD_14 SW_MUX_CTL_PAD_GPIO_SD_14 SW MUX Control Register 0x4C 32 read-write 0 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 1 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_A_DQS of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: FLEXSPI_B_DQS of instance: FLEXSPI 0x1 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_14 0x1 SW_MUX_CTL_PAD_GPIO_SD_13 SW_MUX_CTL_PAD_GPIO_SD_13 SW MUX Control Register 0x50 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_B_SCLK of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: SAI3_RX_BCLK of instance: SAI3 0x1 ALT2 Select mux mode: ALT2 mux port: ARM_CM7_TXEV of instance: cm7_mxrt 0x2 ALT3 Select mux mode: ALT3 mux port: CCM_PMIC_RDY of instance: CCM 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO19 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO13 of instance: GPIO2 0x5 ALT6 Select mux mode: ALT6 mux port: SRC_BT_CFG03 of instance: SRC 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_13 0x1 SW_MUX_CTL_PAD_GPIO_SD_12 SW_MUX_CTL_PAD_GPIO_SD_12 SW MUX Control Register 0x54 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_A_DQS of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: LPSPI2_PCS0 of instance: LPSPI2 0x1 ALT2 Select mux mode: ALT2 mux port: LPUART1_TXD of instance: LPUART1 0x2 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO18 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO12 of instance: GPIO2 0x5 ALT6 Select mux mode: ALT6 mux port: WDOG2_RST_B_DEB of instance: WDOG2 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_12 0x1 SW_MUX_CTL_PAD_GPIO_SD_11 SW_MUX_CTL_PAD_GPIO_SD_11 SW MUX Control Register 0x58 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_A_DATA3 of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: LPSPI2_SCK of instance: LPSPI2 0x1 ALT2 Select mux mode: ALT2 mux port: LPUART1_RXD of instance: LPUART1 0x2 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO17 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO11 of instance: GPIO2 0x5 ALT6 Select mux mode: ALT6 mux port: WDOG1_RST_B_DEB of instance: WDOG1 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_11 0x1 SW_MUX_CTL_PAD_GPIO_SD_10 SW_MUX_CTL_PAD_GPIO_SD_10 SW MUX Control Register 0x5C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_A_SCLK of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: LPSPI2_SDO of instance: LPSPI2 0x1 ALT2 Select mux mode: ALT2 mux port: LPUART2_TXD of instance: LPUART2 0x2 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO16 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO10 of instance: GPIO2 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_10 0x1 SW_MUX_CTL_PAD_GPIO_SD_09 SW_MUX_CTL_PAD_GPIO_SD_09 SW MUX Control Register 0x60 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_A_DATA0 of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: LPSPI2_SDI of instance: LPSPI2 0x1 ALT2 Select mux mode: ALT2 mux port: LPUART2_RXD of instance: LPUART2 0x2 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO15 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: GPIO2 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_09 0x1 SW_MUX_CTL_PAD_GPIO_SD_08 SW_MUX_CTL_PAD_GPIO_SD_08 SW MUX Control Register 0x64 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_A_DATA2 of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: LPI2C2_SCL of instance: LPI2C2 0x1 ALT2 Select mux mode: ALT2 mux port: LPSPI1_SCK of instance: LPSPI1 0x2 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO14 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: GPIO2 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_08 0x1 SW_MUX_CTL_PAD_GPIO_SD_07 SW_MUX_CTL_PAD_GPIO_SD_07 SW MUX Control Register 0x68 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_A_DATA1 of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: LPI2C2_SDA of instance: LPI2C2 0x1 ALT2 Select mux mode: ALT2 mux port: LPSPI1_PCS0 of instance: LPSPI1 0x2 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO13 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: GPIO2 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_07 0x1 SW_MUX_CTL_PAD_GPIO_SD_06 SW_MUX_CTL_PAD_GPIO_SD_06 SW MUX Control Register 0x6C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_A_SS0_B of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: LPI2C1_SCL of instance: LPI2C1 0x1 ALT2 Select mux mode: ALT2 mux port: LPSPI1_SDO of instance: LPSPI1 0x2 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO12 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: GPIO2 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_06 0x1 SW_MUX_CTL_PAD_GPIO_SD_05 SW_MUX_CTL_PAD_GPIO_SD_05 SW MUX Control Register 0x70 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_A_SS1_B of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: LPI2C1_SDA of instance: LPI2C1 0x1 ALT2 Select mux mode: ALT2 mux port: LPSPI1_SDI of instance: LPSPI1 0x2 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO11 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: GPIO2 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_05 0x1 SW_MUX_CTL_PAD_GPIO_SD_04 SW_MUX_CTL_PAD_GPIO_SD_04 SW MUX Control Register 0x74 32 read-write 0x6 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_B_DATA03 of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: SAI3_RX_SYNC of instance: SAI3 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_A of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: CCM_WAIT of instance: CCM 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO10 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: GPIO2 0x5 ALT6 Select mux mode: ALT6 mux port: SRC_BOOT_MODE00 of instance: SRC 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_04 0x1 SW_MUX_CTL_PAD_GPIO_SD_03 SW_MUX_CTL_PAD_GPIO_SD_03 SW MUX Control Register 0x78 32 read-write 0x6 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_B_DATA00 of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: SAI3_RX_DATA of instance: SAI3 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_B of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: CCM_REF_EN_B of instance: CCM 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO09 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO03 of instance: GPIO2 0x5 ALT6 Select mux mode: ALT6 mux port: SRC_BOOT_MODE01 of instance: SRC 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_03 0x1 SW_MUX_CTL_PAD_GPIO_SD_02 SW_MUX_CTL_PAD_GPIO_SD_02 SW MUX Control Register 0x7C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_B_DATA02 of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: SAI3_TX_DATA of instance: SAI3 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM0_A of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: CCM_CLKO1 of instance: CCM 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO08 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO02 of instance: GPIO2 0x5 ALT6 Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: SRC 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_02 0x1 SW_MUX_CTL_PAD_GPIO_SD_01 SW_MUX_CTL_PAD_GPIO_SD_01 SW MUX Control Register 0x80 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_B_DATA01 of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: SAI3_TX_BCLK of instance: SAI3 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM0_B of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: CCM_CLKO2 of instance: CCM 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO07 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO01 of instance: GPIO2 0x5 ALT6 Select mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: SRC 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_01 0x1 SW_MUX_CTL_PAD_GPIO_SD_00 SW_MUX_CTL_PAD_GPIO_SD_00 SW MUX Control Register 0x84 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_B_SS0_B of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: SAI3_TX_SYNC of instance: SAI3 0x1 ALT2 Select mux mode: ALT2 mux port: ARM_CM7_RXEV of instance: cm7_mxrt 0x2 ALT3 Select mux mode: ALT3 mux port: CCM_STOP of instance: CCM 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO06 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIO2_IO00 of instance: GPIO2 0x5 ALT6 Select mux mode: ALT6 mux port: SRC_BT_CFG02 of instance: SRC 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_SD_00 0x1 SW_MUX_CTL_PAD_GPIO_13 SW_MUX_CTL_PAD_GPIO_13 SW MUX Control Register 0x88 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPUART2_RXD of instance: LPUART2 0 ALT1 Select mux mode: ALT1 mux port: LPSPI2_PCS2 of instance: LPSPI2 0x1 ALT2 Select mux mode: ALT2 mux port: KPP_ROW03 of instance: KPP 0x2 ALT3 Select mux mode: ALT3 mux port: OTG1_ID of instance: anatop 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO05 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO13 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: SPDIF_LOCK of instance: SPDIF 0x6 ALT7 Select mux mode: ALT7 mux port: ARM_CM7_TRACE01 of instance: cm7_mxrt 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_13 0x1 SW_MUX_CTL_PAD_GPIO_12 SW_MUX_CTL_PAD_GPIO_12 SW MUX Control Register 0x8C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPUART3_TXD of instance: LPUART3 0 ALT1 Select mux mode: ALT1 mux port: LPI2C1_SCL of instance: LPI2C1 0x1 ALT2 Select mux mode: ALT2 mux port: KPP_COL00 of instance: KPP 0x2 ALT3 Select mux mode: ALT3 mux port: USB_OTG1_OC of instance: USB 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO04 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO12 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: SPDIF_EXT_CLK of instance: SPDIF 0x6 ALT7 Select mux mode: ALT7 mux port: ARM_CM7_TRACE02 of instance: cm7_mxrt 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_12 0x1 SW_MUX_CTL_PAD_GPIO_11 SW_MUX_CTL_PAD_GPIO_11 SW MUX Control Register 0x90 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPUART3_RXD of instance: LPUART3 0 ALT1 Select mux mode: ALT1 mux port: LPI2C1_SDA of instance: LPI2C1 0x1 ALT2 Select mux mode: ALT2 mux port: KPP_ROW00 of instance: KPP 0x2 ALT3 Select mux mode: ALT3 mux port: FLEXSPI_B_SS1_B of instance: FLEXSPI 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO03 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO11 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: SPDIF_OUT of instance: SPDIF 0x6 ALT7 Select mux mode: ALT7 mux port: ARM_CM7_TRACE03 of instance: cm7_mxrt 0x7 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_11 0x1 SW_MUX_CTL_PAD_GPIO_10 SW_MUX_CTL_PAD_GPIO_10 SW MUX Control Register 0x94 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPUART1_TXD of instance: LPUART1 0 ALT1 Select mux mode: ALT1 mux port: LPI2C1_HREQ of instance: LPI2C1 0x1 ALT2 Select mux mode: ALT2 mux port: EWM_OUT_B of instance: EWM 0x2 ALT3 Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: LPI2C2 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO02 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO10 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: SPDIF_IN of instance: SPDIF 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_10 0x1 SW_MUX_CTL_PAD_GPIO_09 SW_MUX_CTL_PAD_GPIO_09 SW MUX Control Register 0x98 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: LPUART1_RXD of instance: LPUART1 0 ALT1 Select mux mode: ALT1 mux port: WDOG1_B of instance: WDOG1 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXSPI_A_SS1_B of instance: FLEXSPI 0x2 ALT3 Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: LPI2C2 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO01 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO09 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: SPDIF_SR_CLK of instance: SPDIF 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_09 0x1 SW_MUX_CTL_PAD_GPIO_08 SW_MUX_CTL_PAD_GPIO_08 SW MUX Control Register 0x9C 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: SAI1_MCLK of instance: SAI1 0 ALT1 Select mux mode: ALT1 mux port: GPT1_CLK of instance: GPT1 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_A of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: LPUART3_TXD of instance: LPUART3 0x3 ALT4 Select mux mode: ALT4 mux port: FLEXIO1_IO00 of instance: FLEXIO1 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO08 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: LPUART1_CTS_B of instance: LPUART1 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_08 0x1 SW_MUX_CTL_PAD_GPIO_07 SW_MUX_CTL_PAD_GPIO_07 SW MUX Control Register 0xA0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: SAI1_TX_SYNC of instance: SAI1 0 ALT1 Select mux mode: ALT1 mux port: GPT1_COMPARE1 of instance: GPT1 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_B of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: LPUART3_RXD of instance: LPUART3 0x3 ALT4 Select mux mode: ALT4 mux port: SPDIF_LOCK of instance: SPDIF 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO07 of instance: GPIOMUX 0x5 ALT6 Select mux mode: ALT6 mux port: LPUART1_RTS_B of instance: LPUART1 0x6 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_07 0x1 SW_MUX_CTL_PAD_GPIO_06 SW_MUX_CTL_PAD_GPIO_06 SW MUX Control Register 0xA4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: SAI1_TX_BCLK of instance: SAI1 0 ALT1 Select mux mode: ALT1 mux port: GPT1_CAPTURE1 of instance: GPT1 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM2_A of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: LPUART4_TXD of instance: LPUART4 0x3 ALT4 Select mux mode: ALT4 mux port: SPDIF_EXT_CLK of instance: SPDIF 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO06 of instance: GPIOMUX 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_06 0x1 SW_MUX_CTL_PAD_GPIO_05 SW_MUX_CTL_PAD_GPIO_05 SW MUX Control Register 0xA8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: SAI1_TX_DATA01 of instance: SAI1 0 ALT1 Select mux mode: ALT1 mux port: GPT1_COMPARE2 of instance: GPT1 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM2_B of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: LPUART4_RXD of instance: LPUART4 0x3 ALT4 Select mux mode: ALT4 mux port: SPDIF_OUT of instance: SPDIF 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO05 of instance: GPIOMUX 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_05 0x1 SW_MUX_CTL_PAD_GPIO_04 SW_MUX_CTL_PAD_GPIO_04 SW MUX Control Register 0xAC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: SAI1_TX_DATA00 of instance: SAI1 0 ALT1 Select mux mode: ALT1 mux port: GPT1_CAPTURE2 of instance: GPT1 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_A of instance: FLEXPWM1 0x2 ALT4 Select mux mode: ALT4 mux port: SPDIF_IN of instance: SPDIF 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO04 of instance: GPIOMUX 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_04 0x1 SW_MUX_CTL_PAD_GPIO_03 SW_MUX_CTL_PAD_GPIO_03 SW MUX Control Register 0xB0 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: SAI1_RX_DATA00 of instance: SAI1 0 ALT1 Select mux mode: ALT1 mux port: GPT1_COMPARE3 of instance: GPT1 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM1_B of instance: FLEXPWM1 0x2 ALT4 Select mux mode: ALT4 mux port: SPDIF_SR_CLK of instance: SPDIF 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO03 of instance: GPIOMUX 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_03 0x1 SW_MUX_CTL_PAD_GPIO_02 SW_MUX_CTL_PAD_GPIO_02 SW MUX Control Register 0xB4 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: SAI1_RX_SYNC of instance: SAI1 0 ALT1 Select mux mode: ALT1 mux port: WDOG2_B of instance: WDOG2 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM0_A of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: LPI2C1_SCL of instance: LPI2C1 0x3 ALT4 Select mux mode: ALT4 mux port: KPP_COL03 of instance: KPP 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO02 of instance: GPIOMUX 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_02 0x1 SW_MUX_CTL_PAD_GPIO_01 SW_MUX_CTL_PAD_GPIO_01 SW MUX Control Register 0xB8 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: SAI1_RX_BCLK of instance: SAI1 0 ALT1 Select mux mode: ALT1 mux port: WDOG1_ANY of instance: WDOG1 0x1 ALT2 Select mux mode: ALT2 mux port: FLEXPWM1_PWM0_B of instance: FLEXPWM1 0x2 ALT3 Select mux mode: ALT3 mux port: LPI2C1_SDA of instance: LPI2C1 0x3 ALT4 Select mux mode: ALT4 mux port: KPP_ROW03 of instance: KPP 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO01 of instance: GPIOMUX 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_01 0x1 SW_MUX_CTL_PAD_GPIO_00 SW_MUX_CTL_PAD_GPIO_00 SW MUX Control Register 0xBC 32 read-write 0x5 0xFFFFFFFF MUX_MODE MUX Mode Select Field. 0 3 read-write ALT0 Select mux mode: ALT0 mux port: FLEXSPI_B_DQS of instance: FLEXSPI 0 ALT1 Select mux mode: ALT1 mux port: SAI3_MCLK of instance: SAI3 0x1 ALT2 Select mux mode: ALT2 mux port: LPSPI2_PCS3 of instance: LPSPI2 0x2 ALT3 Select mux mode: ALT3 mux port: LPSPI1_PCS3 of instance: LPSPI1 0x3 ALT4 Select mux mode: ALT4 mux port: PIT_TRIGGER00 of instance: PIT 0x4 ALT5 Select mux mode: ALT5 mux port: GPIOMUX_IO00 of instance: GPIOMUX 0x5 SION Software Input On Field. 4 1 read-write DISABLED Input Path is determined by functionality 0 ENABLED Force input path of pad GPIO_00 0x1 SW_PAD_CTL_PAD_GPIO_AD_14 SW_PAD_CTL_PAD_GPIO_AD_14 SW PAD Control Register 0xC0 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_13 SW_PAD_CTL_PAD_GPIO_AD_13 SW PAD Control Register 0xC4 32 read-write 0x70A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_12 SW_PAD_CTL_PAD_GPIO_AD_12 SW PAD Control Register 0xC8 32 read-write 0x30A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_11 SW_PAD_CTL_PAD_GPIO_AD_11 SW PAD Control Register 0xCC 32 read-write 0x30A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_10 SW_PAD_CTL_PAD_GPIO_AD_10 SW PAD Control Register 0xD0 32 read-write 0x70A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_09 SW_PAD_CTL_PAD_GPIO_AD_09 SW PAD Control Register 0xD4 32 read-write 0x90B1 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_08 SW_PAD_CTL_PAD_GPIO_AD_08 SW PAD Control Register 0xD8 32 read-write 0x70A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_07 SW_PAD_CTL_PAD_GPIO_AD_07 SW PAD Control Register 0xDC 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_06 SW_PAD_CTL_PAD_GPIO_AD_06 SW PAD Control Register 0xE0 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_05 SW_PAD_CTL_PAD_GPIO_AD_05 SW PAD Control Register 0xE4 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_04 SW_PAD_CTL_PAD_GPIO_AD_04 SW PAD Control Register 0xE8 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_03 SW_PAD_CTL_PAD_GPIO_AD_03 SW PAD Control Register 0xEC 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_02 SW_PAD_CTL_PAD_GPIO_AD_02 SW PAD Control Register 0xF0 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_01 SW_PAD_CTL_PAD_GPIO_AD_01 SW PAD Control Register 0xF4 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_AD_00 SW_PAD_CTL_PAD_GPIO_AD_00 SW PAD Control Register 0xF8 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_14 SW_PAD_CTL_PAD_GPIO_SD_14 SW PAD Control Register 0xFC 32 read-write 0x30A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_13 SW_PAD_CTL_PAD_GPIO_SD_13 SW PAD Control Register 0x100 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_12 SW_PAD_CTL_PAD_GPIO_SD_12 SW PAD Control Register 0x104 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_11 SW_PAD_CTL_PAD_GPIO_SD_11 SW PAD Control Register 0x108 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_10 SW_PAD_CTL_PAD_GPIO_SD_10 SW PAD Control Register 0x10C 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_09 SW_PAD_CTL_PAD_GPIO_SD_09 SW PAD Control Register 0x110 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_08 SW_PAD_CTL_PAD_GPIO_SD_08 SW PAD Control Register 0x114 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_07 SW_PAD_CTL_PAD_GPIO_SD_07 SW PAD Control Register 0x118 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_06 SW_PAD_CTL_PAD_GPIO_SD_06 SW PAD Control Register 0x11C 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_05 SW_PAD_CTL_PAD_GPIO_SD_05 SW PAD Control Register 0x120 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_04 SW_PAD_CTL_PAD_GPIO_SD_04 SW PAD Control Register 0x124 32 read-write 0x30A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_03 SW_PAD_CTL_PAD_GPIO_SD_03 SW PAD Control Register 0x128 32 read-write 0x30A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_02 SW_PAD_CTL_PAD_GPIO_SD_02 SW PAD Control Register 0x12C 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_01 SW_PAD_CTL_PAD_GPIO_SD_01 SW PAD Control Register 0x130 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_SD_00 SW_PAD_CTL_PAD_GPIO_SD_00 SW PAD Control Register 0x134 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_13 SW_PAD_CTL_PAD_GPIO_13 SW PAD Control Register 0x138 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_12 SW_PAD_CTL_PAD_GPIO_12 SW PAD Control Register 0x13C 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_11 SW_PAD_CTL_PAD_GPIO_11 SW PAD Control Register 0x140 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_10 SW_PAD_CTL_PAD_GPIO_10 SW PAD Control Register 0x144 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_09 SW_PAD_CTL_PAD_GPIO_09 SW PAD Control Register 0x148 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_08 SW_PAD_CTL_PAD_GPIO_08 SW PAD Control Register 0x14C 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_07 SW_PAD_CTL_PAD_GPIO_07 SW PAD Control Register 0x150 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_06 SW_PAD_CTL_PAD_GPIO_06 SW PAD Control Register 0x154 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_05 SW_PAD_CTL_PAD_GPIO_05 SW PAD Control Register 0x158 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_04 SW_PAD_CTL_PAD_GPIO_04 SW PAD Control Register 0x15C 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_03 SW_PAD_CTL_PAD_GPIO_03 SW PAD Control Register 0x160 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_02 SW_PAD_CTL_PAD_GPIO_02 SW PAD Control Register 0x164 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_01 SW_PAD_CTL_PAD_GPIO_01 SW PAD Control Register 0x168 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 SW_PAD_CTL_PAD_GPIO_00 SW_PAD_CTL_PAD_GPIO_00 SW PAD Control Register 0x16C 32 read-write 0x10A0 0xFFFFFFFF SRE Slew Rate Field 0 1 read-write SRE_0_Slow_Slew_Rate Slow Slew Rate 0 SRE_1_Fast_Slew_Rate Fast Slew Rate 0x1 DSE Drive Strength Field 3 3 read-write DSE_0_output_driver_disabled_ output driver disabled; 0 DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V__240_Ohm_for_DDR_ R0(150 Ohm @ 3.3V, 260 Ohm@1.8V, 240 Ohm for DDR) 0x1 DSE_2_R0_2 R0/2 0x2 DSE_3_R0_3 R0/3 0x3 DSE_4_R0_4 R0/4 0x4 DSE_5_R0_5 R0/5 0x5 DSE_6_R0_6 R0/6 0x6 DSE_7_R0_7 R0/7 0x7 SPEED Speed Field 6 2 read-write SPEED_0_low_50MHz low(50MHz) 0 SPEED_1_medium_100MHz medium(100MHz) 0x1 SPEED_2_fast_150MHz fast(150MHz) 0x2 SPEED_3_max_200MHz max(200MHz) 0x3 ODE Open Drain Enable Field 11 1 read-write ODE_0_Open_Drain_Disabled Open Drain Disabled 0 ODE_1_Open_Drain_Enabled Open Drain Enabled 0x1 PKE Pull / Keep Enable Field 12 1 read-write PKE_0_Pull_Keeper_Disabled Pull/Keeper Disabled 0 PKE_1_Pull_Keeper_Enabled Pull/Keeper Enabled 0x1 PUE Pull / Keep Select Field 13 1 read-write PUE_0_Keeper Keeper 0 PUE_1_Pull Pull 0x1 PUS Pull Up / Down Config. Field 14 2 read-write PUS_0_100K_Ohm_Pull_Down 100K Ohm Pull Down 0 PUS_1_47K_Ohm_Pull_Up 47K Ohm Pull Up 0x1 PUS_2_100K_Ohm_Pull_Up 100K Ohm Pull Up 0x2 PUS_3_22K_Ohm_Pull_Up 22K Ohm Pull Up 0x3 HYS Hyst. Enable Field 16 1 read-write HYS_0_Hysteresis_Disabled Hysteresis Disabled 0 HYS_1_Hysteresis_Enabled Hysteresis Enabled 0x1 USB_OTG_ID_SELECT_INPUT USB_OTG_ID_SELECT_INPUT DAISY Register 0x170 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_10_ALT6 Selecting Pad: GPIO_AD_10 for Mode: ALT6 0 GPIO_13_ALT3 Selecting Pad: GPIO_13 for Mode: ALT3 0x1 FLEXPWM1_PWMA_SELECT_INPUT_0 FLEXPWM1_PWMA_SELECT_INPUT_0 DAISY Register 0x174 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_SD_02_ALT2 Selecting Pad: GPIO_SD_02 for Mode: ALT2 0 GPIO_02_ALT2 Selecting Pad: GPIO_02 for Mode: ALT2 0x1 FLEXPWM1_PWMA_SELECT_INPUT_1 FLEXPWM1_PWMA_SELECT_INPUT_1 DAISY Register 0x178 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_SD_04_ALT2 Selecting Pad: GPIO_SD_04 for Mode: ALT2 0 GPIO_04_ALT2 Selecting Pad: GPIO_04 for Mode: ALT2 0x1 FLEXPWM1_PWMA_SELECT_INPUT_2 FLEXPWM1_PWMA_SELECT_INPUT_2 DAISY Register 0x17C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_04_ALT2 Selecting Pad: GPIO_AD_04 for Mode: ALT2 0 GPIO_06_ALT2 Selecting Pad: GPIO_06 for Mode: ALT2 0x1 FLEXPWM1_PWMA_SELECT_INPUT_3 FLEXPWM1_PWMA_SELECT_INPUT_3 DAISY Register 0x180 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_06_ALT2 Selecting Pad: GPIO_AD_06 for Mode: ALT2 0 GPIO_08_ALT2 Selecting Pad: GPIO_08 for Mode: ALT2 0x1 FLEXPWM1_PWMB_SELECT_INPUT_0 FLEXPWM1_PWMB_SELECT_INPUT_0 DAISY Register 0x184 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_SD_01_ALT2 Selecting Pad: GPIO_SD_01 for Mode: ALT2 0 GPIO_01_ALT2 Selecting Pad: GPIO_01 for Mode: ALT2 0x1 FLEXPWM1_PWMB_SELECT_INPUT_1 FLEXPWM1_PWMB_SELECT_INPUT_1 DAISY Register 0x188 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_SD_03_ALT2 Selecting Pad: GPIO_SD_03 for Mode: ALT2 0 GPIO_03_ALT2 Selecting Pad: GPIO_03 for Mode: ALT2 0x1 FLEXPWM1_PWMB_SELECT_INPUT_2 FLEXPWM1_PWMB_SELECT_INPUT_2 DAISY Register 0x18C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_03_ALT2 Selecting Pad: GPIO_AD_03 for Mode: ALT2 0 GPIO_05_ALT2 Selecting Pad: GPIO_05 for Mode: ALT2 0x1 FLEXPWM1_PWMB_SELECT_INPUT_3 FLEXPWM1_PWMB_SELECT_INPUT_3 DAISY Register 0x190 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_05_ALT2 Selecting Pad: GPIO_AD_05 for Mode: ALT2 0 GPIO_07_ALT2 Selecting Pad: GPIO_07 for Mode: ALT2 0x1 FLEXSPI_DQS_FA_SELECT_INPUT FLEXSPI_DQS_FA_SELECT_INPUT DAISY Register 0x194 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_SD_14_ALT0 Selecting Pad: GPIO_SD_14 for Mode: ALT0 0 GPIO_SD_12_ALT0 Selecting Pad: GPIO_SD_12 for Mode: ALT0 0x1 FLEXSPI_DQS_FB_SELECT_INPUT FLEXSPI_DQS_FB_SELECT_INPUT DAISY Register 0x198 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_SD_14_ALT1 Selecting Pad: GPIO_SD_14 for Mode: ALT1 0 GPIO_00_ALT0 Selecting Pad: GPIO_00 for Mode: ALT0 0x1 KPP_COL_SELECT_INPUT_0 KPP_COL_SELECT_INPUT_0 DAISY Register 0x19C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_14_ALT2 Selecting Pad: GPIO_AD_14 for Mode: ALT2 0 GPIO_12_ALT2 Selecting Pad: GPIO_12 for Mode: ALT2 0x1 KPP_COL_SELECT_INPUT_1 KPP_COL_SELECT_INPUT_1 DAISY Register 0x1A0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_12_ALT2 Selecting Pad: GPIO_AD_12 for Mode: ALT2 0 GPIO_AD_06_ALT3 Selecting Pad: GPIO_AD_06 for Mode: ALT3 0x1 KPP_COL_SELECT_INPUT_2 KPP_COL_SELECT_INPUT_2 DAISY Register 0x1A4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_10_ALT2 Selecting Pad: GPIO_AD_10 for Mode: ALT2 0 GPIO_AD_04_ALT3 Selecting Pad: GPIO_AD_04 for Mode: ALT3 0x1 KPP_COL_SELECT_INPUT_3 KPP_COL_SELECT_INPUT_3 DAISY Register 0x1A8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_00_ALT2 Selecting Pad: GPIO_AD_00 for Mode: ALT2 0 GPIO_02_ALT4 Selecting Pad: GPIO_02 for Mode: ALT4 0x1 KPP_ROW_SELECT_INPUT_0 KPP_ROW_SELECT_INPUT_0 DAISY Register 0x1AC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_13_ALT2 Selecting Pad: GPIO_AD_13 for Mode: ALT2 0 GPIO_11_ALT2 Selecting Pad: GPIO_11 for Mode: ALT2 0x1 KPP_ROW_SELECT_INPUT_1 KPP_ROW_SELECT_INPUT_1 DAISY Register 0x1B0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_11_ALT2 Selecting Pad: GPIO_AD_11 for Mode: ALT2 0 GPIO_AD_05_ALT3 Selecting Pad: GPIO_AD_05 for Mode: ALT3 0x1 KPP_ROW_SELECT_INPUT_2 KPP_ROW_SELECT_INPUT_2 DAISY Register 0x1B4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_09_ALT2 Selecting Pad: GPIO_AD_09 for Mode: ALT2 0 GPIO_AD_03_ALT3 Selecting Pad: GPIO_AD_03 for Mode: ALT3 0x1 KPP_ROW_SELECT_INPUT_3 KPP_ROW_SELECT_INPUT_3 DAISY Register 0x1B8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_13_ALT2 Selecting Pad: GPIO_13 for Mode: ALT2 0 GPIO_01_ALT4 Selecting Pad: GPIO_01 for Mode: ALT4 0x1 LPI2C1_HREQ_SELECT_INPUT LPI2C1_HREQ_SELECT_INPUT DAISY Register 0x1BC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_06_ALT6 Selecting Pad: GPIO_AD_06 for Mode: ALT6 0 GPIO_10_ALT1 Selecting Pad: GPIO_10 for Mode: ALT1 0x1 LPI2C1_SCL_SELECT_INPUT LPI2C1_SCL_SELECT_INPUT DAISY Register 0x1C0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write GPIO_AD_14_ALT0 Selecting Pad: GPIO_AD_14 for Mode: ALT0 0 GPIO_SD_06_ALT1 Selecting Pad: GPIO_SD_06 for Mode: ALT1 0x1 GPIO_12_ALT1 Selecting Pad: GPIO_12 for Mode: ALT1 0x2 GPIO_02_ALT3 Selecting Pad: GPIO_02 for Mode: ALT3 0x3 LPI2C1_SDA_SELECT_INPUT LPI2C1_SDA_SELECT_INPUT DAISY Register 0x1C4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write GPIO_AD_13_ALT0 Selecting Pad: GPIO_AD_13 for Mode: ALT0 0 GPIO_SD_05_ALT1 Selecting Pad: GPIO_SD_05 for Mode: ALT1 0x1 GPIO_11_ALT1 Selecting Pad: GPIO_11 for Mode: ALT1 0x2 GPIO_01_ALT3 Selecting Pad: GPIO_01 for Mode: ALT3 0x3 LPI2C2_SCL_SELECT_INPUT LPI2C2_SCL_SELECT_INPUT DAISY Register 0x1C8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write GPIO_AD_08_ALT0 Selecting Pad: GPIO_AD_08 for Mode: ALT0 0 GPIO_AD_02_ALT3 Selecting Pad: GPIO_AD_02 for Mode: ALT3 0x1 GPIO_SD_08_ALT1 Selecting Pad: GPIO_SD_08 for Mode: ALT1 0x2 GPIO_10_ALT3 Selecting Pad: GPIO_10 for Mode: ALT3 0x3 LPI2C2_SDA_SELECT_INPUT LPI2C2_SDA_SELECT_INPUT DAISY Register 0x1CC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write GPIO_AD_07_ALT0 Selecting Pad: GPIO_AD_07 for Mode: ALT0 0 GPIO_AD_01_ALT3 Selecting Pad: GPIO_AD_01 for Mode: ALT3 0x1 GPIO_SD_07_ALT1 Selecting Pad: GPIO_SD_07 for Mode: ALT1 0x2 GPIO_09_ALT3 Selecting Pad: GPIO_09 for Mode: ALT3 0x3 LPSPI1_PCS_SELECT_INPUT_0 LPSPI1_PCS_SELECT_INPUT_0 DAISY Register 0x1D0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_05_ALT0 Selecting Pad: GPIO_AD_05 for Mode: ALT0 0 GPIO_SD_07_ALT2 Selecting Pad: GPIO_SD_07 for Mode: ALT2 0x1 LPSPI1_SCK_SELECT_INPUT LPSPI1_SCK_SELECT_INPUT DAISY Register 0x1D4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_06_ALT0 Selecting Pad: GPIO_AD_06 for Mode: ALT0 0 GPIO_SD_08_ALT2 Selecting Pad: GPIO_SD_08 for Mode: ALT2 0x1 LPSPI1_SDI_SELECT_INPUT LPSPI1_SDI_SELECT_INPUT DAISY Register 0x1D8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_03_ALT0 Selecting Pad: GPIO_AD_03 for Mode: ALT0 0 GPIO_SD_05_ALT2 Selecting Pad: GPIO_SD_05 for Mode: ALT2 0x1 LPSPI1_SDO_SELECT_INPUT LPSPI1_SDO_SELECT_INPUT DAISY Register 0x1DC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_04_ALT0 Selecting Pad: GPIO_AD_04 for Mode: ALT0 0 GPIO_SD_06_ALT2 Selecting Pad: GPIO_SD_06 for Mode: ALT2 0x1 LPSPI2_PCS_SELECT_INPUT_0 LPSPI2_PCS_SELECT_INPUT_0 DAISY Register 0x1E0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_11_ALT0 Selecting Pad: GPIO_AD_11 for Mode: ALT0 0 GPIO_SD_12_ALT1 Selecting Pad: GPIO_SD_12 for Mode: ALT1 0x1 LPSPI2_SCK_SELECT_INPUT LPSPI2_SCK_SELECT_INPUT DAISY Register 0x1E4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_12_ALT0 Selecting Pad: GPIO_AD_12 for Mode: ALT0 0 GPIO_SD_11_ALT1 Selecting Pad: GPIO_SD_11 for Mode: ALT1 0x1 LPSPI2_SDI_SELECT_INPUT LPSPI2_SDI_SELECT_INPUT DAISY Register 0x1E8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_09_ALT0 Selecting Pad: GPIO_AD_09 for Mode: ALT0 0 GPIO_SD_09_ALT1 Selecting Pad: GPIO_SD_09 for Mode: ALT1 0x1 LPSPI2_SDO_SELECT_INPUT LPSPI2_SDO_SELECT_INPUT DAISY Register 0x1EC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_10_ALT0 Selecting Pad: GPIO_AD_10 for Mode: ALT0 0 GPIO_SD_10_ALT1 Selecting Pad: GPIO_SD_10 for Mode: ALT1 0x1 LPUART1_RXD_SELECT_INPUT LPUART1_RXD_SELECT_INPUT DAISY Register 0x1F0 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_SD_11_ALT2 Selecting Pad: GPIO_SD_11 for Mode: ALT2 0 GPIO_09_ALT0 Selecting Pad: GPIO_09 for Mode: ALT0 0x1 LPUART1_TXD_SELECT_INPUT LPUART1_TXD_SELECT_INPUT DAISY Register 0x1F4 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_SD_12_ALT2 Selecting Pad: GPIO_SD_12 for Mode: ALT2 0 GPIO_10_ALT0 Selecting Pad: GPIO_10 for Mode: ALT0 0x1 LPUART2_RXD_SELECT_INPUT LPUART2_RXD_SELECT_INPUT DAISY Register 0x1F8 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_SD_09_ALT2 Selecting Pad: GPIO_SD_09 for Mode: ALT2 0 GPIO_13_ALT0 Selecting Pad: GPIO_13 for Mode: ALT0 0x1 LPUART2_TXD_SELECT_INPUT LPUART2_TXD_SELECT_INPUT DAISY Register 0x1FC 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_00_ALT0 Selecting Pad: GPIO_AD_00 for Mode: ALT0 0 GPIO_SD_10_ALT2 Selecting Pad: GPIO_SD_10 for Mode: ALT2 0x1 LPUART3_RXD_SELECT_INPUT LPUART3_RXD_SELECT_INPUT DAISY Register 0x200 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write GPIO_AD_07_ALT1 Selecting Pad: GPIO_AD_07 for Mode: ALT1 0 GPIO_11_ALT0 Selecting Pad: GPIO_11 for Mode: ALT0 0x1 GPIO_07_ALT3 Selecting Pad: GPIO_07 for Mode: ALT3 0x2 LPUART3_TXD_SELECT_INPUT LPUART3_TXD_SELECT_INPUT DAISY Register 0x204 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 2 read-write GPIO_AD_08_ALT1 Selecting Pad: GPIO_AD_08 for Mode: ALT1 0 GPIO_12_ALT0 Selecting Pad: GPIO_12 for Mode: ALT0 0x1 GPIO_08_ALT3 Selecting Pad: GPIO_08 for Mode: ALT3 0x2 LPUART4_RXD_SELECT_INPUT LPUART4_RXD_SELECT_INPUT DAISY Register 0x208 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_01_ALT0 Selecting Pad: GPIO_AD_01 for Mode: ALT0 0 GPIO_05_ALT3 Selecting Pad: GPIO_05 for Mode: ALT3 0x1 LPUART4_TXD_SELECT_INPUT LPUART4_TXD_SELECT_INPUT DAISY Register 0x20C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_02_ALT0 Selecting Pad: GPIO_AD_02 for Mode: ALT0 0 GPIO_06_ALT3 Selecting Pad: GPIO_06 for Mode: ALT3 0x1 NMI_GLUE_NMI_SELECT_INPUT NMI_GLUE_NMI_SELECT_INPUT DAISY Register 0x210 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_13_ALT6 Selecting Pad: GPIO_AD_13 for Mode: ALT6 0 GPIO_AD_00_ALT6 Selecting Pad: GPIO_AD_00 for Mode: ALT6 0x1 SPDIF_IN1_SELECT_INPUT SPDIF_IN1_SELECT_INPUT DAISY Register 0x214 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_10_ALT6 Selecting Pad: GPIO_10 for Mode: ALT6 0 GPIO_04_ALT4 Selecting Pad: GPIO_04 for Mode: ALT4 0x1 SPDIF_TX_CLK2_SELECT_INPUT SPDIF_TX_CLK2_SELECT_INPUT DAISY Register 0x218 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_12_ALT6 Selecting Pad: GPIO_12 for Mode: ALT6 0 GPIO_06_ALT4 Selecting Pad: GPIO_06 for Mode: ALT4 0x1 USB_OTG_OC_SELECT_INPUT USB_OTG_OC_SELECT_INPUT DAISY Register 0x21C 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_01_ALT6 Selecting Pad: GPIO_AD_01 for Mode: ALT6 0 GPIO_12_ALT3 Selecting Pad: GPIO_12 for Mode: ALT3 0x1 XEV_GLUE_RXEV_SELECT_INPUT XEV_GLUE_RXEV_SELECT_INPUT DAISY Register 0x220 32 read-write 0 0xFFFFFFFF DAISY Selecting Pads Involved in Daisy Chain. 0 1 read-write GPIO_AD_07_ALT2 Selecting Pad: GPIO_AD_07 for Mode: ALT2 0 GPIO_SD_00_ALT2 Selecting Pad: GPIO_SD_00 for Mode: ALT2 0x1 KPP KPP Registers KPP KPP_ 0x401FC000 0 0x8 registers KPP 39 KPCR Keypad Control Register 0 16 read-write 0 0xFFFF KRE Keypad Row Enable 0 8 read-write KRE_0 Row is not included in the keypad key press detect. 0 KRE_1 Row is included in the keypad key press detect. 0x1 KCO Keypad Column Strobe Open-Drain Enable 8 8 read-write TOTEM_POLE Column strobe output is totem pole drive. 0 OPEN_DRAIN Column strobe output is open drain. 0x1 KPSR Keypad Status Register 0x2 16 read-write 0x400 0xFFFF KPKD Keypad Key Depress 0 1 read-write oneToClear KPKD_0 No key presses detected 0 KPKD_1 A key has been depressed 0x1 KPKR Keypad Key Release 1 1 read-write oneToClear KPKR_0 No key release detected 0 KPKR_1 All keys have been released 0x1 KDSC Key Depress Synchronizer Clear 2 1 read-write KDSC_0 No effect 0 KDSC_1 Set bits that clear the keypad depress synchronizer chain 0x1 KRSS Key Release Synchronizer Set 3 1 read-write KRSS_0 No effect 0 KRSS_1 Set bits which sets keypad release synchronizer chain 0x1 KDIE Keypad Key Depress Interrupt Enable 8 1 read-write KDIE_0 No interrupt request is generated when KPKD is set. 0 KDIE_1 An interrupt request is generated when KPKD is set. 0x1 KRIE Keypad Release Interrupt Enable 9 1 read-write KRIE_0 No interrupt request is generated when KPKR is set. 0 KRIE_1 An interrupt request is generated when KPKR is set. 0x1 KDDR Keypad Data Direction Register 0x4 16 read-write 0 0xFFFF KRDD Keypad Row Data Direction 0 8 read-write INPUT ROWn pin configured as an input. 0 OUTPUT ROWn pin configured as an output. 0x1 KCDD Keypad Column Data Direction Register 8 8 read-write INPUT COLn pin is configured as an input. 0 OUTPUT COLn pin is configured as an output. 0x1 KPDR Keypad Data Register 0x6 16 read-write 0 0xFFFF KRD Keypad Row Data 0 8 read-write KCD Keypad Column Data 8 8 read-write SystemControl System Control Block SCB SCB_ 0xE000E000 0 0xFAC registers ACTLR Auxiliary Control Register, 0x8 32 read-write 0 0xFFFFFFFF DISFOLD Disables folding of IT instructions. 2 1 read-write DISFOLD_0 Normal operation. 0 FPEXCODIS Disables FPU exception outputs. 10 1 read-write FPEXCODIS_0 Normal operation. 0 FPEXCODIS_1 FPU exception outputs are disabled. 0x1 DISRAMODE Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions. 11 1 read-write DISRAMODE_0 Normal operation. 0 DISRAMODE_1 Dynamic disabled. 0x1 DISITMATBFLUSH Disables ITM and DWT ATB flush. 12 1 read-write DISITMATBFLUSH_1 ITM and DWT ATB flush disabled, this bit is always 1. 0x1 DISBTACREAD Disables BTAC read. 13 1 read-write DISBTACREAD_0 Normal operation. 0 DISBTACREAD_1 BTAC is not used and only static branch prediction can occur. 0x1 DISBTACALLOC Disables BTAC allocate. 14 1 read-write DISBTACALLOC_0 Normal operation. 0 DISBTACALLOC_1 No new entries are allocated in Branch Target Address Cache (BTAC), but existing entries can be updated. 0x1 DISCRITAXIRUR Disables critical AXI Read-Under-Read. 15 1 read-write DISCRITAXIRUR_0 Normal operation. 0 DISCRITAXIRUR_1 An AXI read to Strongly-Ordered or Device memory, or an LDREX to Shareable memory, is not put on AXI if there are any outstanding reads on AXI. Transactions on AXI cannot be interrupted. This bit might reduce the time that these transactions are in progress and might improve worst case interrupt latency. Performance is decreased when this bit is set. 0x1 DISDI Disables dual-issued. 16 5 read-write DISDI_0 Normal operation. 0 DISDI_1 Nothing can be dual-issued when this instruction type is in channel 0. 0x1 DISISSCH1 Disables dual-issued. 21 5 read-write DISISSCH1_0 Normal operation. 0 DISISSCH1_1 Nothing can be dual-issued when this instruction type is in channel 1. 0x1 DISDYNADD Disables dynamic allocation of ADD and SUB instructions 26 1 read-write DISDYNADD_0 Normal operation. Some ADD and SUB instrctions are resolved in EX1. 0 DISDYNADD_1 All ADD and SUB instructions are resolved in EX2. 0x1 DISCRITAXIRUW Disables critical AXI read-under-write 27 1 read-write DISCRITAXIRUW_0 Normal operation. This is backwards compatible with r0. 0 DISCRITAXIRUW_1 AXI reads to DEV/SO memory. Exclusive reads to Shareable memory are not initiated on the AXIM AR channel until all outstanding stores on AXI are complete. 0x1 DISFPUISSOPT Disables critical AXI read-under-write 28 1 read-write DISFPUISSOPT_0 Normal operation. 0 CPUID CPUID Base Register 0xD00 32 read-only 0x410FC240 0xFFFFFFFF REVISION Indicates patch release: 0x0 = Patch 0 0 4 read-only PARTNO Indicates part number 4 12 read-only ARCHITECTURE ARCHITECTURE 16 4 read-only VARIANT Indicates processor revision: 0x2 = Revision 2 20 4 read-only IMPLEMENTER Implementer code 24 8 read-only ICSR Interrupt Control and State Register 0xD04 32 read-write 0 0xFFFFFFFF VECTACTIVE Active exception number 0 9 read-only RETTOBASE Indicates whether there are preempted active exceptions 11 1 read-only RETTOBASE_0 there are preempted active exceptions to execute 0 RETTOBASE_1 there are no active exceptions, or the currently-executing exception is the only active exception 0x1 VECTPENDING Exception number of the highest priority pending enabled exception 12 9 read-only ISRPENDING Interrupt pending flag, excluding NMI and Faults 22 1 read-only ISRPENDING_0 No external interrupt pending. 0 ISRPENDING_1 External interrupt pending. 0x1 PENDSTCLR SysTick exception clear-pending bit 25 1 write-only PENDSTCLR_0 no effect 0 PENDSTCLR_1 removes the pending state from the SysTick exception 0x1 PENDSTSET SysTick exception set-pending bit 26 1 read-write PENDSTSET_0 write: no effect; read: SysTick exception is not pending 0 PENDSTSET_1 write: changes SysTick exception state to pending; read: SysTick exception is pending 0x1 PENDSVCLR PendSV clear-pending bit 27 1 write-only PENDSVCLR_0 no effect 0 PENDSVCLR_1 removes the pending state from the PendSV exception 0x1 PENDSVSET PendSV set-pending bit 28 1 read-write PENDSVSET_0 write: no effect; read: PendSV exception is not pending 0 PENDSVSET_1 write: changes PendSV exception state to pending; read: PendSV exception is pending 0x1 NMIPENDSET NMI set-pending bit 31 1 read-write NMIPENDSET_0 write: no effect; read: NMI exception is not pending 0 NMIPENDSET_1 write: changes NMI exception state to pending; read: NMI exception is pending 0x1 VTOR Vector Table Offset Register 0xD08 32 read-write 0 0xFFFFFFFF TBLOFF Vector table base offset 7 25 read-write AIRCR Application Interrupt and Reset Control Register 0xD0C 32 read-write 0xFA050000 0xFFFFFFFF VECTRESET Writing 1 to this bit causes a local system reset 0 1 write-only VECTRESET_0 No change 0 VECTRESET_1 Causes a local system reset 0x1 VECTCLRACTIVE Writing 1 to this bit clears all active state information for fixed and configurable exceptions. 1 1 write-only VECTCLRACTIVE_0 No change 0 VECTCLRACTIVE_1 Clears all active state information for fixed and configurable exceptions 0x1 SYSRESETREQ System reset request 2 1 write-only SYSRESETREQ_0 no system reset request 0 SYSRESETREQ_1 asserts a signal to the outer system that requests a reset 0x1 PRIGROUP Interrupt priority grouping field. This field determines the split of group priority from subpriority. 8 3 read-write ENDIANNESS Data endianness 15 1 read-only ENDIANNESS_0 Little-endian 0 ENDIANNESS_1 Big-endian 0x1 VECTKEY Register key 16 16 read-write SCR System Control Register 0xD10 32 read-write 0 0xFFFFFFFF SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode 1 1 read-write SLEEPONEXIT_0 o not sleep when returning to Thread mode 0 SLEEPONEXIT_1 enter sleep, or deep sleep, on return from an ISR 0x1 SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode 2 1 read-write SLEEPDEEP_0 sleep 0 SLEEPDEEP_1 deep sleep 0x1 SEVONPEND Send Event on Pending bit 4 1 read-write SEVONPEND_0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 0 SEVONPEND_1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor 0x1 CCR Configuration and Control Register 0xD14 32 read-write 0x40000 0xFFFFFFFF NONBASETHRDENA Indicates how the processor enters Thread mode 0 1 read-write NONBASETHRDENA_0 processor can enter Thread mode only when no exception is active 0 NONBASETHRDENA_1 processor can enter Thread mode from any level under the control of an EXC_RETURN value 0x1 USERSETMPEND Enables unprivileged software access to the STIR 1 1 read-write USERSETMPEND_0 disable 0 USERSETMPEND_1 enable 0x1 UNALIGN_TRP Enables unaligned access traps 3 1 read-write UNALIGN_TRP_0 do not trap unaligned halfword and word accesses 0 UNALIGN_TRP_1 trap unaligned halfword and word accesses 0x1 DIV_0_TRP Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 4 1 read-write DIV_0_TRP_0 do not trap divide by 0 0 DIV_0_TRP_1 trap divide by 0 0x1 BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. 8 1 read-write BFHFNMIGN_0 data bus faults caused by load and store instructions cause a lock-up 0 BFHFNMIGN_1 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions 0x1 STKALIGN Indicates stack alignment on exception entry 9 1 read-write STKALIGN_0 4-byte aligned 0 STKALIGN_1 8-byte aligned 0x1 DC Enables L1 data cache. 16 1 read-write DC_0 L1 data cache disabled 0 DC_1 L1 data cache enabled 0x1 IC Enables L1 instruction cache. 17 1 read-write IC_0 L1 instruction cache disabled 0 IC_1 L1 instruction cache enabled 0x1 BP Always reads-as-one. It indicates branch prediction is enabled. 18 1 read-only SHPR1 System Handler Priority Register 1 0xD18 32 read-write 0 0xFFFFFFFF PRI_4 Priority of system handler 4, MemManage 0 8 read-write PRI_5 Priority of system handler 5, BusFault 8 8 read-write PRI_6 Priority of system handler 6, UsageFault 16 8 read-write SHPR2 System Handler Priority Register 2 0xD1C 32 read-write 0 0xFFFFFFFF PRI_11 Priority of system handler 11, SVCall 24 8 read-write SHPR3 System Handler Priority Register 3 0xD20 32 read-write 0 0xFFFFFFFF PRI_14 Priority of system handler 14, PendSV 16 8 read-write PRI_15 Priority of system handler 15, SysTick exception 24 8 read-write SHCSR System Handler Control and State Register 0xD24 32 read-write 0 0xFFFFFFFF MEMFAULTACT MemManage exception active bit 0 1 read-write MEMFAULTACT_0 exception is not active 0 MEMFAULTACT_1 exception is active 0x1 BUSFAULTACT BusFault exception active bit 1 1 read-write BUSFAULTACT_0 exception is not active 0 BUSFAULTACT_1 exception is active 0x1 USGFAULTACT UsageFault exception active bit 3 1 read-write USGFAULTACT_0 exception is not active 0 USGFAULTACT_1 exception is active 0x1 SVCALLACT SVCall active bit 7 1 read-write SVCALLACT_0 exception is not active 0 SVCALLACT_1 exception is active 0x1 MONITORACT Debug monitor active bit 8 1 read-write MONITORACT_0 exception is not active 0 MONITORACT_1 exception is active 0x1 PENDSVACT PendSV exception active bit 10 1 read-write PENDSVACT_0 exception is not active 0 PENDSVACT_1 exception is active 0x1 SYSTICKACT SysTick exception active bit 11 1 read-write SYSTICKACT_0 exception is not active 0 SYSTICKACT_1 exception is active 0x1 USGFAULTPENDED UsageFault exception pending bit 12 1 read-write USGFAULTPENDED_0 exception is not pending 0 USGFAULTPENDED_1 exception is pending 0x1 MEMFAULTPENDED MemManage exception pending bit 13 1 read-write MEMFAULTPENDED_0 exception is not pending 0 MEMFAULTPENDED_1 exception is pending 0x1 BUSFAULTPENDED BusFault exception pending bit 14 1 read-write BUSFAULTPENDED_0 exception is not pending 0 BUSFAULTPENDED_1 exception is pending 0x1 SVCALLPENDED SVCall pending bit 15 1 read-write SVCALLPENDED_0 exception is not pending 0 SVCALLPENDED_1 exception is pending 0x1 MEMFAULTENA MemManage enable bit 16 1 read-write MEMFAULTENA_0 disable the exception 0 MEMFAULTENA_1 enable the exception 0x1 BUSFAULTENA BusFault enable bit 17 1 read-write BUSFAULTENA_0 disable the exception 0 BUSFAULTENA_1 enable the exception 0x1 USGFAULTENA UsageFault enable bit 18 1 read-write USGFAULTENA_0 disable the exception 0 USGFAULTENA_1 enable the exception 0x1 CFSR Configurable Fault Status Register 0xD28 32 read-write 0 0xFFFFFFFF IACCVIOL Instruction access violation flag 0 1 read-write IACCVIOL_0 no instruction access violation fault 0 IACCVIOL_1 the processor attempted an instruction fetch from a location that does not permit execution 0x1 DACCVIOL Data access violation flag 1 1 read-write DACCVIOL_0 no data access violation fault 0 DACCVIOL_1 the processor attempted a load or store at a location that does not permit the operation 0x1 MUNSTKERR MemManage fault on unstacking for a return from exception 3 1 read-write MUNSTKERR_0 no unstacking fault 0 MUNSTKERR_1 unstack for an exception return has caused one or more access violations 0x1 MSTKERR MemManage fault on stacking for exception entry 4 1 read-write MSTKERR_0 no stacking fault 0 MSTKERR_1 stacking for an exception entry has caused one or more access violations 0x1 MLSPERR MemManage fault occurred during floating-point lazy state preservation 5 1 read-write MLSPERR_0 No MemManage fault occurred during floating-point lazy state preservation 0 MLSPERR_1 A MemManage fault occurred during floating-point lazy state preservation 0x1 MMARVALID MemManage Fault Address Register (MMFAR) valid flag 7 1 read-write MMARVALID_0 value in MMAR is not a valid fault address 0 MMARVALID_1 MMAR holds a valid fault address 0x1 IBUSERR Instruction bus error 8 1 read-write IBUSERR_0 no instruction bus error 0 IBUSERR_1 instruction bus error 0x1 PRECISERR Precise data bus error 9 1 read-write PRECISERR_0 no precise data bus error 0 PRECISERR_1 a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault 0x1 IMPRECISERR Imprecise data bus error 10 1 read-write IMPRECISERR_0 no imprecise data bus error 0 IMPRECISERR_1 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error 0x1 UNSTKERR BusFault on unstacking for a return from exception 11 1 read-write UNSTKERR_0 no unstacking fault 0 UNSTKERR_1 unstack for an exception return has caused one or more BusFaults 0x1 STKERR BusFault on stacking for exception entry 12 1 read-write STKERR_0 no stacking fault 0 STKERR_1 stacking for an exception entry has caused one or more BusFaults 0x1 LSPERR Bus fault occurred during floating-point lazy state preservation 13 1 read-write LSPERR_0 No bus fault occurred during floating-point lazy state preservation 0 LSPERR_1 A bus fault occurred during floating-point lazy state preservation 0x1 BFARVALID BusFault Address Register (BFAR) valid flag 15 1 read-write BFARVALID_0 value in BFAR is not a valid fault address 0 BFARVALID_1 BFAR holds a valid fault address 0x1 UNDEFINSTR Undefined instruction UsageFault 16 1 read-write UNDEFINSTR_0 no undefined instruction UsageFault 0 UNDEFINSTR_1 the processor has attempted to execute an undefined instruction 0x1 INVSTATE Invalid state UsageFault 17 1 read-write INVSTATE_0 no invalid state UsageFault 0 INVSTATE_1 the processor has attempted to execute an instruction that makes illegal use of the EPSR 0x1 INVPC Invalid PC load UsageFault, caused by an invalid PC load by EXC_RETURN 18 1 read-write INVPC_0 no invalid PC load UsageFault 0 INVPC_1 the processor has attempted an illegal load of EXC_RETURN to the PC 0x1 NOCP No coprocessor UsageFault 19 1 read-write NOCP_0 no UsageFault caused by attempting to access a coprocessor 0 NOCP_1 the processor has attempted to access a coprocessor 0x1 UNALIGNED Unaligned access UsageFault 24 1 read-write UNALIGNED_0 no unaligned access fault, or unaligned access trapping not enabled 0 UNALIGNED_1 the processor has made an unaligned memory access 0x1 DIVBYZERO Divide by zero UsageFault 25 1 read-write DIVBYZERO_0 no divide by zero fault, or divide by zero trapping not enabled 0 DIVBYZERO_1 the processor has executed an SDIV or UDIV instruction with a divisor of 0 0x1 HFSR HardFault Status register 0xD2C 32 read-write 0 0xFFFFFFFF VECTTBL Indicates a BusFault on a vector table read during exception processing. 1 1 read-write VECTTBL_0 no BusFault on vector table read 0 VECTTBL_1 BusFault on vector table read 0x1 FORCED Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled. 30 1 read-write FORCED_0 no forced HardFault 0 FORCED_1 forced HardFault 0x1 DEBUGEVT Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. 31 1 read-write DEBUGEVT_0 No Debug event has occurred. 0 DEBUGEVT_1 Debug event has occurred. The Debug Fault Status Register has been updated. 0x1 DFSR Debug Fault Status Register 0xD30 32 read-write 0 0xFFFFFFFF HALTED Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1. 0 1 read-write HALTED_0 No active halt request debug event 0 HALTED_1 Halt request debug event active 0x1 BKPT Debug event generated by BKPT instruction execution or a breakpoint match in FPB 1 1 read-write BKPT_0 No current breakpoint debug event 0 BKPT_1 At least one current breakpoint debug event 0x1 DWTTRAP Debug event generated by the DWT 2 1 read-write DWTTRAP_0 No current debug events generated by the DWT 0 DWTTRAP_1 At least one current debug event generated by the DWT 0x1 VCATCH Indicates triggering of a Vector catch 3 1 read-write VCATCH_0 No Vector catch triggered 0 VCATCH_1 Vector catch triggered 0x1 EXTERNAL Debug event generated because of the assertion of an external debug request 4 1 read-write EXTERNAL_0 No external debug request debug event 0 EXTERNAL_1 External debug request debug event 0x1 MMFAR MemManage Fault Address Register 0xD34 32 read-write 0 0xFFFFFFFF ADDRESS Address of MemManage fault location 0 32 read-write BFAR BusFault Address Register 0xD38 32 read-write 0 0xFFFFFFFF ADDRESS Address of the BusFault location 0 32 read-write ID_PFR0 Processor Feature Register 0 0xD40 32 read-only 0 0xFFFFFFFF STATE0 ARM instruction set support 0 4 read-only STATE0_0 ARMv7-M unused 0 STATE0_1 ARMv7-M unused 0x1 STATE0_2 ARMv7-M unused 0x2 STATE0_3 Support for Thumb encoding including Thumb-2 technology, with all basic 16-bit and 32-bit instructions. 0x3 STATE1 Thumb instruction set support 4 4 read-only STATE1_0 The processor does not support the ARM instruction set. 0 STATE1_1 ARMv7-M unused 0x1 STATE2 ARMv7-M unused 8 4 read-only STATE3 ARMv7-M unused 12 4 read-only ID_PFR1 Processor Feature Register 1 0xD44 32 read-only 0 0xFFFFFFFF PROGMODEL M profile programmers' model 8 4 read-only PROGMODEL_0 ARMv7-M unused 0 PROGMODEL_2 Two-stack programmers' model supported 0x2 ID_DFR0 Debug Feature Register 0xD48 32 read-only 0 0xFFFFFFFF DEBUGMODEL Support for memory-mapped debug model for M profile processors 20 4 read-only DEBUGMODEL_0 Not supported 0 DEBUGMODEL_1 Support for M profile Debug architecture, with memory-mapped access. 0x1 ID_AFR0 Auxiliary Feature Register 0xD4C 32 read-only 0 0xFFFFFFFF IMPLEMENTATION_DEFINED0 Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. 0 4 read-only IMPLEMENTATION_DEFINED1 Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. 4 4 read-only IMPLEMENTATION_DEFINED2 Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. 8 4 read-only IMPLEMENTATION_DEFINED3 Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. 12 4 read-only ID_MMFR0 Memory Model Feature Register 0 0xD50 32 read-only 0 0xFFFFFFFF PMSASUPPORT Indicates support for a PMSA 4 4 read-only PMSASUPPORT_0 Not supported 0 PMSASUPPORT_1 ARMv7-M unused 0x1 PMSASUPPORT_2 ARMv7-M unused 0x2 PMSASUPPORT_3 PMSAv7, providing support for a base region and subregions. 0x3 OUTERMOST_SHAREABILITY Indicates the outermost shareability domain implemented 8 4 read-only OUTERMOST_SHAREABILITY_0 Implemented as Non-cacheable 0 OUTERMOST_SHAREABILITY_1 ARMv7-M unused 0x1 OUTERMOST_SHAREABILITY_2 ARMv7-M unused 0x2 OUTERMOST_SHAREABILITY_3 ARMv7-M unused 0x3 OUTERMOST_SHAREABILITY_4 ARMv7-M unused 0x4 OUTERMOST_SHAREABILITY_5 ARMv7-M unused 0x5 OUTERMOST_SHAREABILITY_6 ARMv7-M unused 0x6 OUTERMOST_SHAREABILITY_7 ARMv7-M unused 0x7 OUTERMOST_SHAREABILITY_8 ARMv7-M unused 0x8 OUTERMOST_SHAREABILITY_9 ARMv7-M unused 0x9 OUTERMOST_SHAREABILITY_10 ARMv7-M unused 0xA OUTERMOST_SHAREABILITY_11 ARMv7-M unused 0xB OUTERMOST_SHAREABILITY_12 ARMv7-M unused 0xC OUTERMOST_SHAREABILITY_13 ARMv7-M unused 0xD OUTERMOST_SHAREABILITY_14 ARMv7-M unused 0xE OUTERMOST_SHAREABILITY_15 Shareability ignored. 0xF SHAREABILITY_LEVELS Indicates the number of shareability levels implemented 12 4 read-only SHAREABILITY_LEVELS_0 One level of shareability implemented 0 SHAREABILITY_LEVELS_1 ARMv7-M unused 0x1 TCM_SUPPORT Indicates the support for Tightly Coupled Memory 16 4 read-only TCM_SUPPORT_0 No tightly coupled memories implemented. 0 TCM_SUPPORT_1 Tightly coupled memories implemented with IMPLEMENTATION DEFINED control. 0x1 TCM_SUPPORT_2 ARMv7-M unused 0x2 AUXILIARY_REGISTERS Indicates the support for Auxiliary registers 20 4 read-only AUXILIARY_REGISTERS_0 Not supported 0 AUXILIARY_REGISTERS_1 Support for Auxiliary Control Register only. 0x1 AUXILIARY_REGISTERS_2 ARMv7-M unused 0x2 ID_MMFR1 Memory Model Feature Register 1 0xD54 32 read-only 0 0xFFFFFFFF ID_MMFR1 Gives information about the implemented memory model and memory management support. 0 32 read-only ID_MMFR2 Memory Model Feature Register 2 0xD58 32 read-only 0 0xFFFFFFFF WFI_STALL Indicates the support for Wait For Interrupt (WFI) stalling 24 4 read-only WFI_STALL_0 Not supported 0 WFI_STALL_1 Support for WFI stalling 0x1 ID_MMFR3 Memory Model Feature Register 3 0xD5C 32 read-only 0 0xFFFFFFFF ID_MMFR3 Gives information about the implemented memory model and memory management support. 0 32 read-only ID_ISAR0 Instruction Set Attributes Register 0 0xD60 32 read-only 0 0xFFFFFFFF BITCOUNT_INSTRS Indicates the supported Bit Counting instructions 4 4 read-only BITCOUNT_INSTRS_0 None supported, ARMv7-M unused 0 BITCOUNT_INSTRS_1 Adds support for the CLZ instruction 0x1 BITFIELD_INSTRS Indicates the supported BitField instructions 8 4 read-only BITFIELD_INSTRS_0 None supported, ARMv7-M unused 0 BITFIELD_INSTRS_1 Adds support for the BFC, BFI, SBFX, and UBFX instructions 0x1 CMPBRANCH_INSTRS Indicates the supported combined Compare and Branch instructions 12 4 read-only CMPBRANCH_INSTRS_0 None supported, ARMv7-M unused 0 CMPBRANCH_INSTRS_1 Adds support for the CBNZ and CBZ instructions 0x1 COPROC_INSTRS Indicates the supported Coprocessor instructions 16 4 read-only COPROC_INSTRS_0 None supported, except for separately attributed architectures, for example the Floating-point extension 0 COPROC_INSTRS_1 Adds support for generic CDP, LDC, MCR, MRC, and STC instructions 0x1 COPROC_INSTRS_2 As for 1, and adds support for generic CDP2, LDC2, MCR2, MRC2, and STC2 instructions 0x2 COPROC_INSTRS_3 As for 2, and adds support for generic MCRR and MRRC instructions 0x3 COPROC_INSTRS_4 As for 3, and adds support for generic MCRR2 and MRRC2 instructions 0x4 DEBUG_INSTRS Indicates the supported Debug instructions 20 4 read-only DEBUG_INSTRS_0 None supported, ARMv7-M unused 0 DEBUG_INSTRS_1 Adds support for the BKPT instruction 0x1 DIVIDE_INSTRS Indicates the supported Divide instructions 24 4 read-only DIVIDE_INSTRS_0 None supported, ARMv7-M unused 0 DIVIDE_INSTRS_1 Adds support for the SDIV and UDIV instructions 0x1 ID_ISAR1 Instruction Set Attributes Register 1 0xD64 32 read-only 0 0xFFFFFFFF EXTEND_INSTRS Indicates the supported Extend instructions 12 4 read-only EXTEND_INSTRS_0 None supported, ARMv7-M unused 0 EXTEND_INSTRS_1 Adds support for the SXTB, SXTH, UXTB, and UXTH instructions 0x1 EXTEND_INSTRS_2 As for 1, and adds support for the SXTAB, SXTAB16, SXTAH, SXTB16, UXTAB, UXTAB16, UXTAH, and UXTB16 instructions 0x2 IFTHEN_INSTRS Indicates the supported IfThen instructions 16 4 read-only IFTHEN_INSTRS_0 None supported, ARMv7-M unused 0 IFTHEN_INSTRS_1 Adds support for the IT instructions, and for the IT bits in the PSRs 0x1 IMMEDIATE_INSTRS Indicates the support for data-processing instructions with long immediate 20 4 read-only IMMEDIATE_INSTRS_0 None supported, ARMv7-M unused 0 IMMEDIATE_INSTRS_1 Adds support for the ADDW, MOVW, MOVT, and SUBW instructions 0x1 INTERWORK_INSTRS Indicates the supported Interworking instructions 24 4 read-only INTERWORK_INSTRS_0 None supported, ARMv7-M unused 0 INTERWORK_INSTRS_1 Adds support for the BX instruction, and the T bit in the PSR 0x1 INTERWORK_INSTRS_2 As for 1, and adds support for the BLX instruction, and PC loads have BX-like behavior 0x2 INTERWORK_INSTRS_3 ARMv7-M unused 0x3 ID_ISAR2 Instruction Set Attributes Register 2 0xD68 32 read-only 0 0xFFFFFFFF LOADSTORE_INSTRS Indicates the supported additional load and store instructions 0 4 read-only LOADSTORE_INSTRS_0 None supported, ARMv7-M unused 0 LOADSTORE_INSTRS_1 Adds support for the LDRD and STRD instructions 0x1 MEMHINT_INSTRS Indicates the supported Memory Hint instructions 4 4 read-only MEMHINT_INSTRS_0 None supported, ARMv7-M unused. 0 MEMHINT_INSTRS_1 Adds support for the PLD instruction, ARMv7-M unused. 0x1 MEMHINT_INSTRS_2 As for 1, ARMv7-M unused. 0x2 MEMHINT_INSTRS_3 As for 1 or 2, and adds support for the PLI instruction. 0x3 MULTIACCESSINT_INSTRS Indicates the support for multi-access interruptible instructions 8 4 read-only MULTIACCESSINT_INSTRS_0 None supported. This means the LDM and STM instructions are not interruptible. ARMv7-M unused. 0 MULTIACCESSINT_INSTRS_1 LDM and STM instructions are restartable. 0x1 MULTIACCESSINT_INSTRS_2 LDM and STM instructions are continuable. 0x2 MULT_INSTRS Indicates the supported additional Multiply instructions 12 4 read-only MULT_INSTRS_0 None supported. This means only MUL is supported. ARMv7-M unused. 0 MULT_INSTRS_1 Adds support for the MLA instruction, ARMv7-M unused. 0x1 MULT_INSTRS_2 As for 1, and adds support for the MLS instruction. 0x2 MULTS_INSTRS Indicates the supported advanced signed Multiply instructions 16 4 read-only MULTS_INSTRS_0 None supported, ARMv7-M unused 0 MULTS_INSTRS_1 Adds support for the SMULL and SMLAL instructions 0x1 MULTS_INSTRS_2 As for 1, and adds support for the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions. 0x2 MULTS_INSTRS_3 As for 2, and adds support for the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions. 0x3 MULTU_INSTRS Indicates the supported advanced unsigned Multiply instructions 20 4 read-only MULTU_INSTRS_0 None supported, ARMv7-M unused 0 MULTU_INSTRS_1 Adds support for the UMULL and UMLAL instructions. 0x1 MULTU_INSTRS_2 As for 1, and adds support for the UMAAL instruction. 0x2 REVERSAL_INSTRS Indicates the supported Reversal instructions 28 4 read-only REVERSAL_INSTRS_0 None supported, ARMv7-M unused 0 REVERSAL_INSTRS_1 Adds support for the REV, REV16, and REVSH instructions, ARMv7-M unused. 0x1 REVERSAL_INSTRS_2 As for 1, and adds support for the RBIT instruction. 0x2 ID_ISAR3 Instruction Set Attributes Register 3 0xD6C 32 read-only 0 0xFFFFFFFF SATURATE_INSTRS Indicates the supported Saturate instructions 0 4 read-only SATURATE_INSTRS_0 None supported 0 SATURATE_INSTRS_1 Adds support for the QADD, QDADD, QDSUB, and QSUB instructions, and for the Q bit in the PSRs. 0x1 SIMD_INSTRS Indicates the supported SIMD instructions 4 4 read-only SIMD_INSTRS_0 None supported, ARMv7-M unused. 0 SIMD_INSTRS_1 Adds support for the SSAT and USAT instructions, and for the Q bit in the PSRs. 0x1 SIMD_INSTRS_3 As for 1, and adds support for the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions. Also adds support for the GE[3:0] bits in the PSRs. 0x3 SVC_INSTRS Indicates the supported SVC instructions 8 4 read-only SVC_INSTRS_0 None supported, ARMv7-M unused. 0 SVC_INSTRS_1 Adds support for the SVC instruction. 0x1 SYNCHPRIM_INSTRS Together with the ID_ISAR4[SYNCHPRIM_INSTRS_FRAC] indicates the supported Synchronization Primitives 12 4 read-only TABBRANCH_INSTRS Indicates the supported Table Branch instructions 16 4 read-only TABBRANCH_INSTRS_0 None supported, ARMv7-M unused. 0 TABBRANCH_INSTRS_1 Adds support for the TBB and TBH instructions. 0x1 THUMBCOPY_INSTRS Indicates the supported non flag-setting MOV instructions 20 4 read-only THUMBCOPY_INSTRS_0 None supported, ARMv7-M unused. 0 THUMBCOPY_INSTRS_1 Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. 0x1 TRUENOP_INSTRS Indicates the supported non flag-setting MOV instructions 24 4 read-only TRUENOP_INSTRS_0 None supported, ARMv7-M unused. 0 TRUENOP_INSTRS_1 Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. 0x1 ID_ISAR4 Instruction Set Attributes Register 4 0xD70 32 read-only 0 0xFFFFFFFF UNPRIV_INSTRS Indicates the supported unprivileged instructions. These are the instruction variants indicated by a T suffix. 0 4 read-only UNPRIV_INSTRS_0 None supported, ARMv7-M unused. 0 UNPRIV_INSTRS_1 Adds support for the LDRBT, LDRT, STRBT, and STRT instructions. 0x1 UNPRIV_INSTRS_2 As for 1, and adds support for the LDRHT, LDRSBT, LDRSHT, and STRHT instructions. 0x2 WITHSHIFTS_INSTRS Indicates the support for instructions with shifts 4 4 read-only WITHSHIFTS_INSTRS_0 Nonzero shifts supported only in MOV and shift instructions. 0 WITHSHIFTS_INSTRS_1 Adds support for shifts of loads and stores over the range LSL 0-3. 0x1 WITHSHIFTS_INSTRS_3 As for 1, and adds support for other constant shift options, on loads, stores, and other instructions. 0x3 WITHSHIFTS_INSTRS_4 ARMv7-M unused. 0x4 WRITEBACK_INSTRS Indicates the support for Writeback addressing modes 8 4 read-only WRITEBACK_INSTRS_0 Basic support. Only the LDM, STM, PUSH, and POP instructions support writeback addressing modes. ARMv7-M unused. 0 WRITEBACK_INSTRS_1 Adds support for all of the writeback addressing modes defined in the ARMv7-M architecture. 0x1 BARRIER_INSTRS Indicates the supported Barrier instructions 16 4 read-only BARRIER_INSTRS_0 None supported, ARMv7-M unused. 0 BARRIER_INSTRS_1 Adds support for the DMB, DSB, and ISB barrier instructions. 0x1 SYNCHPRIM_INSTRS_FRAC Together with the ID_ISAR3[SYNCHPRIM_INSTRS] indicates the supported Synchronization Primitives 20 4 read-only PSR_M_INSTRS Indicates the supported M profile instructions to modify the PSRs 24 4 read-only PSR_M_INSTRS_0 None supported, ARMv7-M unused. 0 PSR_M_INSTRS_1 Adds support for the M-profile forms of the CPS, MRS, and MSR instructions, to access the PSRs. 0x1 CLIDR Cache Level ID register 0xD78 32 read-only 0 0xFFFFFFFF CL1 Indicate the type of cache implemented at level 1. 0 3 read-only CL1_0 No cache 0 CL1_1 Instruction cache only 0x1 CL1_2 Data cache only 0x2 CL1_3 Separate instruction and data caches 0x3 CL1_4 Unified cache 0x4 CL2 Indicate the type of cache implemented at level 2. 3 3 read-only CL2_0 No cache 0 CL2_1 Instruction cache only 0x1 CL2_2 Data cache only 0x2 CL2_3 Separate instruction and data caches 0x3 CL2_4 Unified cache 0x4 CL3 Indicate the type of cache implemented at level 3. 6 3 read-only CL3_0 No cache 0 CL3_1 Instruction cache only 0x1 CL3_2 Data cache only 0x2 CL3_3 Separate instruction and data caches 0x3 CL3_4 Unified cache 0x4 CL4 Indicate the type of cache implemented at level 4. 9 3 read-only CL4_0 No cache 0 CL4_1 Instruction cache only 0x1 CL4_2 Data cache only 0x2 CL4_3 Separate instruction and data caches 0x3 CL4_4 Unified cache 0x4 CL5 Indicate the type of cache implemented at level 5. 12 3 read-only CL5_0 No cache 0 CL5_1 Instruction cache only 0x1 CL5_2 Data cache only 0x2 CL5_3 Separate instruction and data caches 0x3 CL5_4 Unified cache 0x4 CL6 Indicate the type of cache implemented at level 6. 15 3 read-only CL6_0 No cache 0 CL6_1 Instruction cache only 0x1 CL6_2 Data cache only 0x2 CL6_3 Separate instruction and data caches 0x3 CL6_4 Unified cache 0x4 CL7 Indicate the type of cache implemented at level 7. 18 3 read-only CL7_0 No cache 0 CL7_1 Instruction cache only 0x1 CL7_2 Data cache only 0x2 CL7_3 Separate instruction and data caches 0x3 CL7_4 Unified cache 0x4 LOUIS Level of Unification Inner Shareable for the cache hierarchy. This field is RAZ. 21 3 read-only LOUIS_0 0 0 LOUIS_1 1 0x1 LOUIS_2 2 0x2 LOUIS_3 3 0x3 LOUIS_4 4 0x4 LOUIS_5 5 0x5 LOUIS_6 6 0x6 LOUIS_7 7 0x7 LOC Level of Coherency for the cache hierarchy 24 3 read-only LOC_0 0 0 LOC_1 1 0x1 LOC_2 2 0x2 LOC_3 3 0x3 LOC_4 4 0x4 LOC_5 5 0x5 LOC_6 6 0x6 LOC_7 7 0x7 LOU Level of Unification for the cache hierarchy 27 3 read-only LOU_0 0 0 LOU_1 1 0x1 LOU_2 2 0x2 LOU_3 3 0x3 LOU_4 4 0x4 LOU_5 5 0x5 LOU_6 6 0x6 LOU_7 7 0x7 CTR Cache Type register 0xD7C 32 read-only 0x8000C000 0xFFFFFFFF IMINLINE Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor. 0 4 read-only DMINLINE Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor. 16 4 read-only ERG Exclusives Reservation Granule. The maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions, encoded as Log2 of the number of words. 20 4 read-only CWG Cache Write-back Granule. The maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified, encoded as Log2 of the number of words. 24 4 read-only FORMAT Indicates the implemented CTR format. 29 3 read-only FORMAT_4 ARMv7 format. 0x4 CCSIDR Cache Size ID Register 0xD80 32 read-only 0 0xFFFFFFFF LINESIZE (Log2(Number of words in cache line)) - 2. 0 3 read-only LINESIZE_0 The line length of 4 words. 0 LINESIZE_1 The line length of 8 words. 0x1 LINESIZE_2 The line length of 16 words. 0x2 LINESIZE_3 The line length of 32 words. 0x3 LINESIZE_4 The line length of 64 words. 0x4 LINESIZE_5 The line length of 128 words. 0x5 LINESIZE_6 The line length of 256 words. 0x6 LINESIZE_7 The line length of 512 words. 0x7 ASSOCIATIVITY (Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2. 3 10 read-only NUMSETS (Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2. 13 15 read-only WA Indicates whether the cache level supports write-allocation 28 1 read-only WA_0 Feature not supported 0 WA_1 Feature supported 0x1 RA Indicates whether the cache level supports read-allocation 29 1 read-only RA_0 Feature not supported 0 RA_1 Feature supported 0x1 WB Indicates whether the cache level supports write-back 30 1 read-only WB_0 Feature not supported 0 WB_1 Feature supported 0x1 WT Indicates whether the cache level supports write-through 31 1 read-only WT_0 Feature not supported 0 WT_1 Feature supported 0x1 CSSELR Cache Size Selection Register 0xD84 32 read-write 0 0xFFFFFFFF IND Instruction not data bit 0 1 read-write IND_0 Data or unified cache. 0 IND_1 Instruction cache. 0x1 LEVEL Cache level of required cache 1 3 read-write LEVEL_0 Level 1 cache. 0 LEVEL_1 Level 2 cache. 0x1 LEVEL_2 Level 3 cache. 0x2 LEVEL_3 Level 4 cache. 0x3 LEVEL_4 Level 5 cache. 0x4 LEVEL_5 Level 6 cache. 0x5 LEVEL_6 Level 7 cache. 0x6 CPACR Coprocessor Access Control Register 0xD88 32 read-write 0 0xFFFFFFFF CP0 Access privileges for coprocessor 0. 0 2 read-write CP0_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP0_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP0_3 Full access. 0x3 CP1 Access privileges for coprocessor 1. 2 2 read-write CP1_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP1_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP1_3 Full access. 0x3 CP2 Access privileges for coprocessor 2. 4 2 read-write CP2_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP2_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP2_3 Full access. 0x3 CP3 Access privileges for coprocessor 3. 6 2 read-write CP3_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP3_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP3_3 Full access. 0x3 CP4 Access privileges for coprocessor 4. 8 2 read-write CP4_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP4_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP4_3 Full access. 0x3 CP5 Access privileges for coprocessor 5. 10 2 read-write CP5_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP5_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP5_3 Full access. 0x3 CP6 Access privileges for coprocessor 6. 12 2 read-write CP6_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP6_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP6_3 Full access. 0x3 CP7 Access privileges for coprocessor 7. 14 2 read-write CP7_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP7_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP7_3 Full access. 0x3 CP10 Access privileges for coprocessor 10. 20 2 read-write CP10_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP10_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP10_3 Full access. 0x3 CP11 Access privileges for coprocessor 11. 22 2 read-write CP11_0 Access denied. Any attempted access generates a NOCP UsageFault. 0 CP11_1 Privileged access only. An unprivileged access generates a NOCP UsageFault. 0x1 CP11_3 Full access. 0x3 STIR Instruction cache invalidate all to Point of Unification (PoU) 0xF00 32 read-write 0 0xFFFFFFFF INTID Indicates the interrupt to be triggered 0 9 write-only ICIALLU Instruction cache invalidate all to Point of Unification (PoU) 0xF50 32 write-only 0 0xFFFFFFFF ICIALLU I-cache invalidate all to PoU 0 32 write-only ICIMVAU Instruction cache invalidate by address to PoU 0xF58 32 write-only 0 0xFFFFFFFF ICIMVAU I-cache invalidate by MVA to PoU 0 32 write-only DCIMVAC Data cache invalidate by address to Point of Coherency (PoC) 0xF5C 32 write-only 0 0xFFFFFFFF DCIMVAC D-cache invalidate by MVA to PoC 0 32 write-only DCISW Data cache invalidate by set/way 0xF60 32 write-only 0 0xFFFFFFFF DCISW D-cache invalidate by set-way 0 32 write-only DCCMVAU Data cache by address to PoU 0xF64 32 write-only 0 0xFFFFFFFF DCCMVAU D-cache clean by MVA to PoU 0 32 write-only DCCMVAC Data cache clean by address to PoC 0xF68 32 write-only 0 0xFFFFFFFF DCCMVAC D-cache clean by MVA to PoC 0 32 write-only DCCSW Data cache clean by set/way 0xF6C 32 write-only 0 0xFFFFFFFF DCCSW D-cache clean by set-way 0 32 write-only DCCIMVAC Data cache clean and invalidate by address to PoC 0xF70 32 write-only 0 0xFFFFFFFF DCCIMVAC D-cache clean and invalidate by MVA to PoC 0 32 write-only DCCISW Data cache clean and invalidate by set/way 0xF74 32 write-only 0 0xFFFFFFFF DCCISW D-cache clean and invalidate by set-way 0 32 write-only CM7_ITCMCR Instruction Tightly-Coupled Memory Control Register 0xF90 32 read-write 0 0xFFFFFFFF EN TCM enable. When a TCM is disabled all accesses are made to the AXIM interface. 0 1 read-write EN_0 TCM disabled. 0 EN_1 TCM enabled. 0x1 RMW Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence. 1 1 read-write RMW_0 RMW disabled. 0 RMW_1 RMW enabled. 0x1 RETEN Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access. 2 1 read-write RETEN_0 Retry phase disabled. 0 RETEN_1 Retry phase enabled. 0x1 SZ TCM size. Indicates the size of the relevant TCM. 3 4 read-only SZ_0 No TCM implemented. 0 SZ_3 4KB. 0x3 SZ_4 8KB. 0x4 SZ_5 16KB. 0x5 SZ_6 32KB. 0x6 SZ_7 64KB. 0x7 SZ_8 128KB. 0x8 SZ_9 256KB. 0x9 SZ_10 512KB. 0xA SZ_11 1MB. 0xB SZ_12 2MB. 0xC SZ_13 4MB. 0xD SZ_14 8MB. 0xE SZ_15 16MB. 0xF CM7_DTCMCR Data Tightly-Coupled Memory Control Register 0xF94 32 read-write 0 0xFFFFFFFF EN TCM enable. When a TCM is disabled all accesses are made to the AXIM interface. 0 1 read-write EN_0 TCM disabled. 0 EN_1 TCM enabled. 0x1 RMW Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence. 1 1 read-write RMW_0 RMW disabled. 0 RMW_1 RMW enabled. 0x1 RETEN Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access. 2 1 read-write RETEN_0 Retry phase disabled. 0 RETEN_1 Retry phase enabled. 0x1 SZ TCM size. Indicates the size of the relevant TCM. 3 4 read-only SZ_0 No TCM implemented. 0 SZ_3 4KB. 0x3 SZ_4 8KB. 0x4 SZ_5 16KB. 0x5 SZ_6 32KB. 0x6 SZ_7 64KB. 0x7 SZ_8 128KB. 0x8 SZ_9 256KB. 0x9 SZ_10 512KB. 0xA SZ_11 1MB. 0xB SZ_12 2MB. 0xC SZ_13 4MB. 0xD SZ_14 8MB. 0xE SZ_15 16MB. 0xF CM7_AHBPCR AHBP Control Register 0xF98 32 read-write 0 0xFFFFFFFF EN AHBP enable. 0 1 read-write EN_0 AHBP disabled. When disabled all accesses are made to the AXIM interface. 0 EN_1 AHBP enabled. 0x1 SZ AHBP size. 1 3 read-only SZ_0 0MB. AHBP disabled. 0 SZ_1 64MB. 0x1 SZ_2 128MB. 0x2 SZ_3 256MB. 0x3 SZ_4 512MB. 0x4 CM7_CACR L1 Cache Control Register 0xF9C 32 read-write 0 0xFFFFFFFF SIWT Shared cacheable-is-WT for data cache. Enables limited cache coherency usage. 0 1 read-write SIWT_0 Normal Cacheable Shared locations are treated as being Non-cacheable. Default mode of operation for Shared memory. 0 SIWT_1 Normal Cacheable shared locations are treated as Write-Through. 0x1 ECCDIS Enables ECC in the instruction and data cache. 1 1 read-write ECCDIS_0 Enables ECC in the instruction and data cache. 0 ECCDIS_1 Disables ECC in the instruction and data cache. 0x1 FORCEWT Enables Force Write-Through in the data cache. 2 1 read-write FORCEWT_0 Disables Force Write-Through. 0 FORCEWT_1 Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through. 0x1 CM7_AHBSCR AHB Slave Control Register 0xFA0 32 read-write 0 0xFFFFFFFF CTL AHBS prioritization control. 0 2 read-write CTL_0 AHBS access priority demoted. This is the reset value. 0 CTL_1 Software access priority demoted. 0x1 CTL_2 AHBS access priority demoted by initializing the fairness counter to the CM7_AHBSCR[INITCOUNT] value when the software execution priority is higher than or equal to the threshold level programed in CM7_AHBSCR[TPRI]. 0x2 CTL_3 AHBSPRI signal has control of access priority. 0x3 TPRI Threshold execution priority for AHBS traffic demotion. 2 9 read-write INITCOUNT Fairness counter initialization value. 11 5 read-write CM7_ABFSR Auxiliary Bus Fault Status Register 0xFA8 32 read-write 0 0xFFFFFFFF ITCM Asynchronous fault on ITCM interface. 0 1 read-write DTCM Asynchronous fault on DTCM interface. 1 1 read-write AHBP Asynchronous fault on AHBP interface. 2 1 read-write AXIM Asynchronous fault on AXIM interface. 3 1 read-write EPPB Asynchronous fault on EPPB interface. 4 1 read-write AXIMTYPE Indicates the type of fault on the AXIM interface. Only valid when AXIM is 1. 8 2 read-write AXIMTYPE_0 OKAY. 0 AXIMTYPE_1 EXOKAY. 0x1 AXIMTYPE_2 SLVERR. 0x2 AXIMTYPE_3 DECERR. 0x3 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0 0xE04 registers DMA0 0 DMA1 1 DMA2 2 DMA3 3 DMA4 4 DMA5 5 DMA6 6 DMA7 7 DMA8 8 DMA9 9 DMA10 10 DMA11 11 DMA12 12 DMA13 13 DMA14 14 DMA15 15 DMA_ERROR 16 CTI0_ERROR 17 CTI1_ERROR 18 CORE 19 LPUART1 20 LPUART2 21 LPUART3 22 LPUART4 23 PIT 24 USB_OTG1 25 FLEXSPI 26 FLEXRAM 27 LPI2C1 28 LPI2C2 29 GPT1 30 GPT2 31 LPSPI1 32 LPSPI2 33 PWM1_0 34 PWM1_1 35 PWM1_2 36 PWM1_3 37 PWM1_FAULT 38 KPP 39 SRC 40 GPR_IRQ 41 CCM_1 42 CCM_2 43 EWM 44 WDOG2 45 SNVS_HP_WRAPPER 46 SNVS_HP_WRAPPER_TZ 47 SNVS_LP_WRAPPER 48 CSU 49 DCP 50 DCP_VMI 51 Reserved68 52 TRNG 53 Reserved70 54 Reserved71 55 SAI1 56 RTWDOG 57 SAI3_RX 58 SAI3_TX 59 SPDIF 60 PMU 61 XBAR1_IRQ_0_1_2_3 62 TEMP_LOW_HIGH 63 TEMP_PANIC 64 USB_PHY 65 GPC 66 ADC1 67 FLEXIO1 68 DCDC 69 GPIO1_Combined_0_15 70 GPIO1_Combined_16_31 71 GPIO2_Combined_0_15 72 GPIO5_Combined_0_15 73 WDOG1 74 ADC_ETC_IRQ0 75 ADC_ETC_IRQ1 76 ADC_ETC_IRQ2 77 ADC_ETC_IRQ3 78 ADC_ETC_ERROR_IRQ 79 NVICISER0 Interrupt Set Enable Register n 0 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write oneToClear NVICISER1 Interrupt Set Enable Register n 0x4 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write oneToClear NVICISER2 Interrupt Set Enable Register n 0x8 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write oneToClear NVICISER3 Interrupt Set Enable Register n 0xC 32 read-write 0 0xFFFFFFFF SETENA Interrupt set enable bits 0 32 read-write oneToClear NVICICER0 Interrupt Clear Enable Register n 0x80 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write oneToClear NVICICER1 Interrupt Clear Enable Register n 0x84 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write oneToClear NVICICER2 Interrupt Clear Enable Register n 0x88 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write oneToClear NVICICER3 Interrupt Clear Enable Register n 0x8C 32 read-write 0 0xFFFFFFFF CLRENA Interrupt clear-enable bits 0 32 read-write oneToClear NVICISPR0 Interrupt Set Pending Register n 0x100 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write oneToClear NVICISPR1 Interrupt Set Pending Register n 0x104 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write oneToClear NVICISPR2 Interrupt Set Pending Register n 0x108 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write oneToClear NVICISPR3 Interrupt Set Pending Register n 0x10C 32 read-write 0 0xFFFFFFFF SETPEND Interrupt set-pending bits 0 32 read-write oneToClear NVICICPR0 Interrupt Clear Pending Register n 0x180 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write oneToClear NVICICPR1 Interrupt Clear Pending Register n 0x184 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write oneToClear NVICICPR2 Interrupt Clear Pending Register n 0x188 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write oneToClear NVICICPR3 Interrupt Clear Pending Register n 0x18C 32 read-write 0 0xFFFFFFFF CLRPEND Interrupt clear-pending bits 0 32 read-write oneToClear NVICIABR0 Interrupt Active bit Register n 0x200 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIABR1 Interrupt Active bit Register n 0x204 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIABR2 Interrupt Active bit Register n 0x208 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIABR3 Interrupt Active bit Register n 0x20C 32 read-write 0 0xFFFFFFFF ACTIVE Interrupt active flags 0 32 read-write NVICIP0 Interrupt Priority Register 0 0x300 8 read-write 0 0xFF PRI0 Priority of the INT_DMA0 interrupt 0 4 4 read-write NVICIP1 Interrupt Priority Register 1 0x301 8 read-write 0 0xFF PRI1 Priority of the INT_DMA1 interrupt 1 4 4 read-write NVICIP2 Interrupt Priority Register 2 0x302 8 read-write 0 0xFF PRI2 Priority of the INT_DMA2 interrupt 2 4 4 read-write NVICIP3 Interrupt Priority Register 3 0x303 8 read-write 0 0xFF PRI3 Priority of the INT_DMA3 interrupt 3 4 4 read-write NVICIP4 Interrupt Priority Register 4 0x304 8 read-write 0 0xFF PRI4 Priority of the INT_DMA4 interrupt 4 4 4 read-write NVICIP5 Interrupt Priority Register 5 0x305 8 read-write 0 0xFF PRI5 Priority of the INT_DMA5 interrupt 5 4 4 read-write NVICIP6 Interrupt Priority Register 6 0x306 8 read-write 0 0xFF PRI6 Priority of the INT_DMA6 interrupt 6 4 4 read-write NVICIP7 Interrupt Priority Register 7 0x307 8 read-write 0 0xFF PRI7 Priority of the INT_DMA7 interrupt 7 4 4 read-write NVICIP8 Interrupt Priority Register 8 0x308 8 read-write 0 0xFF PRI8 Priority of the INT_DMA8 interrupt 8 4 4 read-write NVICIP9 Interrupt Priority Register 9 0x309 8 read-write 0 0xFF PRI9 Priority of the INT_DMA9 interrupt 9 4 4 read-write NVICIP10 Interrupt Priority Register 10 0x30A 8 read-write 0 0xFF PRI10 Priority of the INT_DMA10 interrupt 10 4 4 read-write NVICIP11 Interrupt Priority Register 11 0x30B 8 read-write 0 0xFF PRI11 Priority of the INT_DMA11 interrupt 11 4 4 read-write NVICIP12 Interrupt Priority Register 12 0x30C 8 read-write 0 0xFF PRI12 Priority of the INT_DMA12 interrupt 12 4 4 read-write NVICIP13 Interrupt Priority Register 13 0x30D 8 read-write 0 0xFF PRI13 Priority of the INT_DMA13 interrupt 13 4 4 read-write NVICIP14 Interrupt Priority Register 14 0x30E 8 read-write 0 0xFF PRI14 Priority of the INT_DMA14 interrupt 14 4 4 read-write NVICIP15 Interrupt Priority Register 15 0x30F 8 read-write 0 0xFF PRI15 Priority of the INT_DMA15 interrupt 15 4 4 read-write NVICIP16 Interrupt Priority Register 16 0x310 8 read-write 0 0xFF PRI16 Priority of the INT_DMA_ERROR interrupt 16 4 4 read-write NVICIP17 Interrupt Priority Register 17 0x311 8 read-write 0 0xFF PRI17 Priority of the INT_CTI0_ERROR interrupt 17 4 4 read-write NVICIP18 Interrupt Priority Register 18 0x312 8 read-write 0 0xFF PRI18 Priority of the INT_CTI1_ERROR interrupt 18 4 4 read-write NVICIP19 Interrupt Priority Register 19 0x313 8 read-write 0 0xFF PRI19 Priority of the INT_CORE interrupt 19 4 4 read-write NVICIP20 Interrupt Priority Register 20 0x314 8 read-write 0 0xFF PRI20 Priority of the INT_LPUART1 interrupt 20 4 4 read-write NVICIP21 Interrupt Priority Register 21 0x315 8 read-write 0 0xFF PRI21 Priority of the INT_LPUART2 interrupt 21 4 4 read-write NVICIP22 Interrupt Priority Register 22 0x316 8 read-write 0 0xFF PRI22 Priority of the INT_LPUART3 interrupt 22 4 4 read-write NVICIP23 Interrupt Priority Register 23 0x317 8 read-write 0 0xFF PRI23 Priority of the INT_LPUART4 interrupt 23 4 4 read-write NVICIP24 Interrupt Priority Register 24 0x318 8 read-write 0 0xFF PRI24 Priority of the INT_PIT interrupt 24 4 4 read-write NVICIP25 Interrupt Priority Register 25 0x319 8 read-write 0 0xFF PRI25 Priority of the INT_USB_OTG1 interrupt 25 4 4 read-write NVICIP26 Interrupt Priority Register 26 0x31A 8 read-write 0 0xFF PRI26 Priority of the INT_FLEXSPI interrupt 26 4 4 read-write NVICIP27 Interrupt Priority Register 27 0x31B 8 read-write 0 0xFF PRI27 Priority of the INT_FLEXRAM interrupt 27 4 4 read-write NVICIP28 Interrupt Priority Register 28 0x31C 8 read-write 0 0xFF PRI28 Priority of the INT_LPI2C1 interrupt 28 4 4 read-write NVICIP29 Interrupt Priority Register 29 0x31D 8 read-write 0 0xFF PRI29 Priority of the INT_LPI2C2 interrupt 29 4 4 read-write NVICIP30 Interrupt Priority Register 30 0x31E 8 read-write 0 0xFF PRI30 Priority of the INT_GPT1 interrupt 30 4 4 read-write NVICIP31 Interrupt Priority Register 31 0x31F 8 read-write 0 0xFF PRI31 Priority of the INT_GPT2 interrupt 31 4 4 read-write NVICIP32 Interrupt Priority Register 32 0x320 8 read-write 0 0xFF PRI32 Priority of the INT_LPSPI1 interrupt 32 4 4 read-write NVICIP33 Interrupt Priority Register 33 0x321 8 read-write 0 0xFF PRI33 Priority of the INT_LPSPI2 interrupt 33 4 4 read-write NVICIP34 Interrupt Priority Register 34 0x322 8 read-write 0 0xFF PRI34 Priority of the INT_PWM1_0 interrupt 34 4 4 read-write NVICIP35 Interrupt Priority Register 35 0x323 8 read-write 0 0xFF PRI35 Priority of the INT_PWM1_1 interrupt 35 4 4 read-write NVICIP36 Interrupt Priority Register 36 0x324 8 read-write 0 0xFF PRI36 Priority of the INT_PWM1_2 interrupt 36 4 4 read-write NVICIP37 Interrupt Priority Register 37 0x325 8 read-write 0 0xFF PRI37 Priority of the INT_PWM1_3 interrupt 37 4 4 read-write NVICIP38 Interrupt Priority Register 38 0x326 8 read-write 0 0xFF PRI38 Priority of the INT_PWM1_FAULT interrupt 38 4 4 read-write NVICIP39 Interrupt Priority Register 39 0x327 8 read-write 0 0xFF PRI39 Priority of the INT_KPP interrupt 39 4 4 read-write NVICIP40 Interrupt Priority Register 40 0x328 8 read-write 0 0xFF PRI40 Priority of the INT_SRC interrupt 40 4 4 read-write NVICIP41 Interrupt Priority Register 41 0x329 8 read-write 0 0xFF PRI41 Priority of the INT_GPR_IRQ interrupt 41 4 4 read-write NVICIP42 Interrupt Priority Register 42 0x32A 8 read-write 0 0xFF PRI42 Priority of the INT_CCM_1 interrupt 42 4 4 read-write NVICIP43 Interrupt Priority Register 43 0x32B 8 read-write 0 0xFF PRI43 Priority of the INT_CCM_2 interrupt 43 4 4 read-write NVICIP44 Interrupt Priority Register 44 0x32C 8 read-write 0 0xFF PRI44 Priority of the INT_EWM interrupt 44 4 4 read-write NVICIP45 Interrupt Priority Register 45 0x32D 8 read-write 0 0xFF PRI45 Priority of the INT_WDOG2 interrupt 45 4 4 read-write NVICIP46 Interrupt Priority Register 46 0x32E 8 read-write 0 0xFF PRI46 Priority of the INT_SNVS_HP_WRAPPER interrupt 46 4 4 read-write NVICIP47 Interrupt Priority Register 47 0x32F 8 read-write 0 0xFF PRI47 Priority of the INT_SNVS_HP_WRAPPER_TZ interrupt 47 4 4 read-write NVICIP48 Interrupt Priority Register 48 0x330 8 read-write 0 0xFF PRI48 Priority of the INT_SNVS_LP_WRAPPER interrupt 48 4 4 read-write NVICIP49 Interrupt Priority Register 49 0x331 8 read-write 0 0xFF PRI49 Priority of the INT_CSU interrupt 49 4 4 read-write NVICIP50 Interrupt Priority Register 50 0x332 8 read-write 0 0xFF PRI50 Priority of the INT_DCP interrupt 50 4 4 read-write NVICIP51 Interrupt Priority Register 51 0x333 8 read-write 0 0xFF PRI51 Priority of the INT_DCP_VMI interrupt 51 4 4 read-write NVICIP52 Interrupt Priority Register 52 0x334 8 read-write 0 0xFF PRI52 Priority of the INT_Reserved68 interrupt 52 4 4 read-write NVICIP53 Interrupt Priority Register 53 0x335 8 read-write 0 0xFF PRI53 Priority of the INT_TRNG interrupt 53 4 4 read-write NVICIP54 Interrupt Priority Register 54 0x336 8 read-write 0 0xFF PRI54 Priority of the INT_Reserved70 interrupt 54 4 4 read-write NVICIP55 Interrupt Priority Register 55 0x337 8 read-write 0 0xFF PRI55 Priority of the INT_Reserved71 interrupt 55 4 4 read-write NVICIP56 Interrupt Priority Register 56 0x338 8 read-write 0 0xFF PRI56 Priority of the INT_SAI1 interrupt 56 4 4 read-write NVICIP57 Interrupt Priority Register 57 0x339 8 read-write 0 0xFF PRI57 Priority of the INT_RTWDOG interrupt 57 4 4 read-write NVICIP58 Interrupt Priority Register 58 0x33A 8 read-write 0 0xFF PRI58 Priority of the INT_SAI3_RX interrupt 58 4 4 read-write NVICIP59 Interrupt Priority Register 59 0x33B 8 read-write 0 0xFF PRI59 Priority of the INT_SAI3_TX interrupt 59 4 4 read-write NVICIP60 Interrupt Priority Register 60 0x33C 8 read-write 0 0xFF PRI60 Priority of the INT_SPDIF interrupt 60 4 4 read-write NVICIP61 Interrupt Priority Register 61 0x33D 8 read-write 0 0xFF PRI61 Priority of the INT_PMU interrupt 61 4 4 read-write NVICIP62 Interrupt Priority Register 62 0x33E 8 read-write 0 0xFF PRI62 Priority of the INT_XBAR1_IRQ_0_1_2_3 interrupt 62 4 4 read-write NVICIP63 Interrupt Priority Register 63 0x33F 8 read-write 0 0xFF PRI63 Priority of the INT_TEMP_LOW_HIGH interrupt 63 4 4 read-write NVICIP64 Interrupt Priority Register 64 0x340 8 read-write 0 0xFF PRI64 Priority of the INT_TEMP_PANIC interrupt 64 4 4 read-write NVICIP65 Interrupt Priority Register 65 0x341 8 read-write 0 0xFF PRI65 Priority of the INT_USB_PHY interrupt 65 4 4 read-write NVICIP66 Interrupt Priority Register 66 0x342 8 read-write 0 0xFF PRI66 Priority of the INT_GPC interrupt 66 4 4 read-write NVICIP67 Interrupt Priority Register 67 0x343 8 read-write 0 0xFF PRI67 Priority of the INT_ADC1 interrupt 67 4 4 read-write NVICIP68 Interrupt Priority Register 68 0x344 8 read-write 0 0xFF PRI68 Priority of the INT_FLEXIO1 interrupt 68 4 4 read-write NVICIP69 Interrupt Priority Register 69 0x345 8 read-write 0 0xFF PRI69 Priority of the INT_DCDC interrupt 69 4 4 read-write NVICIP70 Interrupt Priority Register 70 0x346 8 read-write 0 0xFF PRI70 Priority of the INT_GPIO1_Combined_0_15 interrupt 70 4 4 read-write NVICIP71 Interrupt Priority Register 71 0x347 8 read-write 0 0xFF PRI71 Priority of the INT_GPIO1_Combined_16_31 interrupt 71 4 4 read-write NVICIP72 Interrupt Priority Register 72 0x348 8 read-write 0 0xFF PRI72 Priority of the INT_GPIO2_Combined_0_15 interrupt 72 4 4 read-write NVICIP73 Interrupt Priority Register 73 0x349 8 read-write 0 0xFF PRI73 Priority of the INT_GPIO5_Combined_0_15 interrupt 73 4 4 read-write NVICIP74 Interrupt Priority Register 74 0x34A 8 read-write 0 0xFF PRI74 Priority of the INT_WDOG1 interrupt 74 4 4 read-write NVICIP75 Interrupt Priority Register 75 0x34B 8 read-write 0 0xFF PRI75 Priority of the INT_ADC_ETC_IRQ0 interrupt 75 4 4 read-write NVICIP76 Interrupt Priority Register 76 0x34C 8 read-write 0 0xFF PRI76 Priority of the INT_ADC_ETC_IRQ1 interrupt 76 4 4 read-write NVICIP77 Interrupt Priority Register 77 0x34D 8 read-write 0 0xFF PRI77 Priority of the INT_ADC_ETC_IRQ2 interrupt 77 4 4 read-write NVICIP78 Interrupt Priority Register 78 0x34E 8 read-write 0 0xFF PRI78 Priority of the INT_ADC_ETC_IRQ3 interrupt 78 4 4 read-write NVICIP79 Interrupt Priority Register 79 0x34F 8 read-write 0 0xFF PRI79 Priority of the INT_ADC_ETC_ERROR_IRQ interrupt 79 4 4 read-write NVICSTIR Software Trigger Interrupt Register 0xE00 32 read-write 0 0xFFFFFFFF INTID Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. 0 9 read-write