60075 lines
2.5 MiB
60075 lines
2.5 MiB
<?xml version="1.0" encoding="utf-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
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xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<name>LPC43xx</name>
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<version>10</version>
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<description>Register cmsis file for LPC43xx parts</description>
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<cpu>
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<name>CM4</name>
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<revision>r0p0</revision>
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<endian>little</endian>
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<mpuPresent>0</mpuPresent>
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<fpuPresent>0</fpuPresent>
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<nvicPrioBits>3</nvicPrioBits>
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<vendorSystickConfig>0</vendorSystickConfig>
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</cpu>
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<!-- Bus Interface Properties -->
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<!-- Cortex-M4 is byte addressable -->
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<headerDefinitionsPrefix>LPC_</headerDefinitionsPrefix>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<size>32</size>
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<!-- changes:
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v1: from LPC18xxv16
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creg updated
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event router updated
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pmu pd_sleep0_mode settings updated w/o IO switch
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cgu added base clock 2 (for BASE_PERIPH_CLK)
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sgpio/spi added
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cgu/ccu updated
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gima updated
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v2: AES reset/clock/dma bits removed
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usart osr register added
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v5: ethernet updated
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- pmucon register removed in creg
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v6: sgpio regs updated ctr_status -> clr_status
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address offset fixed for idivc_ctrl and idivd_ctrl
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registers ppsctrl, auxnanoseconds, auxseconds removed
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register fifolvl removed
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schema v1.1 errors fixed
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v7: eeprom registers added
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v8: newly extracted
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event router
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CREG
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PMC
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v8: c_can clkdiv register bit description corrected.
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-->
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<peripherals>
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<peripheral>
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<name>SCT</name>
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<description>State Configurable Timer (SCT) with dither engine </description>
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<groupName>SCT</groupName>
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<baseAddress>0x40000000</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0xFFF</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>SCT</name>
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<value>10</value>
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</interrupt>
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<registers>
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<register>
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<name>CONFIG</name>
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<description>SCT configuration register</description>
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<addressOffset>0x000</addressOffset>
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<access>read-write</access>
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<resetValue>0x00007E00</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>UNIFY</name>
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<description>SCT operation</description>
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<bitRange>[0:0]</bitRange>
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<enumeratedValues>
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<name>ENUM</name>
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<enumeratedValue>
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<name>16_BIT</name>
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<description>16-bit.The SCT operates as two 16-bit counters named L and H.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>32_BIT</name>
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<description>32-bit. The SCT operates as a unified 32-bit counter.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>CLKMODE</name>
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<description>SCT clock mode</description>
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<bitRange>[2:1]</bitRange>
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<enumeratedValues>
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<name>ENUM</name>
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<enumeratedValue>
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<name>BUS_CLOCK</name>
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<description>Bus clock. The bus clock clocks the SCT and prescalers.</description>
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<value>0x0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>PRESCALED_BUS_CLOCK</name>
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<description>Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode.</description>
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<value>0x1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SCT_INPUT</name>
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<description>SCT Input. The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode.</description>
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<value>0x2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>RESERVED</name>
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<description>Reserved.</description>
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<value>0x3</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>CKSEL</name>
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<description>SCT clock select</description>
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<bitRange>[6:3]</bitRange>
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<enumeratedValues>
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<name>ENUM</name>
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<enumeratedValue>
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<name>RISING_EDGES_ON_INPU</name>
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<description>Rising edges on input 0.</description>
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<value>0x0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>FALLING_EDGES_ON_INP</name>
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<description>Falling edges on input 0.</description>
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<value>0x1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>RISING_EDGES_ON_INPU</name>
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<description>Rising edges on input 1.</description>
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<value>0x2</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>FALLING_EDGES_ON_INP</name>
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<description>Falling edges on input 1.</description>
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<value>0x3</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>RISING_EDGES_ON_INPU</name>
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<description>Rising edges on input 2.</description>
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<value>0x4</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>FALLING_EDGES_ON_INP</name>
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<description>Falling edges on input 2.</description>
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<value>0x5</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>RISING_EDGES_ON_INPU</name>
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<description>Rising edges on input 3.</description>
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<value>0x6</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>FALLING_EDGES_ON_INP</name>
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<description>Falling edges on input 3.</description>
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<value>0x7</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>RISING_EDGES_ON_INPU</name>
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<description>Rising edges on input 4.</description>
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<value>0x8</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>FALLING_EDGES_ON_INP</name>
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<description>Falling edges on input 4.</description>
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<value>0x9</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>RISING_EDGES_ON_INPU</name>
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<description>Rising edges on input 5.</description>
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<value>0xA</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>FALLING_EDGES_ON_INP</name>
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<description>Falling edges on input 5.</description>
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<value>0xB</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>RISING_EDGES_ON_INPU</name>
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<description>Rising edges on input 6.</description>
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<value>0xC</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>FALLING_EDGES_ON_INP</name>
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<description>Falling edges on input 6.</description>
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<value>0xD</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>RISING_EDGES_ON_INPU</name>
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<description>Rising edges on input 7.</description>
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<value>0xE</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>FALLING_EDGES_ON_INP</name>
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<description>Falling edges on input 7.</description>
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<value>0xF</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>NORELAOD_L</name>
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<description>A 1 in this bit prevents the lower match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.</description>
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<bitRange>[7:7]</bitRange>
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</field>
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<field>
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<name>NORELOAD_H</name>
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<description>A 1 in this bit prevents the higher match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.</description>
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<bitRange>[8:8]</bitRange>
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</field>
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<field>
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<name>INSYNC</name>
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<description>Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used.</description>
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<bitRange>[16:9]</bitRange>
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</field>
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<field>
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<name>AUTOLIMIT_L</name>
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<description>A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.</description>
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<bitRange>[17:17]</bitRange>
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</field>
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<field>
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<name>AUTOLIMIT_H</name>
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<description>A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.</description>
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<bitRange>[18:18]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved</description>
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<bitRange>[31:19]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>CTRL</name>
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<description>SCT control register</description>
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<addressOffset>0x004</addressOffset>
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<access>read-write</access>
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<resetValue>0x00040004</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>DOWN_L</name>
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<description>This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs.</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>STOP_L</name>
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<description>When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.</description>
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<bitRange>[1:1]</bitRange>
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</field>
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<field>
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<name>HALT_L</name>
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<description>When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation.</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>CLRCTR_L</name>
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<description>Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.</description>
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<bitRange>[3:3]</bitRange>
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</field>
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<field>
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<name>BIDIR_L</name>
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<description>L or unified counter direction select</description>
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<bitRange>[4:4]</bitRange>
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<enumeratedValues>
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<name>ENUM</name>
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<enumeratedValue>
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<name>UP</name>
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<description>Up. The counter counts up to its limit condition, then is cleared to zero.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>UPDOWN</name>
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<description>Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>PRE_L</name>
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<description>Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.</description>
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<bitRange>[12:5]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved</description>
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<bitRange>[15:13]</bitRange>
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</field>
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<field>
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<name>DOWN_H</name>
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<description>This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs.</description>
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<bitRange>[16:16]</bitRange>
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</field>
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<field>
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<name>STOP_H</name>
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<description>When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.</description>
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<bitRange>[17:17]</bitRange>
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</field>
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<field>
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<name>HALT_H</name>
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<description>When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation.</description>
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<bitRange>[18:18]</bitRange>
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</field>
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<field>
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<name>CLRCTR_H</name>
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<description>Writing a 1 to this bit clears the H counter. This bit always reads as 0.</description>
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<bitRange>[19:19]</bitRange>
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</field>
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<field>
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<name>BIDIR_H</name>
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<description>Direction select</description>
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<bitRange>[20:20]</bitRange>
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<enumeratedValues>
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<name>ENUM</name>
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<enumeratedValue>
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<name>UP</name>
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<description>Up. The H counter counts up to its limit condition, then is cleared to zero.</description>
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<value>0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>UPDOWN</name>
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<description>Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0.</description>
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<value>1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>PRE_H</name>
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<description>Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.</description>
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<bitRange>[28:21]</bitRange>
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</field>
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<field>
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<name>RESERVED</name>
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<description>Reserved</description>
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<bitRange>[31:29]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>LIMIT</name>
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<description>SCT limit register</description>
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<addressOffset>0x008</addressOffset>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>LIMMSK_L</name>
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<description>If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).</description>
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<bitRange>[15:0]</bitRange>
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</field>
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<field>
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<name>LIMMSK_H</name>
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<description>If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).</description>
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<bitRange>[31:16]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>HALT</name>
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<description>SCT halt condition register</description>
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<addressOffset>0x00C</addressOffset>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>HALTMSK_L</name>
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<description>If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).</description>
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<bitRange>[15:0]</bitRange>
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</field>
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<field>
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<name>HALTMSK_H</name>
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<description>If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).</description>
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<bitRange>[31:16]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>STOP</name>
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<description>SCT stop condition register</description>
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<addressOffset>0x010</addressOffset>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<fields>
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<field>
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<name>STOPMSK_L</name>
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<description>If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).</description>
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<bitRange>[15:0]</bitRange>
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</field>
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<field>
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<name>STOPMSK_H</name>
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<description>If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).</description>
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<bitRange>[31:16]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>START</name>
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<description>SCT start condition register</description>
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<addressOffset>0x014</addressOffset>
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<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STARTMSK_L</name>
|
|
<description>If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STARTMSK_H</name>
|
|
<description>If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DITHER</name>
|
|
<description>SCT dither condition register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DITHMSK_L</name>
|
|
<description>If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DITHMSK_H</name>
|
|
<description>If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNT</name>
|
|
<description>SCT counter register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTR_L</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CTR_H</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATE</name>
|
|
<description>SCT state register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATE_L</name>
|
|
<description>State variable.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATE_H</name>
|
|
<description>State variable.</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INPUT</name>
|
|
<description>SCT input register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AIN0</name>
|
|
<description>Real-time status of input 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN1</name>
|
|
<description>Real-time status of input 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN2</name>
|
|
<description>Real-time status of input 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN3</name>
|
|
<description>Real-time status of input 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN4</name>
|
|
<description>Real-time status of input 4.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN5</name>
|
|
<description>Real-time status of input 5.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN6</name>
|
|
<description>Real-time status of input 6.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIN7</name>
|
|
<description>Real-time status of input 7.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN0</name>
|
|
<description>Input 0 state synchronized to the SCT clock.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN1</name>
|
|
<description>Input 1 state synchronized to the SCT clock.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN2</name>
|
|
<description>Input 2 state synchronized to the SCT clock.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN3</name>
|
|
<description>Input 3 state synchronized to the SCT clock.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN4</name>
|
|
<description>Input 4 state synchronized to the SCT clock.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN5</name>
|
|
<description>Input 5 state synchronized to the SCT clock.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN6</name>
|
|
<description>Input 6 state synchronized to the SCT clock.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIN7</name>
|
|
<description>Input 7 state synchronized to the SCT clock.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGMODE</name>
|
|
<description>SCT match/capture registers mode register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGMOD_L</name>
|
|
<description>Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). 0 = registers operate as match registers. 1 = registers operate as capture registers.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REGMOD_H</name>
|
|
<description>Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTPUT</name>
|
|
<description>SCT output register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OUT</name>
|
|
<description>Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTPUTDIRCTRL</name>
|
|
<description>SCT output counter direction control register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETCLR0</name>
|
|
<description>Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR1</name>
|
|
<description>Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR2</name>
|
|
<description>Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR3</name>
|
|
<description>Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR4</name>
|
|
<description>Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR5</name>
|
|
<description>Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR6</name>
|
|
<description>Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR7</name>
|
|
<description>Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR8</name>
|
|
<description>Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR9</name>
|
|
<description>Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR10</name>
|
|
<description>Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR11</name>
|
|
<description>Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR12</name>
|
|
<description>Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR13</name>
|
|
<description>Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR14</name>
|
|
<description>Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[29:28]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLR15</name>
|
|
<description>Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INDEPENDENT</name>
|
|
<description>Independent. Set and clear do not depend on any counter.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>L_COUNTER</name>
|
|
<description>L counter. Set and clear are reversed when counter L or the unified counter is counting down.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_COUNTER</name>
|
|
<description>H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RES</name>
|
|
<description>SCT conflict resolution register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>O0RES</name>
|
|
<description>Effect of simultaneous set and clear on output 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR0 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR0 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O1RES</name>
|
|
<description>Effect of simultaneous set and clear on output 1.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR1 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR1 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O2RES</name>
|
|
<description>Effect of simultaneous set and clear on output 2.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR2 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_N_OR_S</name>
|
|
<description>Clear output n (or set based on the SETCLR2 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O3RES</name>
|
|
<description>Effect of simultaneous set and clear on output 3.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR3 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR3 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O4RES</name>
|
|
<description>Effect of simultaneous set and clear on output 4.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR4 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR4 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O5RES</name>
|
|
<description>Effect of simultaneous set and clear on output 5.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR5 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR5 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O6RES</name>
|
|
<description>Effect of simultaneous set and clear on output 6.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR6 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR6 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O7RES</name>
|
|
<description>Effect of simultaneous set and clear on output 7.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR7 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR7 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O8RES</name>
|
|
<description>Effect of simultaneous set and clear on output 8.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR8 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR8 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O9RES</name>
|
|
<description>Effect of simultaneous set and clear on output 9.</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR9 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR9 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O10RES</name>
|
|
<description>Effect of simultaneous set and clear on output 10.</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR10 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR10 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O11RES</name>
|
|
<description>Effect of simultaneous set and clear on output 11.</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR11 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR11 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O12RES</name>
|
|
<description>Effect of simultaneous set and clear on output 12.</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR12 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR12 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O13RES</name>
|
|
<description>Effect of simultaneous set and clear on output 13.</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR13 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR13 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O14RES</name>
|
|
<description>Effect of simultaneous set and clear on output 14.</description>
|
|
<bitRange>[29:28]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR14 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR14 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>O15RES</name>
|
|
<description>Effect of simultaneous set and clear on output 15.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_OUTPUT_OR_CLEAR</name>
|
|
<description>Set output (or clear based on the SETCLR15 field).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_OUTPUT_OR_SET</name>
|
|
<description>Clear output (or set based on the SETCLR15 field).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_OUTPUT</name>
|
|
<description>Toggle output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAREQ0</name>
|
|
<description>SCT DMA request 0 register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEV_00</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_01</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_02</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_03</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_04</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_05</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_06</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_07</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_08</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_09</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_010</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_011</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_012</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_013</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_014</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_015</name>
|
|
<description>If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRL0</name>
|
|
<description>A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRQ0</name>
|
|
<description>This read-only bit indicates the state of DMA Request 0</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAREQ1</name>
|
|
<description>SCT DMA request 1 register</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEV_10</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_11</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_12</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_13</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_14</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_15</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_16</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_17</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_18</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_19</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_110</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_111</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_112</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_113</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_114</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DEV_115</name>
|
|
<description>If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRL1</name>
|
|
<description>A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRQ1</name>
|
|
<description>This read-only bit indicates the state of DMA Request 1.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVEN</name>
|
|
<description>SCT event enable register</description>
|
|
<addressOffset>0x0F0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IEN0</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN1</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN2</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN3</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN4</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN5</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN6</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN7</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN8</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN9</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN10</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN11</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN12</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN13</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN14</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEN15</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVFLAG</name>
|
|
<description>SCT event flag register</description>
|
|
<addressOffset>0x0F4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLAG0</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG1</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG2</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG3</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG4</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG5</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG6</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG7</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG8</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG9</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG10</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG11</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG12</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG13</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG14</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLAG15</name>
|
|
<description>Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONEN</name>
|
|
<description>SCT conflict enable register</description>
|
|
<addressOffset>0x0F8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NCEN0</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN1</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN2</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN3</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN4</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN5</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN6</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN7</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN8</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN9</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN10</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN11</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN12</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN13</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN14</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCEN15</name>
|
|
<description>The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFLAG</name>
|
|
<description>SCT conflict flag register</description>
|
|
<addressOffset>0x0FC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NCFLAG0</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG1</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG2</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG3</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG4</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG5</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG6</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG7</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG8</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG9</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG10</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG11</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG12</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG13</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG14</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NCFLAG15</name>
|
|
<description>Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15).</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[29:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUSERRL</name>
|
|
<description>The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUSERRH</name>
|
|
<description>The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>MATCH%s</name>
|
|
<description>SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH_L</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MATCH_H</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>FRACMAT%s</name>
|
|
<description>Fractional match registers 0 to 5 for SCT match value registers 0 to 5.</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACMAT_L</name>
|
|
<description>When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRACMAT_H</name>
|
|
<description>When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5).</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>CAP%s</name>
|
|
<description>SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1</description>
|
|
<alternateRegister>MATCH%s</alternateRegister>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP_L</name>
|
|
<description>When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP_H</name>
|
|
<description>When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>MATCHREL%s</name>
|
|
<description>SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RELOAD_L</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RELOAD_H</name>
|
|
<description>When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>FRACMATREL%s</name>
|
|
<description>Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5.</description>
|
|
<addressOffset>0x240</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RELFRAC_L</name>
|
|
<description>When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RELFRAC_H</name>
|
|
<description>When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>CAPCTRL%s</name>
|
|
|
|
<description>SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1</description>
|
|
<alternateRegister>MATCHREL%s</alternateRegister>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPCON_L</name>
|
|
<description>If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPCON_H</name>
|
|
<description>If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31).</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>EV%s_STATE</name>
|
|
<description>SCT event state register 0</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATEMSK0</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK1</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK2</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK3</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK4</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK5</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK6</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK7</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK8</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK9</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK10</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK11</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK12</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK13</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK14</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK15</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK16</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK17</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK18</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK19</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK20</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK21</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK22</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK23</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK24</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK25</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK26</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK27</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK28</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK29</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK30</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STATEMSK31</name>
|
|
<description>If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31).</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>EV%s_CTRL</name>
|
|
<description>SCT event control register 0</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCHSEL</name>
|
|
<description>Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HEVENT</name>
|
|
<description>Select L/H counter. Do not set this bit if UNIFY = 1.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>L_STATE</name>
|
|
<description>L state. Selects the L state and the L match register selected by MATCHSEL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>H_STATE</name>
|
|
<description>H state. Selects the H state and the H match register selected by MATCHSEL.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTSEL</name>
|
|
<description>Input/output select</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT</name>
|
|
<description>Input. Selects the input selected by IOSEL.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT</name>
|
|
<description>Output. Selects the output selected by IOSEL.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IOSEL</name>
|
|
<description>Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IOCOND</name>
|
|
<description>Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>LOW</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISE</name>
|
|
<description>Rise</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALL</name>
|
|
<description>Fall</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>HIGH</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBMODE</name>
|
|
<description>Selects how the specified match and I/O condition are used and combined.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OR</name>
|
|
<description>OR. The event occurs when either the specified match or I/O condition occurs.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCH</name>
|
|
<description>MATCH. Uses the specified match only.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IO</name>
|
|
<description>IO. Uses the specified I/O condition only.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AND</name>
|
|
<description>AND. The event occurs when the specified match and I/O condition occur simultaneously.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATELD</name>
|
|
<description>This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STATEV_VALUE_IS_ADDE</name>
|
|
<description>STATEV value is added into STATE (the carry-out is ignored).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATEV_VALUE_IS_LOAD</name>
|
|
<description>STATEV value is loaded into STATE.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STATEV</name>
|
|
<description>This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.</description>
|
|
<bitRange>[19:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MATCHMEM</name>
|
|
<description>If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DIRECTION</name>
|
|
<description>Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.</description>
|
|
<bitRange>[22:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIRECTION_INDEPENDEN</name>
|
|
<description>Direction independent. This event is triggered regardless of the count direction.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTING_UP</name>
|
|
<description>Counting up. This event is triggered only during up-counting when BIDIR = 1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTING_DOWN</name>
|
|
<description>Counting down. This event is triggered only during down-counting when BIDIR = 1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:23]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>OUT%s_SET</name>
|
|
<description>SCT output 0 set register</description>
|
|
<addressOffset>0x500</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET0</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET1</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET2</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET3</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET4</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET5</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET6</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET7</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET8</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET9</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET10</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET11</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET12</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET13</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET14</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SET15</name>
|
|
<description>A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>OUT%s_CLR</name>
|
|
<description>SCT output 0 clear register</description>
|
|
<addressOffset>0x504</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR0</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR1</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR2</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR3</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR4</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR5</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR6</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR7</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR8</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR9</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR10</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR11</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR12</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR13</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR14</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR15</name>
|
|
<description>A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>GPDMA</name>
|
|
<description>General Purpose DMA (GPDMA) </description>
|
|
<groupName>GPDMA</groupName>
|
|
<baseAddress>0x40002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMA</name>
|
|
<value>2</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>DMA Interrupt Status Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTSTAT0</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT1</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT2</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT3</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT4</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT5</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT6</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTSTAT7</name>
|
|
<description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTTCSTAT</name>
|
|
<description>DMA Interrupt Terminal Count Request Status Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTTCSTAT0</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT1</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT2</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT3</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT4</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT5</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT6</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCSTAT7</name>
|
|
<description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTTCCLEAR</name>
|
|
<description>DMA Interrupt Terminal Count Request Clear Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTTCCLEAR0</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR1</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR2</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR3</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR4</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR5</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR6</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTTCCLEAR7</name>
|
|
<description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined. Write reserved bits as zero.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTERRSTAT</name>
|
|
<description>DMA Interrupt Error Status Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTERRSTAT0</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT1</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT2</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT3</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT4</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT5</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT6</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRSTAT7</name>
|
|
<description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTERRCLR</name>
|
|
<description>DMA Interrupt Error Clear Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTERRCLR0</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR1</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR2</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR3</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR4</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR5</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR6</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRCLR7</name>
|
|
<description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined. Write reserved bits as zero.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAWINTTCSTAT</name>
|
|
<description>DMA Raw Interrupt Terminal Count Status Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAWINTTCSTAT0</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT1</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT2</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT3</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT4</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT5</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT6</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTTCSTAT7</name>
|
|
<description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAWINTERRSTAT</name>
|
|
<description>DMA Raw Error Interrupt Status Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAWINTERRSTAT0</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT1</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT2</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT3</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT4</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT5</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT6</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWINTERRSTAT7</name>
|
|
<description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENBLDCHNS</name>
|
|
<description>DMA Enabled Channel Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLEDCHANNELS0</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS1</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS2</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS3</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS4</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS5</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS6</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENABLEDCHANNELS7</name>
|
|
<description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOFTBREQ</name>
|
|
<description>DMA Software Burst Request Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFTBREQ0</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ1</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ2</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ3</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ4</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ5</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ6</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ7</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ8</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ9</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ10</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ11</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ12</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ13</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ14</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTBREQ15</name>
|
|
<description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined. Write reserved bits as zero.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOFTSREQ</name>
|
|
<description>DMA Software Single Request Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFTSREQ0</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ1</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ2</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ3</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ4</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ5</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ6</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ7</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ8</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ9</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ10</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ11</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ12</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ13</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ14</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTSREQ15</name>
|
|
<description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined. Write reserved bits as zero.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOFTLBREQ</name>
|
|
<description>DMA Software Last Burst Request Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFTLBREQ0</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ1</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ2</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ3</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ4</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ5</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ6</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ7</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ8</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ9</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ10</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ11</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ12</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ13</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ14</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLBREQ15</name>
|
|
<description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined. Write reserved bits as zero.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOFTLSREQ</name>
|
|
<description>DMA Software Last Single Request Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFTLSREQ0</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ1</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ2</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ3</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ4</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ5</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ6</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ7</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ8</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ9</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ10</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ11</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ12</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ13</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ14</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SOFTLSREQ15</name>
|
|
<description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined. Write reserved bits as zero.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>DMA Configuration Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>E</name>
|
|
<description>DMA Controller enable:</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED__DEFAULT_</name>
|
|
<description>Disabled (default). Disabling the DMA Controller reduces power consumption.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M0</name>
|
|
<description>AHB Master 0 endianness configuration:</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LITTLE_ENDIAN_MODE</name>
|
|
<description>Little-endian mode (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIG_ENDIAN_MODE_</name>
|
|
<description>Big-endian mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M1</name>
|
|
<description>AHB Master 1 endianness configuration:</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LITTLE_ENDIAN_MODE</name>
|
|
<description>Little-endian mode (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIG_ENDIAN_MODE_</name>
|
|
<description>Big-endian mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined. Write reserved bits as zero.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNC</name>
|
|
<description>DMA Synchronization Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMACSYNC0</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC1</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC2</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC3</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC4</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC5</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC6</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC7</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC8</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC9</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC10</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC11</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC12</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC13</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC14</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMACSYNC15</name>
|
|
<description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:
|
|
0 - synchronization logic for the corresponding DMA request signals are enabled.
|
|
1 - synchronization logic for the corresponding request line signals are disabled.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read undefined. Write reserved bits as zero.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>C%sSRCADDR</name>
|
|
<description>DMA Channel Source Address Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRCADDR</name>
|
|
<description>DMA source address. Reading this register will return the current source address.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>C%sDESTADDR</name>
|
|
<description>DMA Channel Destination Address Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DESTADDR</name>
|
|
<description>DMA Destination address. Reading this register will return the current destination address.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>C%sLLI</name>
|
|
<description>DMA Channel Linked List Item Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LM</name>
|
|
<description>AHB master select for loading the next LLI:</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AHB_MASTER_0_</name>
|
|
<description>AHB Master 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_MASTER_1_</name>
|
|
<description>AHB Master 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>R</name>
|
|
<description>Reserved, and must be written as 0, masked on read.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LLI</name>
|
|
<description>Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>C%sCONTROL</name>
|
|
<description>DMA Channel Control Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRANSFERSIZE</name>
|
|
<description>Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SBSIZE</name>
|
|
<description>Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.</description>
|
|
<bitRange>[14:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SOURCE_BURST_1</name>
|
|
<description>Source burst size = 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_BURST_4</name>
|
|
<description>Source burst size = 4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_BURST_8</name>
|
|
<description>Source burst size = 8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_BURST_16</name>
|
|
<description>Source burst size = 16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_BURST_32</name>
|
|
<description>Source burst size = 32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_BURST_64</name>
|
|
<description>Source burst size = 64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_BURST_128</name>
|
|
<description>Source burst size = 128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_BURST_256</name>
|
|
<description>Source burst size = 256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBSIZE</name>
|
|
<description>Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.</description>
|
|
<bitRange>[17:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_BURST_1</name>
|
|
<description>Destination burst size = 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_BURST_4</name>
|
|
<description>Destination burst size = 4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_BURST_8</name>
|
|
<description>Destination burst size = 8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_BURST_16</name>
|
|
<description>Destination burst size = 16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_BURST_32</name>
|
|
<description>Destination burst size = 32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_BURST_64</name>
|
|
<description>Destination burst size = 64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_BURST_128</name>
|
|
<description>Destination burst size = 128</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_BURST_256</name>
|
|
<description>Destination burst size = 256</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWIDTH</name>
|
|
<description>Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.</description>
|
|
<bitRange>[20:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BYTE_8_BIT</name>
|
|
<description>Byte (8-bit)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALFWORD_16_BIT</name>
|
|
<description>Halfword (16-bit)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WORD_32_BIT</name>
|
|
<description>Word (32-bit)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DWIDTH</name>
|
|
<description>Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BYTE_8_BIT</name>
|
|
<description>Byte (8-bit)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALFWORD_16_BIT</name>
|
|
<description>Halfword (16-bit)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WORD_32_BIT</name>
|
|
<description>Word (32-bit)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S</name>
|
|
<description>Source AHB master select:</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AHB_MASTER_0_SELECTE</name>
|
|
<description>AHB Master 0 selected for source transfer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_MASTER_1_SELECTE</name>
|
|
<description>AHB Master 1 selected for source transfer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>D</name>
|
|
<description>Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AHB_MASTER_0_SELECTE</name>
|
|
<description>AHB Master 0 selected for destination transfer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_MASTER_1_SELECTE</name>
|
|
<description>AHB Master 1 selected for destination transfer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SI</name>
|
|
<description>Source increment:</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INCREMENT</name>
|
|
<description>The source address is not incremented after each transfer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INCREMENT</name>
|
|
<description>The source address is incremented after each transfer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DI</name>
|
|
<description>Destination increment:</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_DESTINATION_ADDR</name>
|
|
<description>The destination address is not incremented after each transfer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_DESTINATION_ADDR</name>
|
|
<description>The destination address is incremented after each transfer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROT1</name>
|
|
<description>Indicates that the access is in user mode or privileged mode:</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACCESS_IS_IN_USER_MO</name>
|
|
<description>Access is in user mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACCESS_IS_IN_PRIVILE</name>
|
|
<description>Access is in privileged mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROT2</name>
|
|
<description>Indicates that the access is bufferable or not bufferable:</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACCESS_IS_NOT_BUFFER</name>
|
|
<description>Access is not bufferable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACCESS_IS_BUFFERABLE</name>
|
|
<description>Access is bufferable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROT3</name>
|
|
<description>Indicates that the access is cacheable or not cacheable:</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACCESS_IS_NOT_CACHEA</name>
|
|
<description>Access is not cacheable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACCESS_IS_CACHEABLE_</name>
|
|
<description>Access is cacheable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I</name>
|
|
<description>Terminal count interrupt enable bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_TERMINAL_COUNT_I</name>
|
|
<description>The terminal count interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_TERMINAL_COUNT_I</name>
|
|
<description>The terminal count interrupt is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>C%sCONFIG</name>
|
|
<description>DMA Channel Configuration Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>E</name>
|
|
<description>Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_DISABLED_</name>
|
|
<description>Channel disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_ENABLED_</name>
|
|
<description>Channel enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRCPERIPHERAL</name>
|
|
<description>Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.</description>
|
|
<bitRange>[5:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_SPIFI</name>
|
|
<description>Source = SPIFI</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_TIMER_0_MAT</name>
|
|
<description>Source = Timer 0 match 0/UART0 transmit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_TIMER_0_MAT</name>
|
|
<description>Source = Timer 0 match 1/UART0 receive</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_TIMER_1_MAT</name>
|
|
<description>Source = Timer 1 match 0/UART1 transmit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_TIMER_1_MAT</name>
|
|
<description>Source = Timer 1 match 1/UART 1 receive</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_TIMER_2_MAT</name>
|
|
<description>Source = Timer 2 match 0/UART 2 transmit</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_TIMER_2_MAT</name>
|
|
<description>Source = Timer 2 match 1/UART 2 receive</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_TIMER_3_MAT</name>
|
|
<description>Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_TIMER_3_MAT</name>
|
|
<description>Source = Timer 3 match 1/UART3 receive/SCT DMA request 1</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_SSP0_RECEIV</name>
|
|
<description>Source = SSP0 receive/I2S channel 0</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_SSP0_TRANSM</name>
|
|
<description>Source = SSP0 transmit/I2S channel 1</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_SSP1_RECEIV</name>
|
|
<description>Source = SSP1 receive</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_SSP1_TRANSM</name>
|
|
<description>Source = SSP1 transmit</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_ADC0</name>
|
|
<description>Source = ADC0</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_ADC1</name>
|
|
<description>Source = ADC1</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_EQ_DAC</name>
|
|
<description>Source = DAC</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DESTPERIPHERAL</name>
|
|
<description>Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.</description>
|
|
<bitRange>[10:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_SPIFI</name>
|
|
<description>Destination = SPIFI</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_TIMER_</name>
|
|
<description>Destination = Timer 0 match 0/UART0 transmit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_TIMER_</name>
|
|
<description>Destination = Timer 0 match 1/UART0 receive</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_TIMER_</name>
|
|
<description>Destination = Timer 1 match 0/UART1 transmit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_TIMER_</name>
|
|
<description>Destination = Timer 1 match 1/UART 1 receive</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_TIMER_</name>
|
|
<description>Destination = Timer 2 match 0/UART 2 transmit</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_TIMER_</name>
|
|
<description>Destination = Timer 2 match 1/UART 2 receive</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_TIMER_</name>
|
|
<description>Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_TIMER_</name>
|
|
<description>Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_SSP0_R</name>
|
|
<description>Destination = SSP0 receive/I2S channel 0</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_SSP0_T</name>
|
|
<description>Destination = SSP0 transmit/I2S channel 1</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_SSP1_R</name>
|
|
<description>Destination = SSP1 receive</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_SSP1_T</name>
|
|
<description>Destination = SSP1 transmit</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_ADC0</name>
|
|
<description>Destination = ADC0</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_ADC1</name>
|
|
<description>Destination = ADC1</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DESTINATION_EQ_DAC</name>
|
|
<description>Destination = DAC</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLOWCNTRL</name>
|
|
<description>Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.</description>
|
|
<bitRange>[13:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MEMORY_TO_MEMORY</name>
|
|
<description>Memory to memory (DMA control)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEMORY_TO_PERIPHERAL</name>
|
|
<description>Memory to peripheral (DMA control)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PERIPHERAL_TO_MEMORY</name>
|
|
<description>Peripheral to memory (DMA control)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_PERIPHERAL_TO</name>
|
|
<description>Source peripheral to destination peripheral (DMA control)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_PERIPHERAL_TO</name>
|
|
<description>Source peripheral to destination peripheral (destination control)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEMORY_TO_PERIPHERAL</name>
|
|
<description>Memory to peripheral (peripheral control)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PERIPHERAL_TO_MEMORY</name>
|
|
<description>Peripheral to memory (peripheral control)</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOURCE_PERIPHERAL_TO</name>
|
|
<description>Source peripheral to destination peripheral (source control)</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ITC</name>
|
|
<description>Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>L</name>
|
|
<description>Lock. When set, this bit enables locked transfers.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>A</name>
|
|
<description>Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>H</name>
|
|
<description>Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_DMA_REQUESTS_</name>
|
|
<description>Enable DMA requests.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IGNORE_FURTHER_SOURC</name>
|
|
<description>Ignore further source DMA requests.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, do not modify, masked on read.</description>
|
|
<bitRange>[31:19]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>SPIFI</name>
|
|
<description>SPI Flash Interface (SPIFI)</description>
|
|
<groupName>SPIFI</groupName>
|
|
<baseAddress>0x40003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPIFI</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>SPIFI control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x400FFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CSHIGH</name>
|
|
<description>This field controls the minimum CS high time, expressed as a number of serial clock periods minus one.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>D_PRFTCH_DIS</name>
|
|
<description>This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MODE3</name>
|
|
<description>SPI Mode 3 select.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SCK_LOW</name>
|
|
<description>SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK_HIGH</name>
|
|
<description>SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PRFTCH_DIS</name>
|
|
<description>Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Cache prefetching enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disables prefetching of cache lines.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DUAL</name>
|
|
<description>Select dual protocol.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>QUAD_PROTOCOL</name>
|
|
<description>Quad protocol. This protocol uses IO3:0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DUAL_PROTOCOL</name>
|
|
<description>Dual protocol. This protocol uses IO1:0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RFCLK</name>
|
|
<description>Select active clock edge for input data.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE</name>
|
|
<description>Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE</name>
|
|
<description>Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FBCLK</name>
|
|
<description>Feedback clock select.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_CLOCK</name>
|
|
<description>Internal clock. The SPIFI samples read data using an internal clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FEEDBACK_CLOCK</name>
|
|
<description>Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>SPIFI command register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATALEN</name>
|
|
<description>Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field.</description>
|
|
<bitRange>[13:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>POLL</name>
|
|
<description>This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DOUT</name>
|
|
<description>If the DATALEN field is not zero, this bit controls the direction of the data:</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_FROM_SERIAL_FL</name>
|
|
<description>Input from serial flash.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_TO_SERIAL_FLA</name>
|
|
<description>Output to serial flash.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTLEN</name>
|
|
<description>This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes.</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIELDFORM</name>
|
|
<description>This field controls how the fields of the command are sent.</description>
|
|
<bitRange>[20:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ALL_SERIAL</name>
|
|
<description>All serial. All fields of the command are serial.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QUADDUAL_DATA</name>
|
|
<description>Quad/dual data. Data field is quad/dual, other fields are serial.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERIAL_OPCODE</name>
|
|
<description>Serial opcode. Opcode field is serial. Other fields are quad/dual.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALL_QUADDUAL</name>
|
|
<description>All quad/dual. All fields of the command are in quad/dual format.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAMEFORM</name>
|
|
<description>This field controls the opcode and address fields.</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPCODE</name>
|
|
<description>Opcode. Opcode only, no address.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPCODE_ONE_BYTE</name>
|
|
<description>Opcode one byte. Opcode, least significant byte of address.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPCODE_TWO_BYTES</name>
|
|
<description>Opcode two bytes. Opcode, two least significant bytes of address.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPCODE_THREE_BYTES</name>
|
|
<description>Opcode three bytes. Opcode, three least significant bytes of address.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPCODE_FOUR_BYTES</name>
|
|
<description>Opcode four bytes. Opcode, 4 bytes of address.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_OPCODE_THREE_BYTE</name>
|
|
<description>No opcode three bytes. No opcode, 3 least significant bytes of address.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_OPCODE_FOUR_BYTES</name>
|
|
<description>No opcode four bytes. No opcode, 4 bytes of address.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPCODE</name>
|
|
<description>The opcode of the command (not used for some FRAMEFORM values).</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDR</name>
|
|
<description>SPIFI address register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Address.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDATA</name>
|
|
<description>SPIFI intermediate data register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IDATA</name>
|
|
<description>Value of intermediate bytes.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLIMIT</name>
|
|
<description>SPIFI cache limit register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x08000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLIMIT</name>
|
|
<description>Zero-based upper limit of cacheable memory</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>SPIFI data register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Input or output data</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCMD</name>
|
|
<description>SPIFI memory command register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[13:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>POLL</name>
|
|
<description>This bit should be written as 0.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DOUT</name>
|
|
<description>This bit should be written as 0.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INTLEN</name>
|
|
<description>This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes.</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIELDFORM</name>
|
|
<description>This field controls how the fields of the command are sent.</description>
|
|
<bitRange>[20:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ALL_SERIAL</name>
|
|
<description>All serial. All fields of the command are serial.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>QUADDUAL_DATA</name>
|
|
<description>Quad/dual data. Data field is quad/dual, other fields are serial.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERIAL_OPCODE</name>
|
|
<description>Serial opcode. Opcode field is serial. Other fields are quad/dual.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALL_QUADDUAL</name>
|
|
<description>All quad/dual. All fields of the command are in quad/dual format.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAMEFORM</name>
|
|
<description>This field controls the opcode and address fields.</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPCODE_ONE_BYTE</name>
|
|
<description>Opcode one byte. Opcode, least-significant byte of address.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPCODE_TWO_BYTES</name>
|
|
<description>Opcode two bytes. Opcode, 2 least-significant bytes of address.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPCODE_THREE_BYTES</name>
|
|
<description>Opcode three bytes. Opcode, 3 least-significant bytes of address.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPCODE_FOUR_BYTES</name>
|
|
<description>Opcode four bytes. Opcode, 4 bytes of address.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_OPCODE_THREE_BYTE</name>
|
|
<description>No opcode three bytes. No opcode, 3 least-significant bytes of address.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_OPCODE_FOUR_BYTES</name>
|
|
<description>No opcode, 4 bytes of address.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPCODE</name>
|
|
<description>The opcode of the command (not used for some FRAMEFORM values).</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>SPIFI status register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MCINIT</name>
|
|
<description>This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTRQ</name>
|
|
<description>This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VERSION</name>
|
|
<description>The SPIFI hardware described in this chapter returns</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>SDMMC</name>
|
|
<description>SD/MMC</description>
|
|
<groupName>SDMMC</groupName>
|
|
<baseAddress>0x40004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SDIO</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CONTROLLER_RESET</name>
|
|
<description>Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets: - BIU/CIU interface - CIU and state machines - abort_read_data, send_irq_response, and read_wait bits of Control register - start_cmd bit of Command register Does not affect any registers or DMA interface, or FIFO. or host interrupts.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset. Reset SD/MMC controller</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_RESET</name>
|
|
<description>Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset. Reset to data FIFO To reset FIFO pointers</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMA_RESET</name>
|
|
<description>Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset. Reset internal DMA interface control logic</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INT_ENABLE</name>
|
|
<description>Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INTERRUPTS</name>
|
|
<description>Disable interrupts</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INTERRUPTS</name>
|
|
<description>Enable interrupts</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write this bit as 0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>READ_WAIT</name>
|
|
<description>Read/wait. For sending read-wait to SDIO cards.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_READ_WAIT</name>
|
|
<description>Clear read wait</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ASSERT_READ_WAIT</name>
|
|
<description>Assert read wait</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEND_IRQ_RESPONSE</name>
|
|
<description>Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEND_AUTO_IRQ_RESPON</name>
|
|
<description>Send auto IRQ response</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABORT_READ_DATA</name>
|
|
<description>Abort read data. Used in SDIO card suspend sequence.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ABORT</name>
|
|
<description>Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEND_CCSD</name>
|
|
<description>Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked. NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_BIT</name>
|
|
<description>Clear bit if the SD/MMC controller does not reset the bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEND_COMMAND_COMPLET</name>
|
|
<description>Send Command Completion Signal Disable (CCSD) to CE-ATA device</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEND_AUTO_STOP</name>
|
|
<description>Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THIS_BIT_IF_TH</name>
|
|
<description>Clear this bit if the SD/MMC controller does not reset the bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEND_INTERNALLY_GENE</name>
|
|
<description>Send internally generated STOP after sending CCSD to CE-ATA device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CEATA_DEVICE_INTERRUPT_STATUS</name>
|
|
<description>CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CARD_VOLTAGE_A0</name>
|
|
<description>Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CARD_VOLTAGE_A1</name>
|
|
<description>Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CARD_VOLTAGE_A2</name>
|
|
<description>Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[23:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write this bit as 0.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USE_INTERNAL_DMAC</name>
|
|
<description>SD/MMC DMA use.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HOST</name>
|
|
<description>Host. The host performs data transfers through the slave interface</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DMA</name>
|
|
<description>DMA. Internal DMA used for data transfer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWREN</name>
|
|
<description>Power Enable Register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POWER_ENABLE</name>
|
|
<description>Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card. 0 - power off 1 - power on Optional feature: port can be used as general-purpose output on the SD_POW pin.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>Clock Divider Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLK_DIVIDER0</name>
|
|
<description>Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLK_DIVIDER1</name>
|
|
<description>Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLK_DIVIDER2</name>
|
|
<description>Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLK_DIVIDER3</name>
|
|
<description>Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKSRC</name>
|
|
<description>SD Clock Source Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLK_SOURCE</name>
|
|
<description>Clock divider source for SD card. 00 - Clock divider 0 01 - Clock divider 1 10 - Clock divider 2 11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKENA</name>
|
|
<description>Clock Enable Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCLK_ENABLE</name>
|
|
<description>Clock-enable control for SD card clock. One MMC card clock supported. 0 - Clock disabled 1 - Clock enabled</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CCLK_LOW_POWER</name>
|
|
<description>Low-power control for SD card clock. One MMC card clock supported. 0 - Non-low-power mode 1 - Low-power mode; stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped).</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMOUT</name>
|
|
<description>Time-out Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESPONSE_TIMEOUT</name>
|
|
<description>Response time-out value. Value is in number of card output clocks - cclk_out.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA_TIMEOUT</name>
|
|
<description>Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTYPE</name>
|
|
<description>Card Type Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CARD_WIDTH0</name>
|
|
<description>Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CARD_WIDTH1</name>
|
|
<description>Indicates if card is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BLKSIZ</name>
|
|
<description>Block Size Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BLOCK_SIZE</name>
|
|
<description>Block size</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BYTCNT</name>
|
|
<description>Byte Count Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x200</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BYTE_COUNT</name>
|
|
<description>Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTMASK</name>
|
|
<description>Interrupt Mask Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CDET</name>
|
|
<description>Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CDONE</name>
|
|
<description>Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTO</name>
|
|
<description>Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDR</name>
|
|
<description>Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDR</name>
|
|
<description>Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RCRC</name>
|
|
<description>Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DCRC</name>
|
|
<description>Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTO</name>
|
|
<description>Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRTO</name>
|
|
<description>Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HTO</name>
|
|
<description>Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRUN</name>
|
|
<description>FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HLE</name>
|
|
<description>Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SBE</name>
|
|
<description>Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACD</name>
|
|
<description>Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EBE</name>
|
|
<description>End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SDIO_INT_MASK</name>
|
|
<description>Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMDARG</name>
|
|
<description>Command Argument Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMD_ARG</name>
|
|
<description>Value indicates command argument to be passed to card.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>Command Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMD_INDEX</name>
|
|
<description>Command index</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESPONSE_EXPECT</name>
|
|
<description>Response expect</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None. No response expected from card</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXPECTED</name>
|
|
<description>Expected. Response expected from card</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESPONSE_LENGTH</name>
|
|
<description>Response length</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SHORT</name>
|
|
<description>Short. Short response expected from card</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LONG</name>
|
|
<description>Long. Long response expected from card</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHECK_RESPONSE_CRC</name>
|
|
<description>Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_CHECK_RESPONS</name>
|
|
<description>Do not check response CRC</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHECK_RESPONSE_CRC</name>
|
|
<description>Check response CRC</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATA_EXPECTED</name>
|
|
<description>Data expected</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None. No data transfer expected (read/write)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA</name>
|
|
<description>Data. Data transfer expected (read/write)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>READ_WRITE</name>
|
|
<description>read/write. Don't care if no data expected from card.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>READ_FROM_CARD</name>
|
|
<description>Read from card</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITE_TO_CARD</name>
|
|
<description>Write to card</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRANSFER_MODE</name>
|
|
<description>Transfer mode. Don't care if no data expected.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BLOCK_DATA_TRANSFER</name>
|
|
<description>Block data transfer command</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STREAM_DATA_TRANSFER</name>
|
|
<description>Stream data transfer command</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEND_AUTO_STOP</name>
|
|
<description>Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine: - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands - open-ended transfers that software should explicitly send to stop command Additionally, when resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_STOP_COMMAND_SENT</name>
|
|
<description>No stop command sent at end of data transfer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEND_STOP_COMMAND_AT</name>
|
|
<description>Send stop command at end of data transfer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAIT_PRVDATA_COMPLETE</name>
|
|
<description>Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SEND</name>
|
|
<description>Send. Send command at once, even if previous data transfer has not completed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT</name>
|
|
<description>Wait. Wait for previous data transfer completion before sending command.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOP_ABORT_CMD</name>
|
|
<description>Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Stop or abort command intended to stop current data transfer in progress.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEND_INITIALIZATION</name>
|
|
<description>Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory).</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No. Do not send initialization sequence (80 clocks of 1) before sending this command.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SEND</name>
|
|
<description>Send. Send initialization sequence before sending this command.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write as 0.</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>UPDATE_CLOCK_REGISTERS_ONLY</name>
|
|
<description>Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal. Normal command sequence</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO</name>
|
|
<description>No. Do not send commands, just update clock register value into card clock domain</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>READ_CEATA_DEVICE</name>
|
|
<description>Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_READ</name>
|
|
<description>No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCS_EXPECTED</name>
|
|
<description>CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE_BOOT</name>
|
|
<description>Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EXPECT_BOOT_ACK</name>
|
|
<description>Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DISABLE_BOOT</name>
|
|
<description>Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BOOT_MODE</name>
|
|
<description>Boot Mode</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MANDATORY_BOOT_OPERA</name>
|
|
<description>Mandatory Boot operation</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ALTERNATE_BOOT_OPERA</name>
|
|
<description>Alternate Boot operation</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VOLT_SWITCH</name>
|
|
<description>Voltage switch bit</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. No voltage switching</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Voltage switching enabled; must be set for CMD11 only</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[30:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>START_CMD</name>
|
|
<description>Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESP0</name>
|
|
<description>Response Register 0</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESPONSE0</name>
|
|
<description>Bit[31:0] of response</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESP1</name>
|
|
<description>Response Register 1</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESPONSE1</name>
|
|
<description>Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always short for them. For information on when CIU sends auto-stop commands, refer to Auto-Stop .</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESP2</name>
|
|
<description>Response Register 2</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESPONSE2</name>
|
|
<description>Bit[95:64] of long response</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESP3</name>
|
|
<description>Response Register 3</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESPONSE3</name>
|
|
<description>Bit[127:96] of long response</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MINTSTS</name>
|
|
<description>Masked Interrupt Status Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CDET</name>
|
|
<description>Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CDONE</name>
|
|
<description>Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTO</name>
|
|
<description>Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDR</name>
|
|
<description>Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDR</name>
|
|
<description>Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RCRC</name>
|
|
<description>Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DCRC</name>
|
|
<description>Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTO</name>
|
|
<description>Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRTO</name>
|
|
<description>Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HTO</name>
|
|
<description>Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRUN</name>
|
|
<description>FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HLE</name>
|
|
<description>Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SBE</name>
|
|
<description>Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACD</name>
|
|
<description>Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EBE</name>
|
|
<description>End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SDIO_INTERRUPT</name>
|
|
<description>Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt). 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, this bit is always 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RINTSTS</name>
|
|
<description>Raw Interrupt Status Register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CDET</name>
|
|
<description>Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CDONE</name>
|
|
<description>Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTO</name>
|
|
<description>Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDR</name>
|
|
<description>Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXDR</name>
|
|
<description>Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RCRC</name>
|
|
<description>Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DCRC</name>
|
|
<description>Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTO_BAR</name>
|
|
<description>Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRTO_BDS</name>
|
|
<description>Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HTO</name>
|
|
<description>Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRUN</name>
|
|
<description>FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HLE</name>
|
|
<description>Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SBE</name>
|
|
<description>Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACD</name>
|
|
<description>Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EBE</name>
|
|
<description>End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SDIO_INTERRUPT</name>
|
|
<description>Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact. 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO_RX_WATERMARK</name>
|
|
<description>FIFO reached Receive watermark level; not qualified with data transfer.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_TX_WATERMARK</name>
|
|
<description>FIFO reached Transmit watermark level; not qualified with data transfer.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_EMPTY</name>
|
|
<description>FIFO is empty status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_FULL</name>
|
|
<description>FIFO is full status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CMDFSMSTATES</name>
|
|
<description>Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are: - Bit 16 - Wait for CCS - Bit 17 - Send CCSD - Bit 18 - Boot Mode Due to this, while command FSM is in Wait for CCS state or Send CCSD or Boot Mode, the Status register indicates status as 0 for the bit field 7:4.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA_3_STATUS</name>
|
|
<description>Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA_BUSY</name>
|
|
<description>Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA_STATE_MC_BUSY</name>
|
|
<description>Data transmit or receive state-machine is busy</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESPONSE_INDEX</name>
|
|
<description>Index of previous response, including any auto-stop sent by core.</description>
|
|
<bitRange>[16:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_COUNT</name>
|
|
<description>FIFO count - Number of filled locations in FIFO</description>
|
|
<bitRange>[29:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMA_ACK</name>
|
|
<description>DMA acknowledge signal state</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMA_REQ</name>
|
|
<description>DMA request signal state</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOTH</name>
|
|
<description>FIFO Threshold Watermark Register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0F800000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TX_WMARK</name>
|
|
<description>FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark >= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2).</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RX_WMARK</name>
|
|
<description>FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1) NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out.</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DMA_MTS</name>
|
|
<description>Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH Allowed combinations for MSize and TX_WMark are: MSize = 1, TX_WMARK = 1-15 MSize = 4, TX_WMark = 8 MSize = 4, TX_WMark = 4 MSize = 4, TX_WMark = 12 MSize = 8, TX_WMark = 8 MSize = 8, TX_WMark = 4. Allowed combinations for MSize and RX_WMark are: MSize = 1, RX_WMARK = 0-14 MSize = 4, RX_WMark = 3 MSize = 4, RX_WMark = 7 MSize = 4, RX_WMark = 11 MSize = 8, RX_WMark = 7 MSize = 8, RX_WMark = 11 Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7</description>
|
|
<bitRange>[30:28]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_TRANSFER</name>
|
|
<description>1 transfer</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_TRANSFERS</name>
|
|
<description>4 transfers</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_TRANSFERS</name>
|
|
<description>8 transfers</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_TRANSFERS</name>
|
|
<description>16 transfers</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32_TRANSFERS</name>
|
|
<description>32 transfers</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64_TRANSFERS</name>
|
|
<description>64 transfers</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_TRANSFERS</name>
|
|
<description>128 transfers</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_TRANSFERS</name>
|
|
<description>256 transfers</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDETECT</name>
|
|
<description>Card Detect Register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CARD_DETECT</name>
|
|
<description>Card detect. 0 represents presence of card.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRTPRT</name>
|
|
<description>Write Protect Register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WRITE_PROTECT</name>
|
|
<description>Write protect. 1 represents write protection.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCBCNT</name>
|
|
<description>Transferred CIU Card Byte Count Register</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRANS_CARD_BYTE_COUNT</name>
|
|
<description>Number of bytes transferred by CIU unit to card. Register should be read only after data transfer completes; during data transfer, register returns 0.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBBCNT</name>
|
|
<description>Transferred Host to BIU-FIFO Byte Count Register</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRANS_FIFO_BYTE_COUNT</name>
|
|
<description>Number of bytes transferred between Host/DMA memory and BIU FIFO.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBNCE</name>
|
|
<description>Debounce Count Register</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEBOUNCE_COUNT</name>
|
|
<description>Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RST_N</name>
|
|
<description>Hardware Reset</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CARD_RESET</name>
|
|
<description>Hardware reset. 1 - Active mode 0 - Reset Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BMOD</name>
|
|
<description>Bus Mode Register</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SWR</name>
|
|
<description>Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FB</name>
|
|
<description>Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSL</name>
|
|
<description>Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write.</description>
|
|
<bitRange>[6:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DE</name>
|
|
<description>SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PBL</name>
|
|
<description>Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_TRANSFER</name>
|
|
<description>1 transfer</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_TRANSFERS</name>
|
|
<description>4 transfers</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_TRANSFERS</name>
|
|
<description>8 transfers</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_TRANSFERS</name>
|
|
<description>16 transfers</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32_TRANSFERS</name>
|
|
<description>32 transfers</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64_TRANSFERS</name>
|
|
<description>64 transfers</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>128_TRANSFERS</name>
|
|
<description>128 transfers</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>256_TRANSFERS</name>
|
|
<description>256 transfers</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLDMND</name>
|
|
<description>Poll Demand Register</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBADDR</name>
|
|
<description>Descriptor List Base Address Register</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SDL</name>
|
|
<description>Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDSTS</name>
|
|
<description>Internal DMAC Status Register</description>
|
|
<addressOffset>0x08C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TI</name>
|
|
<description>Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FBE</name>
|
|
<description>Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DU</name>
|
|
<description>Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CES</name>
|
|
<description>Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits: EBE - End Bit Error RTO - Response Time-out/Boot Ack Time-out RCRC - Response CRC SBE - Start Bit Error DRTO - Data Read Time-out/BDS time-out DCRC - Data CRC for Receive RE - Response Error Writing a 1 clears this bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NIS</name>
|
|
<description>Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIS</name>
|
|
<description>Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EB</name>
|
|
<description>Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt. 001 - Host Abort received during transmission 010 - Host Abort received during reception Others: Reserved EB is read-only.</description>
|
|
<bitRange>[12:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FSM</name>
|
|
<description>DMAC state machine present state. 0 - DMA_IDLE 1 - DMA_SUSPEND 2 - DESC_RD 3 - DESC_CHK 4 - DMA_RD_REQ_WAIT 5 - DMA_WR_REQ_WAIT 6 - DMA_RD 7 - DMA_WR 8 - DESC_CLOSE This bit is read-only.</description>
|
|
<bitRange>[16:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDINTEN</name>
|
|
<description>Internal DMAC Interrupt Enable Register</description>
|
|
<addressOffset>0x090</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TI</name>
|
|
<description>Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FBE</name>
|
|
<description>Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DU</name>
|
|
<description>Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CES</name>
|
|
<description>Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NIS</name>
|
|
<description>Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIS</name>
|
|
<description>Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSCADDR</name>
|
|
<description>Current Host Descriptor Address Register</description>
|
|
<addressOffset>0x094</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HDA</name>
|
|
<description>Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the SD/MMC DMA.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BUFADDR</name>
|
|
<description>Current Buffer Descriptor Address Register</description>
|
|
<addressOffset>0x098</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HBA</name>
|
|
<description>Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the SD/MMC DMA.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>EMC</name>
|
|
<description>External Memory Controller (EMC) </description>
|
|
<groupName>EMC</groupName>
|
|
<baseAddress>0x40005000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CONTROL</name>
|
|
<description>Controls operation of the memory controller.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x3</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>E</name>
|
|
<description>EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1]</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. (POR and warm reset value).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal. Normal memory map.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>L</name>
|
|
<description>Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1]</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal. Normal mode (warm reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_POWER_MODE</name>
|
|
<description>Low-power mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Provides EMC status information.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>B</name>
|
|
<description>Busy indicator. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not:</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>Idle. EMC is idle (warm reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUSY</name>
|
|
<description>Busy. EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S</name>
|
|
<description>Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly:</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Empty. Write buffers empty (POR reset value)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA</name>
|
|
<description>Data. Write buffers contain data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SA</name>
|
|
<description>Self-refresh acknowledge. This bit indicates the operating mode of the EMC:</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_MODE</name>
|
|
<description>Normal mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELF_REFRESH_MODE</name>
|
|
<description>Self-refresh mode. (POR reset value.)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Configures operation of the memory controller.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM</name>
|
|
<description>Endian mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LITTLE_ENDIAN_MODE</name>
|
|
<description>Little-endian mode. (POR reset value.)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIG_ENDIAN_MODE</name>
|
|
<description>Big-endian mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write a 0 to this bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICCONTROL</name>
|
|
<description>Controls dynamic memory operation.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x6</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CE</name>
|
|
<description>Dynamic memory clock enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Clock enable of idle devices are deasserted to save power (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. All clock enables are driven HIGH continuously.[1]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop. CLKOUT stops when all SDRAMs are idle and during self-refresh mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>Run. CLKOUT runs continuously (POR reset value).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SR</name>
|
|
<description>Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_MODE</name>
|
|
<description>Normal mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELF_REFRESH</name>
|
|
<description>Self-refresh. Enter self-refresh mode (POR reset value).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MMC</name>
|
|
<description>Memory clock control.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. CLKOUT enabled (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. CLKOUT disabled.[3]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>I</name>
|
|
<description>SDRAM initialization.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal. Issue SDRAM NORMAL operation command (POR reset value).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE</name>
|
|
<description>Mode. Issue SDRAM MODE command.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PALL</name>
|
|
<description>PALL. Issue SDRAM PALL (precharge all) command.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOP</name>
|
|
<description>NOP. Issue SDRAM NOP (no operation) command)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[13:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICREFRESH</name>
|
|
<description>Configures dynamic memory refresh operation.</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFRESH</name>
|
|
<description>Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICREADCONFIG</name>
|
|
<description>Configures the dynamic memory read strategy.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RD</name>
|
|
<description>Read data strategy.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_USE</name>
|
|
<description>Do not use. POR reset value.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALF</name>
|
|
<description>Command delayed by 1/2 EMC_CCLK.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALFPLUSONE</name>
|
|
<description>Command delayed by 1/2 EMC_CCLK plus one clock cycle.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALFPLUSTWO</name>
|
|
<description>Command delayed by1/2 EMC_CCLK plus two clock cycles,</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICRP</name>
|
|
<description>Selects the precharge command period.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRP</name>
|
|
<description>Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICRAS</name>
|
|
<description>Selects the active to precharge command period.</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRAS</name>
|
|
<description>Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICSREX</name>
|
|
<description>Selects the self-refresh exit time.</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSREX</name>
|
|
<description>Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICAPR</name>
|
|
<description>Selects the last-data-out to active command time.</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAPR</name>
|
|
<description>Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICDAL</name>
|
|
<description>Selects the data-in to active command time.</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDAL</name>
|
|
<description>Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICWR</name>
|
|
<description>Selects the write recovery time.</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TWR</name>
|
|
<description>Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICRC</name>
|
|
<description>Selects the active to active command period.</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRC</name>
|
|
<description>Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICRFC</name>
|
|
<description>Selects the auto-refresh period.</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRFC</name>
|
|
<description>Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICXSR</name>
|
|
<description>Selects the exit self-refresh to active command time.</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXSR</name>
|
|
<description>Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICRRD</name>
|
|
<description>Selects the active bank A to active bank B latency.</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRRD</name>
|
|
<description>Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DYNAMICMRD</name>
|
|
<description>Selects the load mode register to active command time.</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TMRD</name>
|
|
<description>Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATICEXTENDEDWAIT</name>
|
|
<description>Selects time for long static memory read and write transfers.</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXTENDEDWAIT</name>
|
|
<description>Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>DYNAMICCONFIG%s</name>
|
|
<description>Selects the configuration information for dynamic memory chip select 0.</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MD</name>
|
|
<description>Memory device.</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SDRAM</name>
|
|
<description>SDRAM (POR reset value).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AM0</name>
|
|
<description>Address mapping. See Table 382. 000000 = reset value.[1]</description>
|
|
<bitRange>[12:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AM1</name>
|
|
<description>Address mapping See Table 382. 0 = reset value.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[18:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>B</name>
|
|
<description>Buffer enable.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Buffer disabled for accesses to this chip select (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P</name>
|
|
<description>Write protect.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None. Writes not protected (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PROTECTED</name>
|
|
<description>Protected. Writes protected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>DYNAMICRASCAS%s</name>
|
|
<description>Selects the RAS and CAS latencies for dynamic memory chip select 0.</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x303</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAS</name>
|
|
<description>RAS latency (active to read/write delay).</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_EMC_CCLK_CYCLE</name>
|
|
<description>One EMC_CCLK cycle.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO_EMC_CCLK_CYCLES</name>
|
|
<description>Two EMC_CCLK cycles.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THREE_EMC_CCLK_CYCLE</name>
|
|
<description>Three EMC_CCLK cycles (POR reset value).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CAS</name>
|
|
<description>CAS latency.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ONE_EMC_CCLK_CYCLE</name>
|
|
<description>One EMC_CCLK cycle.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TWO_EMC_CCLK_CYCLES</name>
|
|
<description>Two EMC_CCLK cycles.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THREE_EMC_CCLK_CYCLE</name>
|
|
<description>Three EMC_CCLK cycles (POR reset value).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICCONFIG%s</name>
|
|
<description>Selects the memory configuration for static chip select 0.</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MW</name>
|
|
<description>Memory width.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>8_BIT</name>
|
|
<description>8 bit (POR reset value).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BIT</name>
|
|
<description>16 bit.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32_BIT</name>
|
|
<description>32 bit.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. (POR reset value.)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Async page mode enabled (page length four).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Chip select polarity. The value of the chip select polarity on power-on reset is 0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_LOW</name>
|
|
<description>Active LOW chip select.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE_HIGH</name>
|
|
<description>Active HIGH chip select.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PB</name>
|
|
<description>Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EW</name>
|
|
<description>Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Extended wait disabled (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Extended wait enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[18:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>B</name>
|
|
<description>Buffer enable [2].</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Buffer disabled (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Buffer enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P</name>
|
|
<description>Write protect.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NONE</name>
|
|
<description>None. Writes not protected (POR reset value).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PROTECT</name>
|
|
<description>Protect. Write protected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICWAITWEN%s</name>
|
|
<description>Selects the delay from chip select 0 to write enable.</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITWEN</name>
|
|
<description>Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICWAITOEN%s</name>
|
|
<description>Selects the delay from chip select 0 or address change, whichever is later, to output enable.</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITOEN</name>
|
|
<description>Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICWAITRD%s</name>
|
|
<description>Selects the delay from chip select 0 to a read access.</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITRD</name>
|
|
<description>Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICWAITPAGE%s</name>
|
|
<description>Selects the delay for asynchronous page mode sequential accesses for chip select 0.</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITPAGE</name>
|
|
<description>Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICWAITWR%s</name>
|
|
<description>Selects the delay from chip select 0 to a write access.</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITWR</name>
|
|
<description>Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>STATICWAITTURN%s</name>
|
|
<description>Selects the number of bus turnaround cycles for chip select 0.</description>
|
|
<addressOffset>0x218</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAITTURN</name>
|
|
<description>Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value).</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>USB0</name>
|
|
<description>USB0 Host/Device/OTG controller</description>
|
|
<groupName>USB0</groupName>
|
|
<baseAddress>0x40006000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USB0</name>
|
|
<value>8</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CAPLENGTH</name>
|
|
<description>Capability register length</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x01000040</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPLENGTH</name>
|
|
<description>Indicates offset to add to the register base address at the beginning of the Operational Register</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HCIVERSION</name>
|
|
<description>BCD encoding of the EHCI revision number supported by this host controller.</description>
|
|
<bitRange>[23:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are reserved and should be set to zero.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCSPARAMS</name>
|
|
<description>Host controller structural parameters</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00010011</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>N_PORTS</name>
|
|
<description>Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PPC</name>
|
|
<description>Port Power Control. This field indicates whether the host controller implementation includes port power control.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are reserved and should be set to zero.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>N_PCC</name>
|
|
<description>Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>N_CC</name>
|
|
<description>Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PI</name>
|
|
<description>Port indicators. This bit indicates whether the ports support port indicator control.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are reserved and should be set to zero.</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>N_PTT</name>
|
|
<description>Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller.</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>N_TT</name>
|
|
<description>Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller.</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are reserved and should be set to zero.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCCPARAMS</name>
|
|
<description>Host controller capability parameters</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000006</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC</name>
|
|
<description>64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PFL</name>
|
|
<description>Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ASP</name>
|
|
<description>Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IST</name>
|
|
<description>Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EECP</name>
|
|
<description>EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are reserved and should be set to zero.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCIVERSION</name>
|
|
<description>Device interface version number</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCIVERSION</name>
|
|
<description>The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCMD_D</name>
|
|
<description>USB command (device mode)</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00080000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Run/Stop</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETACH</name>
|
|
<description>Writing a 0 to this bit will cause a detach event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ATTACH</name>
|
|
<description>Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESETCOMPLETE</name>
|
|
<description>Set to 0 by hardware when the reset process is complete.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. These bits should be set to 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.These bits should be set to 0.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.These bits should be set to 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SUTW</name>
|
|
<description>Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10).</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ATDTW</name>
|
|
<description>Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ITC</name>
|
|
<description>Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCMD_H</name>
|
|
<description>USB command (host mode)</description>
|
|
<alternateRegister>USBCMD_D</alternateRegister>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00080000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Run/Stop</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PROCEED</name>
|
|
<description>When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESETCOMPLETE</name>
|
|
<description>This bit is set to zero by hardware when the reset process is complete.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FS0</name>
|
|
<description>Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FS1</name>
|
|
<description>Bit 1 of the Frame List Size bits. See Table 220.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PSE</name>
|
|
<description>This bit controls whether the host controller skips processing the periodic schedule.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_PROCESS_THE_P</name>
|
|
<description>Do not process the periodic schedule.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USE_THE_PERIODICLIST</name>
|
|
<description>Use the PERIODICLISTBASE register to access the periodic schedule.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASE</name>
|
|
<description>This bit controls whether the host controller skips processing the asynchronous schedule.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_PROCESS_THE_A</name>
|
|
<description>Do not process the asynchronous schedule.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USE_THE_ASYNCLISTADD</name>
|
|
<description>Use the ASYNCLISTADDR to access the asynchronous schedule.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IAA</name>
|
|
<description>This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_HOST_CONTROLLER_</name>
|
|
<description>The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOFTWARE_MUST_WRITE_</name>
|
|
<description>Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ASP1_0</name>
|
|
<description>Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ASPE</name>
|
|
<description>Asynchronous Schedule Park Mode Enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PARK_MODE_IS_DISABLE</name>
|
|
<description>Park mode is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PARK_MODE_IS_ENABLED</name>
|
|
<description>Park mode is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Host mode.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FS2</name>
|
|
<description>Bit 2 of the Frame List Size bits. See Table 220.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ITC</name>
|
|
<description>Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBSTS_D</name>
|
|
<description>USB status (device mode)</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UI</name>
|
|
<description>USB interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UEI</name>
|
|
<description>USB error interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCI</name>
|
|
<description>Port change detect.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AAI</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>URI</name>
|
|
<description>USB reset received</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>When the device controller detects a USB Reset and enters the default state, this bit will be set to a one.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRI</name>
|
|
<description>SOF received</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLI</name>
|
|
<description>DCSuspend</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>When a device controller enters a suspend state from an active state, this bit will be set to a one.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Software should only write 0 to reserved bits.</description>
|
|
<bitRange>[11:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NAKI</name>
|
|
<description>NAK interrupt bit</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Software should only write 0 to reserved bits.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Software should only write 0 to reserved bits.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBSTS_H</name>
|
|
<description>USB status (host mode)</description>
|
|
<alternateRegister>USBSTS_D</alternateRegister>
|
|
<addressOffset>0x144</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UI</name>
|
|
<description>USB interrupt (USBINT)</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UEI</name>
|
|
<description>USB error interrupt (USBERRINT)</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCI</name>
|
|
<description>Port change detect.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRI</name>
|
|
<description>Frame list roll-over</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AAI</name>
|
|
<description>Interrupt on async advance</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Host controller.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SRI</name>
|
|
<description>SOF received</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Host controller.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[11:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HCH</name>
|
|
<description>HCHalted</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RS</name>
|
|
<description>The RS bit in USBCMD is set to zero. Set by the host controller.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCL</name>
|
|
<description>Reclamation</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EMPTY_ASYNCHRONOU</name>
|
|
<description>No empty asynchronous schedule detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY_ASYNCHRONOU</name>
|
|
<description>An empty asynchronous schedule is detected. Set by the host controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The periodic schedule status is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The periodic schedule status is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AS</name>
|
|
<description>Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Asynchronous schedule status is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Asynchronous schedule status is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used on Host mode.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>UAI</name>
|
|
<description>USB host asynchronous interrupt (USBHSTASYNCINT)</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UPI</name>
|
|
<description>USB host periodic interrupt (USBHSTPERINT)</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBINTR_D</name>
|
|
<description>USB interrupt enable (device mode)</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UE</name>
|
|
<description>USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UEE</name>
|
|
<description>USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCE</name>
|
|
<description>Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Device controller.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Device controller.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>URE</name>
|
|
<description>USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLE</name>
|
|
<description>Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NAKE</name>
|
|
<description>NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Device controller.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Device controller.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBINTR_H</name>
|
|
<description>USB interrupt enable (host mode)</description>
|
|
<alternateRegister>USBINTR_D</alternateRegister>
|
|
<addressOffset>0x148</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UE</name>
|
|
<description>USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UEE</name>
|
|
<description>USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCE</name>
|
|
<description>Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRE</name>
|
|
<description>Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AAE</name>
|
|
<description>Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Host controller.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Host controller.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the host controller.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UAIE</name>
|
|
<description>USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UPIA</name>
|
|
<description>USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRINDEX_D</name>
|
|
<description>USB frame index (device mode)</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRINDEX2_0</name>
|
|
<description>Current micro frame number</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRINDEX13_3</name>
|
|
<description>Current frame number of the last frame transmitted</description>
|
|
<bitRange>[13:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRINDEX_H</name>
|
|
<description>USB frame index (host mode)</description>
|
|
<alternateRegister>FRINDEX_D</alternateRegister>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRINDEX2_0</name>
|
|
<description>Current micro frame number</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRINDEX12_3</name>
|
|
<description>Frame list current index.</description>
|
|
<bitRange>[12:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICEADDR</name>
|
|
<description>USB device address (device mode)</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USBADRA</name>
|
|
<description>Device address advance</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INSTANTANEOUS</name>
|
|
<description>Any write to USBADR are instantaneous.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DELAYED</name>
|
|
<description>When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBADR</name>
|
|
<description>USB device address</description>
|
|
<bitRange>[31:25]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERIODICLISTBASE</name>
|
|
<description>Frame list base address (host mode)</description>
|
|
<alternateRegister>DEVICEADDR</alternateRegister>
|
|
<addressOffset>0x154</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERBASE31_12</name>
|
|
<description>Base Address (Low) These bits correspond to the memory address signals 31:12.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPOINTLISTADDR</name>
|
|
<description>Address of endpoint list in memory</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPBASE31_11</name>
|
|
<description>Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ASYNCLISTADDR</name>
|
|
<description>Address of endpoint list in memory</description>
|
|
<alternateRegister>ENDPOINTLISTADDR</alternateRegister>
|
|
<addressOffset>0x158</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ASYBASE31_5</name>
|
|
<description>Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH).</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TTCTRL</name>
|
|
<description>Asynchronous buffer status for embedded TT (host mode)</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TTHA</name>
|
|
<description>Hub address when FS or LS device are connected directly.</description>
|
|
<bitRange>[30:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BURSTSIZE</name>
|
|
<description>Programmable burst size</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPBURST</name>
|
|
<description>Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXPBURST</name>
|
|
<description>Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFILLTUNING</name>
|
|
<description>Host transmit pre-buffer packet tuning (host mode)</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXSCHOH</name>
|
|
<description>FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSCHEATLTH</name>
|
|
<description>Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31.</description>
|
|
<bitRange>[12:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOTHRES</name>
|
|
<description>Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode for OTG and SPH.</description>
|
|
<bitRange>[21:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BINTERVAL</name>
|
|
<description>Length of virtual frame</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BINT</name>
|
|
<description>bInterval value (see Section 18.7.7)</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTNAK</name>
|
|
<description>Endpoint NAK (device mode)</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPRN0</name>
|
|
<description>Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRN1</name>
|
|
<description>Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRN2</name>
|
|
<description>Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRN3</name>
|
|
<description>Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRN4</name>
|
|
<description>Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRN5</name>
|
|
<description>Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTN0</name>
|
|
<description>Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTN1</name>
|
|
<description>Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTN2</name>
|
|
<description>Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTN3</name>
|
|
<description>Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTN4</name>
|
|
<description>Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTN5</name>
|
|
<description>Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTNAKEN</name>
|
|
<description>Endpoint NAK Enable (device mode)</description>
|
|
<addressOffset>0x17C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPRNE0</name>
|
|
<description>Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRNE1</name>
|
|
<description>Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRNE2</name>
|
|
<description>Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRNE3</name>
|
|
<description>Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRNE4</name>
|
|
<description>Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRNE5</name>
|
|
<description>Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTNE0</name>
|
|
<description>Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTNE1</name>
|
|
<description>Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTNE2</name>
|
|
<description>Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTNE3</name>
|
|
<description>Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTNE4</name>
|
|
<description>Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTNE5</name>
|
|
<description>Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PORTSC1_D</name>
|
|
<description>Port 1 status/control (device mode)</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCS</name>
|
|
<description>Current connect status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DEVICE_NOT_ATTACHED_</name>
|
|
<description>Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEVICE_ATTACHED__A_</name>
|
|
<description>Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Port enable. This bit is always 1. The device port is always enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PEC</name>
|
|
<description>Port enable/disable change This bit is always 0. The device port is always enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FPR</name>
|
|
<description>Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESUME</name>
|
|
<description>No resume (K-state) detected/driven on port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESUME_DETECTED</name>
|
|
<description>Resume detected/driven on port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Suspend In device mode, this is a read-only status bit .</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_NOT_IN_SUSPEND_</name>
|
|
<description>Port not in suspend state</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORT_IN_SUSPEND_STAT</name>
|
|
<description>Port in suspend state</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_IS_NOT_IN_THE_R</name>
|
|
<description>Port is not in the reset state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORT_IS_IN_THE_RESET</name>
|
|
<description>Port is in the reset state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSP</name>
|
|
<description>High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_HIGHSSPEED</name>
|
|
<description>Host/device connected to the port is not in High-speed mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGHSPEED</name>
|
|
<description>Host/device connected to the port is in High-speed mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PIC1_0</name>
|
|
<description>Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Port indicators are off.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AMBER</name>
|
|
<description>amber</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GREEN</name>
|
|
<description>green</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEFINED</name>
|
|
<description>undefined</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTC3_0</name>
|
|
<description>Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TEST_MODE_DISABLE</name>
|
|
<description>TEST_MODE_DISABLE</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>J_STATE</name>
|
|
<description>J_STATE</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>K_STATE</name>
|
|
<description>K_STATE</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE0_NAK</name>
|
|
<description>SE0 (host)/NAK (device)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PACKET</name>
|
|
<description>Packet</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_ENABLE_HS</name>
|
|
<description>FORCE_ENABLE_HS</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_ENABLE_FS</name>
|
|
<description>FORCE_ENABLE_FS</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode. This bit is always 0 in device mode.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode. This bit is always 0 in device mode.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode. This bit is always 0 in device mode.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PHCD</name>
|
|
<description>PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFSC</name>
|
|
<description>Port force full speed connect</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANYSPEED</name>
|
|
<description>Port connects at any speed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULLSPEED</name>
|
|
<description>Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PSPD</name>
|
|
<description>Port speed This register field indicates the speed at which the port is operating.</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FULL_SPEED</name>
|
|
<description>Full-speed</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_IN_DEVICE_MO</name>
|
|
<description>invalid in device mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_SPEED</name>
|
|
<description>High-speed</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PORTSC1_H</name>
|
|
<description>Port 1 status/control (host mode)</description>
|
|
<alternateRegister>PORTSC1_D</alternateRegister>
|
|
<addressOffset>0x184</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCS</name>
|
|
<description>Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_DEVICE_IS_PRESENT</name>
|
|
<description>No device is present.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEVICE_IS_PRESENT_ON</name>
|
|
<description>Device is present on the port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSC</name>
|
|
<description>Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_IN_CURRENT</name>
|
|
<description>No change in current status.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANGE_IN_CURRENT_ST</name>
|
|
<description>Change in current status.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_DISABLED_</name>
|
|
<description>Port disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORT_ENABLED_</name>
|
|
<description>Port enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEC</name>
|
|
<description>Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_</name>
|
|
<description>No change.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANGED</name>
|
|
<description>Port enabled/disabled status has changed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCA</name>
|
|
<description>Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PORT_DOES_NOT_HA</name>
|
|
<description>The port does not have an over-current condition.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PORT_HAS_CURRENT</name>
|
|
<description>The port has currently an over-current condition.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCC</name>
|
|
<description>Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FPR</name>
|
|
<description>Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESUME</name>
|
|
<description>No resume (K-state) detected/driven on port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESUME_DETECTED</name>
|
|
<description>Resume detected/driven on port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_NOT_IN_SUSPEND_</name>
|
|
<description>Port not in suspend state</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORT_IN_SUSPEND_STAT</name>
|
|
<description>Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_IS_NOT_IN_THE_R</name>
|
|
<description>Port is not in the reset state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORT_IS_IN_THE_RESET</name>
|
|
<description>Port is in the reset state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSP</name>
|
|
<description>High-speed status</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_HISPEED</name>
|
|
<description>Host/device connected to the port is not in High-speed mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HISPEED</name>
|
|
<description>Host/device connected to the port is in High-speed mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LS</name>
|
|
<description>Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SE0</name>
|
|
<description>SE0 (USB_DP and USB_DM LOW)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>J_STATE</name>
|
|
<description>J-state (USB_DP HIGH and USB_DM LOW)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>K_STATE</name>
|
|
<description>K-state (USB_DP LOW and USB_DM HIGH)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEFINED</name>
|
|
<description>Undefined</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PP</name>
|
|
<description>Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_POWER_OFF_</name>
|
|
<description>Port power off.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORT_POWER_ON_</name>
|
|
<description>Port power on.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PIC1_0</name>
|
|
<description>Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_INDICATORS_ARE_</name>
|
|
<description>Port indicators are off.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AMBER</name>
|
|
<description>Amber</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GREEN</name>
|
|
<description>Green</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEFINED</name>
|
|
<description>Undefined</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTC3_0</name>
|
|
<description>Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TEST_MODE_DISABLE</name>
|
|
<description>TEST_MODE_DISABLE</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>J_STATE</name>
|
|
<description>J_STATE</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>K_STATE</name>
|
|
<description>K_STATE</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE0_NAK</name>
|
|
<description>SE0 (host)/NAK (device)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PACKET</name>
|
|
<description>Packet</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_ENABLE_HS</name>
|
|
<description>FORCE_ENABLE_HS</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_ENABLE_FS</name>
|
|
<description>FORCE_ENABLE_FS</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_ENABLE_LS</name>
|
|
<description>FORCE_ENABLE_LS</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKCN</name>
|
|
<description>Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLES_THE_PORT_TO</name>
|
|
<description>Disables the port to wake up on device connects.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_THIS_BIT_TO_</name>
|
|
<description>Writing this bit to a one enables the port to be sensitive to device connects as wake-up events.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKDC</name>
|
|
<description>Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLES_THE_PORT_TO</name>
|
|
<description>Disables the port to wake up on device disconnects.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_THIS_BIT_TO_</name>
|
|
<description>Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKOC</name>
|
|
<description>Wake on over-current enable (WKOC_E)</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLES_THE_PORT_TO</name>
|
|
<description>Disables the port to wake up on over-current events.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_ONE_TO_THI</name>
|
|
<description>Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHCD</name>
|
|
<description>PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_0_ENABLES_</name>
|
|
<description>Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_A_1_DISABLES</name>
|
|
<description>Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFSC</name>
|
|
<description>Port force full speed connect</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_CONNECTS_AT_ANY</name>
|
|
<description>Port connects at any speed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITING_THIS_BIT_TO_</name>
|
|
<description>Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PSPD</name>
|
|
<description>Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FULL_SPEED</name>
|
|
<description>Full-speed</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_SPEED</name>
|
|
<description>Low-speed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_SPEED</name>
|
|
<description>High-speed</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>OTGSC</name>
|
|
<description>OTG status and control</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VD</name>
|
|
<description>VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VC</name>
|
|
<description>VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HAAR</name>
|
|
<description>Hardware assist auto_reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTOMATIC_RES</name>
|
|
<description>Enable automatic reset after connect on host port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OT</name>
|
|
<description>OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DP</name>
|
|
<description>Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IDPU</name>
|
|
<description>ID pull-up. This bit provides control over the pull-up resistor.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_OFF_THE_ID_</name>
|
|
<description>Pull-up off. The ID bit will not be sampled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_ON_</name>
|
|
<description>Pull-up on.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HADP</name>
|
|
<description>Hardware assist data pulse Write a 1 to start data pulse sequence.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HABA</name>
|
|
<description>Hardware assist B-disconnect to A-connect</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTOMATIC_B_D</name>
|
|
<description>Enable automatic B-disconnect to A-connect sequence.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>USB ID</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>A_DEVICE</name>
|
|
<description>A-device</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>B_DEVICE</name>
|
|
<description>B-device</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVV</name>
|
|
<description>A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ASV</name>
|
|
<description>A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BSV</name>
|
|
<description>B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BSE</name>
|
|
<description>B-session end Reading 1 indicates that VBUS is below the B-session end threshold.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MS1T</name>
|
|
<description>1 millisecond timer toggle This bit toggles once per millisecond.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DPS</name>
|
|
<description>Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IDIS</name>
|
|
<description>USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AVVIS</name>
|
|
<description>A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ASVIS</name>
|
|
<description>A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BSVIS</name>
|
|
<description>B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BSEIS</name>
|
|
<description>B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold. Software must write a 1 to this bit to clear it.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ms1S</name>
|
|
<description>1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DPIS</name>
|
|
<description>Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IDIE</name>
|
|
<description>USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AVVIE</name>
|
|
<description>A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ASVIE</name>
|
|
<description>A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BSVIE</name>
|
|
<description>B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BSEIE</name>
|
|
<description>B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MS1E</name>
|
|
<description>1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DPIE</name>
|
|
<description>Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBMODE_D</name>
|
|
<description>USB device mode (device mode)</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CM1_0</name>
|
|
<description>Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>Idle</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEVICE_CONTROLLER</name>
|
|
<description>Device controller</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOST_CONTROLLER</name>
|
|
<description>Host controller</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ES</name>
|
|
<description>Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LITTLE_ENDIAN_FIRST</name>
|
|
<description>Little endian: first byte referenced in least significant byte of 32-bit word.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIG_ENDIAN_FIRST_BY</name>
|
|
<description>Big endian: first byte referenced in most significant byte of 32-bit word.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLOM</name>
|
|
<description>Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SETUP_LOCKOUTS_ON</name>
|
|
<description>Setup Lockouts on</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETUP_LOCKOUTS_OFF</name>
|
|
<description>Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDIS</name>
|
|
<description>Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_DISABLED</name>
|
|
<description>Not disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_SETTING_TH</name>
|
|
<description>Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBMODE_H</name>
|
|
<description>USB mode (host mode)</description>
|
|
<alternateRegister>USBMODE_D</alternateRegister>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CM</name>
|
|
<description>Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>Idle</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEVICE_CONTROLLER</name>
|
|
<description>Device controller</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOST_CONTROLLER</name>
|
|
<description>Host controller</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ES</name>
|
|
<description>Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LITTLE_ENDIAN_FIRST</name>
|
|
<description>Little endian: first byte referenced in least significant byte of 32-bit word.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIG_ENDIAN_FIRST_BY</name>
|
|
<description>Big endian: first byte referenced in most significant byte of 32-bit word.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in host mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SDIS</name>
|
|
<description>Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_DISABLED</name>
|
|
<description>Not disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_SETTING_TO</name>
|
|
<description>Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VBPS</name>
|
|
<description>VBUS power select</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>vbus_pwr_select is set LOW.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>vbus_pwr_select is set HIGH</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTSETUPSTAT</name>
|
|
<description>Endpoint setup status</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENDPTSETUPSTAT0</name>
|
|
<description>Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENDPTSETUPSTAT1</name>
|
|
<description>Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENDPTSETUPSTAT2</name>
|
|
<description>Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENDPTSETUPSTAT3</name>
|
|
<description>Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENDPTSETUPSTAT4</name>
|
|
<description>Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENDPTSETUPSTAT5</name>
|
|
<description>Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTPRIME</name>
|
|
<description>Endpoint initialization</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERB0</name>
|
|
<description>Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERB1</name>
|
|
<description>Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERB2</name>
|
|
<description>Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERB3</name>
|
|
<description>Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERB4</name>
|
|
<description>Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERB5</name>
|
|
<description>Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PETB0</name>
|
|
<description>Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PETB1</name>
|
|
<description>Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PETB2</name>
|
|
<description>Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PETB3</name>
|
|
<description>Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PETB4</name>
|
|
<description>Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PETB5</name>
|
|
<description>Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTFLUSH</name>
|
|
<description>Endpoint de-initialization</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FERB0</name>
|
|
<description>Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FERB1</name>
|
|
<description>Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FERB2</name>
|
|
<description>Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FERB3</name>
|
|
<description>Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FERB4</name>
|
|
<description>Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FERB5</name>
|
|
<description>Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FETB0</name>
|
|
<description>Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FETB1</name>
|
|
<description>Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FETB2</name>
|
|
<description>Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FETB3</name>
|
|
<description>Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FETB4</name>
|
|
<description>Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FETB5</name>
|
|
<description>Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTSTAT</name>
|
|
<description>Endpoint status</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERBR0</name>
|
|
<description>Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERBR1</name>
|
|
<description>Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERBR2</name>
|
|
<description>Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERBR3</name>
|
|
<description>Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERBR4</name>
|
|
<description>Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERBR5</name>
|
|
<description>Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETBR0</name>
|
|
<description>Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETBR1</name>
|
|
<description>Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETBR2</name>
|
|
<description>Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETBR3</name>
|
|
<description>Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETBR4</name>
|
|
<description>Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETBR5</name>
|
|
<description>Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCOMPLETE</name>
|
|
<description>Endpoint complete</description>
|
|
<addressOffset>0x1BC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERCE0</name>
|
|
<description>Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERCE1</name>
|
|
<description>Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERCE2</name>
|
|
<description>Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERCE3</name>
|
|
<description>Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERCE4</name>
|
|
<description>Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERCE5</name>
|
|
<description>Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETCE0</name>
|
|
<description>Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETCE1</name>
|
|
<description>Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETCE2</name>
|
|
<description>Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETCE3</name>
|
|
<description>Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETCE4</name>
|
|
<description>Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETCE5</name>
|
|
<description>Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCTRL0</name>
|
|
<description>Endpoint control 0</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Rx endpoint stall</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_OK_</name>
|
|
<description>Endpoint ok.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_STALLED_SOF</name>
|
|
<description>Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXT1_0</name>
|
|
<description>Endpoint type Endpoint 0 is always a control endpoint.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>Tx endpoint stall</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_OK_</name>
|
|
<description>Endpoint ok.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_STALLED_SOF</name>
|
|
<description>Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXT1_0</name>
|
|
<description>Endpoint type Endpoint 0 is always a control endpoint.</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[22:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-5</dimIndex>
|
|
<name>ENDPTCTRL%s</name>
|
|
<description>Endpoint control </description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Rx endpoint stall</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_OK_THIS_BI</name>
|
|
<description>Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_STALLED_SOF</name>
|
|
<description>Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>Endpoint type</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISOCHRONOUS</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXI</name>
|
|
<description>Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXR</name>
|
|
<description>Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>Rx endpoint enable An endpoint should be enabled only after it has been configured.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_DISABLED_</name>
|
|
<description>Endpoint disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_ENABLED_</name>
|
|
<description>Endpoint enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>Tx endpoint stall</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_OK_THIS_BI</name>
|
|
<description>Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_STALLED_SOF</name>
|
|
<description>Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXT1_0</name>
|
|
<description>Tx endpoint type</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISOCHRONOUS</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXI</name>
|
|
<description>Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXR</name>
|
|
<description>Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Tx endpoint enable An endpoint should be enabled only after it has been configured</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_DISABLED_</name>
|
|
<description>Endpoint disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_ENABLED_</name>
|
|
<description>Endpoint enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>USB1</name>
|
|
<description>USB1 Host/Device controller </description>
|
|
|
|
<baseAddress>0x40007000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USB1</name>
|
|
<value>9</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CAPLENGTH</name>
|
|
<description>Capability register length</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00010040</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPLENGTH</name>
|
|
<description>Indicates offset to add to the register base address at the beginning of the Operational Register</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HCIVERSION</name>
|
|
<description>BCD encoding of the EHCI revision number supported by this host controller.</description>
|
|
<bitRange>[23:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are reserved and should be set to zero.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCSPARAMS</name>
|
|
<description>Host controller structural parameters</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00010011</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>N_PORTS</name>
|
|
<description>Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PPC</name>
|
|
<description>Port Power Control. This field indicates whether the host controller implementation includes port power control.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are reserved and should be set to zero.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>N_PCC</name>
|
|
<description>Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>N_CC</name>
|
|
<description>Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PI</name>
|
|
<description>Port indicators. This bit indicates whether the ports support port indicator control.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are reserved and should be set to zero.</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>N_PTT</name>
|
|
<description>Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller.</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>N_TT</name>
|
|
<description>Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller.</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are reserved and should be set to zero.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCCPARAMS</name>
|
|
<description>Host controller capability parameters</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000005</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC</name>
|
|
<description>64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PFL</name>
|
|
<description>Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ASP</name>
|
|
<description>Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IST</name>
|
|
<description>Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EECP</name>
|
|
<description>EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are reserved and should be set to zero.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCIVERSION</name>
|
|
<description>Device interface version number</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCIVERSION</name>
|
|
<description>The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are reserved and should be set to zero.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCMD_D</name>
|
|
<description>USB command (device mode)</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00040000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Run/Stop</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETACH</name>
|
|
<description>Writing a 0 to this bit will cause a detach event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ATACH</name>
|
|
<description>Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESETCOMPLETE</name>
|
|
<description>Set to 0 by hardware when the reset process is complete.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. These bits should be set to 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.These bits should be set to 0.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.These bits should be set to 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SUTW</name>
|
|
<description>Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10).</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ATDTW</name>
|
|
<description>Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FS2</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ITC</name>
|
|
<description>Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBCMD_H</name>
|
|
<description>USB command (host mode)</description>
|
|
<alternateRegister>USBCMD_D</alternateRegister>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000400B0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Run/Stop</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HALT</name>
|
|
<description>When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PROCEED</name>
|
|
<description>When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESETCOMPLETE</name>
|
|
<description>This bit is set to zero by hardware when the reset process is complete.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FS0</name>
|
|
<description>Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FS1</name>
|
|
<description>Bit 1 of the Frame List Size bits. See Table 281</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PSE</name>
|
|
<description>This bit controls whether the host controller skips processing the periodic schedule.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_PROCESS_THE_P</name>
|
|
<description>Do not process the periodic schedule.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USE_THE_PERIODICLIST</name>
|
|
<description>Use the PERIODICLISTBASE register to access the periodic schedule.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ASE</name>
|
|
<description>This bit controls whether the host controller skips processing the asynchronous schedule.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_PROCESS_THE_A</name>
|
|
<description>Do not process the asynchronous schedule.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USE_THE_ASYNCLISTADD</name>
|
|
<description>Use the ASYNCLISTADDR to access the asynchronous schedule.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IAA</name>
|
|
<description>This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOORBELL</name>
|
|
<description>Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ASP1_0</name>
|
|
<description>Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ASPE</name>
|
|
<description>Asynchronous Schedule Park Mode Enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PARK_MODE_IS_DISABLE</name>
|
|
<description>Park mode is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PARK_MODE_IS_ENABLED</name>
|
|
<description>Park mode is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Host mode.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FS2</name>
|
|
<description>Bit 2 of the Frame List Size bits. See Table 281.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ITC</name>
|
|
<description>Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBSTS_D</name>
|
|
<description>USB status (device mode)</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UI</name>
|
|
<description>USB interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UEI</name>
|
|
<description>USB error interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCI</name>
|
|
<description>Port change detect.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>URI</name>
|
|
<description>USB reset received</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>When the device controller detects a USB Reset and enters the default state, this bit will be set to a one.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRI</name>
|
|
<description>SOF received</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLI</name>
|
|
<description>DCSuspend</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>When a device controller enters a suspend state from an active state, this bit will be set to a one.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Software should only write 0 to reserved bits.</description>
|
|
<bitRange>[11:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NAKI</name>
|
|
<description>NAK interrupt bit</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENDPCLEAR</name>
|
|
<description>This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Software should only write 0 to reserved bits.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in Device mode.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Software should only write 0 to reserved bits.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBSTS_H</name>
|
|
<description>USB status (host mode)</description>
|
|
<alternateRegister>USBSTS_D</alternateRegister>
|
|
<addressOffset>0x144</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00001000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UI</name>
|
|
<description>USB interrupt (USBINT)</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UEI</name>
|
|
<description>USB error interrupt (USBERRINT)</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCI</name>
|
|
<description>Port change detect.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRI</name>
|
|
<description>Frame list roll-over</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AAI</name>
|
|
<description>Interrupt on async advance</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Host controller.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SRI</name>
|
|
<description>SOF received</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLI</name>
|
|
<description>Not used by the Host controller.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[11:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>HCH</name>
|
|
<description>HCHalted</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RS</name>
|
|
<description>The RS bit in USBCMD is set to zero. Set by the host controller.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCL</name>
|
|
<description>Reclamation</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EMPTY_ASYNCHRONOU</name>
|
|
<description>No empty asynchronous schedule detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY_ASYNCHRONOU</name>
|
|
<description>An empty asynchronous schedule is detected. Set by the host controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The periodic schedule status is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The periodic schedule status is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AS</name>
|
|
<description>Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Asynchronous schedule status is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Asynchronous schedule status is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used on Host mode.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>UAI</name>
|
|
<description>USB host asynchronous interrupt (USBHSTASYNCINT)</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UPI</name>
|
|
<description>USB host periodic interrupt (USBHSTPERINT)</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ST</name>
|
|
<description>This bit is cleared by software writing a one to it.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBINTR_D</name>
|
|
<description>USB interrupt enable (device mode)</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UE</name>
|
|
<description>USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UEE</name>
|
|
<description>USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCE</name>
|
|
<description>Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Device controller.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Device controller.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>URE</name>
|
|
<description>USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SLE</name>
|
|
<description>Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NAKE</name>
|
|
<description>NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UAIE</name>
|
|
<description>Not used by the Device controller.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UPIA</name>
|
|
<description>Not used by the Device controller.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBINTR_H</name>
|
|
<description>USB interrupt enable (host mode)</description>
|
|
<alternateRegister>USBINTR_D</alternateRegister>
|
|
<addressOffset>0x148</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UE</name>
|
|
<description>USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UEE</name>
|
|
<description>USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCE</name>
|
|
<description>Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRE</name>
|
|
<description>Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AAE</name>
|
|
<description>Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Host controller.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the Host controller.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used by the host controller.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UAIE</name>
|
|
<description>USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UPIA</name>
|
|
<description>USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRINDEX_D</name>
|
|
<description>USB frame index (device mode)</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRINDEX2_0</name>
|
|
<description>Current micro frame number</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRINDEX13_3</name>
|
|
<description>Current frame number of the last frame transmitted</description>
|
|
<bitRange>[13:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRINDEX_H</name>
|
|
<description>USB frame index (host mode)</description>
|
|
<alternateRegister>FRINDEX_D</alternateRegister>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRINDEX2_0</name>
|
|
<description>Current micro frame number</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRINDEX12_3</name>
|
|
<description>Frame list current index for 1024 elements.</description>
|
|
<bitRange>[12:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICEADDR</name>
|
|
<description>USB device address</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USBADRA</name>
|
|
<description>Device address advance</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ADVANCE</name>
|
|
<description>Any write to USBADR are instantaneous.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOLD</name>
|
|
<description>When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USBADR</name>
|
|
<description>USB device address</description>
|
|
<bitRange>[31:25]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERIODICLISTBASE</name>
|
|
<description>Frame list base address</description>
|
|
<alternateRegister>DEVICEADDR</alternateRegister>
|
|
<addressOffset>0x154</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERBASE31_12</name>
|
|
<description>Base Address (Low) These bits correspond to the memory address signals[31:12].</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPOINTLISTADDR</name>
|
|
<description>Address of endpoint list in memory (device mode)</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[10:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPBASE31_11</name>
|
|
<description>Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ASYNCLISTADDR</name>
|
|
<description>Address of endpoint list in memory (host mode)</description>
|
|
<alternateRegister>ENDPOINTLISTADDR</alternateRegister>
|
|
<addressOffset>0x158</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ASYBASE31_5</name>
|
|
<description>Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH).</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TTCTRL</name>
|
|
<description>Asynchronous buffer status for embedded TT (host mode)</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TTHA</name>
|
|
<description>Hub address when FS or LS device are connected directly.</description>
|
|
<bitRange>[30:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BURSTSIZE</name>
|
|
<description>Programmable burst size</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXPBURST</name>
|
|
<description>Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXPBURST</name>
|
|
<description>Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFILLTUNING</name>
|
|
<description>Host transmit pre-buffer packet tuning (host mode)</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXSCHOH</name>
|
|
<description>FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSCHEATLTH</name>
|
|
<description>Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31.</description>
|
|
<bitRange>[12:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOTHRES</name>
|
|
<description>Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode.</description>
|
|
<bitRange>[21:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ULPIVIEWPORT</name>
|
|
<description>ULPI viewport</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ULPIDATWR</name>
|
|
<description>When a write operation is commanded, the data to be sent is written to this field.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ULPIDATRD</name>
|
|
<description>After a read operation completes, the result is placed in this field.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ULPIADDR</name>
|
|
<description>When a read or write operation is commanded, the address of the operation is written to this field.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ULPIPORT</name>
|
|
<description>For the wakeup or read/write operation to be executed, this value must be written as 0.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ULPISS</name>
|
|
<description>ULPI sync state. This bit represents the state of the ULPI interface.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IN_ANOTHER_STATE</name>
|
|
<description>In another state (ie. carkit, serial, low power)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NORMAL_SYNC_STATE_</name>
|
|
<description>Normal Sync. State.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ULPIRW</name>
|
|
<description>ULPI Read/Write control. This bit selects between running a read or write operation.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>READ</name>
|
|
<description>Read</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WRITE</name>
|
|
<description>Write</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ULPIRUN</name>
|
|
<description>ULPI Read/Write Run. Writing the 1 to this bit will begin the read/write operation. The bit will automatically transition to 0 after the read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ULPIWU</name>
|
|
<description>ULPI Wake-up. Writing the 1 to this bit will begin the wakeup operation. The bit will automatically transition to 0 after the wakeup is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BINTERVAL</name>
|
|
<description>Length of virtual frame</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BINT</name>
|
|
<description>bInterval value</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTNAK</name>
|
|
<description>Endpoint NAK (device mode)</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPRN0</name>
|
|
<description>Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRN1</name>
|
|
<description>Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRN2</name>
|
|
<description>Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRN3</name>
|
|
<description>Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTN16</name>
|
|
<description>Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTN17</name>
|
|
<description>Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTN18</name>
|
|
<description>Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTN19</name>
|
|
<description>Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTNAKEN</name>
|
|
<description>Endpoint NAK Enable (device mode)</description>
|
|
<addressOffset>0x17C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPRNE0</name>
|
|
<description>Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRNE1</name>
|
|
<description>Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRNE2</name>
|
|
<description>Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPRNE3</name>
|
|
<description>Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTNE16</name>
|
|
<description>Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTNE17</name>
|
|
<description>Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTNE18</name>
|
|
<description>Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EPTNE19</name>
|
|
<description>Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PORTSC1_D</name>
|
|
<description>Port 1 status/control (device mode)</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCS</name>
|
|
<description>Current connect status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DEVICE_NOT_ATTACHED_</name>
|
|
<description>Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEVICE_ATTACHED__A_</name>
|
|
<description>Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSC</name>
|
|
<description>Not used in device mode</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Port enable. This bit is always 1. The device port is always enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PEC</name>
|
|
<description>Port enable/disable change This bit is always 0. The device port is always enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FPR</name>
|
|
<description>Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESUME</name>
|
|
<description>No resume (K-state) detected/driven on port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESUME_DETECTED</name>
|
|
<description>Resume detected/driven on port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Suspend In device mode, this is a read-only status bit .</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_NOT_IN_SUSPEND_</name>
|
|
<description>Port not in suspend state</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORT_IN_SUSPEND_STAT</name>
|
|
<description>Port in suspend state</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_IS_NOT_IN_THE_R</name>
|
|
<description>Port is not in the reset state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORT_IS_IN_THE_RESET</name>
|
|
<description>Port is in the reset state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSP</name>
|
|
<description>High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOHISPEED</name>
|
|
<description>Host/device connected to the port is not in High-speed mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HISPEED</name>
|
|
<description>Host/device connected to the port is in High-speed mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LS</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PP</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PIC1_0</name>
|
|
<description>Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Port indicators are off.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AMBER</name>
|
|
<description>amber</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GREEN</name>
|
|
<description>green</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEFINED</name>
|
|
<description>undefined</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTC3_0</name>
|
|
<description>Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TEST_MODE_DISABLE</name>
|
|
<description>TEST_MODE_DISABLE</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>J_STATE</name>
|
|
<description>J_STATE</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>K_STATE</name>
|
|
<description>K_STATE</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE0</name>
|
|
<description>SE0 (host)/NAK (device)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PACKET</name>
|
|
<description>Packet</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_ENABLE_HS</name>
|
|
<description>FORCE_ENABLE_HS</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_ENABLE_FS</name>
|
|
<description>FORCE_ENABLE_FS</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode. This bit is always 0 in device mode.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode. This bit is always 0 in device mode.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode. This bit is always 0 in device mode.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PHCD</name>
|
|
<description>PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFSC</name>
|
|
<description>Port force full speed connect</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANYSPEED</name>
|
|
<description>Port connects at any speed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULLSPEED</name>
|
|
<description>Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PSPD</name>
|
|
<description>Port speed This register field indicates the speed at which the port is operating.</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FULL_SPEED</name>
|
|
<description>Full-speed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVALID_IN_DEVICE_MO</name>
|
|
<description>invalid in device mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_SPEED</name>
|
|
<description>High-speed</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PTS</name>
|
|
<description>Parallel transceiver select. All other values are reserved.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ULPI</name>
|
|
<description>ULPI</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERIAL</name>
|
|
<description>Serial/ 1.1 PHY (Full-speed only)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PORTSC1_H</name>
|
|
<description>Port 1 status/control (host mode)</description>
|
|
<alternateRegister>PORTSC1_D</alternateRegister>
|
|
<addressOffset>0x184</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCS</name>
|
|
<description>Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_DEVICE_IS_PRESENT</name>
|
|
<description>No device is present.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEVICE_IS_PRESENT_ON</name>
|
|
<description>Device is present on the port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSC</name>
|
|
<description>Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_IN_CURRENT</name>
|
|
<description>No change in current status.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANGE_IN_CURRENT_ST</name>
|
|
<description>Change in current status.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_DISABLED_</name>
|
|
<description>Port disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORT_ENABLED_</name>
|
|
<description>Port enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEC</name>
|
|
<description>Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_</name>
|
|
<description>No change.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANGED</name>
|
|
<description>Port enabled/disabled status has changed.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCA</name>
|
|
<description>Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_PORT_DOES_NOT_HA</name>
|
|
<description>The port does not have an over-current condition.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_PORT_HAS_CURRENT</name>
|
|
<description>The port has currently an over-current condition.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OCC</name>
|
|
<description>Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FPR</name>
|
|
<description>Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESUME</name>
|
|
<description>No resume (K-state) detected/driven on port.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESUME_DETECTED</name>
|
|
<description>Resume detected/driven on port.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_NOT_IN_SUSPEND_</name>
|
|
<description>Port not in suspend state</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORT_IN_SUSPEND_STAT</name>
|
|
<description>Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_IN_RESET</name>
|
|
<description>Port is not in the reset state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORT_IS_IN_THE_RESET</name>
|
|
<description>Port is in the reset state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSP</name>
|
|
<description>High-speed status</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOHIGHSPEED</name>
|
|
<description>Host/device connected to the port is not in High-speed mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGHSPEED</name>
|
|
<description>Host/device connected to the port is in High-speed mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LS</name>
|
|
<description>Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SE0</name>
|
|
<description>SE0 (USB_DP and USB_DM LOW)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>J_STATE</name>
|
|
<description>J-state (USB_DP HIGH and USB_DM LOW)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>K_STATE</name>
|
|
<description>K-state (USB_DP LOW and USB_DM HIGH)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEFINED</name>
|
|
<description>Undefined</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PP</name>
|
|
<description>Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PORT_POWER_OFF_</name>
|
|
<description>Port power off.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PORT_POWER_ON_</name>
|
|
<description>Port power on.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PIC1_0</name>
|
|
<description>Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OFF</name>
|
|
<description>Port indicators are off.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AMBER</name>
|
|
<description>Amber</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GREEN</name>
|
|
<description>Green</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNDEFINED</name>
|
|
<description>Undefined</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PTC3_0</name>
|
|
<description>Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TEST_MODE_DISABLE</name>
|
|
<description>TEST_MODE_DISABLE</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>J_STATE</name>
|
|
<description>J_STATE</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>K_STATE</name>
|
|
<description>K_STATE</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SE0_NAK</name>
|
|
<description>SE0 (host)/NAK (device)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PACKET</name>
|
|
<description>Packet</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_ENABLE_HS</name>
|
|
<description>FORCE_ENABLE_HS</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_ENABLE_FS</name>
|
|
<description>FORCE_ENABLE_FS</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_ENABLE_LS</name>
|
|
<description>FORCE_ENABLE_LS</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKCN</name>
|
|
<description>Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLES_THE_PORT_TO</name>
|
|
<description>Disables the port to wake up on device connects.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_DEVICE_CON</name>
|
|
<description>Writing this bit to a one enables the port to be sensitive to device connects as wake-up events.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKDC</name>
|
|
<description>Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLES_THE_PORT_TO</name>
|
|
<description>Disables the port to wake up on device disconnects.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_DEVICE_CON</name>
|
|
<description>Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WKOC</name>
|
|
<description>Wake on over-current enable (WKOC_E)</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLES_OVERCURRENT</name>
|
|
<description>Disables the port to wake up on over-current events.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_OVERCURRENT</name>
|
|
<description>Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHCD</name>
|
|
<description>PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PHY_CLK</name>
|
|
<description>Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PHY_CLK</name>
|
|
<description>Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFSC</name>
|
|
<description>Port force full speed connect</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANYSPEED</name>
|
|
<description>Port connects at any speed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FULLSPEED</name>
|
|
<description>Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PSPD</name>
|
|
<description>Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FULL_SPEED</name>
|
|
<description>Full-speed</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_SPEED</name>
|
|
<description>Low-speed</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_SPEED</name>
|
|
<description>High-speed</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:28]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PTS</name>
|
|
<description>Parallel transceiver select. All other values are reserved.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ULPI</name>
|
|
<description>ULPI</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SERIAL</name>
|
|
<description>Serial/ 1.1 PHY (Full-speed only)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBMODE_D</name>
|
|
<description>USB mode (device mode)</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CM1_0</name>
|
|
<description>Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>Idle</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEVICE_CONTROLLER</name>
|
|
<description>Device controller</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOST_CONTROLLER</name>
|
|
<description>Host controller</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ES</name>
|
|
<description>Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LITTLE_ENDIAN_FIRST</name>
|
|
<description>Little endian: first byte referenced in least significant byte of 32-bit word.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIG_ENDIAN_FIRST_BY</name>
|
|
<description>Big endian: first byte referenced in most significant byte of 32-bit word.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLOM</name>
|
|
<description>Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SETUP_LOCKOUTS_ON</name>
|
|
<description>Setup Lockouts on</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SETUP_LOCKOUTS_OFF</name>
|
|
<description>Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDIS</name>
|
|
<description>Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_DISABLED</name>
|
|
<description>Not disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_SETTING_TH</name>
|
|
<description>Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in device mode.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USBMODE_H</name>
|
|
<description>USB mode (host mode)</description>
|
|
<alternateRegister>USBMODE_D</alternateRegister>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CM1_0</name>
|
|
<description>Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IDLE</name>
|
|
<description>Idle</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEVICE_CONTROLLER</name>
|
|
<description>Device controller</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HOST_CONTROLLER</name>
|
|
<description>Host controller</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ES</name>
|
|
<description>Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LITTLE_ENDIAN_FIRST</name>
|
|
<description>Little endian: first byte referenced in least significant byte of 32-bit word.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIG_ENDIAN_FIRST_BY</name>
|
|
<description>Big endian: first byte referenced in most significant byte of 32-bit word.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Not used in host mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SDIS</name>
|
|
<description>Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_DISABLED</name>
|
|
<description>Not disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED_SETTING_TO</name>
|
|
<description>Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VBPS</name>
|
|
<description>VBUS power select</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>vbus_pwr_select is set LOW.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>vbus_pwr_select is set HIGH</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTSETUPSTAT</name>
|
|
<description>Endpoint setup status</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENDPTSETUPSTAT0</name>
|
|
<description>Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENDPTSETUPSTAT1</name>
|
|
<description>Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENDPTSETUPSTAT2</name>
|
|
<description>Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENDPTSETUPSTAT3</name>
|
|
<description>Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTPRIME</name>
|
|
<description>Endpoint initialization</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERB0</name>
|
|
<description>Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERB1</name>
|
|
<description>Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERB2</name>
|
|
<description>Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERB3</name>
|
|
<description>Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PETB0</name>
|
|
<description>Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PETB1</name>
|
|
<description>Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PETB2</name>
|
|
<description>Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PETB3</name>
|
|
<description>Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTFLUSH</name>
|
|
<description>Endpoint de-initialization</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FERB0</name>
|
|
<description>Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FERB1</name>
|
|
<description>Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FERB2</name>
|
|
<description>Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FERB3</name>
|
|
<description>Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FETB0</name>
|
|
<description>Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FETB1</name>
|
|
<description>Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FETB2</name>
|
|
<description>Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FETB3</name>
|
|
<description>Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTSTAT</name>
|
|
<description>Endpoint status</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERBR0</name>
|
|
<description>Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERBR1</name>
|
|
<description>Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERBR2</name>
|
|
<description>Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERBR3</name>
|
|
<description>Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETBR0</name>
|
|
<description>Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETBR1</name>
|
|
<description>Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETBR2</name>
|
|
<description>Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETBR3</name>
|
|
<description>Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCOMPLETE</name>
|
|
<description>Endpoint complete</description>
|
|
<addressOffset>0x1BC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERCE0</name>
|
|
<description>Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERCE1</name>
|
|
<description>Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERCE2</name>
|
|
<description>Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERCE3</name>
|
|
<description>Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETCE0</name>
|
|
<description>Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETCE1</name>
|
|
<description>Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETCE2</name>
|
|
<description>Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETCE3</name>
|
|
<description>Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDPTCTRL0</name>
|
|
<description>Endpoint control 0</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Rx endpoint stall</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_OK_</name>
|
|
<description>Endpoint ok.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_STALLED_SOF</name>
|
|
<description>Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>Endpoint type Endpoint 0 is always a control endpoint.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>Tx endpoint stall</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_OK_</name>
|
|
<description>Endpoint ok.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_STALLED_SOF</name>
|
|
<description>Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXT</name>
|
|
<description>Endpoint type Endpoint 0 is always a control endpoint.</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[22:20]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-3</dimIndex>
|
|
<name>ENDPTCTRL%s</name>
|
|
<description>Endpoint control </description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXS</name>
|
|
<description>Rx endpoint stall</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_OK_THIS_BI</name>
|
|
<description>Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_STALLED_SOF</name>
|
|
<description>Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXT</name>
|
|
<description>Endpoint type</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISOCHRONOUS</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXI</name>
|
|
<description>Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXR</name>
|
|
<description>Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXE</name>
|
|
<description>Rx endpoint enable An endpoint should be enabled only after it has been configured.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_DISABLED_</name>
|
|
<description>Endpoint disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_ENABLED_</name>
|
|
<description>Endpoint enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>Tx endpoint stall</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_OK_THIS_BI</name>
|
|
<description>Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_STALLED_SOF</name>
|
|
<description>Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXT</name>
|
|
<description>Tx endpoint type</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>CONTROL</name>
|
|
<description>Control</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ISOCHRONOUS</name>
|
|
<description>Isochronous</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BULK</name>
|
|
<description>Bulk</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT</name>
|
|
<description>Interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXI</name>
|
|
<description>Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXR</name>
|
|
<description>Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Tx endpoint enable An endpoint should be enabled only after it has been configured</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_DISABLED_</name>
|
|
<description>Endpoint disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENDPOINT_ENABLED_</name>
|
|
<description>Endpoint enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>LCD</name>
|
|
<description>LCD controller </description>
|
|
<groupName>LCD</groupName>
|
|
<baseAddress>0x40008000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LCD</name>
|
|
<value>7</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TIMH</name>
|
|
<description>Horizontal Timing Control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PPL</name>
|
|
<description>Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HSW</name>
|
|
<description>Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HFP</name>
|
|
<description>Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HBP</name>
|
|
<description>Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMV</name>
|
|
<description>Vertical Timing Control register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPP</name>
|
|
<description>Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VSW</name>
|
|
<description>Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs.</description>
|
|
<bitRange>[15:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VFP</name>
|
|
<description>Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VBP</name>
|
|
<description>Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POL</name>
|
|
<description>Clock and Signal Polarity Control register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCD_LO</name>
|
|
<description>Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACB</name>
|
|
<description>AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal.</description>
|
|
<bitRange>[10:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IVS</name>
|
|
<description>Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IHS</name>
|
|
<description>Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IPC</name>
|
|
<description>Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IOE</name>
|
|
<description>Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CPL</name>
|
|
<description>Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly.</description>
|
|
<bitRange>[25:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BCD</name>
|
|
<description>Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCD_HI</name>
|
|
<description>Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register.</description>
|
|
<bitRange>[31:27]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LE</name>
|
|
<description>Line End Control register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LED</name>
|
|
<description>Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1.</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LEE</name>
|
|
<description>LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UPBASE</name>
|
|
<description>Upper Panel Frame Base Address register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDUPBASE</name>
|
|
<description>LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPBASE</name>
|
|
<description>Lower Panel Frame Base Address register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDLPBASE</name>
|
|
<description>LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>LCD Control register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCDEN</name>
|
|
<description>LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDBPP</name>
|
|
<description>LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode.</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDBW</name>
|
|
<description>STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDTFT</name>
|
|
<description>LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDMONO8</name>
|
|
<description>Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDDUAL</name>
|
|
<description>Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BGR</name>
|
|
<description>Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BEBO</name>
|
|
<description>Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BEPO</name>
|
|
<description>Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDPWR</name>
|
|
<description>LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active). See LCD power-up and power-down sequence for details on LCD power sequencing.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCDVCOMP</name>
|
|
<description>LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WATERMARK</name>
|
|
<description>LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTMSK</name>
|
|
<description>Interrupt Mask register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FUFIM</name>
|
|
<description>FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LNBUIM</name>
|
|
<description>LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VCOMPIM</name>
|
|
<description>Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BERIM</name>
|
|
<description>AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTRAW</name>
|
|
<description>Raw Interrupt Status register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FUFRIS</name>
|
|
<description>FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the INTMSK register is set.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LNBURIS</name>
|
|
<description>LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the INTMSK register is set.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VCOMPRIS</name>
|
|
<description>Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. Generates an interrupt if the VCompIM bit in the INTMSK register is set.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BERRAW</name>
|
|
<description>AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the INTMSK register is set.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>Masked Interrupt Status register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FUFMIS</name>
|
|
<description>FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the INTRAW register and the FUFIM bit in the INTMSK register are set.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LNBUMIS</name>
|
|
<description>LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the INTRAW register and the LNBUIM bit in the INTMSK register are set.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VCOMPMIS</name>
|
|
<description>Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the INTRAW register and the VCompIM bit in the INTMSK register are set.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BERMIS</name>
|
|
<description>AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the INTRAW register and the BERIM bit in the INTMSK register are set.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<description>Interrupt Clear register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FUFIC</name>
|
|
<description>FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LNBUIC</name>
|
|
<description>LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VCOMPIC</name>
|
|
<description>Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BERIC</name>
|
|
<description>AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UPCURR</name>
|
|
<description>Upper Panel Current Address Value register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCDUPCURR</name>
|
|
<description>LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPCURR</name>
|
|
<description>Lower Panel Current Address Value register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCDLPCURR</name>
|
|
<description>LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>256</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-255</dimIndex>
|
|
<name>PAL[%s]</name>
|
|
|
|
<description>256x16-bit Color Palette registers</description>
|
|
|
|
<addressOffset>0x200</addressOffset>
|
|
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R04_0</name>
|
|
<description>Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>G04_0</name>
|
|
<description>Green palette data.</description>
|
|
<bitRange>[9:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>B04_0</name>
|
|
<description>Blue palette data.</description>
|
|
<bitRange>[14:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I0</name>
|
|
<description>Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>R14_0</name>
|
|
<description>Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields.</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>G14_0</name>
|
|
<description>Green palette data.</description>
|
|
<bitRange>[25:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>B14_0</name>
|
|
<description>Blue palette data.</description>
|
|
<bitRange>[30:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I1</name>
|
|
<description>Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>256</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-255</dimIndex>
|
|
<name>CRSR_IMG[%s]</name>
|
|
<description>Cursor Image registers</description>
|
|
<addressOffset>0x800</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSR_IMG</name>
|
|
<description>Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_CTRL</name>
|
|
<description>Cursor Control register</description>
|
|
<addressOffset>0xC00</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CrsrOn</name>
|
|
<description>Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRSRNUM1_0</name>
|
|
<description>Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_CFG</name>
|
|
<description>Cursor Configuration register</description>
|
|
<addressOffset>0xC04</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CrsrSize</name>
|
|
<description>Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FRAMESYNC</name>
|
|
<description>Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_PAL0</name>
|
|
<description>Cursor Palette register 0</description>
|
|
<addressOffset>0xC08</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RED</name>
|
|
<description>Red color component</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GREEN</name>
|
|
<description>Green color component</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BLUE</name>
|
|
<description>Blue color component.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_PAL1</name>
|
|
<description>Cursor Palette register 1</description>
|
|
<addressOffset>0xC0C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RED</name>
|
|
<description>Red color component</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GREEN</name>
|
|
<description>Green color component</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BLUE</name>
|
|
<description>Blue color component.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_XY</name>
|
|
<description>Cursor XY Position register</description>
|
|
<addressOffset>0xC10</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRX</name>
|
|
<description>X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRSRY</name>
|
|
<description>Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display.</description>
|
|
<bitRange>[25:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_CLIP</name>
|
|
<description>Cursor Clip Position register</description>
|
|
<addressOffset>0xC14</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRCLIPX</name>
|
|
<description>Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRSRCLIPY</name>
|
|
<description>Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image.</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_INTMSK</name>
|
|
<description>Cursor Interrupt Mask register</description>
|
|
<addressOffset>0xC20</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRIM</name>
|
|
<description>Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_INTCLR</name>
|
|
<description>Cursor Interrupt Clear register</description>
|
|
<addressOffset>0xC24</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRIC</name>
|
|
<description>Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_INTRAW</name>
|
|
<description>Cursor Raw Interrupt Status register</description>
|
|
<addressOffset>0xC28</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRRIS</name>
|
|
<description>Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRSR_INTSTAT</name>
|
|
<description>Cursor Masked Interrupt Status register</description>
|
|
<addressOffset>0xC2C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRSRMIS</name>
|
|
<description>Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>EEPROM</name>
|
|
<description>EEPROM</description>
|
|
<groupName>EEPROM</groupName>
|
|
<baseAddress>0x4000E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FLASH</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CMD</name>
|
|
<description>EEPROM command register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RWSTATE</name>
|
|
<description>EEPROM read wait state register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000905</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RPHASE2</name>
|
|
<description>Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RPHASE1</name>
|
|
<description>Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AUTOPROG</name>
|
|
<description>EEPROM auto programming register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUTOPROG</name>
|
|
<description>Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with ......1111100 (last word of a page)</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WSTATE</name>
|
|
<description>EEPROM wait state register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00020602</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PHASE3</name>
|
|
<description>Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PHASE2</name>
|
|
<description>Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PHASE1</name>
|
|
<description>Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[30:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCK_PARWEP</name>
|
|
<description>Lock timing parameters for write, erase and program operation 0 = WSTATE and CLKDIV registers have R/W access 1 = WSTATE and CLKDIV registers have R only access</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>EEPROM clock divider register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000063</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>Division factor (minus 1 encoded).</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWRDWN</name>
|
|
<description>EEPROM power-down register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWRDWN</name>
|
|
<description>Power down mode bit. 0 = not in power down mode. 1 = power down mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENCLR</name>
|
|
<description>EEPROM interrupt enable clear</description>
|
|
<addressOffset>0xFD8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PROG_CLR_EN</name>
|
|
<description>Clear program operation finished interrupt enable bit for EEPROM. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTENSET</name>
|
|
<description>EEPROM interrupt enable set</description>
|
|
<addressOffset>0xFDC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PROG_SET_EN</name>
|
|
<description>Set program operation finished interrupt enable bit for EEPROM device 1. 0 = leave corresponding bit unchanged. 1 = set corresponding bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>EEPROM interrupt status</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>END_OF_PROG</name>
|
|
<description>EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when one is written to the corresponding bit of the INTSTATSET register. - cleared when one is written to the corresponding bit of the INTSTATCLR register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>EEPROM interrupt enable</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EE_PROG_DONE</name>
|
|
<description>EEPROM program operation finished interrupt enable bit. Bit is: - set when one is written in the corresponding bit of the INTENSET register. - cleared when one is written to the corresponding bit of the INTENCLR register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTATCLR</name>
|
|
<description>EEPROM interrupt status clear</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PROG_CLR_ST</name>
|
|
<description>Clear program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>ETHERNET</name>
|
|
<description>Ethernet</description>
|
|
<groupName>ETHERNET</groupName>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ETHERNET</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MAC_CONFIG</name>
|
|
<description>MAC configuration register</description>
|
|
<addressOffset>0x0000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00008000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DF</name>
|
|
<description>Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BL</name>
|
|
<description>Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration. 00: k = min (n, 10) 01: k = min (n, 8) 10: k = min (n, 4) 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 <= r <= 2k.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACS</name>
|
|
<description>Automatic Pad/CRC Stripping When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field. When this bit is reset, the MAC will pass all incoming frames to the Host unmodified.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Link Up/Down Indicates whether the link is up or down during the transmission of configuration in SMII interface: 0 = Link down 1 = Link up</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>Disable Retry When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DM</name>
|
|
<description>Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LM</name>
|
|
<description>Loopback Mode When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DO</name>
|
|
<description>Disable Receive Own When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in Full-Duplex mode.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FES</name>
|
|
<description>Speed Indicates the speed in Fast Ethernet (MII) mode: 0 = 10 Mbps 1 = 100 Mbps</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Port select 1 = MII (100 Mbp) - this is the only allowed value.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DCRS</name>
|
|
<description>Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IFG</name>
|
|
<description>Inter-frame gap These bits control the minimum IFG between frames during transmission. 000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>JE</name>
|
|
<description>Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>JD</name>
|
|
<description>Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WD</name>
|
|
<description>Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes. When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_FRAME_FILTER</name>
|
|
<description>MAC frame filter</description>
|
|
<addressOffset>0x0004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HUC</name>
|
|
<description>Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HMC</name>
|
|
<description>Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DAIF</name>
|
|
<description>DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Pass All Multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DBF</name>
|
|
<description>Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames. When this bit is reset, the AFM module passes all received broadcast frames.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PCF</name>
|
|
<description>Pass Control Frames These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register. 00 = MAC filters all control frames from reaching the application. 01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter. 10 = MAC forwards all control frames to application even if they fail the Address Filter. 11 = MAC forwards control frames that pass the Address Filter.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HPF</name>
|
|
<description>Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[30:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RA</name>
|
|
<description>Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_HASHTABLE_HIGH</name>
|
|
<description>Hash table high register</description>
|
|
<addressOffset>0x0008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HTH</name>
|
|
<description>Hash table high This field contains the upper 32 bits of Hash table.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_HASHTABLE_LOW</name>
|
|
<description>Hash table low register</description>
|
|
<addressOffset>0x000C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HTL</name>
|
|
<description>Hash table low This field contains the upper 32 bits of Hash table.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_MII_ADDR</name>
|
|
<description>MII address register</description>
|
|
<addressOffset>0x0010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GB</name>
|
|
<description>MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>W</name>
|
|
<description>MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR</name>
|
|
<description>CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M4_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks. See Table 554 for bit values.</description>
|
|
<bitRange>[5:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GR</name>
|
|
<description>MII register These bits select the desired MII register in the selected PHY device.</description>
|
|
<bitRange>[10:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Physical layer address This field tells which of the 32 possible PHY devices are being accessed.</description>
|
|
<bitRange>[15:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_MII_DATA</name>
|
|
<description>MII data register</description>
|
|
<addressOffset>0x0014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GD</name>
|
|
<description>MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_FLOW_CTRL</name>
|
|
<description>Flow control register</description>
|
|
<addressOffset>0x0018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FCB</name>
|
|
<description>Flow Control Busy/Backpressure Activate This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TFE</name>
|
|
<description>Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFE</name>
|
|
<description>Receive Flow Control Enable When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UP</name>
|
|
<description>Unicast Pause Frame Detect When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PLT</name>
|
|
<description>Pause Low Threshold This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DZPQ</name>
|
|
<description>Disable Zero-Quanta Pause When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_VLAN_TAG</name>
|
|
<description>VLAN tag register</description>
|
|
<addressOffset>0x001C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VL</name>
|
|
<description>VLAN Tag Identifier for Receive Frames This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETV</name>
|
|
<description>Enable 12-Bit VLAN Tag Comparison When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_DEBUG</name>
|
|
<description>Debug register</description>
|
|
<addressOffset>0x0024</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXIDLESTAT</name>
|
|
<description>When high, it indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFOSTAT0</name>
|
|
<description>When high, it indicates the active state of the small FIFO Read and Write controllers respectively of the MAC receive Frame Controller module.</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFOSTAT1</name>
|
|
<description>When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFOSTAT</name>
|
|
<description>State of the RxFIFO read Controller: 00 = idle state 01 = reading frame data 10 = reading frame status (or Time stamp) 11 = flushing the frame data and status</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFOLVL</name>
|
|
<description>Status of the RxFIFO Fill-level 00 = RxFIFO Empty 01 = RxFIFO fill-level below flow-control de-activate threshold 10 = RxFIFO fill-level above flow-control activate threshold 11 = RxFIFO Full</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXIDLESTAT</name>
|
|
<description>When high, it indicates that the MAC MII transmit protocol engine is actively transmitting data and not in IDLE state.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXSTAT</name>
|
|
<description>State of the MAC Transmit Frame Controller module: 00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over 10 = Generating and transmitting a PAUSE control frame (in full duplex mode) 11 = Transferring input frame for transmission</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PAUSE</name>
|
|
<description>When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOSTAT</name>
|
|
<description>State of the TxFIFO read Controller 00 = idle state 01 = READ state (transferring data to MAC transmitter) 10 = Waiting for TxStatus from MAC transmitter 11 = Writing the received TxStatus or flushing the TxFIFO</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOSTAT1</name>
|
|
<description>When high, it indicates that the TxFIFO Write Controller is active and transferring data to the TxFIFO.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOLVL</name>
|
|
<description>When high, it indicates that the TxFIFO is not empty and has some data left for transmission.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOFULL</name>
|
|
<description>When high, it indicates that the TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_RWAKE_FRFLT</name>
|
|
<description>Remote wake-up frame filter</description>
|
|
<addressOffset>0x0028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>WKUPFMFILTER address</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_PMT_CTRL_STAT</name>
|
|
<description>PMT control and status</description>
|
|
<addressOffset>0x002C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPE</name>
|
|
<description>Magic packet enable When set, enables generation of a power management event due to Magic Packet reception.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WFE</name>
|
|
<description>Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPR</name>
|
|
<description>Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WFR</name>
|
|
<description>Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GU</name>
|
|
<description>Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[30:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WFFRPR</name>
|
|
<description>Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_INTR</name>
|
|
<description>Interrupt status register</description>
|
|
<addressOffset>0x0038</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMT</name>
|
|
<description>PMT Interrupt Status This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power- Down mode (See bits 5 and 6 in Table 560). This bit is cleared when both bits[6:5] are cleared because of a read operation to the PMT Control and Status register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers - There is an overflow in the seconds register This bit is cleared on reading the byte 0 of the Timestamp Status register (Table 576). Otherwise, when default Time stamping is enabled, this bit when set indicates that the system time value equals or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this Interrupt Status Register[9]. In all other modes, this bit is reserved.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_INTR_MASK</name>
|
|
<description>Interrupt mask register</description>
|
|
<addressOffset>0x003C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMTIM</name>
|
|
<description>PMT Interrupt Mask This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[8:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSIM</name>
|
|
<description>Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_ADDR0_HIGH</name>
|
|
<description>MAC address 0 high register</description>
|
|
<addressOffset>0x0040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8000FFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>A47_32</name>
|
|
<description>MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[30:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MO</name>
|
|
<description>Always 1</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_ADDR0_LOW</name>
|
|
<description>MAC address 0 low register</description>
|
|
<addressOffset>0x0044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>A31_0</name>
|
|
<description>MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_TIMESTP_CTRL</name>
|
|
<description>Time stamp control register</description>
|
|
<addressOffset>0x0700</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00002000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSENA</name>
|
|
<description>Time stamp Enable When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSCFUPDT</name>
|
|
<description>Time stamp Fine or Coarse Update When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSINIT</name>
|
|
<description>Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSUPDT</name>
|
|
<description>Time stamp Update This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSTRIG</name>
|
|
<description>Time stamp Interrupt Trigger Enable This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSADDREG</name>
|
|
<description>Addend Reg Update When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSENALL</name>
|
|
<description>Enable Time stamp for All Frames When set, the Time stamp snapshot is enabled for all frames received by the core.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSCTRLSSR</name>
|
|
<description>Time stamp Digital or Binary rollover control When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSVER2ENA</name>
|
|
<description>Enable PTP packet snooping for version 2 format When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSIPENA</name>
|
|
<description>Enable Time stamp Snapshot for PTP over Ethernet frames When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSIPV6ENA</name>
|
|
<description>Enable Time stamp Snapshot for IPv6 frames When set, the Time stamp snapshot is taken for IPv6 frames.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSIPV4ENA</name>
|
|
<description>Enable Time stamp Snapshot for IPv4 frames When set, the Time stamp snapshot is taken for IPv4 frames.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSEVNTENA</name>
|
|
<description>Enable Time stamp Snapshot for Event Messages When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSMSTRENA</name>
|
|
<description>Enable Snapshot for Messages Relevant to Master When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSCLKTYPE</name>
|
|
<description>Select the type of clock node The following are the options to select the type of clock node: 00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSENMACADDR</name>
|
|
<description>Enable MAC address for PTP frame filtering When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SUBSECOND_INCR</name>
|
|
<description>Sub-second increment register</description>
|
|
<addressOffset>0x0704</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSINC</name>
|
|
<description>Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.)</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SECONDS</name>
|
|
<description>System time seconds register</description>
|
|
<addressOffset>0x0708</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSS</name>
|
|
<description>Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the core.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NANOSECONDS</name>
|
|
<description>System time nanoseconds register</description>
|
|
<addressOffset>0x070C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSSS</name>
|
|
<description>Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR in the MAC_TIMESTAMP_CTRL register is set, each bit represents 1 ns and the maximum value will be 0x3B9A_C9FF, after which it rolls-over to zero).</description>
|
|
<bitRange>[30:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSNT</name>
|
|
<description>Positive or negative time This bit indicates positive or negative time value. If the bit is reset, it indicates that the time representation is positive, and if it is set, it indicates negative time value. (This bit represents the 32nd bit of the nanoseconds value when the Advance Time stamp feature is enabled).</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SECONDSUPDATE</name>
|
|
<description>System time seconds update register</description>
|
|
<addressOffset>0x0710</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSS</name>
|
|
<description>Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NANOSECONDSUPDATE</name>
|
|
<description>System time nanoseconds update register</description>
|
|
<addressOffset>0x0714</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSSS</name>
|
|
<description>Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.)</description>
|
|
<bitRange>[30:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADDSUB</name>
|
|
<description>Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDEND</name>
|
|
<description>Time stamp addend register</description>
|
|
<addressOffset>0x0718</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSAR</name>
|
|
<description>Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TARGETSECONDS</name>
|
|
<description>Target time seconds register</description>
|
|
<addressOffset>0x071C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSTR</name>
|
|
<description>Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TARGETNANOSECONDS</name>
|
|
<description>Target time nanoseconds register</description>
|
|
<addressOffset>0x0720</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSTR</name>
|
|
<description>Target Time stamp low This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.)</description>
|
|
<bitRange>[30:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HIGHWORD</name>
|
|
<description>System time higher word seconds register</description>
|
|
<addressOffset>0x0724</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSHWR</name>
|
|
<description>Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMESTAMPSTAT</name>
|
|
<description>Time stamp status register</description>
|
|
<addressOffset>0x0728</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSSOVF</name>
|
|
<description>Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSTARGT</name>
|
|
<description>Time stamp target reached When set, indicates the value of system time is greater or equal to the value specified in the Target Time High and Low registers</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_BUS_MODE</name>
|
|
<description>Bus Mode Register</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00020100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SWR</name>
|
|
<description>Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core. The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DA</name>
|
|
<description>DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14] 1 = Rx has priority over Tx</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DSL</name>
|
|
<description>Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode.</description>
|
|
<bitRange>[6:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ATDS</name>
|
|
<description>Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PBL</name>
|
|
<description>Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only. The PBL values have the following limitations. The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly.</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset. 00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FB</name>
|
|
<description>Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RPBL</name>
|
|
<description>RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high.</description>
|
|
<bitRange>[22:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USP</name>
|
|
<description>Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PBL8X</name>
|
|
<description>8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AAL</name>
|
|
<description>Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXPR</name>
|
|
<description>When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_TRANS_POLL_DEMAND</name>
|
|
<description>Transmit poll demand register</description>
|
|
<addressOffset>0x1004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TPD</name>
|
|
<description>Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered. When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_REC_POLL_DEMAND</name>
|
|
<description>Receive poll demand register</description>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RPD</name>
|
|
<description>Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered. When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_REC_DES_ADDR</name>
|
|
<description>Receive descriptor list address register</description>
|
|
<addressOffset>0x100C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRL</name>
|
|
<description>Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_TRANS_DES_ADDR</name>
|
|
<description>Transmit descriptor list address register</description>
|
|
<addressOffset>0x1010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRL</name>
|
|
<description>Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_STAT</name>
|
|
<description>Status register</description>
|
|
<addressOffset>0x1014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TI</name>
|
|
<description>Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TPS</name>
|
|
<description>Transmit process stopped This bit is set when the transmission is stopped.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TU</name>
|
|
<description>Transmit buffer unavailable This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TJT</name>
|
|
<description>Transmit jabber timeout This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVF</name>
|
|
<description>Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11].</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UNF</name>
|
|
<description>Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>Receive interrupt This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RU</name>
|
|
<description>Receive buffer unavailable This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RPS</name>
|
|
<description>Received process stopped This bit is asserted when the Receive Process enters the Stopped state.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RWT</name>
|
|
<description>Receive watchdog timeout This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETI</name>
|
|
<description>Early transmit interrupt This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FBI</name>
|
|
<description>Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERI</name>
|
|
<description>Early receive interrupt This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIE</name>
|
|
<description>Abnormal interrupt summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NIS</name>
|
|
<description>Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued. 001 = Running: Fetching Receive Transfer Descriptor. 010 = Reserved. 011 = Running: Waiting for receive packet. 100 = Suspended: Receive Descriptor Unavailable. 101 = Running: Closing Receive Descriptor. 110 = TIME_STAMP write state. 111 = Running: Transferring the receive packet data from receive buffer to host memory.</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued. 001 = Running; Fetching Transmit Transfer Descriptor. 010 = Running; Waiting for status. 011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO). 100 = TIME_STAMP write state. 101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow. 111 = Running; Closing Transmit Descriptor.</description>
|
|
<bitRange>[22:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EB1</name>
|
|
<description>Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EB2</name>
|
|
<description>Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during read transfer. 0 = Error during write transfer.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EB3</name>
|
|
<description>Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during descriptor access. 0 = Error during data buffer access.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_OP_MODE</name>
|
|
<description>Operation mode register</description>
|
|
<addressOffset>0x1018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SR</name>
|
|
<description>Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OSF</name>
|
|
<description>Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTC</name>
|
|
<description>Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. 00 = 64 01 = 32 10 = 96 11 = 128</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FUF</name>
|
|
<description>Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC). When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[12:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Start/Stop Transmission Command When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TTC</name>
|
|
<description>Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16</description>
|
|
<bitRange>[16:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FTF</name>
|
|
<description>Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission. The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DFF</name>
|
|
<description>Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See).</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:27]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_INT_EN</name>
|
|
<description>Interrupt enable register</description>
|
|
<addressOffset>0x101C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSE</name>
|
|
<description>Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TUE</name>
|
|
<description>Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TJE</name>
|
|
<description>Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVE</name>
|
|
<description>Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UNE</name>
|
|
<description>Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RUE</name>
|
|
<description>Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSE</name>
|
|
<description>Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RWE</name>
|
|
<description>Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETE</name>
|
|
<description>Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FBE</name>
|
|
<description>Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERE</name>
|
|
<description>Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AIE</name>
|
|
<description>Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NIE</name>
|
|
<description>Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_MFRM_BUFOF</name>
|
|
<description>Missed frame and buffer overflow register</description>
|
|
<addressOffset>0x1020</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FMC</name>
|
|
<description>Number of frames missed This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OC</name>
|
|
<description>Overflow bit for missed frame counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FMA</name>
|
|
<description>Number of frames missed by the application This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. Indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal. The counter is cleared when this register is read with .</description>
|
|
<bitRange>[27:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Overflow bit for FIFO overflow counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_REC_INT_WDT</name>
|
|
<description>Receive interrupt watchdog timer register</description>
|
|
<addressOffset>0x1024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RIWT</name>
|
|
<description>RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CURHOST_TRANS_DES</name>
|
|
<description>Current host transmit descriptor register</description>
|
|
<addressOffset>0x1048</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HTD</name>
|
|
<description>Host Transmit Descriptor Address Pointer Cleared on Reset. Pointer updated by DMA during operation.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CURHOST_REC_DES</name>
|
|
<description>Current host receive descriptor register</description>
|
|
<addressOffset>0x104C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HRD</name>
|
|
<description>Host Receive Descriptor Address Pointer Cleared on Reset. Pointer updated by DMA during operation.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CURHOST_TRANS_BUF</name>
|
|
<description>Current host transmit buffer address register</description>
|
|
<addressOffset>0x1050</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HTB</name>
|
|
<description>Host Transmit Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CURHOST_REC_BUF</name>
|
|
<description>Current host receive buffer address register</description>
|
|
<addressOffset>0x1054</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HRB</name>
|
|
<description>Host Receive Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ATIMER</name>
|
|
<description>Alarm timer </description>
|
|
<groupName>ATIMER</groupName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ATIMER</name>
|
|
<value>46</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DOWNCOUNTER</name>
|
|
<description>Downcounter register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CVAL</name>
|
|
<description>When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRESET</name>
|
|
<description>Preset value register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRESETVAL</name>
|
|
<description>Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_EN</name>
|
|
<description>Interrupt clear enable register</description>
|
|
<addressOffset>0xFD8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR_EN</name>
|
|
<description>Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_EN</name>
|
|
<description>Interrupt set enable register</description>
|
|
<addressOffset>0xFDC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET_EN</name>
|
|
<description>Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Status register</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STAT</name>
|
|
<description>A 1 in this bit shows that the STATUS interrupt has been raised.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENABLE</name>
|
|
<description>Enable register</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_STAT</name>
|
|
<description>Clear register</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSTAT</name>
|
|
<description>Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_STAT</name>
|
|
<description>Set register</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSTAT</name>
|
|
<description>Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>REGFILE</name>
|
|
<description> RTC REGFILE </description>
|
|
<groupName>REGFILE</groupName>
|
|
<baseAddress>0x40041000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>64</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-63</dimIndex>
|
|
<name>REGFILE[%s]</name>
|
|
<description>General purpose storage register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REGVAL</name>
|
|
<description>General purpose storage.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMC</name>
|
|
<description>Power Management Controller (PMC)</description>
|
|
<groupName>PMC</groupName>
|
|
<baseAddress>0x40042000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PD0_SLEEP0_HW_ENA</name>
|
|
<description>Hardware sleep event enable register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA_EVENT0</name>
|
|
<description>Writing a 1 enables the Cortex-M4 core to put the part
|
|
into any of the Power-down modes Deep-sleep,
|
|
Power-down, or Deep power-down depending on the
|
|
value in the PD0_SLEEP0_MODE register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_EVENT1</name>
|
|
<description>Writing a 1 enables the Cortex-M0 core and the
|
|
Cortex-M0 subsystem core to put the part into any of
|
|
the Power-down modes Deep-sleep, Power-down, or
|
|
Deep power-down depending on the value in the
|
|
PD0_SLEEP0_MODE register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PD0_SLEEP0_MODE</name>
|
|
<description>Sleep power mode register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x003FFF7F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWR_STATE</name>
|
|
<description>Selects between Deep-sleep, Power-down, and Deep power-down modes.
|
|
Only one of the following three values can be programmed in this register:
|
|
0x0030 00AA = Deep-sleep mode
|
|
0x0030 FCBA = Power-down mode
|
|
0x0030 3CBA = Power-down mode with M0SUB SRAM maintained
|
|
0x0030 FF7F = Deep power-down mode</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CREG</name>
|
|
<description>Configuration Registers (CREG)</description>
|
|
<groupName>CREG</groupName>
|
|
<baseAddress>0x40043000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CREG0</name>
|
|
<description>Chip configuration register 32 kHz oscillator output and BOD control register.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN1KHZ</name>
|
|
<description>Enable 1 kHz output.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_KHZ_OUTPUT_DISABLE</name>
|
|
<description>1 kHz output disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_KHZ_OUTPUT_ENABLED</name>
|
|
<description>1 kHz output enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN32KHZ</name>
|
|
<description>Enable 32 kHz output</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OUTPUT_DISABL</name>
|
|
<description>32 kHz output disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OUTPUT_ENABLE</name>
|
|
<description>32 kHz output enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESET32KHZ</name>
|
|
<description>32 kHz oscillator reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_RESET</name>
|
|
<description>Clear reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_ACTIVE</name>
|
|
<description>Reset active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PD32KHZ</name>
|
|
<description>32 kHz power control.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered-down.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USB0PHY</name>
|
|
<description>USB0 PHY power control.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_USB0_PHY_POWE</name>
|
|
<description>Enable USB0 PHY power.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_USB0_PHY</name>
|
|
<description>Disable USB0 PHY. PHY powered down.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALARMCTRL</name>
|
|
<description>RTC_ALARM pin output control</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RTC_ALARM</name>
|
|
<description>RTC alarm.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT_ROUTER_EVENT</name>
|
|
<description>Event router event.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Inactive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODLVL1</name>
|
|
<description>BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_0_INTERRUPT</name>
|
|
<description>Level 0 interrupt</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_1_INTERRUPT</name>
|
|
<description>Level 1 interrupt</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_2_INTERRUPT</name>
|
|
<description>Level 2 interrupt</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_3_INTERRUPT</name>
|
|
<description>Level 3 interrupt</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODLVL2</name>
|
|
<description>BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_0_RESET</name>
|
|
<description>Level 0 reset</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_1_RESET</name>
|
|
<description>Level 1 reset</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_2_RESET</name>
|
|
<description>Level 2 reset</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_3_RESET</name>
|
|
<description>Level 3 reset</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLECTRL</name>
|
|
<description>SAMPLE pin input/output control</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAMPLE_OUTPUT_FROM_T</name>
|
|
<description>Sample output from the event monitor/recorder.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_FROM_THE_EVEN</name>
|
|
<description>Output from the event router.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP0CTRL</name>
|
|
<description>WAKEUP0 pin input/output control</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_TO_THE_EVENT_R</name>
|
|
<description>Input to the event router.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_FROM_THE_EVEN</name>
|
|
<description>Output from the event router.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_TO_THE_EVENT_R</name>
|
|
<description>Input to the event router.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP1CTRL</name>
|
|
<description>WAKEUP1 pin input/output control</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INPUT_TO_EVENT_ROUTE</name>
|
|
<description>Input to event router.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_FROM_THE_EVEN</name>
|
|
<description>Output from the event router.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_TO_EVENT_ROUTE</name>
|
|
<description>Input to event router.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M4MEMMAP</name>
|
|
<description>ARM Cortex-M4 memory mapping</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x10400000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M4MAP</name>
|
|
<description>Shadow address when accessing memory at address 0x0000 0000</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CREG5</name>
|
|
<description>Chip configuration register 5. Controls JTAG access.</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>M0SUBTAPSEL</name>
|
|
<description>JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_JTAG_DEBUG</name>
|
|
<description>Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M4TAPSEL</name>
|
|
<description>JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_JTAG_DEBUG</name>
|
|
<description>Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M0APPTAPSEL</name>
|
|
<description>JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_JTAG_DEBUG</name>
|
|
<description>Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:13]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAMUX</name>
|
|
<description>DMA mux control</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAMUXPER0</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SPIFI</name>
|
|
<description>SPIFI</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT_CTOUT_2</name>
|
|
<description>SCT CTOUT_2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO14</name>
|
|
<description>SGPIO14</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3_MATCH_1</name>
|
|
<description>Timer3 match 1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER1</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 1</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER0_MATCH_0</name>
|
|
<description>Timer0 match 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_TRANSMIT</name>
|
|
<description>USART0 transmit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER2</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 2.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER0_MATCH_1</name>
|
|
<description>Timer0 match 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_RECEIVE</name>
|
|
<description>USART0 receive</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER3</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 3.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER1_MATCH_0</name>
|
|
<description>Timer1 match 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1_TRANSMIT</name>
|
|
<description>UART1 transmit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S1_DMA_REQUEST_1</name>
|
|
<description>I2S1 DMA request 1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_TRANSMIT</name>
|
|
<description>SSP1 transmit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER4</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 4.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER1_MATCH_1</name>
|
|
<description>Timer1 match 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART1_RECEIVE</name>
|
|
<description>UART1 receive</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S1_DMA_REQUEST_2</name>
|
|
<description>I2S1 DMA request 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_RECEIVE</name>
|
|
<description>SSP1 receive</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER5</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 5.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER2_MATCH_0</name>
|
|
<description>Timer2 match 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2_TRANSMIT</name>
|
|
<description>USART2 transmit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_TRANSMIT</name>
|
|
<description>SSP1 transmit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO15</name>
|
|
<description>SGPIO15</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER6</name>
|
|
<description>Selects DMA to peripheral connection for DMA peripheral 6.</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER2_MATCH_1</name>
|
|
<description>Timer2 match 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2_RECEIVE</name>
|
|
<description>USART2 receive</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_RECEIVE</name>
|
|
<description>SSP1 receive</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO14</name>
|
|
<description>SGPIO14</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER7</name>
|
|
<description>Selects DMA to peripheral connection for DMA peripheral 7.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER3_MATCH_0</name>
|
|
<description>Timer3 match 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART3_TRANSMIT</name>
|
|
<description>USART3 transmit</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT_DMA_REQUEST_0</name>
|
|
<description>SCT DMA request 0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCHS_WRITE</name>
|
|
<description>ADCHS write</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER8</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 8.</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER3_MATCH_1</name>
|
|
<description>Timer3 match 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART3_RECEIVE</name>
|
|
<description>USART3 receive</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT_DMA_REQUEST_1</name>
|
|
<description>SCT DMA request 1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCHS_READ</name>
|
|
<description>ADCHS read</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER9</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 9.</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SSP0_RECEIVE</name>
|
|
<description>SSP0 receive</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_DMA_REQUEST_1</name>
|
|
<description>I2S0 DMA request 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT_DMA_REQUEST_1</name>
|
|
<description>SCT DMA request 1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER10</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 10.</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SSP0_TRANSMIT</name>
|
|
<description>SSP0 transmit</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_DMA_REQUEST_2</name>
|
|
<description>I2S0 DMA request 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT_DMA_REQUEST_0</name>
|
|
<description>SCT DMA request 0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER11</name>
|
|
<description>Selects DMA to peripheral connection for DMA peripheral 11.</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SSP1_RECEIVE</name>
|
|
<description>SSP1 receive</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO14</name>
|
|
<description>SGPIO14</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_TRANSMIT</name>
|
|
<description>USART0 transmit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER12</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 12.</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SSP1_TRANSMIT</name>
|
|
<description>SSP1 transmit</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO15</name>
|
|
<description>SGPIO15</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_RECEIVE</name>
|
|
<description>USART0 receive</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER13</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 13.</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ADC0</name>
|
|
<description>ADC0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_RECEIVE</name>
|
|
<description>SSP1 receive</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART3_RECEIVE</name>
|
|
<description>USART3 receive</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER14</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 14.</description>
|
|
<bitRange>[29:28]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ADC1</name>
|
|
<description>ADC1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SSP1_TRANSMIT</name>
|
|
<description>SSP1 transmit</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART3_TRANSMIT</name>
|
|
<description>USART3 transmit</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXPER15</name>
|
|
<description>Select DMA to peripheral connection for DMA peripheral 15.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DAC</name>
|
|
<description>DAC</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT_CTOUT_3</name>
|
|
<description>SCT CTOUT_3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO15</name>
|
|
<description>SGPIO15</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER3_MATCH_0</name>
|
|
<description>Timer3 match 0</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLASHCFGA</name>
|
|
<description>Flash accelerator configuration register for flash bank A</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8000F03A</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not change these bits from the reset value.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FLASHTIM</name>
|
|
<description>Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_BASE_M4_CLK_CLOCK</name>
|
|
<description>1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_BASE_M4_CLK_CLOCKS</name>
|
|
<description>2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_BASE_M4_CLK_CLOCKS</name>
|
|
<description>3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_BASE_M4_CLK_CLOCKS</name>
|
|
<description>4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_BASE_M4_CLK_CLOCKS</name>
|
|
<description>5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BASE_M4_CLK_CLOCKS</name>
|
|
<description>6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BASE_M4_CLK_CLOCKS</name>
|
|
<description>7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BASE_M4_CLK_CLOCKS</name>
|
|
<description>8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BASE_M4_CLK_CLOCKS</name>
|
|
<description>9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10_BASE_M4_CLK_CLOCK</name>
|
|
<description>10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Write zeros only to these bits.</description>
|
|
<bitRange>[30:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>POW</name>
|
|
<description>Flash bank A power control</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power-down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Active (Default)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLASHCFGB</name>
|
|
<description>Flash accelerator configuration register for flash bank B</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8000F03A</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not change these bits from the reset value.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FLASHTIM</name>
|
|
<description>Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_BASE_M4_CLK_CLOCK</name>
|
|
<description>1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_BASE_M4_CLK_CLOCKS</name>
|
|
<description>2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_BASE_M4_CLK_CLOCKS</name>
|
|
<description>3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_BASE_M4_CLK_CLOCKS</name>
|
|
<description>4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_BASE_M4_CLK_CLOCKS</name>
|
|
<description>5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BASE_M4_CLK_CLOCKS</name>
|
|
<description>6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BASE_M4_CLK_CLOCKS</name>
|
|
<description>7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BASE_M4_CLK_CLOCKS</name>
|
|
<description>8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BASE_M4_CLK_CLOCKS</name>
|
|
<description>9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz.</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10_BASE_M4_CLK_CLOCK</name>
|
|
<description>10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions.</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Write zeros only to these bits.</description>
|
|
<bitRange>[30:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>POW</name>
|
|
<description>Flash bank A power control</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power-down</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Active (Default)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ETBCFG</name>
|
|
<description>ETB RAM configuration</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ETB</name>
|
|
<description>Select SRAM interface</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ETB_ACCESSES_SRAM_AT</name>
|
|
<description>ETB accesses SRAM at address 0x2000 C000.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AHB_ACCESSES_SRAM_AT</name>
|
|
<description>AHB accesses SRAM at address 0x2000 C000.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CREG6</name>
|
|
<description>Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock.</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ETHMODE</name>
|
|
<description>Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MII</name>
|
|
<description>MII</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RMII</name>
|
|
<description>RMII</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTOUTCTRL</name>
|
|
<description>Selects the functionality of the SCT outputs.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>COMBINE_SCT_AND_TIME</name>
|
|
<description>Combine SCT and timer match outputs. SCT outputs are Red with timer outputs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCT_OUTPUTS_ONLY</name>
|
|
<description>SCT outputs only. SCT outputs are used without timer match outputs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[11:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>I2S0_TX_SCK_IN_SEL</name>
|
|
<description>I2S0_TX_SCK input select</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>I2S_REGISTER</name>
|
|
<description>I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BASE_AUDIO_CLK_FOR_I</name>
|
|
<description>BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2S0_RX_SCK_IN_SEL</name>
|
|
<description>I2S0_RX_SCK input select</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>I2S_REGISTER</name>
|
|
<description>I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BASE_AUDIO_CLK_FOR_I</name>
|
|
<description>BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2S1_TX_SCK_IN_SEL</name>
|
|
<description>I2S1_TX_SCK input select</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>I2S_REGISTER</name>
|
|
<description>I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BASE_AUDIO_CLK_FOR_I</name>
|
|
<description>BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2S1_RX_SCK_IN_SEL</name>
|
|
<description>I2S1_RX_SCK input select</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>I2S_REGISTER</name>
|
|
<description>I2S register. I2S clock selected as defined by the I2S receive mode register Table 961.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BASE_AUDIO_CLK_FOR_I</name>
|
|
<description>BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC_CLK_SEL</name>
|
|
<description>EMC_CLK divided clock select (see Section 21.1).</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_BY_1</name>
|
|
<description>Divide by 1. EMC_CLK_DIV not divided.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDE_BY_2</name>
|
|
<description>Divide by 2. EMC_CLK_DIV divided by 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M4TXEVENT</name>
|
|
<description>Cortex-M4 TXEV event clear</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXEVCLR</name>
|
|
<description>Cortex-M4 TXEV event.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_TXEV_EVENT</name>
|
|
<description>Clear the TXEV event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHIPID</name>
|
|
<description>Part ID</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID</name>
|
|
<description>Boundary scan ID code 0x5906 002B or 0x6906 002B = LPC4350/30/20/10 (flashless parts) 0x4906 002B = LPC4357/53 (parts with on-chip flash)</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M0SUBMEMMAP</name>
|
|
<description>ARM Cortex-M0SUB memory mapping</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x18400000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M0SUBMAP</name>
|
|
<description>Shadow address when accessing memory at address 0x0000 0000</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M0SUBTXEVENT</name>
|
|
<description>Cortex-M0SUB TXEV event clear</description>
|
|
<addressOffset>0x314</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXEVCLR</name>
|
|
<description>Cortex-M0SUB TXEV event handling.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_TXEV_EVENT</name>
|
|
<description>Clear the TXEV event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M0APPTXEVENT</name>
|
|
<description>Cortex-M0APP TXEV event clear</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXEVCLR</name>
|
|
<description>Cortex-M0APP TXEV event handling.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_TXEV_EVENT</name>
|
|
<description>Clear the TXEV event.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>M0APPMEMMAP</name>
|
|
<description>ARM Cortex-M0APP memory mapping</description>
|
|
<addressOffset>0x404</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M0APPMAP</name>
|
|
<description>Shadow address when accessing memory at address 0x0000 0000</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB0FLADJ</name>
|
|
<description>USB0 frame length adjust register</description>
|
|
<addressOffset>0x500</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLTV</name>
|
|
<description>Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USB1FLADJ</name>
|
|
<description>USB1 frame length adjust register</description>
|
|
<addressOffset>0x600</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLTV</name>
|
|
<description>Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EVENTROUTER</name>
|
|
<description>Event router</description>
|
|
<groupName>EVENTROUTER</groupName>
|
|
<baseAddress>0x40044000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EVENTROUTER</name>
|
|
<value>42</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>HILO</name>
|
|
<description>Level configuration register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAKEUP0_L</name>
|
|
<description>Level detect mode for WAKEUP0 event.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP1_L</name>
|
|
<description>Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP2_L</name>
|
|
<description>Level detect mode for WAKEUP2 event.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP3_L</name>
|
|
<description>Level detect mode for WAKEUP3 event.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATIMER_L</name>
|
|
<description>Level detect mode for alarm timer event.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_L</name>
|
|
<description>Level detect mode for RTC event.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOD_L</name>
|
|
<description>Level detect mode for BOD event.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WWDT_L</name>
|
|
<description>Level detect mode for WWDT event.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ETH_L</name>
|
|
<description>Level detect mode for Ethernet event</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB0_L</name>
|
|
<description>Level detect mode for USB0 event</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB1_L</name>
|
|
<description>Level detect mode for USB1 event</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDMMC_L</name>
|
|
<description>Level detect mode for SD/MMC event</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAN_L</name>
|
|
<description>Level detect mode for C_CAN event.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIM2_L</name>
|
|
<description>Level detect mode for combined timer output 2 event.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIM6_L</name>
|
|
<description>Level detect mode for combined timer output 6 event.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QEI_L</name>
|
|
<description>Level detect mode for QEI event.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIM14_L</name>
|
|
<description>Level detect mode for combined timer output 14 event.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESET_L</name>
|
|
<description>Level detect mode for Reset</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL_IF</name>
|
|
<description>Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL_IF</name>
|
|
<description>Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODRESET_L</name>
|
|
<description>Level detect mode for BOD Reset</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL_IF</name>
|
|
<description>Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL_IF</name>
|
|
<description>Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPDRESET_L</name>
|
|
<description>Level detect mode for Deep power-down Reset</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL_IF</name>
|
|
<description>Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL_IF</name>
|
|
<description>Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EDGE</name>
|
|
<description>Edge configuration</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAKEUP0_E</name>
|
|
<description>Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_WAKEU</name>
|
|
<description>Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP1_E</name>
|
|
<description>Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_WAKEU</name>
|
|
<description>Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP2_E</name>
|
|
<description>Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_WAKEU</name>
|
|
<description>Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP3_E</name>
|
|
<description>Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_WAKEU</name>
|
|
<description>Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATIMER_E</name>
|
|
<description>Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_THE_A</name>
|
|
<description>Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC_E</name>
|
|
<description>Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_THE_R</name>
|
|
<description>Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOD_E</name>
|
|
<description>Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_THE_B</name>
|
|
<description>Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WWDT_E</name>
|
|
<description>Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_THE_W</name>
|
|
<description>Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ETH_E</name>
|
|
<description>Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_THE_E</name>
|
|
<description>Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB0_E</name>
|
|
<description>Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_THE_U</name>
|
|
<description>Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB1_E</name>
|
|
<description>Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_THE_U</name>
|
|
<description>Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDMMC_E</name>
|
|
<description>Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_THE_S</name>
|
|
<description>Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAN_E</name>
|
|
<description>Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_THE_C</name>
|
|
<description>Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIM2_E</name>
|
|
<description>Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_GIMA</name>
|
|
<description>Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIM6_E</name>
|
|
<description>Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_GIMA</name>
|
|
<description>Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QEI_E</name>
|
|
<description>Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_QEI_I</name>
|
|
<description>Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIM14_E</name>
|
|
<description>Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_GIMA</name>
|
|
<description>Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESET_E</name>
|
|
<description>Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_THE_R</name>
|
|
<description>Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODRESET_E</name>
|
|
<description>Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_THE_R</name>
|
|
<description>Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DPDRESET_E</name>
|
|
<description>Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_DETECT</name>
|
|
<description>Level detect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGE_DETECT_OF_THE_R</name>
|
|
<description>Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_EN</name>
|
|
<description>Clear event enable register</description>
|
|
<addressOffset>0xFD8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAKEUP0_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP1_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP2_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP3_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ATIMER_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTC_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BOD_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WWDT_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETH_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB0_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB1_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SDMMC_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM2_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM6_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM14_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESET_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BODRESET_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 20 in the ENABLE register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DPDRESET_CLREN</name>
|
|
<description>Writing a 1 to this bit clears the event enable bit 21 in the ENABLE register.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_EN</name>
|
|
<description>Set event enable register</description>
|
|
<addressOffset>0xFDC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAKEUP0_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP1_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP2_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP3_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ATIMER_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTC_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BOD_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WWDT_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETH_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB0_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB1_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SDMMC_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM2_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM6_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM14_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESET_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BODRESET_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 20 in the ENABLE register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DPDRESET_SETEN</name>
|
|
<description>Writing a 1 to this bit sets the event enable bit 21 in the ENABLE register.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Event Status register</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x03FDFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAKEUP0_ST</name>
|
|
<description>A 1 in this bit shows that the WAKEUP0 event has been raised.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP1_ST</name>
|
|
<description>A 1 in this bit shows that the WAKEUP1 event has been raised.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP2_ST</name>
|
|
<description>A 1 in this bit shows that the WAKEUP2 event has been raised.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP3_ST</name>
|
|
<description>A 1 in this bit shows that the WAKEUP3 event has been raised.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ATIMER_ST</name>
|
|
<description>A 1 in this bit shows that the ATIMER event has been raised.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTC_ST</name>
|
|
<description>A 1 in this bit shows that the RTC event has been raised.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BOD_ST</name>
|
|
<description>A 1 in this bit shows that the BOD event has been raised.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WWDT_ST</name>
|
|
<description>A 1 in this bit shows that the WWDT event has been raised.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETH_ST</name>
|
|
<description>A 1 in this bit shows that the ETHERNET event has been raised.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB0_ST</name>
|
|
<description>A 1 in this bit shows that the USB0 event has been raised.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB1_ST</name>
|
|
<description>A 1 in this bit shows that the USB1 event has been raised.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SDMMC_ST</name>
|
|
<description>A 1 in this bit indicates that the SDMMC event has been raised.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_ST</name>
|
|
<description>A 1 in this bit shows that the C_CAN event has been raised.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM2_ST</name>
|
|
<description>A 1 in this bit shows that the combined timer 2 output event has been raised.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM6_ST</name>
|
|
<description>A 1 in this bit shows that the combined timer 6 output event has been raised.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_ST</name>
|
|
<description>A 1 in this bit shows that the QEI event has been raised.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM14_ST</name>
|
|
<description>A 1 in this bit shows that the combined timer 14 output event has been raised.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESET_ST</name>
|
|
<description>A 1 in this bit shows that the reset event has been raised.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BODRESET_ST</name>
|
|
<description>A 1 in this bit indicates that the reset event has been raised.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DPDRESET_ST</name>
|
|
<description>A 1 in this bit indicates that the reset event has been raised.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENABLE</name>
|
|
<description>Event Enable register</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAKEUP0_EN</name>
|
|
<description>A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP1_EN</name>
|
|
<description>A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP2_EN</name>
|
|
<description>A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP3_EN</name>
|
|
<description>A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ATIMER_EN</name>
|
|
<description>A 1 in this bit shows that the ATIMER event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTC_EN</name>
|
|
<description>A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BOD_EN</name>
|
|
<description>A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WWDT_EN</name>
|
|
<description>A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETH_EN</name>
|
|
<description>A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB0_EN</name>
|
|
<description>A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB1_EN</name>
|
|
<description>A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SDMMC_EN</name>
|
|
<description>A 1 in this bit indicates that the SDMMC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_EN</name>
|
|
<description>A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM2_EN</name>
|
|
<description>A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM6_EN</name>
|
|
<description>A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_EN</name>
|
|
<description>A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM14_EN</name>
|
|
<description>A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESET_EN</name>
|
|
<description>A 1 in this bit shows that the RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BODRESET_EN</name>
|
|
<description>A 1 in this bit indicates that the BOD RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DPDRESET_EN</name>
|
|
<description>A 1 in this bit indicates that the deep power-down RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_STAT</name>
|
|
<description>Clear event status register</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAKEUP0_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP1_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP2_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP3_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ATIMER_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTC_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BOD_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WWDT_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETH_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB0_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB1_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SDMMC_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM2_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM6_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM14_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESET_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BODRESET_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 20 in the STATUS register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DPDRESET_CLRST</name>
|
|
<description>Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_STAT</name>
|
|
<description>Set event status register</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WAKEUP0_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP1_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP2_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP3_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ATIMER_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTC_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BOD_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WWDT_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETH_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB0_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB1_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SDMMC_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM2_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM6_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM14_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[18:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESET_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BODRESET_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DPDRESET_SETST</name>
|
|
<description>Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
|
|
</peripheral>
|
|
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description>Real-Time Clock (RTC) and event recorder </description>
|
|
<groupName>RTC</groupName>
|
|
<baseAddress>0x40046000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTC</name>
|
|
<value>47</value>
|
|
</interrupt>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>ILR</name>
|
|
<description>Interrupt Location Register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RTCCIF</name>
|
|
<description>When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTCALF</name>
|
|
<description>When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Clock Control Register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>Clock Enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The time counters are disabled so that they may be initialized.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The time counters are enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTCRST</name>
|
|
<description>CTC Reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Internal test mode controls. These bits must be 0 for normal RTC operation.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CCALEN</name>
|
|
<description>Calibration counter enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and Section 29.7.1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The calibration counter is disabled and reset to zero.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIIR</name>
|
|
<description>Counter Increment Interrupt Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IMSEC</name>
|
|
<description>When 1, an increment of the Second value generates an interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMMIN</name>
|
|
<description>When 1, an increment of the Minute value generates an interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMHOUR</name>
|
|
<description>When 1, an increment of the Hour value generates an interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMDOM</name>
|
|
<description>When 1, an increment of the Day of Month value generates an interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMDOW</name>
|
|
<description>When 1, an increment of the Day of Week value generates an interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMDOY</name>
|
|
<description>When 1, an increment of the Day of Year value generates an interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMMON</name>
|
|
<description>When 1, an increment of the Month value generates an interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMYEAR</name>
|
|
<description>When 1, an increment of the Year value generates an interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AMR</name>
|
|
<description>Alarm Mask Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMRSEC</name>
|
|
<description>When 1, the Second value is not compared for the alarm.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRMIN</name>
|
|
<description>When 1, the Minutes value is not compared for the alarm.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRHOUR</name>
|
|
<description>When 1, the Hour value is not compared for the alarm.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRDOM</name>
|
|
<description>When 1, the Day of Month value is not compared for the alarm.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRDOW</name>
|
|
<description>When 1, the Day of Week value is not compared for the alarm.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRDOY</name>
|
|
<description>When 1, the Day of Year value is not compared for the alarm.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRMON</name>
|
|
<description>When 1, the Month value is not compared for the alarm.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AMRYEAR</name>
|
|
<description>When 1, the Year value is not compared for the alarm.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIME0</name>
|
|
<description>Consolidated Time Register 0</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SECONDS</name>
|
|
<description>Seconds value in the range of 0 to 59</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MINUTES</name>
|
|
<description>Minutes value in the range of 0 to 59</description>
|
|
<bitRange>[13:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HOURS</name>
|
|
<description>Hours value in the range of 0 to 23</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DOW</name>
|
|
<description>Day of week value in the range of 0 to 6</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:27]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIME1</name>
|
|
<description>Consolidated Time Register 1</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOM</name>
|
|
<description>Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month value in the range of 1 to 12.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year value in the range of 0 to 4095.</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIME2</name>
|
|
<description>Consolidated Time Register 2</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOY</name>
|
|
<description>Day of year value in the range of 1 to 365 (366 for leap years).</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEC</name>
|
|
<description>Seconds Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SECONDS</name>
|
|
<description>Seconds value in the range of 0 to 59</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIN</name>
|
|
<description>Minutes Register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MINUTES</name>
|
|
<description>Minutes value in the range of 0 to 59</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HRS</name>
|
|
<description>Hours Register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HOURS</name>
|
|
<description>Hours value in the range of 0 to 23</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOM</name>
|
|
<description>Day of Month Register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOM</name>
|
|
<description>Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOW</name>
|
|
<description>Day of Week Register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOW</name>
|
|
<description>Day of week value in the range of 0 to 6.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOY</name>
|
|
<description>Day of Year Register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOY</name>
|
|
<description>Day of year value in the range of 1 to 365 (366 for leap years).</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MONTH</name>
|
|
<description>Months Register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month value in the range of 1 to 12.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>YEAR</name>
|
|
<description>Years Register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year value in the range of 0 to 4095.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALIBRATION</name>
|
|
<description>Calibration Value Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CALVAL</name>
|
|
<description>If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0.</description>
|
|
<bitRange>[16:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CALDIR</name>
|
|
<description>Calibration direction</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FORWARD_CALIBRATION_</name>
|
|
<description>Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BACKWARD_CALIBRATION</name>
|
|
<description>Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ASEC</name>
|
|
<description>Alarm value for Seconds</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SECONDS</name>
|
|
<description>Seconds value in the range of 0 to 59</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AMIN</name>
|
|
<description>Alarm value for Minutes</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MINUTES</name>
|
|
<description>Minutes value in the range of 0 to 59</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHRS</name>
|
|
<description>Alarm value for Hours</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HOURS</name>
|
|
<description>Hours value in the range of 0 to 23</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADOM</name>
|
|
<description>Alarm value for Day of Month</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOM</name>
|
|
<description>Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADOW</name>
|
|
<description>Alarm value for Day of Week</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOW</name>
|
|
<description>Day of week value in the range of 0 to 6.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADOY</name>
|
|
<description>Alarm value for Day of Year</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOY</name>
|
|
<description>Day of year value in the range of 1 to 365 (366 for leap years).</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AMON</name>
|
|
<description>Alarm value for Months</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MONTH</name>
|
|
<description>Month value in the range of 1 to 12.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AYRS</name>
|
|
<description>Alarm value for Year</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>Year value in the range of 0 to 4095.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>ERCONTRO</name>
|
|
<description>Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup.</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTWAKE_EN0</name>
|
|
<description>Interrupt and wake-up enable for channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>No interrupt or wake-up will be generated by event channel 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An event in channel 0 will trigger an (RTC) interrupt and a wake-up request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPCLEAR_EN0</name>
|
|
<description>Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Channel 0 has no influence on the general purpose registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An event in channel 0 will clear the general purpose registers asynchronously.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL0</name>
|
|
<description>Selects the polarity of an event on input pin WAKEUP0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NEGATIVE</name>
|
|
<description>A channel 0 event is defined as a negative edge on WAKEUP0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSITIVE</name>
|
|
<description>A channel 0 event is defined as a positive edge on WAKEUP0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EV0_INPUT_EN</name>
|
|
<description>Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Event 0 input is disabled and forced high internally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Event 0 input is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[9:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INTWAKE_EN1</name>
|
|
<description>Interrupt and wake-up enable for channel 1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>No interrupt or wake-up will be generated by event channel 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An event in channel 1 will trigger an (RTC) interrupt and a wake-up request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPCLEAR_EN1</name>
|
|
<description>Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Channel 1 has no influence on the general purpose registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>A n event in channel 1 will clear the general purpose registers asynchronously.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Selects the polarity of an event on input pin WAKEUP1.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NEGATIVE</name>
|
|
<description>A channel 1 event is defined as a negative edge on WAKEUP1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSITIVE</name>
|
|
<description>A channel 1 event is defined as a positive edge on WAKEUP1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EV1_INPUT_EN</name>
|
|
<description>Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Event 1 input is disabled and forced high internally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Event 1 input is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[19:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INTWAKE_EN2</name>
|
|
<description>Interrupt and wake-up enable for channel 2.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>No interrupt or wake-up will be generated by event channel 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An event in channel 2 will trigger an (RTC) interrupt and a wake-up request.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPCLEAR_EN2</name>
|
|
<description>Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Channel 2 has no influence on the general purpose registers.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>An event in channel 2 will clear the general purpose registers asynchronously.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Selects the polarity of an event on input pin WAKEUP2.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NEGATIVE</name>
|
|
<description>A channel 2 event is defined as a negative edge on WAKEUP2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POSITIVE</name>
|
|
<description>A channel 2 event is defined as a positive edge on WAKEUP2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EV2_INPUT_EN</name>
|
|
<description>Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Event 2 input is disabled and forced high internally.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Event 2 input is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[29:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ERMODE</name>
|
|
<description>Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_EVENT_MONITO</name>
|
|
<description>Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_HZ_SAMPLE_CLOCK</name>
|
|
<description>16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>64_HZ_SAMPLE_CLOCK</name>
|
|
<description>64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_KHZ_SAMPLE_CLOCK</name>
|
|
<description>1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERSTATUS</name>
|
|
<description>Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions.</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EV0</name>
|
|
<description>Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No event change on channel 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT</name>
|
|
<description>At least one event has occurred on channel 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EV1</name>
|
|
<description>Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No event change on channel 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT</name>
|
|
<description>At least one event has occurred on channel 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EV2</name>
|
|
<description>Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No event change on channel 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT</name>
|
|
<description>At least one event has occurred on channel 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GP_CLEARED</name>
|
|
<description>General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>General purpose registers have not been asynchronous cleared.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVENT</name>
|
|
<description>General purpose registers have been asynchronous cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[30:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOINTERRUPTWAKEUP</name>
|
|
<description>No interrupt/wake-up request is pending</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPTWAKEUP</name>
|
|
<description>An interrupt/wake-up request is pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERCOUNTERS</name>
|
|
<description>Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels.</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNTER0</name>
|
|
<description>Value of the counter for Event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COUNTER1</name>
|
|
<description>Value of the counter for event 1. See description for COUNTER0.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COUNTER2</name>
|
|
<description>Value of the counter for event 2. See description for COUNTER0.</description>
|
|
<bitRange>[18:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:19]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>ERFIRSTSTAMP%s</name>
|
|
<description>Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0.</description>
|
|
<addressOffset>0x090</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Seconds value in the range of 0 to 59.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MIN</name>
|
|
<description>Minutes value in the range of 0 to 59.</description>
|
|
<bitRange>[11:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Hours value in the range of 0 to 23.</description>
|
|
<bitRange>[16:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DOY</name>
|
|
<description>Day of Year value in the range of 1 to 366.</description>
|
|
<bitRange>[25:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>ERLASTSTAMP%s</name>
|
|
<description>Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0.</description>
|
|
<addressOffset>0x0A0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Seconds value in the range of 0 to 59.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MIN</name>
|
|
<description>Minutes value in the range of 0 to 59.</description>
|
|
<bitRange>[11:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HOUR</name>
|
|
<description>Hours value in the range of 0 to 23.</description>
|
|
<bitRange>[16:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DOY</name>
|
|
<description>Day of Year value in the range of 1 to 366.</description>
|
|
<bitRange>[25:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CGU</name>
|
|
<description>Clock Generation Unit (CGU)</description>
|
|
<groupName>CGU</groupName>
|
|
<baseAddress>0x40050000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
|
|
|
|
|
|
|
|
|
|
<register>
|
|
<name>FREQ_MON</name>
|
|
<description>Frequency monitor register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RCNT</name>
|
|
<description>9-bit reference clock-counter value</description>
|
|
<bitRange>[8:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FCNT</name>
|
|
<description>14-bit selected clock-counter value</description>
|
|
<bitRange>[22:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MEAS</name>
|
|
<description>Measure frequency</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RCNT_AND_FCNT_DISABL</name>
|
|
<description>RCNT and FCNT disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FREQUENCY_COUNTERS_S</name>
|
|
<description>Frequency counters started</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock-source selection for the clock to be measured. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR_D</name>
|
|
<description>32 kHz oscillator (default)</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC</name>
|
|
<description>IRC</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x05</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0USB</name>
|
|
<description>PLL0USB</description>
|
|
<value>0x07</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0AUDIO</name>
|
|
<description>PLL0AUDIO</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x0A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x0B</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XTAL_OSC_CTRL</name>
|
|
<description>Crystal oscillator control register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000005</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power-down (default)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL</name>
|
|
<description>Crystal. Operation with crystal connected (default).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BYPASS_MODE</name>
|
|
<description>Bypass mode. Use this mode when an external clock source is used instead of a crystal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HF</name>
|
|
<description>Select frequency range</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL0USB_STAT</name>
|
|
<description>PLL0USB status register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>PLL0 lock indicator</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FR</name>
|
|
<description>PLL0 free running indicator</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL0USB_CTRL</name>
|
|
<description>PLL0USB control register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>PLL0 power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PLL0_ENABLED</name>
|
|
<description>PLL0 enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_POWERED_DOWN</name>
|
|
<description>PLL0 powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Input clock bypass control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CCO_CLOCK_SENT_TO_PO</name>
|
|
<description>CCO clock sent to post-dividers. Use this in normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_INPUT_CLOCK_SEN</name>
|
|
<description>PLL0 input clock sent to post-dividers (default).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRECTI</name>
|
|
<description>PLL0 direct input</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DIRECTO</name>
|
|
<description>PLL0 direct output</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>PLL0 clock enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FRM</name>
|
|
<description>Free running mode</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Reads as zero. Do not write one to this register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Reads as zero. Do not write one to this register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Reads as zero. Do not write one to this register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL0USB_MDIV</name>
|
|
<description>PLL0USB M-divider register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x05F85B6A</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MDEC</name>
|
|
<description>Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071.</description>
|
|
<bitRange>[16:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SELP</name>
|
|
<description>Bandwidth select P value</description>
|
|
<bitRange>[21:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SELI</name>
|
|
<description>Bandwidth select I value</description>
|
|
<bitRange>[27:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SELR</name>
|
|
<description>Bandwidth select R value; SELR = 0.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL0USB_NP_DIV</name>
|
|
<description>PLL0USB N/P-divider register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000B1002</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDEC</name>
|
|
<description>Decoded P-divider coefficient value</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[11:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NDEC</name>
|
|
<description>Decoded N-divider coefficient value</description>
|
|
<bitRange>[21:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL0AUDIO_STAT</name>
|
|
<description>PLL0AUDIO status register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>PLL0 lock indicator</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FR</name>
|
|
<description>PLL0 free running indicator</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL0AUDIO_CTRL</name>
|
|
<description>PLL0AUDIO control register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01004003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>PLL0 power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PLL0_ENABLED</name>
|
|
<description>PLL0 enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_POWERED_DOWN</name>
|
|
<description>PLL0 powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Input clock bypass control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CCO_CLOCK_SENT_TO_PO</name>
|
|
<description>CCO clock sent to post-dividers. Use this in normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_INPUT_CLOCK_SEN</name>
|
|
<description>PLL0 input clock sent to post-dividers (default).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRECTI</name>
|
|
<description>PLL0 direct input</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DIRECTO</name>
|
|
<description>PLL0 direct output</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>PLL0 clock enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FRM</name>
|
|
<description>Free running mode</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Reads as zero. Do not write one to this register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Reads as zero. Do not write one to this register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Reads as zero. Do not write one to this register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLLFRACT_REQ</name>
|
|
<description>Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SEL_EXT</name>
|
|
<description>Select fractional divider.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FRAC_ENABLED</name>
|
|
<description>FRAC Enabled. Enable fractional divider.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MDEC_ENABLED</name>
|
|
<description>MDEC enabled. Fractional divider not used.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MOD_PD</name>
|
|
<description>Sigma-Delta modulator power-down</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Sigma-Delta modulator enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Sigma-Delta modulator powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL0AUDIO_MDIV</name>
|
|
<description>PLL0AUDIO M-divider register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x05F85B6A</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MDEC</name>
|
|
<description>Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071.</description>
|
|
<bitRange>[16:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL0AUDIO_NP_DIV</name>
|
|
<description>PLL0AUDIO N/P-divider register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000B1002</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDEC</name>
|
|
<description>Decoded P-divider coefficient value</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[11:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NDEC</name>
|
|
<description>Decoded N-divider coefficient value</description>
|
|
<bitRange>[21:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL0AUDIO_FRAC</name>
|
|
<description>PLL0AUDIO fractional divider register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00200000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PLLFRACT_CTRL</name>
|
|
<description>PLL fractional divider control word</description>
|
|
<bitRange>[21:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:22]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL1_STAT</name>
|
|
<description>PLL1 status register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>PLL1 lock indicator</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL1_CTRL</name>
|
|
<description>PLL1 control register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>PLL1 power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PLL1_ENABLED</name>
|
|
<description>PLL1 enabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1_POWERED_DOWN</name>
|
|
<description>PLL1 powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Input clock bypass control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>Normal. CCO clock sent to post-dividers. Use for normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_CLOCK</name>
|
|
<description>Input clock. PLL1 input clock sent to post-dividers (default).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write one to this bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write one to these bits.</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FBSEL</name>
|
|
<description>PLL feedback select.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CCO_OUT</name>
|
|
<description>CCO out. CCO output is used as feedback divider input clock.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL_OUT</name>
|
|
<description>PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIRECT</name>
|
|
<description>PLL direct CCO output</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Post-divider division ratio P. The value applied is 2xP.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PEQ2</name>
|
|
<description>2 (default)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PEQ4</name>
|
|
<description>4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8</name>
|
|
<description>8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSEL</name>
|
|
<description>Pre-divider division ratio N</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEQ2</name>
|
|
<description>2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEQ3</name>
|
|
<description>3 (default)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4</name>
|
|
<description>4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2 ... 11111111 = 256</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock-source selection.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x05</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0USB</name>
|
|
<description>PLL0USB</description>
|
|
<value>0x07</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0AUDIO</name>
|
|
<description>PLL0AUDIO</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x0A</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDIVA_CTRL</name>
|
|
<description>Integer divider A control register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Integer divider A power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. IDIVA enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IDIV</name>
|
|
<description>Integer divider A divider values (1/(IDIV + 1))</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIV1</name>
|
|
<description>1 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV2</name>
|
|
<description>2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV3</name>
|
|
<description>3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIV4</name>
|
|
<description>4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0USB</name>
|
|
<description>PLL0USB</description>
|
|
<value>0x07</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0AUDIO</name>
|
|
<description>PLL0AUDIO</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDIVB_CTRL</name>
|
|
<description>Integer divider B control register</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Integer divider power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. IDIV enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IDIV</name>
|
|
<description>Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16</description>
|
|
<bitRange>[5:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock-source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0AUDIO</name>
|
|
<description>PLL0AUDIO</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDIVC_CTRL</name>
|
|
<description>Integer divider C control register</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Integer divider power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. IDIV enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IDIV</name>
|
|
<description>Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16</description>
|
|
<bitRange>[5:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock-source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0AUDIO</name>
|
|
<description>PLL0AUDIO</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDIVD_CTRL</name>
|
|
<description>Integer divider D control register</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Integer divider power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. IDIV enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IDIV</name>
|
|
<description>Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16</description>
|
|
<bitRange>[5:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock-source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0AUDIO</name>
|
|
<description>PLL0AUDIO</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>IDIVE_CTRL</name>
|
|
<description>Integer divider E control register</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Integer divider power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. IDIV enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>IDIV</name>
|
|
<description>Integer divider E divider values (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2 ... 111111111 = 256</description>
|
|
<bitRange>[9:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock-source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0AUDIO</name>
|
|
<description>PLL0AUDIO</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_SAFE_CLK</name>
|
|
<description>Output stage 0 control register for base clock BASE_SAFE_CLK</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_USB0_CLK</name>
|
|
<description>Output stage 1 control register for base clock BASE_USB0_CLK</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x07000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock-source selection.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PLL0USB</name>
|
|
<description>PLL0USB (default)</description>
|
|
<value>0x07</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_PERIPH_CLK</name>
|
|
<description>Output stage 2 control register for base clock BASE_PERIPH_CLK</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x07000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0AUDIO</name>
|
|
<description>PLL0AUDIO</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_USB1_CLK</name>
|
|
<description>Output stage 3 control register for base clock BASE_USB1_CLK</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>Power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0USB</name>
|
|
<description>PLL0USB</description>
|
|
<value>0x07</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0AUDIO</name>
|
|
<description>PLL0AUDIO</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
<register>
|
|
<name>BASE_M4_CLK</name>
|
|
<description>Output stage BASE_M4_CLK control register</description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_SPIFI_CLK</name>
|
|
<description>Output stage BASE_SPIFI_CLK control register</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_SPI_CLK</name>
|
|
<description>Output stage BASE_SPI_CLK control register</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_PHY_RX_CLK</name>
|
|
<description>Output stage BASE_PHY_RX_CLK control register</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_PHY_TX_CLK</name>
|
|
<description>Output stage BASE_PHY_TX_CLK control register</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_APB1_CLK</name>
|
|
<description>Output stage BASE_APB1_CLK control register</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_APB3_CLK</name>
|
|
<description>Output stage BASE_APB3_CLK control register</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_LCD_CLK</name>
|
|
<description>Output stage BASE_LCD_CLK control register</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_SDIO_CLK</name>
|
|
<description>Output stage BASE_SDIO_CLK control register</description>
|
|
<addressOffset>0x090</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_SSP0_CLK</name>
|
|
<description>Output stage BASE_SSP0_CLK control register</description>
|
|
<addressOffset>0x094</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_SSP1_CLK</name>
|
|
<description>Output stage BASE_SSP1_CLK control register</description>
|
|
<addressOffset>0x098</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_UART0_CLK</name>
|
|
<description>Output stage BASE_UART0_CLK control register</description>
|
|
<addressOffset>0x09C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_UART1_CLK</name>
|
|
<description>Output stage BASE_UART1_CLK control register</description>
|
|
<addressOffset>0x0A0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_UART2_CLK</name>
|
|
<description>Output stage BASE_UART2_CLK control register</description>
|
|
<addressOffset>0x0A4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_UART3_CLK</name>
|
|
<description>Output stage BASE_UART3_CLK control register</description>
|
|
<addressOffset>0x0A8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock source selection. All other values are reserved.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_OUT_CLK</name>
|
|
<description>Output stage 20 control register for base clock BASE_OUT_CLK</description>
|
|
<addressOffset>0x0AC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AUTOBLOCKING_DISABLE</name>
|
|
<description>Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTOBLOCKING_ENABLED</name>
|
|
<description>Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock-source selection.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x05</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_USB</name>
|
|
<description>PLL0 (for USB)</description>
|
|
<value>0x07</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_AUDIO_CLK</name>
|
|
<description>Output stage 25 control register for base clock BASE_AUDIO_CLK</description>
|
|
<addressOffset>0x0C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AUTOBLOCKING_DISABLE</name>
|
|
<description>Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTOBLOCKING_ENABLED</name>
|
|
<description>Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock-source selection.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x05</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x07</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_CGU_OUT0_CLK</name>
|
|
<description>Output stage 25 control register for base clock BASE_CGU_OUT0_CLK</description>
|
|
<addressOffset>0x0C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AUTOBLOCKING_DISABLE</name>
|
|
<description>Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTOBLOCKING_ENABLED</name>
|
|
<description>Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock-source selection.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x05</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x07</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_CGU_OUT1_CLK</name>
|
|
<description>Output stage 25 control register for base clock BASE_CGU_OUT1_CLK</description>
|
|
<addressOffset>0x0C8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Output stage power down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OUTPUT_STAGE_ENABLED</name>
|
|
<description>Output stage enabled (default)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWER_DOWN</name>
|
|
<description>power-down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTOBLOCK</name>
|
|
<description>Block clock automatically during frequency change</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AUTOBLOCKING_DISABLE</name>
|
|
<description>Autoblocking disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTOBLOCKING_ENABLED</name>
|
|
<description>Autoblocking enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLK_SEL</name>
|
|
<description>Clock-source selection.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>32_KHZ_OSCILLATOR</name>
|
|
<description>32 kHz oscillator</description>
|
|
<value>0x00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IRC_DEFAULT</name>
|
|
<description>IRC (default)</description>
|
|
<value>0x01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_RX_CLK</name>
|
|
<description>ENET_RX_CLK</description>
|
|
<value>0x02</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENET_TX_CLK</name>
|
|
<description>ENET_TX_CLK</description>
|
|
<value>0x03</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GP_CLKIN</name>
|
|
<description>GP_CLKIN</description>
|
|
<value>0x04</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x05</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRYSTAL_OSCILLATOR</name>
|
|
<description>Crystal oscillator</description>
|
|
<value>0x06</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x07</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL0_FOR_AUDIO</name>
|
|
<description>PLL0 (for audio)</description>
|
|
<value>0x08</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL1</name>
|
|
<description>PLL1</description>
|
|
<value>0x09</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVA</name>
|
|
<description>IDIVA</description>
|
|
<value>0x0C</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVB</name>
|
|
<description>IDIVB</description>
|
|
<value>0x0D</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVC</name>
|
|
<description>IDIVC</description>
|
|
<value>0x0E</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVD</name>
|
|
<description>IDIVD</description>
|
|
<value>0x0F</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IDIVE</name>
|
|
<description>IDIVE</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
|
|
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>CCU1</name>
|
|
<description>Clock Control Unit (CCU)</description>
|
|
<groupName>CCU1</groupName>
|
|
<baseAddress>0x40051000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PM</name>
|
|
<description>CCU1 power mode register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Initiate power-down mode</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_OPERATION_</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOCKS_WITH_WAKE_UP_</name>
|
|
<description>Clocks with wake-up mode enabled (W = 1) are disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_STAT</name>
|
|
<description>CCU1 base clocks status register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000FFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BASE_APB3_CLK_IND</name>
|
|
<description>Base clock indicator for BASE_APB3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BASE_APB1_CLK_IND</name>
|
|
<description>Base clock indicator for BASE_APB1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BASE_SPIFI_CLK_IND</name>
|
|
<description>Base clock indicator for BASE_SPIFI_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BASE_M3_CLK_IND</name>
|
|
<description>Base clock indicator for BASE_M3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BASE_USB0_CLK_IND</name>
|
|
<description>Base clock indicator for BASE_USB0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BASE_USB1_CLK_IND</name>
|
|
<description>Base clock indicator for BASE_USB1_CLK 0 = All branch clocks switched off. 1 = at least one branch clock running.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB3_BUS_CFG</name>
|
|
<description>CLK_APB3_BUS clock configuration register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB3_I2C1_CFG</name>
|
|
<description>CLK_APB3_I2C1 clock configuration register</description>
|
|
<addressOffset>0x0108</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB3_DAC_CFG</name>
|
|
<description>CLK_APB3_DAC clock configuration register</description>
|
|
<addressOffset>0x0110</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB3_ADC0_CFG</name>
|
|
<description>CLK_APB3_ADC0 clock configuration register</description>
|
|
<addressOffset>0x0118</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB3_ADC1_CFG</name>
|
|
<description>CLK_APB3_ADC1 clock configuration register</description>
|
|
<addressOffset>0x0120</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB3_CAN0_CFG</name>
|
|
<description>CLK_APB3_CAN0 clock configuration register</description>
|
|
<addressOffset>0x0128</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB1_BUS_CFG</name>
|
|
<description>CLK_APB1_BUS clock configuration register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB1_MOTOCONPWM_CFG</name>
|
|
<description>CLK_APB1_MOTOCONPWM clock configuration register</description>
|
|
<addressOffset>0x0208</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB1_I2C0_CFG</name>
|
|
<description>CLK_ABP1_I2C0 clock configuration register</description>
|
|
<addressOffset>0x0210</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>CLK_APB1_I2S_CFG</name>
|
|
<description>CLK_APB1_I2S clock configuration register</description>
|
|
<addressOffset>0x0218</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB1_CAN1_CFG</name>
|
|
<description>CLK_APB1_CAN1 clock configuration register</description>
|
|
<addressOffset>0x0220</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_SPIFI_CFG</name>
|
|
<description>CLK_SPIFI clock configuration register</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_BUS_CFG</name>
|
|
<description>CLK_M4_BUS clock configuration register</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_SPIFI_CFG</name>
|
|
<description>CLK_M4_SPIFI clock configuration register</description>
|
|
<addressOffset>0x0408</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_GPIO_CFG</name>
|
|
<description>CLK_M4_GPIO clock configuration register</description>
|
|
<addressOffset>0x0410</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_LCD_CFG</name>
|
|
<description>CLK_M4_LCD clock configuration register</description>
|
|
<addressOffset>0x0418</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_ETHERNET_CFG</name>
|
|
<description>CLK_M4_ETHERNET clock configuration register</description>
|
|
<addressOffset>0x0420</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_USB0_CFG</name>
|
|
<description>CLK_M4_USB0 clock configuration register</description>
|
|
<addressOffset>0x0428</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_EMC_CFG</name>
|
|
<description>CLK_M4_EMC clock configuration register</description>
|
|
<addressOffset>0x0430</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_SDIO_CFG</name>
|
|
<description>CLK_M4_SDIO clock configuration register</description>
|
|
<addressOffset>0x0438</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_DMA_CFG</name>
|
|
<description>CLK_M4_DMA clock configuration register</description>
|
|
<addressOffset>0x0440</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_M4CORE_CFG</name>
|
|
<description>CLK_M4_M4CORE clock configuration register</description>
|
|
<addressOffset>0x0448</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>CLK_M4_SCT_CFG</name>
|
|
<description>CLK_M4_SCT clock configuration register</description>
|
|
<addressOffset>0x0468</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_USB1_CFG</name>
|
|
<description>CLK_M4_USB1 clock configuration register</description>
|
|
<addressOffset>0x0470</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_EMCDIV_CFG</name>
|
|
<description>CLK_M4_EMCDIV clock configuration register</description>
|
|
<addressOffset>0x0478</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Clock divider value</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>DIVIDEBY1</name>
|
|
<description>No division. Divide by 1.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIVIDEBY2</name>
|
|
<description>Divide by 2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>CLK_M4_FLASHA_CFG</name>
|
|
<description>CLK_M4_FLASHA clock configuration register</description>
|
|
<addressOffset>0x0480</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_FLASHB_CFG</name>
|
|
<description>CLK_M4_FLASHB clock configuration register</description>
|
|
<addressOffset>0x0488</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_M0APP_CFG</name>
|
|
<description>CLK_M0APP_CFG clock configuration register</description>
|
|
<addressOffset>0x0490</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_ADCHS_CFG</name>
|
|
<description>CLK_ADCHS_CFG clock configuration register</description>
|
|
<addressOffset>0x0498</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_EEPROM_CFG</name>
|
|
<description>CLK_EEPROM_CFG clock configuration register</description>
|
|
<addressOffset>0x04A0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_WWDT_CFG</name>
|
|
<description>CLK_M4_WWDT clock configuration register</description>
|
|
<addressOffset>0x500</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_USART0_CFG</name>
|
|
<description>CLK_M4_USART0 clock configuration register</description>
|
|
<addressOffset>0x0508</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_UART1_CFG</name>
|
|
<description>CLK_M4_UART1 clock configuration register</description>
|
|
<addressOffset>0x0510</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_SSP0_CFG</name>
|
|
<description>CLK_M4_SSP0 clock configuration register</description>
|
|
<addressOffset>0x0518</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_TIMER0_CFG</name>
|
|
<description>CLK_M4_TIMER0 clock configuration register</description>
|
|
<addressOffset>0x0520</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_TIMER1_CFG</name>
|
|
<description>CLK_M4_TIMER1clock configuration register</description>
|
|
<addressOffset>0x0528</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_SCU_CFG</name>
|
|
<description>CLK_M4_SCU clock configuration register</description>
|
|
<addressOffset>0x0530</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_CREG_CFG</name>
|
|
<description>CLK_M4_CREGclock configuration register</description>
|
|
<addressOffset>0x0538</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_RITIMER_CFG</name>
|
|
<description>CLK_M4_RITIMER clock configuration register</description>
|
|
<addressOffset>0x600</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_USART2_CFG</name>
|
|
<description>CLK_M4_USART2 clock configuration register</description>
|
|
<addressOffset>0x0608</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_USART3_CFG</name>
|
|
<description>CLK_M4_USART3 clock configuration register</description>
|
|
<addressOffset>0x0610</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_TIMER2_CFG</name>
|
|
<description>CLK_M4_TIMER2 clock configuration register</description>
|
|
<addressOffset>0x0618</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_TIMER3_CFG</name>
|
|
<description>CLK_M4_TIMER3 clock configuration register</description>
|
|
<addressOffset>0x0620</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_SSP1_CFG</name>
|
|
<description>CLK_M4_SSP1 clock configuration register</description>
|
|
<addressOffset>0x0628</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_QEI_CFG</name>
|
|
<description>CLK_M4_QEIclock configuration register</description>
|
|
<addressOffset>0x0630</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_PERIPH_BUS_CFG</name>
|
|
<description>CLK_PERIPH_BUS_CFG clock configuration register</description>
|
|
<addressOffset>0x0700</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_PERIPH_CORE_CFG</name>
|
|
<description>CLK_PERIPH_CORE_CFG clock configuration register</description>
|
|
<addressOffset>0x0710</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_PERIPH_SGPIO_CFG</name>
|
|
<description>CLK_PERIPH_SGPIO_CFG clock configuration register</description>
|
|
<addressOffset>0x0718</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_USB0_CFG</name>
|
|
<description>CLK_M4_USB0 clock configuration register</description>
|
|
<addressOffset>0x800</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>AUTO_IS_DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO_IS_ENABLED_</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>WAKE_UP_IS_DISABLED_</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE_UP_IS_ENABLED_</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_USB1_CFG</name>
|
|
<description>CLK_USB1 clock configuration register</description>
|
|
<addressOffset>0x900</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>AUTO_IS_DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO_IS_ENABLED_</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>WAKE_UP_IS_DISABLED_</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE_UP_IS_ENABLED_</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_SPI_CFG</name>
|
|
<description>CLK_SPI clock configuration register</description>
|
|
<addressOffset>0xA00</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>AUTO_IS_DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO_IS_ENABLED_</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>WAKE_UP_IS_DISABLED_</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE_UP_IS_ENABLED_</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_ADCHS_CFG</name>
|
|
<description>CLK_ADCHS clock configuration register</description>
|
|
<addressOffset>0xB00</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>AUTO_IS_DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AUTO_IS_ENABLED_</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>WAKE_UP_IS_DISABLED_</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAKE_UP_IS_ENABLED_</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB3_BUS_STAT</name>
|
|
<description>CLK_APB3_BUS clock status register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB3_I2C1_STAT</name>
|
|
<description>CLK_APB3_I2C1 clock status register</description>
|
|
<addressOffset>0x010C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB3_DAC_STAT</name>
|
|
<description>CLK_APB3_DAC clock status register</description>
|
|
<addressOffset>0x0114</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB3_ADC0_STAT</name>
|
|
<description>CLK_APB3_ADC0 clock status register</description>
|
|
<addressOffset>0x011C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB3_ADC1_STAT</name>
|
|
<description>CLK_APB3_ADC1 clock status register</description>
|
|
<addressOffset>0x0124</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB3_CAN0_STAT</name>
|
|
<description>CLK_APB3_CAN0 clock status register</description>
|
|
<addressOffset>0x012C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB1_BUS_STAT</name>
|
|
<description>CLK_APB1_BUS clock status register</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB1_MOTOCONPWM_STAT</name>
|
|
<description>CLK_APB1_MOTOCONPWM clock status register</description>
|
|
<addressOffset>0x020C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB1_I2C0_STAT</name>
|
|
<description>CLK_APB1_I2C0 clock status register</description>
|
|
<addressOffset>0x0214</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB1_I2S_STAT</name>
|
|
<description>CLK_APB1_I2S clock status register</description>
|
|
<addressOffset>0x021C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB1_CAN1_STAT</name>
|
|
<description>CLK_APB1_CAN1 clock status register</description>
|
|
<addressOffset>0x0224</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_SPIFI_STAT</name>
|
|
<description>CLK_APB1_SPIFI clock status register</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_BUS_STAT</name>
|
|
<description>CLK_M4_BUSclock status register</description>
|
|
<addressOffset>0x404</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_SPIFI_STAT</name>
|
|
<description>CLK_M4_SPIFI clock status register</description>
|
|
<addressOffset>0x040C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_GPIO_STAT</name>
|
|
<description>CLK_M4_GPIO clock status register</description>
|
|
<addressOffset>0x0414</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_LCD_STAT</name>
|
|
<description>CLK_M4_LCD clock status register</description>
|
|
<addressOffset>0x041C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_ETHERNET_STAT</name>
|
|
<description>CLK_M4_ETHERNET clock status register</description>
|
|
<addressOffset>0x0424</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_USB0_STAT</name>
|
|
<description>CLK_M4_USB0 clock status register</description>
|
|
<addressOffset>0x042C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_EMC_STAT</name>
|
|
<description>CLK_M4_EMC clock status register</description>
|
|
<addressOffset>0x0434</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_SDIO_STAT</name>
|
|
<description>CLK_M4_SDIO clock status register</description>
|
|
<addressOffset>0x043C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_DMA_STAT</name>
|
|
<description>CLK_M4_DMA clock status register</description>
|
|
<addressOffset>0x0444</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_M4CORE_STAT</name>
|
|
<description>CLK_M4_M3CORE clock status register</description>
|
|
<addressOffset>0x044C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>CLK_M4_SCT_STAT</name>
|
|
<description>CLK_M4_SCT clock status register</description>
|
|
<addressOffset>0x046C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_USB1_STAT</name>
|
|
<description>CLK_M4_USB1 clock status register</description>
|
|
<addressOffset>0x0474</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_EMCDIV_STAT</name>
|
|
<description>CLK_M4_EMCDIV clock status register</description>
|
|
<addressOffset>0x047C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_FLASHA_STAT</name>
|
|
<description>CLK_M4_FLASHA clock status register</description>
|
|
<addressOffset>0x0484</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>CLK_M4_FLASHB_STAT</name>
|
|
<description>CLK_M4_FLASHB clock status register</description>
|
|
<addressOffset>0x048C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
<register>
|
|
<name>CLK_M4_M0APP_STAT</name>
|
|
<description>CLK_M4_MOAPP clock status register</description>
|
|
<addressOffset>0x0494</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>CLK_M4_ADCHS_STAT</name>
|
|
<description>CLK_M4_ADCHS clock status register</description>
|
|
<addressOffset>0x049C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
<register>
|
|
<name>CLK_M4_EEPROM_STAT</name>
|
|
<description>CLK_M4_EEPROM clock status register</description>
|
|
<addressOffset>0x04A4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_WWDT_STAT</name>
|
|
<description>CLK_M4_WWDT clock status register</description>
|
|
<addressOffset>0x504</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_USART0_STAT</name>
|
|
<description>CLK_M4_USART0 clock status register</description>
|
|
<addressOffset>0x050C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_UART1_STAT</name>
|
|
<description>CLK_M4_UART1 clock status register</description>
|
|
<addressOffset>0x0514</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_SSP0_STAT</name>
|
|
<description>CLK_M4_SSP0 clock status register</description>
|
|
<addressOffset>0x051C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_TIMER0_STAT</name>
|
|
<description>CLK_M4_TIMER0 clock status register</description>
|
|
<addressOffset>0x0524</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_TIMER1_STAT</name>
|
|
<description>CLK_M4_TIMER1 clock status register</description>
|
|
<addressOffset>0x052C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_SCU_STAT</name>
|
|
<description>CLK_SCU_XXX clock status register</description>
|
|
<addressOffset>0x0534</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_CREG_STAT</name>
|
|
<description>CLK_M4_CREG clock status register</description>
|
|
<addressOffset>0x053C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_RITIMER_STAT</name>
|
|
<description>CLK_M4_RITIMER clock status register</description>
|
|
<addressOffset>0x604</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_USART2_STAT</name>
|
|
<description>CLK_M4_USART2 clock status register</description>
|
|
<addressOffset>0x060C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_USART3_STAT</name>
|
|
<description>CLK_M4_USART3 clock status register</description>
|
|
<addressOffset>0x0614</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_TIMER2_STAT</name>
|
|
<description>CLK_M4_TIMER2 clock status register</description>
|
|
<addressOffset>0x061C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_TIMER3_STAT</name>
|
|
<description>CLK_M4_TIMER3 clock status register</description>
|
|
<addressOffset>0x0624</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_SSP1_STAT</name>
|
|
<description>CLK_M4_SSP1 clock status register</description>
|
|
<addressOffset>0x062C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_M4_QEI_STAT</name>
|
|
<description>CLK_M4_QEI clock status register</description>
|
|
<addressOffset>0x0634</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_PERIPH_BUS_STAT</name>
|
|
<description>CLK_PERIPH_BUS_STAT clock status register</description>
|
|
<addressOffset>0x0704</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_PERIPH_CORE_STAT</name>
|
|
<description>CLK_CORE_BUS_STAT clock status register</description>
|
|
<addressOffset>0x0714</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_PERIPH_SGPIO_STAT</name>
|
|
<description>CLK_CORE_SGPIO_STAT clock status register</description>
|
|
<addressOffset>0x071C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_USB0_STAT</name>
|
|
<description>CLK_USB0 clock status register</description>
|
|
<addressOffset>0x804</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_USB1_STAT</name>
|
|
<description>CLK_USB1 clock status register</description>
|
|
<addressOffset>0x904</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_SPI_STAT</name>
|
|
<description>CLK_SPI clock status register</description>
|
|
<addressOffset>0xA04</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_ADCHS_STAT</name>
|
|
<description>CLK_ADCHS clock status register</description>
|
|
<addressOffset>0xB04</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CCU2</name>
|
|
<description>Clock Control Unit (CCU2)</description>
|
|
<groupName>CCU2</groupName>
|
|
<baseAddress>0x40052000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PM</name>
|
|
<description>Power mode register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>Initiate power-down mode</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_OPERATION_</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLOCKS_WITH_WAKE_UP_</name>
|
|
<description>Clocks with wake-up mode enabled (W = 1) are disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_STAT</name>
|
|
<description>CCU base clocks status register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000FFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BASE_UART3_CLK</name>
|
|
<description>Base clock indicator for BASE_UART3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BASE_UART2_CLK</name>
|
|
<description>Base clock indicator for BASE_UART2_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BASE_UART1_CLK</name>
|
|
<description>Base clock indicator for BASE_UART1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BASE_UART0_CLK</name>
|
|
<description>Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BASE_SSP1_CLK</name>
|
|
<description>Base clock indicator for BASE_SSP1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BASE_SSP0_CLK</name>
|
|
<description>Base clock indicator for BASE_SSP0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_AUDIO_CFG</name>
|
|
<description>CLK_AUDIO clock configuration register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB2_USART3_CFG</name>
|
|
<description>CLK_APB2_USART3 clock configuration register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB2_USART2_CFG</name>
|
|
<description>CLK_APB2_USART2 clock configuration register</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB0_UART1_BUS_CFG</name>
|
|
<description>CLK_APB2_UART1 clock configuration register</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB0_USART0_CFG</name>
|
|
<description>CLK_APB2_USART0 clock configuration register</description>
|
|
<addressOffset>0x500</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB0_SSP0_CFG</name>
|
|
<description>CLK_APB0_SSP0 clock configuration register</description>
|
|
<addressOffset>0x700</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB2_SSP1_CFG</name>
|
|
<description>CLK_APB2_SSP1 clock configuration register</description>
|
|
<addressOffset>0x600</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_SDIO_CFG</name>
|
|
<description>CLK_SDIO clock configuration register</description>
|
|
<addressOffset>0x800</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Clock is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Clock is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED_</name>
|
|
<description>Auto is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Wake-up is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Wake-up is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_AUDIO_STAT</name>
|
|
<description>CLK_AUDIO clock status register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB2_USART3_STAT</name>
|
|
<description>CLK_APB2_USART3 clock status register</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB2_USART2_STAT</name>
|
|
<description>CLK_APB2_USART clock status register</description>
|
|
<addressOffset>0x0304</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB0_UART1_STAT</name>
|
|
<description>CLK_APB0_UART1 clock status register</description>
|
|
<addressOffset>0x0404</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB0_USART0_STAT</name>
|
|
<description>CLK_APB0_USART0 clock status register</description>
|
|
<addressOffset>0x0504</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB2_SSP1_STAT</name>
|
|
<description>CLK_APB2_SSP1 clock status register</description>
|
|
<addressOffset>0x0604</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_APB0_SSP0_STAT</name>
|
|
<description>CLK_APB0_SSP0 clock status register</description>
|
|
<addressOffset>0x0704</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLK_SDIO_STAT</name>
|
|
<description>CLK_SDIO clock status register</description>
|
|
<addressOffset>0x0804</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN</name>
|
|
<description>Run enable status 0 = clock is disabled. 1 = clock is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AUTO</name>
|
|
<description>Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WAKEUP</name>
|
|
<description>Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>RGU</name>
|
|
<description>Reset Generation Unit (RGU)</description>
|
|
<groupName>RGU</groupName>
|
|
<baseAddress>0x40053000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
|
|
|
|
|
|
<register>
|
|
<name>RESET_CTRL0</name>
|
|
<description>Reset control register 0</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CORE_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPH_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WWDT_RST</name>
|
|
<description>Writing a one to this bit has no effect.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CREG_RST</name>
|
|
<description>Writing a one to this bit has no effect.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUS_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCU_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>M0_SUB_RST</name>
|
|
<description>Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>M4_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCD_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB0_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB1_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMA_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SDIO_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMC_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETHERNET_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASHA_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASHB_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_CTRL1</name>
|
|
<description>Reset control register 1</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER0_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER1_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER2_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER3_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RITIMER_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MOTOCONPWM_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DAC_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART0_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART1_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART2_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART3_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C0_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C1_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP0_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP1_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2S_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPIFI_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN1_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN0_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>M0APP_RST</name>
|
|
<description>Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SGPIO_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPI_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADCHS_RST</name>
|
|
<description>Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_STATUS0</name>
|
|
<description>Reset status register 0</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x55550050</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPH_RST</name>
|
|
<description>Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RST</name>
|
|
<description>Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WWDT_RST</name>
|
|
<description>Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CREG_RST</name>
|
|
<description>Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUS_RST</name>
|
|
<description>Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCU_RST</name>
|
|
<description>Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>M0SUB_RST</name>
|
|
<description>Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>M4_RST</name>
|
|
<description>Status of the M4_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_STATUS1</name>
|
|
<description>Reset status register 1</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x55555555</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LCD_RST</name>
|
|
<description>Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB0_RST</name>
|
|
<description>Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB1_RST</name>
|
|
<description>Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMA_RST</name>
|
|
<description>Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SDIO_RST</name>
|
|
<description>Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMC_RST</name>
|
|
<description>Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETHERNET_RST</name>
|
|
<description>Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASHA_RST</name>
|
|
<description>Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM_RST</name>
|
|
<description>Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_RST</name>
|
|
<description>Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASHB_RST</name>
|
|
<description>Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_STATUS2</name>
|
|
<description>Reset status register 2</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x55555555</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER0_RST</name>
|
|
<description>Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER1_RST</name>
|
|
<description>Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER2_RST</name>
|
|
<description>Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER3_RST</name>
|
|
<description>Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RITIMER_RST</name>
|
|
<description>Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT_RST</name>
|
|
<description>Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MOTOCONPWM_RST</name>
|
|
<description>Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_RST</name>
|
|
<description>Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_RST</name>
|
|
<description>Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_RST</name>
|
|
<description>Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DAC_RST</name>
|
|
<description>Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART0_RST</name>
|
|
<description>Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART1_RST</name>
|
|
<description>Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART2_RST</name>
|
|
<description>Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[29:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART3_RST</name>
|
|
<description>Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_STATUS3</name>
|
|
<description>Reset status register 3</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x55555555</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2C0_RST</name>
|
|
<description>Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C1_RST</name>
|
|
<description>Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP0_RST</name>
|
|
<description>Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP1_RST</name>
|
|
<description>Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2S_RST</name>
|
|
<description>Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPIFI_RST</name>
|
|
<description>Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN1_RST</name>
|
|
<description>Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN0_RST</name>
|
|
<description>Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>M0APP_RST</name>
|
|
<description>Status of the M0APP_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SGPIO_RST</name>
|
|
<description>Status of the SGPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[19:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPI_RST</name>
|
|
<description>Status of the SPI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADCHS_RST</name>
|
|
<description>Status of the ADCHS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[27:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[29:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_ACTIVE_STATUS0</name>
|
|
<description>Reset active status register 0</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFEFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CORE_RST</name>
|
|
<description>Current status of the CORE_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPH_RST</name>
|
|
<description>Current status of the PERIPH_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RST</name>
|
|
<description>Current status of the MASTER_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WWDT_RST</name>
|
|
<description>Current status of the WWDT_RS 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CREG_RST</name>
|
|
<description>Current status of the CREG_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUS_RST</name>
|
|
<description>Current status of the BUS_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCU_RST</name>
|
|
<description>Current status of the SCU_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>M0SUB_RST</name>
|
|
<description>Current status of the M0SUB_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>M4_RST</name>
|
|
<description>Current status of the M4_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LCD_RST</name>
|
|
<description>Current status of the LCD_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB0_RST</name>
|
|
<description>Current status of the USB0_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>USB1_RST</name>
|
|
<description>Current status of the USB1_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMA_RST</name>
|
|
<description>Current status of the DMA_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SDIO_RST</name>
|
|
<description>Current status of the SDIO_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMC_RST</name>
|
|
<description>Current status of the EMC_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ETHERNET_RST</name>
|
|
<description>Current status of the ETHERNET_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASHA_RST</name>
|
|
<description>Current status of the FLASHA_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EEPROM_RST</name>
|
|
<description>Current status of the EEPROM_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_RST</name>
|
|
<description>Current status of the GPIO_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASHB_RST</name>
|
|
<description>Current status of the FLASHB_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_ACTIVE_STATUS1</name>
|
|
<description>Reset active status register 1</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFEFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER0_RST</name>
|
|
<description>Current status of the TIMER0_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER1_RST</name>
|
|
<description>Current status of the TIMER1_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER2_RST</name>
|
|
<description>Current status of the TIMER2_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER3_RST</name>
|
|
<description>Current status of the TIMER3_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RITIMER_RST</name>
|
|
<description>Current status of the RITIMER_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SCT_RST</name>
|
|
<description>Current status of the SCT_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MOTOCONPWM_RST</name>
|
|
<description>Current status of the MOTOCONPWM_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>QEI_RST</name>
|
|
<description>Current status of the QEI_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_RST</name>
|
|
<description>Current status of the ADC0_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_RST</name>
|
|
<description>Current status of the ADC1_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DAC_RST</name>
|
|
<description>Current status of the DAC_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART0_RST</name>
|
|
<description>Current status of the UART0_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART1_RST</name>
|
|
<description>Current status of the UART1_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART2_RST</name>
|
|
<description>Current status of the UART2_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART3_RST</name>
|
|
<description>Current status of the UART3_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C0_RST</name>
|
|
<description>Current status of the I2C0_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C1_RST</name>
|
|
<description>Current status of the I2C1_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP0_RST</name>
|
|
<description>Current status of the SSP0_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSP1_RST</name>
|
|
<description>Current status of the SSP1_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2S_RST</name>
|
|
<description>Current status of the I2S_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPIFI_RST</name>
|
|
<description>Current status of the SPIFI_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN1_RST</name>
|
|
<description>Current status of the CAN1_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAN0_RST</name>
|
|
<description>Current status of the CAN0_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>M0APP_RST</name>
|
|
<description>Current status of the M0APP_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SGPIO_RST</name>
|
|
<description>Current status of the SGPIO_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPI_RST</name>
|
|
<description>Current status of the SPI_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADCHS_RST</name>
|
|
<description>Current status of the ADCHS_RST 0 = Reset asserted 1 = No reset</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
<register>
|
|
<name>RESET_EXT_STAT1</name>
|
|
<description>Reset external status register 1 for PERIPH_RST</description>
|
|
<addressOffset>0x404</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CORE_RESET</name>
|
|
<description>Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT2</name>
|
|
<description>Reset external status register 2 for MASTER_RST</description>
|
|
<addressOffset>0x408</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>RESET_EXT_STAT5</name>
|
|
<description>Reset external status register 5 for CREG_RST</description>
|
|
<addressOffset>0x414</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CORE_RESET</name>
|
|
<description>Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT8</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x420</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT9</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0424</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT12</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x430</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RESET</name>
|
|
<description>Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT13</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x434</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RESET</name>
|
|
<description>Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT16</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x440</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RESET</name>
|
|
<description>Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT17</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0444</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RESET</name>
|
|
<description>Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT18</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0448</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RESET</name>
|
|
<description>Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT19</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x044C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RESET</name>
|
|
<description>Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT20</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0450</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RESET</name>
|
|
<description>Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT21</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0454</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RESET</name>
|
|
<description>Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT22</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0458</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RESET</name>
|
|
<description>Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT25</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0464</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RESET</name>
|
|
<description>Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT27</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x046C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RESET</name>
|
|
<description>Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT28</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x470</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT29</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0474</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASTER_RESET</name>
|
|
<description>Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT32</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x480</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT33</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0484</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT34</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0488</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT35</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x048C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT36</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0490</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT37</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0494</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT38</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x0498</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT39</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x049C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT40</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04A0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT41</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04A4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT42</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04A8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT44</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04B0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT45</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04B4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT46</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04B8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT47</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04BC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT48</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT49</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT50</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04C8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT51</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04CC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT52</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04D0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT53</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04D4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT54</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04D8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT55</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04DC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT56</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04E0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT57</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04E4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT58</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04E8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESET_EXT_STAT60</name>
|
|
<description>Reset external status register</description>
|
|
<addressOffset>0x04F0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PERIPHERAL_RESET</name>
|
|
<description>Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not modify; read as logic 0.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>WWDT</name>
|
|
<description>Windowed Watchdog timer (WWDT) </description>
|
|
<groupName>WWDT</groupName>
|
|
<baseAddress>0x40080000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x300</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WWDT</name>
|
|
<value>49</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDEN</name>
|
|
<description>Watchdog enable bit. This bit is Set Only.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WWDTSTOPPED</name>
|
|
<description>The watchdog timer is stopped.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WWDTRUN</name>
|
|
<description>The watchdog timer is running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDRESET</name>
|
|
<description>Watchdog reset enable bit. This bit is Set Only.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WWDTINT</name>
|
|
<description>A watchdog time-out will not cause a chip reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WWDTRESET</name>
|
|
<description>A watchdog time-out will cause a chip reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTOF</name>
|
|
<description>Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDINT</name>
|
|
<description>Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDPROTECT</name>
|
|
<description>Watchdog update mode. This bit is Set Only.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_LOCK</name>
|
|
<description>The watchdog time-out value (WDTC) can be changed at any time.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOCK</name>
|
|
<description>The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Watchdog timer constant register. This register determines the time-out value.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDTC</name>
|
|
<description>Watchdog time-out value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FEED</name>
|
|
<description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Feed</name>
|
|
<description>Feed value should be 0xAA followed by 0x55.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TV</name>
|
|
<description>Watchdog timer value register. This register reads out the current value of the Watchdog timer.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Count</name>
|
|
<description>Counter timer value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WARNINT</name>
|
|
<description>Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDWARNINT</name>
|
|
<description>Watchdog warning interrupt compare value.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINDOW</name>
|
|
<description>Watchdog timer window register. This register contains the Watchdog window value.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00FFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDWINDOW</name>
|
|
<description>Watchdog window value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>USART0</name>
|
|
<description>USART0_2_3</description>
|
|
<groupName>USART</groupName>
|
|
<baseAddress>0x40081000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x300</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART0</name>
|
|
<value>24</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>RBR</name>
|
|
<description>Receiver Buffer Register. Contains the next received character to be read (DLAB = 0).</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RBR</name>
|
|
<description>Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0).</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLL</name>
|
|
<description>Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1).</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLLSB</name>
|
|
<description>Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLM</name>
|
|
<description>Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1).</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLMSB</name>
|
|
<description>Divisor latch MSB. The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0).</description>
|
|
<alternateRegister>DLM</alternateRegister>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBRIE</name>
|
|
<description>RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disable the RDA interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Enable the RDA interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THREIE</name>
|
|
<description>THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disable the THRE interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Enable the THRE interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIE</name>
|
|
<description>RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disable the RX line status interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Enable the RX line status interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINTEN</name>
|
|
<description>Enables the end of auto-baud interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disable end of auto-baud Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Enable end of auto-baud Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOINTEN</name>
|
|
<description>Enables the auto-baud time-out interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disable auto-baud time-out Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Enable auto-baud time-out Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IIR</name>
|
|
<description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTSTATUS</name>
|
|
<description>Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_PENDING</name>
|
|
<description>Interrupt pending. At least one interrupt is pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOT_PENDING</name>
|
|
<description>Not pending. No interrupt is pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RLS</name>
|
|
<description>RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDA</name>
|
|
<description>RDA. Priority 2 - Receive Data Available (RDA).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTI</name>
|
|
<description>CTI. Priority 2 - Character Time-out Indicator (CTI).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRE</name>
|
|
<description>THRE. Priority 3 - THRE Interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Priority 4 (lowest) - Reserved.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFOENABLE</name>
|
|
<description>Copies of FCR[0].</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINT</name>
|
|
<description>End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABTOINT</name>
|
|
<description>Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>FIFO Control Register. Controls USART FIFO usage and modes.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOEN</name>
|
|
<description>FIFO Enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. USART FIFOs are disabled. Must not be used in the application.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFORES</name>
|
|
<description>RX FIFO Reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect. No impact on either of USART FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFORES</name>
|
|
<description>TX FIFO Reset.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect. No impact on either of USART FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMODE</name>
|
|
<description>DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXTRIGLVL</name>
|
|
<description>RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_0</name>
|
|
<description>Level 0. Trigger level 0 (1 character or 0x01).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_1</name>
|
|
<description>Level 1. Trigger level 1 (4 characters or 0x04).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_2</name>
|
|
<description>Level 2. Trigger level 2 (8 characters or 0x08).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_3</name>
|
|
<description>Level 3. Trigger level 3 (14 characters or 0x0E).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCR</name>
|
|
<description>Line Control Register. Contains controls for frame formatting and break generation.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WLS</name>
|
|
<description>Word Length Select.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>5_BIT_CHARACTER_LENG</name>
|
|
<description>5-bit character length.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT_CHARACTER_LENG</name>
|
|
<description>6-bit character length.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT_CHARACTER_LENG</name>
|
|
<description>7-bit character length.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT_CHARACTER_LENG</name>
|
|
<description>8-bit character length.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBS</name>
|
|
<description>Stop Bit Select.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_STOP_BIT</name>
|
|
<description>1 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP_BITS_1</name>
|
|
<description>2 stop bits (1.5 if LCR[1:0]=00).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PARITY_GENER</name>
|
|
<description>Disable parity generation and checking.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PARITY_GENERA</name>
|
|
<description>Enable parity generation and checking.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Parity Select.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ODD_PARITY</name>
|
|
<description>Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN_PARITY</name>
|
|
<description>Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_HIGH</name>
|
|
<description>Force HIGH. Forced 1 stick parity.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_LOW</name>
|
|
<description>Force LOW. Forced 0 stick parity.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BC</name>
|
|
<description>Break Control.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Disable break transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLAB</name>
|
|
<description>Divisor Latch Access Bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Disable access to Divisor Latches.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Enable access to Divisor Latches.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LSR</name>
|
|
<description>Line Status Register. Contains flags for transmit and receive status, including line errors.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x60</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Empty. RBR is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA</name>
|
|
<description>Data. RBR contains valid data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OE</name>
|
|
<description>Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Inactive. Overrun error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Active. Overrun error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Inactive. Parity error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Active. Parity error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Inactive. Framing error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Active. Framing error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BI</name>
|
|
<description>Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Inactive. Break interrupt status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Active. Break interrupt status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THRE</name>
|
|
<description>Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_EMPTY</name>
|
|
<description>Not empty. THR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Empty. THR is empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEMT</name>
|
|
<description>Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_EMPTY</name>
|
|
<description>Not empty. THR and/or the TSR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Empty. THR and the TSR are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ERROR</name>
|
|
<description>No error. RBR contains no USART RX errors or FCR[0]=0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERROR</name>
|
|
<description>Error. USART RBR contains at least one USART RX error.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXERR</name>
|
|
<description>Error in transmitted character. A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ERROR</name>
|
|
<description>No error. No error (normal default condition).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NACK</name>
|
|
<description>NACK. A NACK response is received during Smart card T=0 operation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>Scratch Pad Register. Eight-bit temporary storage for software.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PAD</name>
|
|
<description>Scratch pad. A readable, writable byte.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR</name>
|
|
<description>Auto-baud Control Register. Contains controls for the auto-baud feature.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop. Auto-baud stop (auto-baud is not running).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Auto-baud mode select bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MODE_0</name>
|
|
<description>Mode 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1</name>
|
|
<description>Mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTORESTART</name>
|
|
<description>Restart bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESTART</name>
|
|
<description>No restart.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESTART</name>
|
|
<description>Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINTCLR</name>
|
|
<description>End of auto-baud interrupt clear bit (write-only).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect. Writing a 0 has no impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Writing a 1 will clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOINTCLR</name>
|
|
<description>Auto-baud time-out interrupt clear bit (write-only).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect. Writing a 0 has no impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Writing a 1 will clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>IrDA control register (USART3 only)</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRDAEN</name>
|
|
<description>IrDA mode enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. IrDA mode on USART3 is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRDAINV</name>
|
|
<description>Serial input direction.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted. The serial input is not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED</name>
|
|
<description>Inverted. The serial input is inverted. This has no effect on the serial output.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIXPULSEEN</name>
|
|
<description>IrDA fixed pulse width mode.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. IrDA fixed pulse width mode disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. IrDA fixed pulse width mode enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSEDIV</name>
|
|
<description>Configures the pulse when FixPulseEn = 1. See Table 885 for details.</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDR</name>
|
|
<description>Fractional Divider Register. Generates a clock input for the baud rate divider.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVADDVAL</name>
|
|
<description>Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MULVAL</name>
|
|
<description>Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSR</name>
|
|
<description>Oversampling Register. Controls the degree of oversampling during each bit time.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xF0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OSFRAC</name>
|
|
<description>Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OSINT</name>
|
|
<description>Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDINT</name>
|
|
<description>In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372.</description>
|
|
<bitRange>[14:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HDEN</name>
|
|
<description>Half-duplex enable Register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HDEN</name>
|
|
<description>Half-duplex mode enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Disable half-duplex mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Enable half-duplex mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCICTRL</name>
|
|
<description>Smart card interface control register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCIEN</name>
|
|
<description>Smart Card Interface Enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Smart card interface disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. synchronous half duplex smart card interface is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NACKDIS</name>
|
|
<description>NACK response disable. Only applicable in T=0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. A NACK response is enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. A NACK response is inhibited.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROTSEL</name>
|
|
<description>Protocol selection as defined in the ISO7816-3 standard.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>T_EQ_0</name>
|
|
<description>T = 0</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T_EQ_1</name>
|
|
<description>T = 1</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXRETRY</name>
|
|
<description>Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>GUARDTIME</name>
|
|
<description>Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485CTRL</name>
|
|
<description>RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NMMEN</name>
|
|
<description>NMM enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The receiver is enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.The receiver is disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AADEN</name>
|
|
<description>AAD enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Auto Address Detect (AAD) is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Auto Address Detect (AAD) is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCTRL</name>
|
|
<description>Direction control for DIR pin.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Disable Auto Direction Control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Enable Auto Direction Control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OINV</name>
|
|
<description>Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485ADRMATCH</name>
|
|
<description>RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRMATCH</name>
|
|
<description>Contains the address match value.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485DLY</name>
|
|
<description>RS-485/EIA-485 direction control delay.</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>Contains the direction control delay value. This register works in conjunction with an 8-bit counter.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCCTRL</name>
|
|
<description>Synchronous mode control register.</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Enables synchronous mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSRC</name>
|
|
<description>Clock source select.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLAVE_MODE</name>
|
|
<description>Slave mode. Synchronous slave mode (SCLK in)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTER_MODE</name>
|
|
<description>Master mode. Synchronous master mode (SCLK out)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FES</name>
|
|
<description>Edge sampling.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising. RxD is sampled on the rising edge of SCLK.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Falling. RxD is sampled on the falling edge of SCLK.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSBYPASS</name>
|
|
<description>Transmit synchronization bypass in synchronous slave mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SYNCHRONIZED</name>
|
|
<description>Synchronized. The input clock is synchronized prior to being used in clock edge detection logic.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOT_SYNCHRONIZED</name>
|
|
<description>Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CSCEN</name>
|
|
<description>Continuous master clock enable (used only when CSRC is 1)</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ON_CHARACTER</name>
|
|
<description>On character. SCLK cycles only when characters are being sent on TxD.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTINUOUSLY</name>
|
|
<description>Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSSDIS</name>
|
|
<description>Start/stop bits</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SEND</name>
|
|
<description>Send. Send start and stop bits as in other modes.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_SEND</name>
|
|
<description>Do not send. Do not send start/stop bits.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCCLR</name>
|
|
<description>Continuous clock clear</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SOFTWARE</name>
|
|
<description>Software. CSCEN is under software control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HARDWARE</name>
|
|
<description>Hardware. Hardware clears CSCEN after each character is received.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TER</name>
|
|
<description>Transmit Enable Register. Turns off USART transmitter for use with software flow control.</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
|
|
|
|
<peripheral derivedFrom="USART0">
|
|
<name>USART2</name>
|
|
<baseAddress>0x400C1000</baseAddress>
|
|
<interrupt>
|
|
<name>USART2</name>
|
|
<value>26</value>
|
|
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="USART0">
|
|
<name>USART3</name>
|
|
<baseAddress>0x400C2000</baseAddress>
|
|
<interrupt>
|
|
<name>USART3</name>
|
|
<value>27</value>
|
|
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>UART1</name>
|
|
<description>UART1</description>
|
|
<groupName>UART1</groupName>
|
|
<baseAddress>0x40082000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x300</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART1</name>
|
|
<value>25</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>RBR</name>
|
|
<description>Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RBR</name>
|
|
<description>Receiver Buffer. Contains the oldest received byte in the UART1 RX FIFO.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register. Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLL</name>
|
|
<description>Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLLSB</name>
|
|
<description>Divisor Latch LSB. The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLM</name>
|
|
<description>Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1)</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLMSB</name>
|
|
<description>Divisor Latch MSB. The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)</description>
|
|
<alternateRegister>DLM</alternateRegister>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBRIE</name>
|
|
<description>RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disable the RDA interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Enable the RDA interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THREIE</name>
|
|
<description>THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disable the THRE interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Enable the THRE interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIE</name>
|
|
<description>RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disable the RX line status interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Enable the RX line status interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSIE</name>
|
|
<description>Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disable the modem interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Enable the modem interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTSIE</name>
|
|
<description>CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disable the CTS interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Enable the CTS interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABEOIE</name>
|
|
<description>Enables the end of auto-baud interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disable end of auto-baud Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Enable end of auto-baud Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOIE</name>
|
|
<description>Enables the auto-baud time-out interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable. Disable auto-baud time-out Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable. Enable auto-baud time-out Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IIR</name>
|
|
<description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTSTATUS</name>
|
|
<description>Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_PENDING</name>
|
|
<description>Interrupt pending. At least one interrupt is pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOT_PENDING</name>
|
|
<description>Not pending. No interrupt is pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RLS</name>
|
|
<description>RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RDA</name>
|
|
<description>RDA. Priority 2 - Receive Data Available (RDA).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTI</name>
|
|
<description>CTI. Priority 2 - Character Time-out Indicator (CTI).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THRE</name>
|
|
<description>THRE. Priority 3 - THRE Interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Priority 4 (lowest) - Reserved.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFOENABLE</name>
|
|
<description>Copies of FCR[0].</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINT</name>
|
|
<description>End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABTOINT</name>
|
|
<description>Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>FIFO Control Register. Controls UART1 FIFO usage and modes.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOEN</name>
|
|
<description>FIFO enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Must not be used in the application.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFORES</name>
|
|
<description>RX FIFO Reset.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect. No impact on either of UART1 FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFORES</name>
|
|
<description>TX FIFO Reset.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect. No impact on either of UART1 FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAMODE</name>
|
|
<description>DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 39.6.6.1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXTRIGLVL</name>
|
|
<description>RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_0</name>
|
|
<description>Level 0. Trigger level 0 (1 character or 0x01).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_1</name>
|
|
<description>Level 1. Trigger level 1 (4 characters or 0x04).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_2</name>
|
|
<description>Level 2. Trigger level 2 (8 characters or 0x08).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_3</name>
|
|
<description>Level 3. Trigger level 3 (14 characters or 0x0E).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCR</name>
|
|
<description>Line Control Register. Contains controls for frame formatting and break generation.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WLS</name>
|
|
<description>Word Length Select.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>5_BIT_CHARACTER_LENG</name>
|
|
<description>5-bit character length.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT_CHARACTER_LENG</name>
|
|
<description>6-bit character length.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT_CHARACTER_LENG</name>
|
|
<description>7-bit character length.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT_CHARACTER_LENG</name>
|
|
<description>8-bit character length.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBS</name>
|
|
<description>Stop Bit Select.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_STOP_BIT</name>
|
|
<description>1 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP_BITS</name>
|
|
<description>2 stop bits. (1.5 if LCR[1:0]=00).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PARITY_GENER</name>
|
|
<description>Disable parity generation and checking.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PARITY_GENERA</name>
|
|
<description>Enable parity generation and checking.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Parity Select.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ODD_PARITY</name>
|
|
<description>Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN_PARITY</name>
|
|
<description>Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_HIGH</name>
|
|
<description>Force HIGH. Forced 1 stick parity.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCE_LOW</name>
|
|
<description>Force LOW. Forced 0 stick parity.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BC</name>
|
|
<description>Break Control.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Disable break transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLAB</name>
|
|
<description>Divisor Latch Access Bit (DLAB)</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Disable access to Divisor Latches.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Enable access to Divisor Latches.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Modem Control Register. Contains controls for flow control handshaking and loopback mode.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTRCTRL</name>
|
|
<description>DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTSCTRL</name>
|
|
<description>RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LMS</name>
|
|
<description>Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Disable modem loopback mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Enable modem loopback mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>RTS enable.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Disable auto-rts flow control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Enable auto-rts flow control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>CTS enable.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Disable auto-cts flow control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Enable auto-cts flow control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LSR</name>
|
|
<description>Line Status Register. Contains flags for transmit and receive status, including line errors.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x60</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Empty. The UART1 receiver FIFO is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA</name>
|
|
<description>Data. The UART1 receiver FIFO is not empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OE</name>
|
|
<description>Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Inactive. Overrun error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Active. Overrun error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Inactive. Parity error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Active. Parity error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Inactive. Framing error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Active. Framing error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BI</name>
|
|
<description>Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BREAK_INTERRUPT_STAT</name>
|
|
<description>Break interrupt status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BREAK_INTERRUPT_STAT</name>
|
|
<description>Break interrupt status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THRE</name>
|
|
<description>Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_EMPTY</name>
|
|
<description>Not empty. THR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Empty. THR is empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEMT</name>
|
|
<description>Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_EMPTY</name>
|
|
<description>Not empty. THR and/or the TSR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY</name>
|
|
<description>Empty. THR and the TSR are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ERROR</name>
|
|
<description>No error. RBR contains no UART1 RX errors or FCR[0]=0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERROR</name>
|
|
<description>Error. UART1 RBR contains at least one UART1 RX error.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSR</name>
|
|
<description>Modem Status Register. Contains handshake signal status flags.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DCTS</name>
|
|
<description>Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change. No change detected on modem input, CTS.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_CHANGE</name>
|
|
<description>State change. State change detected on modem input, CTS.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDSR</name>
|
|
<description>Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change. No change detected on modem input, DSR.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_CHANGE</name>
|
|
<description>State change. State change detected on modem input, DSR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TERI</name>
|
|
<description>Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change. No change detected on modem input, RI.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Rising. Low-to-high transition detected on RI.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDCD</name>
|
|
<description>Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change. No change detected on modem input, DCD.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_CHANGE</name>
|
|
<description>State change. State change detected on modem input, DCD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSR</name>
|
|
<description>Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCD</name>
|
|
<description>Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>Scratch Pad Register. 8-bit temporary storage for software.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Pad</name>
|
|
<description>Scratch pad. A readable, writable byte.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, the value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR</name>
|
|
<description>Auto-baud Control Register. Contains controls for the auto-baud feature.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Auto-baud start bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop. Auto-baud stop (auto-baud is not running).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Auto-baud mode select bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MODE_0</name>
|
|
<description>Mode 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1</name>
|
|
<description>Mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTORESTART</name>
|
|
<description>Auto-baud restart bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESTART</name>
|
|
<description>No restart</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESTART</name>
|
|
<description>Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINTCLR</name>
|
|
<description>End of auto-baud interrupt clear bit (write-only).</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect. Writing a 0 has no impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Writing a 1 will clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOINTCLR</name>
|
|
<description>Auto-baud time-out interrupt clear bit (write-only).</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EFFECT</name>
|
|
<description>No effect. Writing a 0 has no impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Writing a 1 will clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDR</name>
|
|
<description>Fractional Divider Register. Generates a clock input for the baud rate divider.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVADDVAL</name>
|
|
<description>Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MULVAL</name>
|
|
<description>Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485CTRL</name>
|
|
<description>RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NMMEN</name>
|
|
<description>Multidrop mode select.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receive enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. The receiver is enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled.The receiver is disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AADEN</name>
|
|
<description>Auto Address Detect enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Auto Address Detect (AAD) is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Auto Address Detect (AAD) is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Direction control.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RTS</name>
|
|
<description>RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTR</name>
|
|
<description>DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCTRL</name>
|
|
<description>Direction control enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Disable Auto Direction Control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Enable Auto Direction Control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OINV</name>
|
|
<description>Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485ADRMATCH</name>
|
|
<description>RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRMATCH</name>
|
|
<description>Contains the address match value.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485DLY</name>
|
|
<description>RS-485/EIA-485 direction control delay.</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TER</name>
|
|
<description>Transmit Enable Register. Turns off UART transmitter for use with software flow control.</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>SSP0</name>
|
|
<description>SSP0/1</description>
|
|
<groupName>SSP</groupName>
|
|
<baseAddress>0x40083000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x300</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SSP0</name>
|
|
<value>22</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>Control Register 0. Selects the serial clock rate, bus type, and data size.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSS</name>
|
|
<description>Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>4_BIT_TRANSFER</name>
|
|
<description>4-bit transfer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_BIT_TRANSFER</name>
|
|
<description>5-bit transfer</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT_TRANSFER</name>
|
|
<description>6-bit transfer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT_TRANSFER</name>
|
|
<description>7-bit transfer</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT_TRANSFER</name>
|
|
<description>8-bit transfer</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BIT_TRANSFER</name>
|
|
<description>9-bit transfer</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10_BIT_TRANSFER</name>
|
|
<description>10-bit transfer</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11_BIT_TRANSFER</name>
|
|
<description>11-bit transfer</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12_BIT_TRANSFER</name>
|
|
<description>12-bit transfer</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>13_BIT_TRANSFER</name>
|
|
<description>13-bit transfer</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>14_BIT_TRANSFER</name>
|
|
<description>14-bit transfer</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>15_BIT_TRANSFER</name>
|
|
<description>15-bit transfer</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BIT_TRANSFER</name>
|
|
<description>16-bit transfer</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRF</name>
|
|
<description>Frame Format.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SPI</name>
|
|
<description>SPI</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TI</name>
|
|
<description>TI</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MICROWIRE</name>
|
|
<description>Microwire</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THIS_COMBINATION_IS_</name>
|
|
<description>This combination is not supported and should not be used.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Out Polarity. This bit is only used in SPI mode.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BUS_LOW</name>
|
|
<description>SSP controller maintains the bus clock low between frames.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BUS_HIGH</name>
|
|
<description>SSP controller maintains the bus clock high between frames.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Out Phase. This bit is only used in SPI mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FIRST_CLOCK</name>
|
|
<description>SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SECOND_CLOCK</name>
|
|
<description>SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCR</name>
|
|
<description>Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>Control Register 1. Selects master/slave and other modes.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LBM</name>
|
|
<description>Loop Back Mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>During normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OUPTU</name>
|
|
<description>Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSE</name>
|
|
<description>SSP Enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The SSP controller is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MS</name>
|
|
<description>Master/Slave Mode.This bit can only be written when the SSE bit is 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MASTER</name>
|
|
<description>The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLAVE</name>
|
|
<description>The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOD</name>
|
|
<description>Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFE</name>
|
|
<description>Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TNF</name>
|
|
<description>Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RNE</name>
|
|
<description>Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFF</name>
|
|
<description>Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPSR</name>
|
|
<description>Clock Prescale Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CPSDVSR</name>
|
|
<description>This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMSC</name>
|
|
<description>Interrupt Mask Set and Clear Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORIM</name>
|
|
<description>Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTIM</name>
|
|
<description>Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXIM</name>
|
|
<description>Software should set this bit to enable interrupt when the Rx FIFO is at least half full.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXIM</name>
|
|
<description>Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>Raw Interrupt Status Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000008</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORRIS</name>
|
|
<description>This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTRIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXRIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is at least half full.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXRIS</name>
|
|
<description>This bit is 1 if the Tx FIFO is at least half empty.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>Masked Interrupt Status Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORMIS</name>
|
|
<description>This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTMIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXMIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXMIS</name>
|
|
<description>This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>SSPICR Interrupt Clear Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORIC</name>
|
|
<description>Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTIC</name>
|
|
<description>Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACR</name>
|
|
<description>SSP0 DMA control register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDMAE</name>
|
|
<description>Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAE</name>
|
|
<description>Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral derivedFrom="SSP0">
|
|
<name>SSP1</name>
|
|
<baseAddress>0x400C5000</baseAddress>
|
|
<interrupt>
|
|
<name>SSP1</name>
|
|
<value>23</value>
|
|
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER0</name>
|
|
<description>Timer0/1/2/3</description>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40084000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x300</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER0</name>
|
|
<value>12</value>
|
|
|
|
</interrupt>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0INT</name>
|
|
<description>Interrupt flag for match channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR1INT</name>
|
|
<description>Interrupt flag for match channel 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR2INT</name>
|
|
<description>Interrupt flag for match channel 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR3INT</name>
|
|
<description>Interrupt flag for match channel 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR0INT</name>
|
|
<description>Interrupt flag for capture channel 0 event.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR1INT</name>
|
|
<description>Interrupt flag for capture channel 1 event.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR2INT</name>
|
|
<description>Interrupt flag for capture channel 2 event.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR3INT</name>
|
|
<description>Interrupt flag for capture channel 3 event.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRST</name>
|
|
<description>When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Timer counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<description>Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Prescale counter maximum value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Prescale counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0I</name>
|
|
<description>Interrupt on MR0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Interrupt is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled. Interrupt is generated when MR0 matches the value in the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0R</name>
|
|
<description>Reset on MR0</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset. TC will be reset if MR0 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0S</name>
|
|
<description>Stop on MR0</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCH</name>
|
|
<description>Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1I</name>
|
|
<description>Interrupt on MR1</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCH</name>
|
|
<description>Match. Interrupt is generated when MR1 matches the value in the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1R</name>
|
|
<description>Reset on MR1</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>Reset. TC will be reset if MR1 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1S</name>
|
|
<description>Stop on MR1</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2I</name>
|
|
<description>Interrupt on MR2</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Interrupt is disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCH</name>
|
|
<description>Match. Interrupt is generated when MR2 matches the value in the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2R</name>
|
|
<description>Reset on MR2</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCH</name>
|
|
<description>Match. TC will be reset if MR2 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2S</name>
|
|
<description>Stop on MR2.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3I</name>
|
|
<description>Interrupt on MR3</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This interrupt is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT</name>
|
|
<description>Interrupt. Interrupt is generated when MR3 matches the value in the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3R</name>
|
|
<description>Reset on MR3</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCH</name>
|
|
<description>Match. TC will be reset if MR3 matches it.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3S</name>
|
|
<description>Stop on MR3</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. Feature disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MR%s</name>
|
|
<description>Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Timer counter match value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0RE</name>
|
|
<description>Capture on CAPn.0 rising edge</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_TO_HIGH</name>
|
|
<description>Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0FE</name>
|
|
<description>Capture on CAPn.0 falling edge</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_TO_LOW</name>
|
|
<description>High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0I</name>
|
|
<description>Interrupt on CAPn.0 event</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOAD</name>
|
|
<description>Load. A CR0 load due to a CAPn.0 event will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1RE</name>
|
|
<description>Capture on CAPn.1 rising edge</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_TO_HIGH</name>
|
|
<description>Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1FE</name>
|
|
<description>Capture on CAPn.1 falling edge</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_TO_LOW</name>
|
|
<description>High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1I</name>
|
|
<description>Interrupt on CAPn.1 event</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOAD</name>
|
|
<description>Load. A CR1 load due to a CAPn.1 event will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP2RE</name>
|
|
<description>Capture on CAPn.2 rising edge</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_TO_HIGH</name>
|
|
<description>Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP2FE</name>
|
|
<description>Capture on CAPn.2 falling edge:</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_TO_LOW</name>
|
|
<description>High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP2I</name>
|
|
<description>Interrupt on CAPn.2 event</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOAD</name>
|
|
<description>Load. A CR2 load due to a CAPn.2 event will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP3RE</name>
|
|
<description>Capture on CAPn.3 rising edge</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_TO_HIGH</name>
|
|
<description>Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP3FE</name>
|
|
<description>High to low. Capture on CAPn.3 falling edge</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_TO_LOW</name>
|
|
<description>A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP3I</name>
|
|
<description>Interrupt on CAPn.3 event:</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled. This feature is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOAD</name>
|
|
<description>Load. A CR3 load due to a CAPn.3 event will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>CR%s</name>
|
|
<description>Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Timer counter capture value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMR</name>
|
|
<description>External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively).</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM0</name>
|
|
<description>External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM1</name>
|
|
<description>External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM2</name>
|
|
<description>External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM3</name>
|
|
<description>External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EMC0</name>
|
|
<description>External Match Control 0. Determines the functionality of External Match 0.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOP</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle. Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC1</name>
|
|
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOP</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle. Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC2</name>
|
|
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOP</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle. Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC3</name>
|
|
<description>External Match Control 3. Determines the functionality of External Match 3.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOP</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE</name>
|
|
<description>Toggle. Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTCR</name>
|
|
<description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTMODE</name>
|
|
<description>Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER_MODE</name>
|
|
<description>Timer Mode. Counts every rising PCLK edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_RISING</name>
|
|
<description>Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_FALLING</name>
|
|
<description>Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_EDGES</name>
|
|
<description>Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CINSEL</name>
|
|
<description>Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CAP0</name>
|
|
<description>CAP0. CAPn.0 for TIMERn</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAP1</name>
|
|
<description>CAP1. CAPn.1 for TIMERn</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAP2</name>
|
|
<description>CAP2. CAPn.2 for TIMERn</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CAP3</name>
|
|
<description>CAP3. CAPn.3 for TIMERn</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER1</name>
|
|
<baseAddress>0x40085000</baseAddress>
|
|
<interrupt>
|
|
<name>TIMER1</name>
|
|
<value>13</value>
|
|
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER2</name>
|
|
<baseAddress>0x400C3000</baseAddress>
|
|
<interrupt>
|
|
<name>TIMER2</name>
|
|
<value>14</value>
|
|
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER3</name>
|
|
<baseAddress>0x400C4000</baseAddress>
|
|
<interrupt>
|
|
<name>TIMER3</name>
|
|
<value>15</value>
|
|
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SCU</name>
|
|
<description>System Control Unit (SCU) I/O configuration </description>
|
|
<groupName>SCU</groupName>
|
|
<baseAddress>0x40086000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>SFSP0_%s</name>
|
|
<description>Pin configuration register for pins P0</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
|
|
</register>
|
|
<register>
|
|
<dim>17</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-16</dimIndex>
|
|
<name>SFSP1_%s</name>
|
|
<description>Pin configuration register for pins P1</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
|
|
<name>SFSP1_17</name>
|
|
<description>Pin configuration register for pins P1_17</description>
|
|
<addressOffset>0x0C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHD</name>
|
|
<description>Select drive strength.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_DRIVE_4_MA_D</name>
|
|
<description>Normal-drive: 4 mA drive strength</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEDIUM_DRIVE_8_MA_D</name>
|
|
<description>Medium-drive: 8 mA drive strength</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_DRIVE_14_MA_DR</name>
|
|
<description>High-drive: 14 mA drive strength</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULTRA_HIGH_DRIVE_20</name>
|
|
<description>Ultra high-drive: 20 mA drive strength</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>18-20</dimIndex>
|
|
<name>SFSP1_%s</name>
|
|
<description>Pin configuration register for pins P1</description>
|
|
<addressOffset>0x0C8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>SFSP2_%s</name>
|
|
<description>Pin configuration register for pins P2</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>3-5</dimIndex>
|
|
<name>SFSP2_%s</name>
|
|
<description>Pin configuration register for pins P2</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHD</name>
|
|
<description>Select drive strength.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_DRIVE_4_MA_D</name>
|
|
<description>Normal-drive: 4 mA drive strength</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEDIUM_DRIVE_8_MA_D</name>
|
|
<description>Medium-drive: 8 mA drive strength</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_DRIVE_14_MA_DR</name>
|
|
<description>High-drive: 14 mA drive strength</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULTRA_HIGH_DRIVE_20</name>
|
|
<description>Ultra high-drive: 20 mA drive strength</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>6-12</dimIndex>
|
|
<name>SFSP2_%s</name>
|
|
<description>Pin configuration register for pins P2</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>SFSP3_%s</name>
|
|
<description>Pin configuration register for pins P3</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
|
|
<name>SFSP3_3</name>
|
|
<description>Pin configuration register for pins P3</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Slew rate</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FAST_LOW_NOISE_WITH</name>
|
|
<description>Fast (low noise with fast speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_SPEED_MEDIUM_N</name>
|
|
<description>High-speed (medium noise with high speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_FILTER</name>
|
|
<description>Enable input filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_FILTER</name>
|
|
<description>Disable input filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
|
|
</register>
|
|
|
|
<register>
|
|
<dim>5</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>4-8</dimIndex>
|
|
<name>SFSP3_%s</name>
|
|
<description>Pin configuration register for pins P3</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<dim>11</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-10</dimIndex>
|
|
<name>SFSP4_%s</name>
|
|
<description>Pin configuration register for pins P4</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>SFSP5_%s</name>
|
|
<description>Pin configuration register for pins P5</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>13</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-12</dimIndex>
|
|
<name>SFSP6_%s</name>
|
|
<description>Pin configuration register for pins P6</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>SFSP7_%s</name>
|
|
<description>Pin configuration register for pins P7</description>
|
|
<addressOffset>0x380</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>SFSP8_%s</name>
|
|
<description>Pin configuration register for pins P8</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>3-8</dimIndex>
|
|
<name>SFSP8_%s</name>
|
|
<description>Pin configuration register for pins P8</description>
|
|
<addressOffset>0x40C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-6</dimIndex>
|
|
<name>SFSP9_%s</name>
|
|
<description>Pin configuration register for pins P9</description>
|
|
<addressOffset>0x480</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN_</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN_</name>
|
|
<description>Enable pull-down.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Slew rate</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW</name>
|
|
<description>Slow</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST</name>
|
|
<description>Fast</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EHD</name>
|
|
<description>Select drive strength</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_DRIVE_4_MA</name>
|
|
<description>Standard drive: 4 mA drive strength</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEDIUM_DRIVE_8_MA_D</name>
|
|
<description>Medium drive: 8 mA drive strength</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_DRIVE_14_MA_DR</name>
|
|
<description>High drive: 14 mA drive strength</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULTRA_HIGH_DRIVE_20</name>
|
|
<description>Ultra-high drive: 20 mA drive strength</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
|
|
<name>SFSPA_0</name>
|
|
<description>Pin configuration register for pins PA</description>
|
|
<addressOffset>0x500</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-3</dimIndex>
|
|
<name>SFSPA_%s</name>
|
|
<description>Pin configuration register for pins PA</description>
|
|
<addressOffset>0x504</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHD</name>
|
|
<description>Select drive strength.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_DRIVE_4_MA_D</name>
|
|
<description>Normal-drive: 4 mA drive strength</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MEDIUM_DRIVE_8_MA_D</name>
|
|
<description>Medium-drive: 8 mA drive strength</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_DRIVE_14_MA_DR</name>
|
|
<description>High-drive: 14 mA drive strength</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ULTRA_HIGH_DRIVE_20</name>
|
|
<description>Ultra high-drive: 20 mA drive strength</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
|
|
<name>SFSPA_4</name>
|
|
<description>Pin configuration register for pins PA</description>
|
|
<addressOffset>0x510</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<dim>7</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-6</dimIndex>
|
|
<name>SFSPB_%s</name>
|
|
<description>Pin configuration register for pins PB</description>
|
|
<addressOffset>0x580</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>15</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-14</dimIndex>
|
|
<name>SFSPC_%s</name>
|
|
<description>Pin configuration register for pins PC</description>
|
|
<addressOffset>0x600</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>17</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-16</dimIndex>
|
|
<name>SFSPD_%s</name>
|
|
<description>Pin configuration register for pins PD</description>
|
|
<addressOffset>0x680</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>SFSPE_%s</name>
|
|
<description>Pin configuration register for pins PE</description>
|
|
<addressOffset>0x700</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>12</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-11</dimIndex>
|
|
<name>SFSPF_%s</name>
|
|
<description>Pin configuration register for pins PF</description>
|
|
<addressOffset>0x780</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Select Slew rate.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLOW_LOW_NOISE_WITH</name>
|
|
<description>Slow (low noise with medium speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MEDIUM_NOISE_W</name>
|
|
<description>Fast (medium noise with fast speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_GLITCH</name>
|
|
<description>Enable input glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_GLITCH</name>
|
|
<description>Disable input glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>SFSCLK_%s</name>
|
|
<description>Pin configuration register for pins CLK</description>
|
|
<addressOffset>0xC00</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Select pin function.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_0_DEFAULT</name>
|
|
<description>Function 0 (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_1</name>
|
|
<description>Function 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_2</name>
|
|
<description>Function 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_3</name>
|
|
<description>Function 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_4</name>
|
|
<description>Function 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_5</name>
|
|
<description>Function 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_6</name>
|
|
<description>Function 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FUNCTION_7</name>
|
|
<description>Function 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Enable pull-down resistor at pad.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_DOWN</name>
|
|
<description>Disable pull-down.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_DOWN</name>
|
|
<description>Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPUN</name>
|
|
<description>Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PULL_UP</name>
|
|
<description>Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PULL_UP</name>
|
|
<description>Disable pull-up.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EHS</name>
|
|
<description>Slew rate</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FAST_LOW_NOISE_WITH</name>
|
|
<description>Fast (low noise with fast speed)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH_SPEED_MEDIUM_N</name>
|
|
<description>High-speed (medium noise with high speed)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EZI</name>
|
|
<description>Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_BUFFER</name>
|
|
<description>Disable input buffer</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_BUFFER</name>
|
|
<description>Enable input buffer</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ZIF</name>
|
|
<description>Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_FILTER</name>
|
|
<description>Enable input filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_FILTER</name>
|
|
<description>Disable input filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
<register>
|
|
<name>SFSUSB</name>
|
|
<description>Pin configuration register for pins USB1_DM and USB1_DP</description>
|
|
<addressOffset>0xC80</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x02</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USB_AIM</name>
|
|
<description>Differential data input AIP/AIM.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>GOING_LOW_WITH_FULL</name>
|
|
<description>Going LOW with full speed edge rate</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GOING_HIGH_WITH_FULL</name>
|
|
<description>Going HIGH with full speed edge rate</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_ESEA</name>
|
|
<description>Control signal for differential input or single input.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not use.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SINGLE_INPUT</name>
|
|
<description>Single input. Enables USB1. Use with the on-chip full-speed PHY.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_EPD</name>
|
|
<description>Enable pull-down connect.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_DISCONNECT</name>
|
|
<description>Pull-down disconnected</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_CONNECTED</name>
|
|
<description>Pull-down connected</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>USB_EPWR</name>
|
|
<description>Power mode.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWER_SAVING_MODE_S</name>
|
|
<description>Power saving mode (Suspend mode)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NORMAL_MODE</name>
|
|
<description>Normal mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USB_VBUS</name>
|
|
<description>Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register. The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VBUS_SIGNAL_LOW_OR_I</name>
|
|
<description>VBUS signal LOW or inactive</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VBUS_SIGNAL_HIGH_OR</name>
|
|
<description>VBUS signal HIGH or active</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SFSI2C0</name>
|
|
<description>Pin configuration register for I2C0-bus pins</description>
|
|
<addressOffset>0xC84</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCL_EFP</name>
|
|
<description>Select input glitch filter time constant for the SCL pin.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>50_NS_GLITCH_FILTER</name>
|
|
<description>50 ns glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_NS_GLITCH_FILTER</name>
|
|
<description>3 ns glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write a 0 to this bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SCL_EHD</name>
|
|
<description>Select I2C mode for the SCL pin.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARDFAST_MODE</name>
|
|
<description>Standard/Fast mode transmit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MODE_PLUS_TRANS</name>
|
|
<description>Fast-mode Plus transmit</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCL_EZI</name>
|
|
<description>Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SCL_ZIF</name>
|
|
<description>Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_FILTER</name>
|
|
<description>Enable input filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_FILTER</name>
|
|
<description>Disable input filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDA_EFP</name>
|
|
<description>Select input glitch filter time constant for the SDA pin.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>50_NS_GLITCH_FILTER</name>
|
|
<description>50 ns glitch filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_NS_GLITCH_FILTER</name>
|
|
<description>3 ns glitch filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always write a 0 to this bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SDA_EHD</name>
|
|
<description>Select I2C mode for the SDA pin.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARDFAST_MODE</name>
|
|
<description>Standard/Fast mode transmit</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MODE_PLUS_TRANS</name>
|
|
<description>Fast-mode Plus transmit</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDA_EZI</name>
|
|
<description>Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[14:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SDA_ZIF</name>
|
|
<description>Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_INPUT_FILTER</name>
|
|
<description>Enable input filter</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_INPUT_FILTER</name>
|
|
<description>Disable input filter</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENAIO0</name>
|
|
<description>ADC0 function select register</description>
|
|
<addressOffset>0xC88</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC0_0</name>
|
|
<description>Select ADC0_0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin P4_3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC0</name>
|
|
<description>Analog function ADC0_0 selected on pin P4_3</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_1</name>
|
|
<description>Select ADC0_1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin P4_1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC0</name>
|
|
<description>Analog function ADC0_1 selected on pin P4_1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_2</name>
|
|
<description>Select ADC0_2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin PF_8.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC0</name>
|
|
<description>Analog function ADC0_2 selected on pin PF_8.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_3</name>
|
|
<description>Select ADC0_3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin P7_5.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC0</name>
|
|
<description>Analog function ADC0_3 selected on pin P7_5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_4</name>
|
|
<description>Select ADC0_4</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin P7_4.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC0</name>
|
|
<description>Analog function ADC0_4 selected on pin P7_4.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_5</name>
|
|
<description>Select ADC0_5</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin PF_10.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC0</name>
|
|
<description>Analog function ADC0_5 selected on pin PF_10.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0_6</name>
|
|
<description>Select ADC0_6</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin PB_6.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC0</name>
|
|
<description>Analog function ADC0_6 selected on pin PB_6.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENAIO1</name>
|
|
<description>ADC1 function select register</description>
|
|
<addressOffset>0xC8C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC1_0</name>
|
|
<description>Select ADC1_0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin PC_3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC1</name>
|
|
<description>Analog function ADC1_0 selected on pin PC_3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_1</name>
|
|
<description>Select ADC1_1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin PC_0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC1</name>
|
|
<description>Analog function ADC1_1 selected on pin PC_0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_2</name>
|
|
<description>Select ADC1_2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin PF_9.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC1</name>
|
|
<description>Analog function ADC1_2 selected on pin PF_9.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_3</name>
|
|
<description>Select ADC1_3</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin PF_6.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC1</name>
|
|
<description>Analog function ADC1_3 selected on pin PF_6.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_4</name>
|
|
<description>Select ADC1_4</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin PF_5.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC1</name>
|
|
<description>Analog function ADC1_4 selected on pin PF_5.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_5</name>
|
|
<description>Select ADC1_5</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin PF_11.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC1</name>
|
|
<description>Analog function ADC1_5 selected on pin PF_11.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_6</name>
|
|
<description>Select ADC1_6</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin P7_7.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC1</name>
|
|
<description>Analog function ADC1_6 selected on pin P7_7.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1_7</name>
|
|
<description>Select ADC1_7.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin PF_7.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_ADC1</name>
|
|
<description>Analog function ADC1_7 selected on pin PF_7.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENAIO2</name>
|
|
<description>Analog function select register</description>
|
|
<addressOffset>0xC90</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DAC</name>
|
|
<description>Select DAC</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin P4_4.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANALOG_FUNCTION_DAC</name>
|
|
<description>Analog function DAC selected on pin P4_4.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BG</name>
|
|
<description>Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTION_SEL</name>
|
|
<description>Digital function selected on pin PF_7.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BAND_GAP_OUTPUT_SELE</name>
|
|
<description>Band gap output selected for pin PF_7.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMCDELAYCLK</name>
|
|
<description>EMC clock delay register</description>
|
|
<addressOffset>0xD00</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLK_DELAY</name>
|
|
<description>EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to reserved register bits.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDDELAY</name>
|
|
<description>SD/MMC sample and drive delay register</description>
|
|
<addressOffset>0xD80</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SAMPLE_DELAY</name>
|
|
<description>SD/MMC sample delay. The delay value is SAMPLE_DELAY x 0.5 ns.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to reserved register bits.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DRV_DELAY</name>
|
|
<description>SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to reserved register bits.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINTSEL0</name>
|
|
<description>Pin interrupt select register for pin interrupts 0 to 3.</description>
|
|
<addressOffset>0xE00</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTPIN0</name>
|
|
<description>Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PORTSEL0</name>
|
|
<description>Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_0</name>
|
|
<description>GPIO Port 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_1</name>
|
|
<description>GPIO Port 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_2</name>
|
|
<description>GPIO Port 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_3</name>
|
|
<description>GPIO Port 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_4</name>
|
|
<description>GPIO Port 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_5</name>
|
|
<description>GPIO Port 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_6</name>
|
|
<description>GPIO Port 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_7</name>
|
|
<description>GPIO Port 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTPIN1</name>
|
|
<description>Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register.</description>
|
|
<bitRange>[12:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PORTSEL1</name>
|
|
<description>Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_0</name>
|
|
<description>GPIO Port 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_1</name>
|
|
<description>GPIO Port 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_2</name>
|
|
<description>GPIO Port 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_3</name>
|
|
<description>GPIO Port 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_4</name>
|
|
<description>GPIO Port 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_5</name>
|
|
<description>GPIO Port 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_6</name>
|
|
<description>GPIO Port 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_7</name>
|
|
<description>GPIO Port 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTPIN2</name>
|
|
<description>Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register.</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PORTSEL2</name>
|
|
<description>Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register.</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_0</name>
|
|
<description>GPIO Port 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_1</name>
|
|
<description>GPIO Port 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_2</name>
|
|
<description>GPIO Port 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_3</name>
|
|
<description>GPIO Port 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_4</name>
|
|
<description>GPIO Port 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_5</name>
|
|
<description>GPIO Port 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_6</name>
|
|
<description>GPIO Port 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_7</name>
|
|
<description>GPIO Port 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTPIN3</name>
|
|
<description>Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PORTSEL3</name>
|
|
<description>Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register.</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_0</name>
|
|
<description>GPIO Port 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_1</name>
|
|
<description>GPIO Port 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_2</name>
|
|
<description>GPIO Port 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_3</name>
|
|
<description>GPIO Port 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_4</name>
|
|
<description>GPIO Port 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_5</name>
|
|
<description>GPIO Port 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_6</name>
|
|
<description>GPIO Port 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_7</name>
|
|
<description>GPIO Port 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINTSEL1</name>
|
|
<description>Pin interrupt select register for pin interrupts 4 to 7.</description>
|
|
<addressOffset>0xE04</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTPIN4</name>
|
|
<description>Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PORTSEL4</name>
|
|
<description>Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_0</name>
|
|
<description>GPIO Port 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_1</name>
|
|
<description>GPIO Port 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_2</name>
|
|
<description>GPIO Port 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_3</name>
|
|
<description>GPIO Port 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_4</name>
|
|
<description>GPIO Port 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_5</name>
|
|
<description>GPIO Port 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_6</name>
|
|
<description>GPIO Port 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_7</name>
|
|
<description>GPIO Port 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTPIN5</name>
|
|
<description>Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register.</description>
|
|
<bitRange>[12:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PORTSEL5</name>
|
|
<description>Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_0</name>
|
|
<description>GPIO Port 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_1</name>
|
|
<description>GPIO Port 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_2</name>
|
|
<description>GPIO Port 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_3</name>
|
|
<description>GPIO Port 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_4</name>
|
|
<description>GPIO Port 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_5</name>
|
|
<description>GPIO Port 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_6</name>
|
|
<description>GPIO Port 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_7</name>
|
|
<description>GPIO Port 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTPIN6</name>
|
|
<description>Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register.</description>
|
|
<bitRange>[20:16]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PORTSEL6</name>
|
|
<description>Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register.</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_0</name>
|
|
<description>GPIO Port 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_1</name>
|
|
<description>GPIO Port 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_2</name>
|
|
<description>GPIO Port 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_3</name>
|
|
<description>GPIO Port 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_4</name>
|
|
<description>GPIO Port 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_5</name>
|
|
<description>GPIO Port 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_6</name>
|
|
<description>GPIO Port 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_7</name>
|
|
<description>GPIO Port 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTPIN7</name>
|
|
<description>Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register.</description>
|
|
<bitRange>[28:24]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PORTSEL7</name>
|
|
<description>Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register.</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_0</name>
|
|
<description>GPIO Port 0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_1</name>
|
|
<description>GPIO Port 1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_2</name>
|
|
<description>GPIO Port 2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_3</name>
|
|
<description>GPIO Port 3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_4</name>
|
|
<description>GPIO Port 4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_5</name>
|
|
<description>GPIO Port 5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_6</name>
|
|
<description>GPIO Port 6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_PORT_7</name>
|
|
<description>GPIO Port 7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>GPIO_PIN_INT</name>
|
|
<description>GPIO pin interrupt</description>
|
|
<groupName>GPIO_PIN_INT</groupName>
|
|
<baseAddress>0x40087000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PIN_INT0</name>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT1</name>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT2</name>
|
|
<value>34</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT3</name>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT4</name>
|
|
<value>36</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT5</name>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT6</name>
|
|
<value>38</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIN_INT7</name>
|
|
<value>39</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ISEL</name>
|
|
<description>Pin Interrupt Mode register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMODE0</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE1</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE2</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE3</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE4</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE5</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE6</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PMODE7</name>
|
|
<description>Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IENR</name>
|
|
<description>Pin Interrupt Enable (Rising) register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENRL0</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL1</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL2</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL3</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL4</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL5</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL6</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENRL7</name>
|
|
<description>Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIENR</name>
|
|
<description>Set Pin Interrupt Enable (Rising) register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENRL0</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL1</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL2</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL3</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL4</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL5</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL6</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENRL7</name>
|
|
<description>Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIENR</name>
|
|
<description>Clear Pin Interrupt Enable (Rising) register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CENRL0</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL1</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL2</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL3</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL4</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL5</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL6</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENRL7</name>
|
|
<description>Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IENF</name>
|
|
<description>Pin Interrupt Enable Falling Edge / Active Level register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENAF0</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF1</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF2</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF3</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF4</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF5</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF6</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENAF7</name>
|
|
<description>Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIENF</name>
|
|
<description>Set Pin Interrupt Enable Falling Edge / Active Level register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETENAF0</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF1</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF2</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF3</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF4</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF5</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF6</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETENAF7</name>
|
|
<description>Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIENF</name>
|
|
<description>Clear Pin Interrupt Enable Falling Edge / Active Level address</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CENAF0</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF1</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF2</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF3</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF4</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF5</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF6</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENAF7</name>
|
|
<description>Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RISE</name>
|
|
<description>Pin Interrupt Rising Edge register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RDET0</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET1</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET2</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET3</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET4</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET5</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET6</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RDET7</name>
|
|
<description>Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FALL</name>
|
|
<description>Pin Interrupt Falling Edge register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FDET0</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET1</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET2</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET3</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET4</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET5</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET6</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FDET7</name>
|
|
<description>Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IST</name>
|
|
<description>Pin Interrupt Status register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSTAT0</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT1</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT2</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT3</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT4</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT5</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT6</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PSTAT7</name>
|
|
<description>Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register).</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>GPIO_GROUP_INT0</name>
|
|
<description>GPIO group interrupt 0</description>
|
|
<groupName>GPIO_GROUP_INT0</groupName>
|
|
<baseAddress>0x40088000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GINT0</name>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>GPIO grouped interrupt control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT</name>
|
|
<description>Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_REQUEST</name>
|
|
<description>No interrupt request is pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_REQUEST_IS</name>
|
|
<description>Interrupt request is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMB</name>
|
|
<description>Combine enabled inputs for group interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OR_FUNCTIONALITY_A_</name>
|
|
<description>OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>AND_FUNCTIONALITY_A</name>
|
|
<description>AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG</name>
|
|
<description>Group interrupt trigger</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE_TRIGGERED</name>
|
|
<description>Edge-triggered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_TRIGGERED</name>
|
|
<description>Level-triggered</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>PORT_POL%s</name>
|
|
<description>GPIO grouped interrupt port polarity register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POL_0</name>
|
|
<description>Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_1</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_2</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_3</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_4</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_5</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_6</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_7</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_8</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_9</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_10</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_11</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_12</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_13</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_14</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_15</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_16</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_17</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_18</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_19</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_20</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_21</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_22</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_23</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_24</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_25</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_26</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_27</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_28</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_29</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_30</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POL_31</name>
|
|
<description>Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>PORT_ENA%s</name>
|
|
<description>GPIO grouped interrupt port m enable register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA_0</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_1</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_2</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_3</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_4</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_5</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_6</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_7</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_8</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_9</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_10</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_11</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_12</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_13</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_14</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_15</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_16</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_17</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_18</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_19</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_20</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_21</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_22</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_23</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_24</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_25</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_26</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_27</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_28</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_29</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_30</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENA_31</name>
|
|
<description>Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIO_GROUP_INT0">
|
|
<name>GPIO_GROUP_INT1</name>
|
|
<baseAddress>0x40089000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GINT1</name>
|
|
<value>41</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MCPWM</name>
|
|
<description>Motor Control PWM (MOTOCONPWM) </description>
|
|
<groupName>MCPWM</groupName>
|
|
<baseAddress>0x400A0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>MCPWM</name>
|
|
<value>16</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CON</name>
|
|
<description>PWM Control read address</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN0</name>
|
|
<description>Stops/starts timer channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP_</name>
|
|
<description>Stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN_</name>
|
|
<description>Run.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CENTER0</name>
|
|
<description>Edge/center aligned operation for channel 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE_ALIGNED_</name>
|
|
<description>Edge-aligned.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_</name>
|
|
<description>Center-aligned.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLA0</name>
|
|
<description>Selects polarity of the MCOA0 and MCOB0 pins.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PASSIVE_STATE_IS_LOW</name>
|
|
<description>Passive state is LOW, active state is HIGH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PASSIVE_STATE_IS_HIG</name>
|
|
<description>Passive state is HIGH, active state is LOW.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTE0</name>
|
|
<description>Controls the dead-time feature for channel 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DEAD_TIME_DISABLED_</name>
|
|
<description>Dead-time disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEAD_TIME_ENABLED_</name>
|
|
<description>Dead-time enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISUP0</name>
|
|
<description>Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Functional registers are updated from the write registers at the end of each PWM cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOUPDATE</name>
|
|
<description>Functional registers remain the same as long as the timer is running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RUN1</name>
|
|
<description>Stops/starts timer channel 1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP_</name>
|
|
<description>Stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN_</name>
|
|
<description>Run.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CENTER1</name>
|
|
<description>Edge/center aligned operation for channel 1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE_ALIGNED_</name>
|
|
<description>Edge-aligned.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_</name>
|
|
<description>Center-aligned.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLA1</name>
|
|
<description>Selects polarity of the MCOA1 and MCOB1 pins.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PASSIVE_STATE_IS_LOW</name>
|
|
<description>Passive state is LOW, active state is HIGH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PASSIVE_STATE_IS_HIG</name>
|
|
<description>Passive state is HIGH, active state is LOW.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTE1</name>
|
|
<description>Controls the dead-time feature for channel 1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DEAD_TIME_DISABLED_</name>
|
|
<description>Dead-time disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEAD_TIME_ENABLED_</name>
|
|
<description>Dead-time enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISUP1</name>
|
|
<description>Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Functional registers are updated from the write registers at the end of each PWM cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOUPDATE</name>
|
|
<description>Functional registers remain the same as long as the timer is running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RUN2</name>
|
|
<description>Stops/starts timer channel 2.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP_</name>
|
|
<description>Stop.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN_</name>
|
|
<description>Run.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CENTER2</name>
|
|
<description>Edge/center aligned operation for channel 2.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EDGE_ALIGNED_</name>
|
|
<description>Edge-aligned.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CENTER_ALIGNED_</name>
|
|
<description>Center-aligned.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POLA2</name>
|
|
<description>Selects polarity of the MCOA2 and MCOB2 pins.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PASSIVE_STATE_IS_LOW</name>
|
|
<description>Passive state is LOW, active state is HIGH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PASSIVE_STATE_IS_HIG</name>
|
|
<description>Passive state is HIGH, active state is LOW.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTE2</name>
|
|
<description>Controls the dead-time feature for channel 1.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DEAD_TIME_DISABLED_</name>
|
|
<description>Dead-time disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEAD_TIME_ENABLED_</name>
|
|
<description>Dead-time enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DISUP2</name>
|
|
<description>Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>UPDATE</name>
|
|
<description>Functional registers are updated from the write registers at the end of each PWM cycle.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOUPDATE</name>
|
|
<description>Functional registers remain the same as long as the timer is running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[28:21]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>INVBDC</name>
|
|
<description>Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>OPPOSITE</name>
|
|
<description>The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SAME</name>
|
|
<description>The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACMODE</name>
|
|
<description>3-phase AC mode select (see Section 24.8.7).</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>3_PHASE_AC_MODE_OFF</name>
|
|
<description>3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_PHASE_AC_MODE_ON_</name>
|
|
<description>3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCMODE</name>
|
|
<description>3-phase DC mode select (see Section 24.8.6).</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>3_PHASE_DC_MODE_OFF</name>
|
|
<description>3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_PHASE_DC_MODE_ON_</name>
|
|
<description>3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CON_SET</name>
|
|
<description>PWM Control set address</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENTER0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POLA0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTE0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DISUP0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RUN1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENTER1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POLA1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTE1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DISUP1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RUN2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENTER2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POLA2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTE2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DISUP2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[28:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INVBDC_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACMODE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DCMODE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CON register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CON_CLR</name>
|
|
<description>PWM Control clear address</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RUN0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENTER0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POLA0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTE0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DISUP0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RUN1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENTER1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POLA1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTE1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DISUP1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RUN2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CENTER2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POLA2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DTE2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DISUP2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[28:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INVBDC_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACMOD_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DCMODE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CON register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAPCON</name>
|
|
<description>Capture Control read address</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0MCI0_RE</name>
|
|
<description>A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI0_FE</name>
|
|
<description>A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI1_RE</name>
|
|
<description>A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI1_FE</name>
|
|
<description>A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI2_RE</name>
|
|
<description>A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI2_FE</name>
|
|
<description>A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI0_RE</name>
|
|
<description>A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI0_FE</name>
|
|
<description>A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI1_RE</name>
|
|
<description>A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI1_FE</name>
|
|
<description>A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI2_RE</name>
|
|
<description>A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI2_FE</name>
|
|
<description>A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI0_RE</name>
|
|
<description>A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI0_FE</name>
|
|
<description>A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI1_RE</name>
|
|
<description>A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI1_FE</name>
|
|
<description>A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI2_RE</name>
|
|
<description>A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI2_FE</name>
|
|
<description>A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT0</name>
|
|
<description>If this bit is 1, TC0 is reset by a channel 0 capture event.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT1</name>
|
|
<description>If this bit is 1, TC1 is reset by a channel 1 capture event.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT2</name>
|
|
<description>If this bit is 1, TC2 is reset by a channel 2 capture event.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
|
|
|
|
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAPCON_SET</name>
|
|
<description>Capture Control set address</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0MCI0_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI0_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI1_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI1_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI2_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI2_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI0_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI0_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI1_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI1_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI2_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI2_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI0_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI0_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI1_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI1_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI2_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI2_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT0_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT1_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT2_SET</name>
|
|
<description>Writing a one sets the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
|
|
|
|
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAPCON_CLR</name>
|
|
<description>Event Control clear address</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0MCI0_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI0_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI1_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI1_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI2_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP0MCI2_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI0_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI0_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI1_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI1_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI2_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP1MCI2_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI0_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI0_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI1_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI1_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI2_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP2MCI2_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT0_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT1_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RT2_CLR</name>
|
|
<description>Writing a one clears the corresponding bits in the CAPCON register.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
|
|
|
|
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>TC%s</name>
|
|
<description>Timer Counter register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MCTC</name>
|
|
<description>Timer/Counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>LIM%s</name>
|
|
<description>Limit register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MCLIM</name>
|
|
<description>Limit value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>MAT%s</name>
|
|
<description>Match register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MCMAT</name>
|
|
<description>Match value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DT</name>
|
|
<description>Dead time register</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x3FFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DT0</name>
|
|
<description>Dead time for channel 0.[1]</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DT1</name>
|
|
<description>Dead time for channel 1.[2]</description>
|
|
<bitRange>[19:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DT2</name>
|
|
<description>Dead time for channel 2.[2]</description>
|
|
<bitRange>[29:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCP</name>
|
|
<description>Communication Pattern register</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCPA0</name>
|
|
<description>Communication pattern output A, channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MCOA0_PASSIVE_</name>
|
|
<description>MCOA0 passive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_MCOA0_</name>
|
|
<description>internal MCOA0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCPB0</name>
|
|
<description>Communication pattern output B, channel 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MCOB0_PASSIVE_</name>
|
|
<description>MCOB0 passive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCOB0_TRACKS_INTERNA</name>
|
|
<description>MCOB0 tracks internal MCOA0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCPA1</name>
|
|
<description>Communication pattern output A, channel 1.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MCOA1_PASSIVE_</name>
|
|
<description>MCOA1 passive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCOA1_TRACKS_INTERNA</name>
|
|
<description>MCOA1 tracks internal MCOA0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCPB1</name>
|
|
<description>Communication pattern output B, channel 1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MCOB1_PASSIVE_</name>
|
|
<description>MCOB1 passive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCOB1_TRACKS_INTERNA</name>
|
|
<description>MCOB1 tracks internal MCOA0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCPA2</name>
|
|
<description>Communication pattern output A, channel 2.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MCOA2_PASSIVE_</name>
|
|
<description>MCOA2 passive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCOA2_TRACKS_INTERNA</name>
|
|
<description>MCOA2 tracks internal MCOA0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCPB2</name>
|
|
<description>Communication pattern output B, channel 2.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MCOB2_PASSIVE_</name>
|
|
<description>MCOB2 passive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCOB2_TRACKS_INTERNA</name>
|
|
<description>MCOB2 tracks internal MCOA0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-2</dimIndex>
|
|
<name>CAP%s</name>
|
|
<description>Capture register</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Current TC value at a capture event.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>Interrupt Enable read address</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILIM0</name>
|
|
<description>Limit interrupt for channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAT0</name>
|
|
<description>Match interrupt for channel 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICAP0</name>
|
|
<description>Capture interrupt for channel 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ILIM1</name>
|
|
<description>Limit interrupt for channel 1.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAT1</name>
|
|
<description>Match interrupt for channel 1.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICAP1</name>
|
|
<description>Capture interrupt for channel 1.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ILIM2</name>
|
|
<description>Limit interrupt for channel 2.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAT2</name>
|
|
<description>Match interrupt for channel 2.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICAP2</name>
|
|
<description>Capture interrupt for channel 2.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[14:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABORT</name>
|
|
<description>Fast abort interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_DISABLED_</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTERRUPT_ENABLED_</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN_SET</name>
|
|
<description>Interrupt Enable set address</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILIM0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[14:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABORT_SET</name>
|
|
<description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN_CLR</name>
|
|
<description>Interrupt Enable clear address</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILIM0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[14:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABORT_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF</name>
|
|
<description>Interrupt flags read address</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILIM0_F</name>
|
|
<description>Limit interrupt flag for channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAT0_F</name>
|
|
<description>Match interrupt flag for channel 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICAP0_F</name>
|
|
<description>Capture interrupt flag for channel 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ILIM1_F</name>
|
|
<description>Limit interrupt flag for channel 1.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAT1_F</name>
|
|
<description>Match interrupt flag for channel 1.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICAP1_F</name>
|
|
<description>Capture interrupt flag for channel 1.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ILIM2_F</name>
|
|
<description>Limit interrupt flag for channel 2.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IMAT2_F</name>
|
|
<description>Match interrupt flag for channel 2.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICAP2_F</name>
|
|
<description>Capture interrupt flag for channel 2.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[14:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABORT_F</name>
|
|
<description>Fast abort interrupt flag.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_INTERRUPT_SOURC</name>
|
|
<description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>IF_THE_CORRESPONDING</name>
|
|
<description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF_SET</name>
|
|
<description>Interrupt flags set address</description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILIM0_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT0_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP0_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM1_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT1_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP1_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM2_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT2_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP2_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[14:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABORT_F_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF_CLR</name>
|
|
<description>Interrupt flags clear address</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ILIM0_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT0_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP0_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM1_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT1_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP1_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ILIM2_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IMAT2_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ICAP2_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[14:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABORT_F_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTCON</name>
|
|
<description>Count Control read address</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC0MCI0_RE</name>
|
|
<description>Counter 0 rising edge mode, channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A rising edge on MCI0 does not affect counter 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE0 is 1, counter 0 advances on a rising edge on MCI0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI0_FE</name>
|
|
<description>Counter 0 falling edge mode, channel 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFECT</name>
|
|
<description>A falling edge on MCI0 does not affect counter 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE0 is 1, counter 0 advances on a falling edge on MCI0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI1_RE</name>
|
|
<description>Counter 0 rising edge mode, channel 1.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A rising edge on MCI1 does not affect counter 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE0 is 1, counter 0 advances on a rising edge on MCI1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI1_FE</name>
|
|
<description>Counter 0 falling edge mode, channel 1.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A falling edge on MCI1 does not affect counter 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE0 is 1, counter 0 advances on a falling edge on MCI1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI2_RE</name>
|
|
<description>Counter 0 rising edge mode, channel 2.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A rising edge on MCI0 does not affect counter 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE0 is 1, counter 0 advances on a rising edge on MCI2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI2_FE</name>
|
|
<description>Counter 0 falling edge mode, channel 2.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A falling edge on MCI0 does not affect counter 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE0 is 1, counter 0 advances on a falling edge on MCI2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI0_RE</name>
|
|
<description>Counter 1 rising edge mode, channel 0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A rising edge on MCI0 does not affect counter 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE1 is 1, counter 1 advances on a rising edge on MCI0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI0_FE</name>
|
|
<description>Counter 1 falling edge mode, channel 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>A falling edge on MCI0 does not affect counter 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE1 is 1, counter 1 advances on a falling edge on MCI0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI1_RE</name>
|
|
<description>Counter 1 rising edge mode, channel 1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A rising edge on MCI1 does not affect counter 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE1 is 1, counter 1 advances on a rising edge on MCI1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI1_FE</name>
|
|
<description>Counter 1 falling edge mode, channel 1.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A falling edge on MCI0 does not affect counter 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE1 is 1, counter 1 advances on a falling edge on MCI1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI2_RE</name>
|
|
<description>Counter 1 rising edge mode, channel 2.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A rising edge on MCI2 does not affect counter 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE1 is 1, counter 1 advances on a rising edge on MCI2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI2_FE</name>
|
|
<description>Counter 1 falling edge mode, channel 2.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A falling edge on MCI2 does not affect counter 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>If MODE1 is 1, counter 1 advances on a falling edge on MCI2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI0_RE</name>
|
|
<description>Counter 2 rising edge mode, channel 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A rising edge on MCI0 does not affect counter 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE2 is 1, counter 2 advances on a rising edge on MCI0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI0_FE</name>
|
|
<description>Counter 2 falling edge mode, channel 0.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A falling edge on MCI0 does not affect counter 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE2 is 1, counter 2 advances on a falling edge on MCI0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI1_RE</name>
|
|
<description>Counter 2 rising edge mode, channel 1.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A rising edge on MCI1 does not affect counter 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE2 is 1, counter 2 advances on a rising edge on MCI1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI1_FE</name>
|
|
<description>Counter 2 falling edge mode, channel 1.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A falling edge on MCI1 does not affect counter 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE2 is 1, counter 2 advances on a falling edge on MCI1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI2_RE</name>
|
|
<description>Counter 2 rising edge mode, channel 2.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A rising edge on MCI2 does not affect counter 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE2 is 1, counter 2 advances on a rising edge on MCI2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI2_FE</name>
|
|
<description>Counter 2 falling edge mode, channel 2.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOEFFECT</name>
|
|
<description>A falling edge on MCI2 does not affect counter 2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>If MODE2 is 1, counter 2 advances on a falling edge on MCI2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[28:18]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CNTR0</name>
|
|
<description>Channel 0 counter/timer mode.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_0_IS_IN_TIME</name>
|
|
<description>Channel 0 is in timer mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_0_IS_IN_COUN</name>
|
|
<description>Channel 0 is in counter mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTR1</name>
|
|
<description>Channel 1 counter/timer mode.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_1_IS_IN_TIME</name>
|
|
<description>Channel 1 is in timer mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_1_IS_IN_COUN</name>
|
|
<description>Channel 1 is in counter mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTR2</name>
|
|
<description>Channel 2 counter/timer mode.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_2_IS_IN_TIME</name>
|
|
<description>Channel 2 is in timer mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CHANNEL_2_IS_IN_COUN</name>
|
|
<description>Channel 2 is in counter mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTCON_SET</name>
|
|
<description>Count Control set address</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC0MCI0_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI0_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI1_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI1_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI2_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI2_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI0_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI0_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI1_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI1_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI2_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI2_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI0_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI0_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI1_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI1_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI2_RE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI2_FE_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[28:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTR0_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTR1_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTR2_SET</name>
|
|
<description>Writing a one sets the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTCON_CLR</name>
|
|
<description>Count Control clear address</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC0MCI0_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI0_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI1_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI1_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI2_RE</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC0MCI2_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI0_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI0_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI1_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI1_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI2_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC1MCI2_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI0_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI0_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI1_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI1_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI2_RE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TC2MCI2_FE_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[28:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTR0_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTR1_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CNTR2_CLR</name>
|
|
<description>Writing a one clears the corresponding bit in the CNTCON register.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP_CLR</name>
|
|
<description>Capture clear address</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP_CLR0</name>
|
|
<description>Writing a 1 to this bit clears the CAP0 register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP_CLR1</name>
|
|
<description>Writing a 1 to this bit clears the CAP1 register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAP_CLR2</name>
|
|
<description>Writing a 1 to this bit clears the CAP2 register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>I2C0</name>
|
|
<description>I2C-bus interface</description>
|
|
<groupName>I2C</groupName>
|
|
<baseAddress>0x400A1000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C0</name>
|
|
<value>18</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CONSET</name>
|
|
<description>I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AA</name>
|
|
<description>Assert acknowledge flag.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SI</name>
|
|
<description>I2C interrupt flag.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STO</name>
|
|
<description>STOP flag.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STA</name>
|
|
<description>START flag.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2EN</name>
|
|
<description>I2C interface enable.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xF8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are unused and are always 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Status</name>
|
|
<description>These bits give the actual status information about the I 2C interface.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAT</name>
|
|
<description>I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Data</name>
|
|
<description>This register holds data values that have been received or are to be transmitted.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADR0</name>
|
|
<description>I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GC</name>
|
|
<description>General Call enable bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Address</name>
|
|
<description>The I2C device address for slave mode.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCLH</name>
|
|
<description>SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x04</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCLH</name>
|
|
<description>Count for SCL HIGH time period selection.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCLL</name>
|
|
<description>SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x04</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCLL</name>
|
|
<description>Count for SCL low time period selection.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONCLR</name>
|
|
<description>I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AAC</name>
|
|
<description>Assert acknowledge Clear bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIC</name>
|
|
<description>I2C interrupt Clear bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STAC</name>
|
|
<description>START flag Clear bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2ENC</name>
|
|
<description>I2C interface Disable bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMCTRL</name>
|
|
<description>Monitor mode control register.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MM_ENA</name>
|
|
<description>Monitor mode enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MONITOR_MODE_DISABLE</name>
|
|
<description>Monitor mode disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_I_2C_MODULE_WILL</name>
|
|
<description>The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENA_SCL</name>
|
|
<description>SCL output enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WHEN_THIS_BIT_IS_CLE</name>
|
|
<description>When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WHEN_THIS_BIT_IS_SET</name>
|
|
<description>When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCH_ALL</name>
|
|
<description>Select interrupt register match.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>WHEN_THIS_BIT_IS_CLE</name>
|
|
<description>When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WHEN_THIS_BIT_IS_SET</name>
|
|
<description>When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from reserved bits is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-3</dimIndex>
|
|
<name>ADR%s</name>
|
|
<description>I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GC</name>
|
|
<description>General Call enable bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Address</name>
|
|
<description>The I2C device address for slave mode.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_BUFFER</name>
|
|
<description>Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Data</name>
|
|
<description>This register holds contents of the 8 MSBs of the DAT shift register.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MASK%s</name>
|
|
<description>I2C Slave address mask register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Mask bits.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C1</name>
|
|
<baseAddress>0x400E0000</baseAddress>
|
|
<interrupt>
|
|
<name>I2C1</name>
|
|
<value>19</value>
|
|
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>I2S0</name>
|
|
<description>I2S interface </description>
|
|
<groupName>I2S</groupName>
|
|
<baseAddress>0x400A2000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2S0</name>
|
|
<value>28</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DAO</name>
|
|
<description>I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x87E1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WORDWIDTH</name>
|
|
<description>Selects the number of bytes in data as follows:</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>8_BIT_DATA</name>
|
|
<description>8-bit data</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BIT_DATA</name>
|
|
<description>16-bit data</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, do not use this setting</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32_BIT_DATA</name>
|
|
<description>32-bit data</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONO</name>
|
|
<description>When 1, data is of monaural format. When 0, the data is in stereo format.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>When 1, disables accesses on FIFOs, places the transmit channel in mute mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>When 1, asynchronously resets the transmit channel and FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WS_SEL</name>
|
|
<description>When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WS_HALFPERIOD</name>
|
|
<description>Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.</description>
|
|
<bitRange>[14:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MUTE</name>
|
|
<description>When 1, the transmit channel sends only zeroes.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAI</name>
|
|
<description>I2S Digital Audio Input Register. Contains control bits for the I2S receive channel.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x07E1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WORDWIDTH</name>
|
|
<description>Selects the number of bytes in data as follows:</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>8_BIT_DATA</name>
|
|
<description>8-bit data</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BIT_DATA</name>
|
|
<description>16-bit data</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, do not use this setting</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32_BIT_DATA</name>
|
|
<description>32-bit data</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MONO</name>
|
|
<description>When 1, data is of monaural format. When 0, the data is in stereo format.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>When 1, disables accesses on FIFOs, places the transmit channel in mute mode.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>When 1, asynchronously reset the transmit channel and FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WS_SEL</name>
|
|
<description>When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WS_HALFPERIOD</name>
|
|
<description>Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.</description>
|
|
<bitRange>[14:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFIFO</name>
|
|
<description>I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>I2STXFIFO</name>
|
|
<description>8 x 32-bit transmit FIFO.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXFIFO</name>
|
|
<description>I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>I2SRXFIFO</name>
|
|
<description>8 x 32-bit transmit FIFO.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATE</name>
|
|
<description>I2S Status Feedback Register. Contains status information about the I2S interface.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQ</name>
|
|
<description>This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMAREQ1</name>
|
|
<description>This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DMAREQ2</name>
|
|
<description>This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX_LEVEL</name>
|
|
<description>Reflects the current level of the Receive FIFO.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_LEVEL</name>
|
|
<description>Reflects the current level of the Transmit FIFO.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA1</name>
|
|
<description>I2S DMA Configuration Register 1. Contains control information for DMA request 1.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_DMA1_ENABLE</name>
|
|
<description>When 1, enables DMA1 for I2S receive.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_DMA1_ENABLE</name>
|
|
<description>When 1, enables DMA1 for I2S transmit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX_DEPTH_DMA1</name>
|
|
<description>Set the FIFO level that triggers a receive DMA request on DMA1.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_DEPTH_DMA1</name>
|
|
<description>Set the FIFO level that triggers a transmit DMA request on DMA1.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA2</name>
|
|
<description>I2S DMA Configuration Register 2. Contains control information for DMA request 2.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_DMA2_ENABLE</name>
|
|
<description>When 1, enables DMA1 for I2S receive.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_DMA2_ENABLE</name>
|
|
<description>When 1, enables DMA1 for I2S transmit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX_DEPTH_DMA2</name>
|
|
<description>Set the FIFO level that triggers a receive DMA request on DMA2.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_DEPTH_DMA2</name>
|
|
<description>Set the FIFO level that triggers a transmit DMA request on DMA2.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRQ</name>
|
|
<description>I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_IRQ_ENABLE</name>
|
|
<description>When 1, enables I2S receive interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_IRQ_ENABLE</name>
|
|
<description>When 1, enables I2S transmit interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RX_DEPTH_IRQ</name>
|
|
<description>Set the FIFO level on which to create an irq request.</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TX_DEPTH_IRQ</name>
|
|
<description>Set the FIFO level on which to create an irq request.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXRATE</name>
|
|
<description>I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Y_DIVIDER</name>
|
|
<description>I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>X_DIVIDER</name>
|
|
<description>I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXRATE</name>
|
|
<description>I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Y_DIVIDER</name>
|
|
<description>I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>X_DIVIDER</name>
|
|
<description>I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBITRATE</name>
|
|
<description>I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TX_BITRATE</name>
|
|
<description>I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXBITRATE</name>
|
|
<description>I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RX_BITRATE</name>
|
|
<description>I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXMODE</name>
|
|
<description>I2S Transmit mode control.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCLKSEL</name>
|
|
<description>Clock source selection for the transmit bit clock divider.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECT_THE_TX_FRACTI</name>
|
|
<description>Select the TX fractional rate divider clock output as the source</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_THE_RX_MCLK_S</name>
|
|
<description>Select the RX_MCLK signal as the TX_MCLK clock source</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX4PIN</name>
|
|
<description>Transmit 4-pin mode selection. When 1, enables 4-pin mode.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>TXMCENA</name>
|
|
<description>Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXMODE</name>
|
|
<description>I2S Receive mode control.</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXCLKSEL</name>
|
|
<description>Clock source selection for the receive bit clock divider.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECT_THE_RX_FRACTI</name>
|
|
<description>Select the RX fractional rate divider clock output as the source</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_THE_TX_MCLK_S</name>
|
|
<description>Select the TX_MCLK signal as the RX_MCLK clock source</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RX4PIN</name>
|
|
<description>Receive 4-pin mode selection. When 1, enables 4-pin mode.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXMCENA</name>
|
|
<description>Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2S0">
|
|
<name>I2S1</name>
|
|
<baseAddress>0x400A3000</baseAddress>
|
|
<interrupt>
|
|
<name>I2S1</name>
|
|
<value>29</value>
|
|
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>C_CAN1</name>
|
|
<description>C_CAN </description>
|
|
<groupName>C_CAN1</groupName>
|
|
<baseAddress>0x400A4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>C_CAN1</name>
|
|
<value>43</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CNTL</name>
|
|
<description>CAN control</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initialization</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INITIALIZATION_IS_ST</name>
|
|
<description>Initialization is started. On reset, software needs to initialize the CAN controller.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NORMAL_OPERATION_</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>Module interrupt enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_CAN_INTERRUPT</name>
|
|
<description>Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_CAN_INTERRUP</name>
|
|
<description>Disable CAN interrupts. The interrupt line is always HIGH.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIE</name>
|
|
<description>Status change interrupt enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_STATUS_CHANGE</name>
|
|
<description>Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_STATUS_CHANG</name>
|
|
<description>Disable status change interrupts. No status change interrupt will be generated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE_ERROR_INTERRU</name>
|
|
<description>Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE_ERROR_INTERR</name>
|
|
<description>Disable error interrupt. No error status interrupt will be generated.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Disable automatic retransmission</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Automatic retransmission disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Automatic retransmission of disturbed messages enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCE</name>
|
|
<description>Configuration change enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_CPU_HAS_WRITE_AC</name>
|
|
<description>The CPU has write access to the CANBT register while the INIT bit is one.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_CPU_HAS_NO_WRITE</name>
|
|
<description>The CPU has no write access to the bit timing register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEST</name>
|
|
<description>Test mode enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TEST_MODE_</name>
|
|
<description>Test mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NORMAL_OPERATION_</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>Status register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LEC</name>
|
|
<description>Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_ERROR_</name>
|
|
<description>No error.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STUFF_ERROR_MORE_TH</name>
|
|
<description>Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORM_ERROR_A_FIXED_</name>
|
|
<description>Form error: A fixed format part of a received frame has the wrong format.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACKERROR_THE_MESSAG</name>
|
|
<description>AckError: The message this CAN core transmitted was not acknowledged.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIT1ERROR_DURING_TH</name>
|
|
<description>Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BIT0ERROR_DURING_TH</name>
|
|
<description>Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed).</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CRCERROR_THE_CRC_CH</name>
|
|
<description>CRCError: The CRC checksum was incorrect in the message received.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNUSED_NO_CAN_BUS_E</name>
|
|
<description>Unused: No CAN bus event was detected (written by the CPU).</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOK</name>
|
|
<description>Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MSGTRANSFER</name>
|
|
<description>Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOMSGTRANSFER</name>
|
|
<description>Since this bit was reset by the CPU, no message has been successfully transmitted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXOK</name>
|
|
<description>Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MSGTRANSFER</name>
|
|
<description>Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOMSGTRANSFER</name>
|
|
<description>Since this bit was last reset by the CPU, no message has been successfully transmitted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPASS</name>
|
|
<description>Error passive</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PASSIVE</name>
|
|
<description>The CAN controller is in the error passive state as defined in the CAN 2.0 specification.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>The CAN controller is in the error active state.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EWARN</name>
|
|
<description>Warning status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>AT_LEAST_ONE_OF_THE_</name>
|
|
<description>At least one of the error counters in the EML has reached the error warning limit of 96.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOTH_ERROR_COUNTERS_</name>
|
|
<description>Both error counters are below the error warning limit of 96.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOFF</name>
|
|
<description>Busoff status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BUSOFF</name>
|
|
<description>The CAN controller is in busoff state.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOBUSOFF</name>
|
|
<description>The CAN module is not in busoff.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EC</name>
|
|
<description>Error counter</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEC_7_0</name>
|
|
<description>Transmit error counter Current value of the transmit error counter (maximum value 127)</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>REC_6_0</name>
|
|
<description>Receive error counter Current value of the receive error counter (maximum value 255).</description>
|
|
<bitRange>[14:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RP</name>
|
|
<description>Receive error passive</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PASSIVE</name>
|
|
<description>The receive counter has reached the error passive level as defined in the CAN2.0 specification.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BELOWPASSIVE</name>
|
|
<description>The receive counter is below the error passive level.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BT</name>
|
|
<description>Bit timing register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x2301</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRP</name>
|
|
<description>Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1]. Valid programmed values are 0x01 - 0x3F[1].</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SJW</name>
|
|
<description>(Re)synchronization jump width Valid programmed values are 0 to 3[1].</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSEG1</name>
|
|
<description>Time segment after the sample point Valid values are 0 to 7[1].</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TSEG2</name>
|
|
<description>Time segment before the sample point Valid values are 1 to 15[1].</description>
|
|
<bitRange>[14:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT</name>
|
|
<description>Interrupt register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTID15_0</name>
|
|
<description>0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEST</name>
|
|
<description>Test register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>tbd.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BASIC</name>
|
|
<description>Basic mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IF1_TX_if2_rx</name>
|
|
<description>IF1 registers used as TX buffer, IF2 registers used as RX buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BASIC_MODE_DISABLED_</name>
|
|
<description>Basic mode disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SILENT</name>
|
|
<description>Silent mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SILENT</name>
|
|
<description>The module is in silent mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NORMAL_OPERATION_</name>
|
|
<description>Normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBACK</name>
|
|
<description>Loop back mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Loop back mode is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Loop back mode is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TX1_0</name>
|
|
<description>Control of TD pins</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_AT_THE_TD_PIN_</name>
|
|
<description>Level at the TD pin is controlled by the CAN controller. This is the value at reset.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_SAMPLE_POINT_CAN</name>
|
|
<description>The sample point can be monitored at the TD pin.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TD_PIN_IS_DRIVEN_LOW</name>
|
|
<description>TD pin is driven LOW/dominant.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TD_PIN_IS_DRIVEN_HIG</name>
|
|
<description>TD pin is driven HIGH/recessive.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RX</name>
|
|
<description>Monitors the actual value of the RD Pin</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_CAN_BUS_IS_RECES</name>
|
|
<description>The CAN bus is recessive (RD = 1).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_CAN_BUS_IS_DOMIN</name>
|
|
<description>The CAN bus is dominant (RD = 0).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRPE</name>
|
|
<description>Baud rate prescaler extension register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BRPE</name>
|
|
<description>Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_CMDREQ</name>
|
|
<description>Message interface command request </description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MESSNUM</name>
|
|
<description>Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[14:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_CMDMSK_W</name>
|
|
<description>Message interface command mask (write direction)</description>
|
|
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA_B</name>
|
|
<description>Access data bytes 4-7</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSFER_DATA_BYTES_</name>
|
|
<description>Transfer data bytes 4-7 to message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_BYTES_4_7_UNCHA</name>
|
|
<description>data bytes 4-7 unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATA_A</name>
|
|
<description>Access data bytes 0-3</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSFER_DATA_BYTES_</name>
|
|
<description>Transfer data bytes 0-3 to message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_BYTES_0_3_UNCHA</name>
|
|
<description>data bytes 0-3 unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRQST</name>
|
|
<description>Access transmission request bit</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>REQUEST_A_TRANSMISSI</name>
|
|
<description>Request a transmission. Set the TXRQST bit IF1/2_MCTRL.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_TRANSMISSION_REQU</name>
|
|
<description>No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRINTPND</name>
|
|
<description>This bit is ignored in the write direction.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>Access control bits</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSFER_CONTROL_BIT</name>
|
|
<description>Transfer control bits to message object</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTROL_BITS_UNCHANG</name>
|
|
<description>Control bits unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARB</name>
|
|
<description>Access arbitration bits</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSFER_IDENTIFIER</name>
|
|
<description>Transfer Identifier, DIR, XTD, and MSGVAL bits to message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARBITRATION_BITS_UNC</name>
|
|
<description>Arbitration bits unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Access mask bits</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSFER_IDENTIFIER_</name>
|
|
<description>Transfer Identifier MASK + MDIR + MXTD to message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK_BITS_UNCHANGED_</name>
|
|
<description>Mask bits unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WR_RD</name>
|
|
<description>Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_CMDMSK_R</name>
|
|
<description>Message interface command mask (read direction)</description>
|
|
<alternateRegister>IF%s_CMDMSK_W</alternateRegister>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA_B</name>
|
|
<description>Access data bytes 4-7</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSFER_DATA_BYTES_</name>
|
|
<description>Transfer data bytes 4-7 to IFx message buffer register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_BYTES_4_7_UNCHA</name>
|
|
<description>data bytes 4-7 unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATA_A</name>
|
|
<description>Access data bytes 0-3</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSFER_DATA_BYTES_</name>
|
|
<description>Transfer data bytes 0-3 to IFx message buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DATA_BYTES_0_3_UNCHA</name>
|
|
<description>data bytes 0-3 unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEWDAT</name>
|
|
<description>Access new data bit</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_NEWDAT_BIT_IN_</name>
|
|
<description>Clear NEWDAT bit in the message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NEWDAT_BIT_REMAINS_U</name>
|
|
<description>NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLRINTPND</name>
|
|
<description>Clear interrupt pending bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLEAR_INTPND_BIT_IN_</name>
|
|
<description>Clear INTPND bit in the message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INTPND_BIT_REMAINS_U</name>
|
|
<description>INTPND bit remains unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTRL</name>
|
|
<description>Access control bits</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSFER_CONTROL_BIT</name>
|
|
<description>Transfer control bits to IFx message buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONTROL_BITS_UNCHANG</name>
|
|
<description>Control bits unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ARB</name>
|
|
<description>Access arbitration bits</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSFER_IDENTIFIER</name>
|
|
<description>Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ARBITRATION_BITS_UNC</name>
|
|
<description>Arbitration bits unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Access mask bits</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRANSFER_IDENTIFIER_</name>
|
|
<description>Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK_BITS_UNCHANGED_</name>
|
|
<description>Mask bits unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WR_RD</name>
|
|
<description>Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_MSK1</name>
|
|
<description>Message interface mask 1</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSK15_0</name>
|
|
<description>Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_MSK2</name>
|
|
<description>Message interface 1 mask 2</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSK28_16</name>
|
|
<description>Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering.</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>MDIR</name>
|
|
<description>Mask message direction</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_MESSAGE_DIRECTIO</name>
|
|
<description>The message direction bit (DIR) is used for acceptance filtering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_MESSAGE_DIRECTIO</name>
|
|
<description>The message direction bit (DIR) has no effect on acceptance filtering.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MXTD</name>
|
|
<description>Mask extend identifier</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_EXTENDED_IDENTIF</name>
|
|
<description>The extended identifier bit (IDE) is used for acceptance filtering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_EXTENDED_IDENTIF</name>
|
|
<description>The extended identifier bit (IDE) has no effect on acceptance filtering.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_ARB1</name>
|
|
<description>Message interface 1 arbitration 1</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID15_0</name>
|
|
<description>Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_ARB2</name>
|
|
<description>Message interface 1 arbitration 2</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ID28_16</name>
|
|
<description>Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame)</description>
|
|
<bitRange>[12:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Message direction</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DIRECTION_EQ_TRANSMIT</name>
|
|
<description>Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIRECTION_EQ_RECEIVE_</name>
|
|
<description>Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>XTD</name>
|
|
<description>Extend identifier</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_29_BIT_EXTENDED_</name>
|
|
<description>The 29-bit extended identifier will be used for this message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_11_BIT_STANDARD_</name>
|
|
<description>The 11-bit standard identifier will be used for this message object.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSGVAL</name>
|
|
<description>Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_MESSAGE_OBJECT_I</name>
|
|
<description>The message object is configured and should be considered by the message handler.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_MESSAGE_OBJECT_I</name>
|
|
<description>The message object is ignored by the message handler.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_MCTRL</name>
|
|
<description>Message interface 1 message control</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLC3_0</name>
|
|
<description>Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EOB</name>
|
|
<description>End of buffer</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SINGLE_MESSAGE_OBJEC</name>
|
|
<description>Single message object or last message object of a FIFO buffer.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MESSAGE_OBJECT_BELON</name>
|
|
<description>Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRQST</name>
|
|
<description>Transmit request</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>REQUEST</name>
|
|
<description>The transmission of this message object is requested and is not yet done</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WAIT</name>
|
|
<description>This message object is not waiting for transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RMTEN</name>
|
|
<description>Remote enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TXRQSTSET</name>
|
|
<description>At the reception of a remote frame, TXRQST is set.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>At the reception of a remote frame, TXRQST is left unchanged.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIE</name>
|
|
<description>Receive interrupt enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTPNDSET</name>
|
|
<description>INTPND will be set after successful reception of a frame.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>INTPND will be left unchanged after successful reception of a frame.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXIE</name>
|
|
<description>Transmit interrupt enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTPNDSET</name>
|
|
<description>INTPND will be set after a successful reception of a frame.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UNCHANGED</name>
|
|
<description>The INTPND bit will be left unchanged after a successful reception of a frame.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UMASK</name>
|
|
<description>Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>USE_MASK</name>
|
|
<description>Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASK_IGNORED_</name>
|
|
<description>Mask ignored.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTPND</name>
|
|
<description>Interrupt pending</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTSOURCE</name>
|
|
<description>This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NOINTSOURCE</name>
|
|
<description>This message object is not the source of an interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSGLST</name>
|
|
<description>Message lost (only valid for message objects in the direction receive).</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_MESSAGE_HANDLER_</name>
|
|
<description>The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_MESSAGE_LOST_SINC</name>
|
|
<description>No message lost since this bit was reset last by the CPU.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEWDAT</name>
|
|
<description>New data</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_MESSAGE_HANDLER_</name>
|
|
<description>The message handler or the CPU has written new data into the data portion of this message object.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_NEW_DATA_HAS_BEEN</name>
|
|
<description>No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_DA1</name>
|
|
<description>Message interface data A1</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA0</name>
|
|
<description>Data byte 0</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA1</name>
|
|
<description>Data byte 1</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_DA2</name>
|
|
<description>Message interface 1 data A2</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA2</name>
|
|
<description>Data byte 2</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA3</name>
|
|
<description>Data byte 3</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_DB1</name>
|
|
<description>Message interface 1 data B1</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA4</name>
|
|
<description>Data byte 4</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA5</name>
|
|
<description>Data byte 5</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x60</dimIncrement>
|
|
<dimIndex>1-2</dimIndex>
|
|
<name>IF%s_DB2</name>
|
|
<description>Message interface 1 data B2</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA6</name>
|
|
<description>Data byte 6</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA7</name>
|
|
<description>Data byte 7</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXREQ1</name>
|
|
<description>Transmission request 1</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXRQST16_1</name>
|
|
<description>Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXREQ2</name>
|
|
<description>Transmission request 2</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXRQST32_17</name>
|
|
<description>Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ND1</name>
|
|
<description>New data 1</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NEWDAT16_1</name>
|
|
<description>New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ND2</name>
|
|
<description>New data 2</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NEWDAT32_17</name>
|
|
<description>New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IR1</name>
|
|
<description>Interrupt pending 1</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTPND16_1</name>
|
|
<description>Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IR2</name>
|
|
<description>Interrupt pending 2</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTPND32_17</name>
|
|
<description>Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSGV1</name>
|
|
<description>Message valid 1</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSGVAL16_1</name>
|
|
<description>Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSGV2</name>
|
|
<description>Message valid 2</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSGVAL32_17</name>
|
|
<description>Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKDIV</name>
|
|
<description>CAN clock divider register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKDIVVAL</name>
|
|
<description>
|
|
Clock divider value
|
|
CAN_CLK = PCLK/(CLKDIVVAL +1)
|
|
|
|
0000: CAN_CLK = PCLK divided by 1.
|
|
0001: CAN_CLK = PCLK divided by 2.
|
|
0010: CAN_CLK = PCLK divided by 3.
|
|
0011: CAN_CLK = PCLK divided by 4.
|
|
0100: CAN_CLK = PCLK divided by 5.
|
|
...
|
|
1111: CAN_CLK = PCLK divided by 16.
|
|
|
|
</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RITIMER</name>
|
|
<description>Repetitive Interrupt Timer (RIT) </description>
|
|
<groupName>RITIMER</groupName>
|
|
<baseAddress>0x400C0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RITIMER</name>
|
|
<value>11</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>COMPVAL</name>
|
|
<description>Compare register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RICOMP</name>
|
|
<description>Compare register. Holds the compare value which is compared to the counter.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK</name>
|
|
<description>Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RIMASK</name>
|
|
<description>Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control register.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xC</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RITINT</name>
|
|
<description>Interrupt flag</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THIS_BIT_IS_SET_TO_1</name>
|
|
<description>This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_COUNTER_VALUE_DO</name>
|
|
<description>The counter value does not equal the masked compare value.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RITENCLR</name>
|
|
<description>Timer enable clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_WILL_BE_CL</name>
|
|
<description>The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_WILL_NOT_B</name>
|
|
<description>The timer will not be cleared to 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RITENBR</name>
|
|
<description>Timer enable for debug</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_TIMER_IS_HALTED_</name>
|
|
<description>The timer is halted when the processor is halted for debugging.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEBUG_HAS_NO_EFFECT_</name>
|
|
<description>Debug has no effect on the timer operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RITEN</name>
|
|
<description>Timer enable.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER_ENABLED_THIS_</name>
|
|
<description>Timer enabled. This can be overruled by a debug halt if enabled in bit 2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_DISABLED_</name>
|
|
<description>Timer disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COUNTER</name>
|
|
<description>32-bit counter</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RICOUNTER</name>
|
|
<description>32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>QEI</name>
|
|
<description>Quadrature Encoder Interface (QEI) </description>
|
|
<groupName>QEI</groupName>
|
|
<baseAddress>0x400C6000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>QEI</name>
|
|
<value>52</value>
|
|
</interrupt>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CON</name>
|
|
<description>Control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESP</name>
|
|
<description>Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESPI</name>
|
|
<description>Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESV</name>
|
|
<description>Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESI</name>
|
|
<description>Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Configuration register</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000F0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIRINV</name>
|
|
<description>Direction invert. When = 1, complements the DIR bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIGMODE</name>
|
|
<description>Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPMODE</name>
|
|
<description>Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INVINX</name>
|
|
<description>Invert Index. When set, inverts the sense of the index input.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRESPI</name>
|
|
<description>Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[15:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INXGATE</name>
|
|
<description>Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block.</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:20]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>Encoder status register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 516.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POS</name>
|
|
<description>Position register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POS</name>
|
|
<description>Current position value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAXPOS</name>
|
|
<description>Maximum position register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAXPOS</name>
|
|
<description>Maximum position value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPOS0</name>
|
|
<description>position compare register 0</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCMP0</name>
|
|
<description>Position compare value 0.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPOS1</name>
|
|
<description>position compare register 1</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCMP1</name>
|
|
<description>Position compare value 1.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPOS2</name>
|
|
<description>position compare register 2</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCMP2</name>
|
|
<description>Position compare value 2.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INXCNT</name>
|
|
<description>Index count register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENCPOS</name>
|
|
<description>Current encoder position value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INXCMP0</name>
|
|
<description>Index compare register 0</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICMP0</name>
|
|
<description>Index compare value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOAD</name>
|
|
<description>Velocity timer reload register</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELLOAD</name>
|
|
<description>Current velocity timer load value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIME</name>
|
|
<description>Velocity timer register</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELVAL</name>
|
|
<description>Current velocity timer value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VEL</name>
|
|
<description>Velocity counter register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELPC</name>
|
|
<description>Current velocity pulse count.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP</name>
|
|
<description>Velocity capture register</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELCAP</name>
|
|
<description>Velocity capture value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VELCOMP</name>
|
|
<description>Velocity compare register</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VELCMP</name>
|
|
<description>Velocity compare value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTERPHA</name>
|
|
<description>Digital filter register on input phase A (QEI_A)</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILTA</name>
|
|
<description>Digital filter sampling delay</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTERPHB</name>
|
|
<description>Digital filter register on input phase B (QEI_B)</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILTB</name>
|
|
<description>Digital filter sampling delay</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTERINX</name>
|
|
<description>Digital filter register on input index (QEI_IDX)</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FITLINX</name>
|
|
<description>Digital filter sampling delay</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WINDOW</name>
|
|
<description>Index acceptance window register</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINDOW</name>
|
|
<description>Index acceptance window width</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INXCMP1</name>
|
|
<description>Index compare register 1</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICMP1</name>
|
|
<description>Index compare value 1.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INXCMP2</name>
|
|
<description>Index compare register 2</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ICMP2</name>
|
|
<description>Index compare value 2.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEC</name>
|
|
<description>Interrupt enable clear register</description>
|
|
<addressOffset>0xFD8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_EN</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_EN</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_EN</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_EN</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_EN</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_EN</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_Int</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_Int</name>
|
|
<description>Indicates that the position 1compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_Int</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV_Int</name>
|
|
<description>Indicates that the index compare value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_Int</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_Int</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_Int</name>
|
|
<description>Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_Int</name>
|
|
<description>Indicates that the index 1 compare value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_Int</name>
|
|
<description>Indicates that the index 2 compare value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_Int</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IES</name>
|
|
<description>Interrupt enable set register</description>
|
|
<addressOffset>0xFDC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_EN</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_EN</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_EN</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_EN</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_EN</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_EN</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_Int</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_Int</name>
|
|
<description>Indicates that the position 1compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_Int</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV_Int</name>
|
|
<description>Indicates that the index compare value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_Int</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_Int</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_Int</name>
|
|
<description>Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_Int</name>
|
|
<description>Indicates that the index 1 compare value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_Int</name>
|
|
<description>Indicates that the index 2 compare value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_Int</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTSTAT</name>
|
|
<description>Interrupt status register</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_Int</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_Int</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_Int</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_Int</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_Int</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_Int</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_Int</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_Int</name>
|
|
<description>Indicates that the position 1compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_Int</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV_Int</name>
|
|
<description>Indicates that the index compare value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_Int</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_Int</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_Int</name>
|
|
<description>Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_Int</name>
|
|
<description>Indicates that the index 1 compare value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_Int</name>
|
|
<description>Indicates that the index 2 compare value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_Int</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>Interrupt enable register</description>
|
|
<addressOffset>0xFE4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_Int</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_Int</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_Int</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_Int</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_Int</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_Int</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_Int</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_Int</name>
|
|
<description>Indicates that the position 1compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_Int</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV_Int</name>
|
|
<description>Indicates that the index compare value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_Int</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_Int</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_Int</name>
|
|
<description>Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_Int</name>
|
|
<description>Indicates that the index 1 compare value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_Int</name>
|
|
<description>Indicates that the index 2 compare value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_Int</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR</name>
|
|
<description>Interrupt status clear register</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_Int</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_Int</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_Int</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_Int</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_Int</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_Int</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_Int</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_Int</name>
|
|
<description>Indicates that the position 1compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_Int</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV_Int</name>
|
|
<description>Indicates that the index compare value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_Int</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_Int</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_Int</name>
|
|
<description>Indicates that the index 1 compare value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_Int</name>
|
|
<description>Indicates that the index 2 compare value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_Int</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET</name>
|
|
<description>Interrupt status set register</description>
|
|
<addressOffset>0xFEC</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INX_Int</name>
|
|
<description>Indicates that an index pulse was detected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIM_Int</name>
|
|
<description>Indicates that a velocity timer overflow occurred</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>VELC_Int</name>
|
|
<description>Indicates that captured velocity is less than compare velocity.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIR_Int</name>
|
|
<description>Indicates that a change of direction was detected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERR_Int</name>
|
|
<description>Indicates that an encoder phase error was detected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ENCLK_Int</name>
|
|
<description>Indicates that and encoder clock pulse was detected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0_Int</name>
|
|
<description>Indicates that the position 0 compare value is equal to the current position.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1_Int</name>
|
|
<description>Indicates that the position 1compare value is equal to the current position.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2_Int</name>
|
|
<description>Indicates that the position 2 compare value is equal to the current position.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV_Int</name>
|
|
<description>Indicates that the index compare value is equal to the current index count.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS0REV_Int</name>
|
|
<description>Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS1REV_Int</name>
|
|
<description>Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS2REV_Int</name>
|
|
<description>Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV1_Int</name>
|
|
<description>Indicates that the index 1 compare value is equal to the current index count.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>REV2_Int</name>
|
|
<description>Indicates that the index 2 compare value is equal to the current index count.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MAXPOS_Int</name>
|
|
<description>Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>GIMA</name>
|
|
<description>Global Input Multiplexer Array (GIMA)</description>
|
|
<groupName>GIMA</groupName>
|
|
<baseAddress>0x400C7000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CAP0_0_IN</name>
|
|
<description>Timer 0 CAP0_0 capture input multiplexer (GIMA output 0)</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_0</name>
|
|
<description>CTIN_0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO3</name>
|
|
<description>SGPIO3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_CAP0</name>
|
|
<description>T0_CAP0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP0_1_IN</name>
|
|
<description>Timer 0 CAP0_1 capture input multiplexer (GIMA output 1)</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_1</name>
|
|
<description>CTIN_1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2_TX_ACTIVE</name>
|
|
<description>USART2 TX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_CAP1</name>
|
|
<description>T0_CAP1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP0_2_IN</name>
|
|
<description>Timer 0 CAP0_2 capture input multiplexer (GIMA output 2)</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_2</name>
|
|
<description>CTIN_2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO3_DIV</name>
|
|
<description>SGPIO3_DIV</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_CAP2</name>
|
|
<description>T0_CAP2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP0_3_IN</name>
|
|
<description>Timer 0 CAP0_3 capture input multiplexer (GIMA output 3)</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTOUT_15_OR_T3_MAT3</name>
|
|
<description>CTOUT_15 or T3_MAT3</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_CAP3</name>
|
|
<description>T0_CAP3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT3</name>
|
|
<description>T3_MAT3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP1_0_IN</name>
|
|
<description>Timer 1 CAP1_0 capture input multiplexer (GIMA output 4)</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_0</name>
|
|
<description>CTIN_0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO12</name>
|
|
<description>SGPIO12</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_CAP0</name>
|
|
<description>T1_CAP0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP1_1_IN</name>
|
|
<description>Timer 1 CAP1_1 capture input multiplexer (GIMA output 5)</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_3</name>
|
|
<description>CTIN_3</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_TX_ACTIVE</name>
|
|
<description>USART0 TX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_CAP1</name>
|
|
<description>T1_CAP1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP1_2_IN</name>
|
|
<description>Timer 1 CAP1_2 capture input multiplexer (GIMA output 6)</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_4</name>
|
|
<description>CTIN_4</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_RX_ACTIVE</name>
|
|
<description>USART0 RX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_CAP2</name>
|
|
<description>T1_CAP2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP1_3_IN</name>
|
|
<description>Timer 1 CAP1_3 capture input multiplexer (GIMA output 7)</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTOUT_3_OR_T0_MAT3</name>
|
|
<description>CTOUT_3 or T0_MAT3</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_CAP3</name>
|
|
<description>T1_CAP3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_MAT3</name>
|
|
<description>T0_MAT3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP2_0_IN</name>
|
|
<description>Timer 2 CAP2_0 capture input multiplexer (GIMA output 8)</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x4 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_0</name>
|
|
<description>CTIN_0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO12_DIV</name>
|
|
<description>SGPIO12_DIV</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_CAP0</name>
|
|
<description>T2_CAP0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP2_1_IN</name>
|
|
<description>Timer 2 CAP2_1 capture input multiplexer (GIMA output 9)</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x4 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_1</name>
|
|
<description>CTIN_1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2_TX_ACTIVE</name>
|
|
<description>USART2 TX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>_I2S1_RX_MWS</name>
|
|
<description>- I2S1_RX_MWS</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_CAP1</name>
|
|
<description>T2_CAP1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP2_2_IN</name>
|
|
<description>Timer 2 CAP2_2 capture input multiplexer (GIMA output 10)</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x4 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_5</name>
|
|
<description>CTIN_5</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2_RX_ACTIVE</name>
|
|
<description>USART2 RX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>_I2S1_TX_MWS</name>
|
|
<description>- I2S1_TX_MWS</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_CAP2</name>
|
|
<description>T2_CAP2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP2_3_IN</name>
|
|
<description>Timer 2 CAP2_3 capture input multiplexer (GIMA output 11)</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTOUT_7_OR_T1_MAT3</name>
|
|
<description>CTOUT_7 or T1_MAT3</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_CAP3</name>
|
|
<description>T2_CAP3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_MAT3</name>
|
|
<description>T1_MAT3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP3_0_IN</name>
|
|
<description>Timer 3 CAP3_0 capture input multiplexer (GIMA output 12)</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_0</name>
|
|
<description>CTIN_0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_RX_MWS</name>
|
|
<description>I2S0_RX_MWS</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_CAP0</name>
|
|
<description>T3_CAP0</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP3_1_IN</name>
|
|
<description>Timer 3 CAP3_1 capture input multiplexer (GIMA output 13)</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x4 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_6</name>
|
|
<description>CTIN_6</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART3_TX_ACTIVE</name>
|
|
<description>USART3 TX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TBD__I2S0_TX_MWS</name>
|
|
<description>TBD - I2S0_TX_MWS</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_CAP1</name>
|
|
<description>T3_CAP1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP3_2_IN</name>
|
|
<description>Timer 3 CAP3_2 capture input multiplexer (GIMA output 14)</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x4 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_7</name>
|
|
<description>CTIN_7</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART3_RX_ACTIVE</name>
|
|
<description>USART3 RX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOF0_START_OF_FRAME</name>
|
|
<description>SOF0 (Start-Of-Frame USB0)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_CAP2</name>
|
|
<description>T3_CAP2</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAP3_3_IN</name>
|
|
<description>Timer 3 CAP3_3 capture input multiplexer (GIMA output 15)</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x4 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTOUT11_OR_T2_MAT3</name>
|
|
<description>CTOUT11 or T2_MAT3</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOF1_START_OF_FRAME</name>
|
|
<description>SOF1 (Start-Of-Frame USB1)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_CAP3</name>
|
|
<description>T3_CAP3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT3</name>
|
|
<description>T2_MAT3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIN_0_IN</name>
|
|
<description>SCT CTIN_0 capture input multiplexer (GIMA output 16)</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_0</name>
|
|
<description>CTIN_0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO3</name>
|
|
<description>SGPIO3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO3_DIV</name>
|
|
<description>SGPIO3_DIV</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIN_1_IN</name>
|
|
<description>SCT CTIN_1 capture input multiplexer (GIMA output 17)</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_1</name>
|
|
<description>CTIN_1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2_TX_ACTIVE</name>
|
|
<description>USART2 TX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO12</name>
|
|
<description>SGPIO12</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIN_2_IN</name>
|
|
<description>SCT CTIN_2 capture input multiplexer (GIMA output 18)</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_2</name>
|
|
<description>CTIN_2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO12</name>
|
|
<description>SGPIO12</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO12_DIV</name>
|
|
<description>SGPIO12_DIV</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIN_3_IN</name>
|
|
<description>SCT CTIN_3 capture input multiplexer (GIMA output 19)</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x4 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_3</name>
|
|
<description>CTIN_3</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_TX_ACTIVE</name>
|
|
<description>USART0 TX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIN_4_IN</name>
|
|
<description>SCT CTIN_4 capture input multiplexer (GIMA output 20)</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x4 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_4</name>
|
|
<description>CTIN_4</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART0_RX_ACTIVE</name>
|
|
<description>USART0 RX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>_I2S1_RX_MWS1</name>
|
|
<description>- I2S1_RX_MWS1</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>_I2S1_TX_MWS1</name>
|
|
<description>- I2S1_TX_MWS1</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIN_5_IN</name>
|
|
<description>SCT CTIN_5 capture input multiplexer (GIMA output 21)</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_5</name>
|
|
<description>CTIN_5</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART2_RX_ACTIVE</name>
|
|
<description>USART2 RX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO12_DIV</name>
|
|
<description>SGPIO12_DIV</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIN_6_IN</name>
|
|
<description>SCT CTIN_6 capture input multiplexer (GIMA output 22)</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x4 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_6</name>
|
|
<description>CTIN_6</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART3_TX_ACTIVE</name>
|
|
<description>USART3 TX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_RX_MWS</name>
|
|
<description>I2S0_RX_MWS</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2S0_TX_MWS</name>
|
|
<description>I2S0_TX_MWS</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTIN_7_IN</name>
|
|
<description>SCT CTIN_7 capture input multiplexer (GIMA output 23)</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x4 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTIN_7</name>
|
|
<description>CTIN_7</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USART3_RX_ACTIVE</name>
|
|
<description>USART3 RX active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOF0_START_OF_FRAME</name>
|
|
<description>SOF0 (Start-Of-Frame USB0)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SOF1_START_OF_FRAME</name>
|
|
<description>SOF1 (Start-Of-Frame USB1)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCHS_TRIGGER_IN</name>
|
|
<description>ADCHS trigger input multiplexer (GIMA output 24)</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0xA to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>GPIO6_28</name>
|
|
<description>GPIO6[28]</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO5_3</name>
|
|
<description>GPIO5[3]</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO10</name>
|
|
<description>SGPIO10</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO12</name>
|
|
<description>SGPIO12</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCOB2</name>
|
|
<description>MCOB2</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTOUT_0_OR_T0_MAT0</name>
|
|
<description>CTOUT_0 or T0_MAT0</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTOUT_8_OR_T2_MAT0</name>
|
|
<description>CTOUT_8 or T2_MAT0</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_MAT0</name>
|
|
<description>T0_MAT0</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT0</name>
|
|
<description>T2_MAT0</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVENTROUTER_13_IN</name>
|
|
<description>Event router input 13 multiplexer (GIMA output 25)</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CTOUT_2_OR_T0_MAT2</name>
|
|
<description>CTOUT_2 or T0_MAT2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO3</name>
|
|
<description>SGPIO3</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_MAT2</name>
|
|
<description>T0_MAT2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVENTROUTER_14_IN</name>
|
|
<description>Event router input 14 multiplexer (GIMA output 26)</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x3 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>CTOUT_6_OR_T1_MAT2</name>
|
|
<description>CTOUT_6 or T1_MAT2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO12</name>
|
|
<description>SGPIO12</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T1_MAT2</name>
|
|
<description>T1_MAT2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVENTROUTER_16_IN</name>
|
|
<description>Event router input 16 multiplexer (GIMA output 27)</description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x2 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>CTOUT_14_OR_T3_MAT2</name>
|
|
<description>CTOUT_14 or T3_MAT2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T3_MAT2</name>
|
|
<description>T3_MAT2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCSTART0_IN</name>
|
|
<description>ADC start0 input multiplexer (GIMA output 28)</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x2 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>CTOUT_15_OR_T3_MAT3</name>
|
|
<description>CTOUT_15 or T3_MAT3</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T0_MAT0</name>
|
|
<description>T0_MAT0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCSTART1_IN</name>
|
|
<description>ADC start1 input multiplexer (GIMA output 29)</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV</name>
|
|
<description>Invert input</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>NOT_INVERTED</name>
|
|
<description>Not inverted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_INVERTED</name>
|
|
<description>Input inverted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>Enable rising edge detection</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>NO_EDGE_DETECTION</name>
|
|
<description>No edge detection.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_DETECTIO</name>
|
|
<description>Rising edge detection enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCH</name>
|
|
<description>Enable synchronization</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE__SYNCHRONIZ</name>
|
|
<description>Disable synchronization.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE__SYNCHRONIZA</name>
|
|
<description>Enable synchronization.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_SINGLE_PULSE</name>
|
|
<description>Disable single pulse generation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_SINGLE_PULSE</name>
|
|
<description>Enable single pulse generation.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SELECT</name>
|
|
<description>Select input. Values 0x2 to 0xF are reserved.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>CTOUT_8_OR_T2_MAT0</name>
|
|
<description>CTOUT_8 or T2_MAT0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>T2_MAT0</name>
|
|
<description>T2_MAT0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
</registers>
|
|
|
|
|
|
</peripheral>
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>DAC</name>
|
|
<description>Digital-to-Analog Converter (DAC) </description>
|
|
<groupName>DAC</groupName>
|
|
<baseAddress>0x400E1000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DAC</name>
|
|
<value>0</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>DAC register. Holds the conversion data.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA.</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BIAS</name>
|
|
<description>Settling time</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SHORT</name>
|
|
<description>The settling time of the DAC is 1 micros max, and the maximum current is 700 microA.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LONG</name>
|
|
<description>The settling time of the DAC is 2.5 micros and the maximum current is 350 microA.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>DAC control register.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT_DMA_REQ</name>
|
|
<description>DMA request</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CLR</name>
|
|
<description>This bit is cleared on any write to the DACR register.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET</name>
|
|
<description>This bit is set by hardware when the timer times out.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBLBUF_ENA</name>
|
|
<description>DMA double-buffering</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>DACR double-buffering is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNT_ENA</name>
|
|
<description>DMA time-out</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Time-out counter operation is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Time-out counter operation is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMA_ENA</name>
|
|
<description>DMA enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>DMA access is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>DMA Burst Request Input 15 is enabled for the DAC (see Table 136).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTVAL</name>
|
|
<description>DAC counter value register.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>16-bit reload value for the DAC interrupt/DMA timer.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="C_CAN1">
|
|
<name>C_CAN0</name>
|
|
<baseAddress>0x400E2000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>C_CAN0</name>
|
|
<value>51</value>
|
|
</interrupt>
|
|
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>ADC0</name>
|
|
<description>10-bit Analog-to-Digital Converter (ADC) </description>
|
|
<groupName>ADC</groupName>
|
|
<baseAddress>0x400E3000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC0</name>
|
|
<value>17</value>
|
|
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>Burst mode</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SOFTWARE</name>
|
|
<description>Conversions are software controlled and require 11 clocks.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BURST</name>
|
|
<description>The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>11_CLOCKS_10_BITS</name>
|
|
<description>11 clocks / 10 bits</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10_CLOCKS_9_BITS</name>
|
|
<description>10 clocks / 9 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_CLOCKS_8_BITS</name>
|
|
<description>9 clocks / 8 bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_CLOCKS_7_BITS</name>
|
|
<description>8 clocks / 7 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_CLOCKS_6_BITS</name>
|
|
<description>7 clocks / 6 bits</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_CLOCKS_5_BITS</name>
|
|
<description>6 clocks / 5 bits</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_CLOCKS_4_BITS</name>
|
|
<description>5 clocks / 4 bits</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_CLOCKS_3_BITS</name>
|
|
<description>4 clocks / 3 bits</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PDN</name>
|
|
<description>Power mode</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERDOWN</name>
|
|
<description>The A/D converter is in Power-down mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUNNING</name>
|
|
<description>The A/D converter is operational.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_START</name>
|
|
<description>No start (this value should be used when clearing PDN to 0).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START_CONVERSION_NOW</name>
|
|
<description>Start conversion now.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTOUT_15</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CTOUT_8</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCTRIG0</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADCTRIG1</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MCOA2</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>This bit is significant only when the START field contains 0x2 -0x6. In these cases:</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Start conversion on a rising edge on the selected signal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Start conversion on a falling edge on the selected signal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GDR</name>
|
|
<description>A/D Global Data Register. Contains the result of the most recent A/D conversion.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. These bits always read as zeroes.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>V_VREF</name>
|
|
<description>When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA.</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. These bits always read as zeroes.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHN</name>
|
|
<description>These bits contain the channel from which the LS bits were converted.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. These bits always read as zeroes.</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADINTEN</name>
|
|
<description>These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADGINTEN</name>
|
|
<description>When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always 0.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x04</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>DR[%s]</name>
|
|
<description>A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always 0.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>V_VREF</name>
|
|
<description>When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA.</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always 0.</description>
|
|
<bitRange>[29:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>These bits mirror the DONE status flags that appear in the result register for each A/D channel.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERUN</name>
|
|
<description>These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADINT</name>
|
|
<description>This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Always 0.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ADC0">
|
|
<name>ADC1</name>
|
|
<baseAddress>0x400E4000</baseAddress>
|
|
<interrupt>
|
|
<name>ADC1</name>
|
|
<value>21</value>
|
|
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADCHS</name>
|
|
<description>12-bit Analog-to-Digital Converter High-Speed (ADCHS)</description>
|
|
<groupName>ADCHS</groupName>
|
|
<baseAddress>0x400F0000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADCHS</name>
|
|
<value>45</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FLUSH</name>
|
|
<description>Flushes FIFO</description>
|
|
<addressOffset>0x0000</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO_FLUSH</name>
|
|
<description>1= fifo is cleared</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_REQ</name>
|
|
<description>Set or clear DMA write request</description>
|
|
<addressOffset>0x0004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMA_REQ_WR</name>
|
|
<description>1 = Dma_req_wr is set (initially used to fill second table), 0 = Dma_req_wr is cleared</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO_STS</name>
|
|
<description>Indicates FIFO fill level status</description>
|
|
<addressOffset>0x0008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LEVEL</name>
|
|
<description>0 = FIFO is empty 1...15 = FIFO is partially full 16 = FIFO is full</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO_CFG</name>
|
|
<description>Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word.</description>
|
|
<addressOffset>0x000C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000010</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PACKED_READ</name>
|
|
<description>0 = one sample is packed in one 32-bit read cycle 1 = two samples are packed in one 32-bit read cycle</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>LEVEL</name>
|
|
<description>When the FIFO contains more or equal than FIFO_LEVEL samples interrupt flag FIFO_FULL interrupt will be set and DMA_Read_Req will be raised.</description>
|
|
<bitRange>[5:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRIGGER</name>
|
|
<description>Enable software trigger to start descriptor processing</description>
|
|
<addressOffset>0x0010</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW_TRIGGER</name>
|
|
<description>Auto cleared</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSCR_STS</name>
|
|
<description>Indicates active descriptor table and descriptor entry</description>
|
|
<addressOffset>0x0014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACT_TABLE</name>
|
|
<description>0 = table 0 is active 1 = table 1 is active.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ACT_DESCRIPTOR</name>
|
|
<description>ID of the descriptor that is active.</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POWER_DOWN</name>
|
|
<description>Set or clear power down mode</description>
|
|
<addressOffset>0x0018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PD_CTRL</name>
|
|
<description>0 = disable power down mode. Register holds value until set by writing 1 to this bit or by descriptor processor when descriptor field POWER_DOWN is set. 1 = enable power down mode. Register holds value until cleared by writing 0 to this bit or by descriptor processor when waking up RECOVERY_TIME before a conversion.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONFIG</name>
|
|
<description>Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down.</description>
|
|
<addressOffset>0x001C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00002400</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIGGER__MASK</name>
|
|
<description>00 = triggers off 01 = software trigger only 10 = external trigger only 11 = both triggers allowed</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRIGGER_MODE</name>
|
|
<description>00 = rising external trigger 01 = falling external trigger 10 = low external trigger 11 = high external trigger</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TRIGGER_SYNC</name>
|
|
<description>0 = do not synchronize external trigger input 1 = synchronize external trigger input</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHANNEL_ID_EN</name>
|
|
<description>0 = do not add channel ID to FIFO output data 1 = add channel ID to FIFO output data</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RECOVERY_TIME</name>
|
|
<description>ADC recovery time from power down</description>
|
|
<bitRange>[13:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR_A</name>
|
|
<description>Configures window comparator A levels.</description>
|
|
<addressOffset>0x0020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFF0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>THR_LOW_A</name>
|
|
<description>Low Compare Threshold Register A: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THR_HIGH_A</name>
|
|
<description>High Compare Threshold Register A: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A.</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR_B</name>
|
|
<description>Configures window comparator B levels.</description>
|
|
<addressOffset>0x0024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFF0000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>THR_LOW_B</name>
|
|
<description>Low Compare Threshold Register B: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THR_HIGH_B</name>
|
|
<description>High Compare Threshold Register B: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A.</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>6</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-5</dimIndex>
|
|
<name>LAST_SAMPLE[%s]</name>
|
|
<description>Contains last converted sample of input M [M=0..5) and result of window comparator.</description>
|
|
<addressOffset>0x0028</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read. This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_RANGE</name>
|
|
<description>Threshold Range Comparison result 00: In Range 01: Below Range 10: Above Range 11: Reserved</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_CROSS</name>
|
|
<description>Threshold Crossing Comparison result 00: No Threshold Crossing detected 01: Downward Threshold Crossing detected 10: Upward Threshold Crossing detected 11: Reserved</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>12-Bit value of last converted sample for this channel</description>
|
|
<bitRange>[17:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[20:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC_SPEED</name>
|
|
<description>ADC speed control</description>
|
|
<addressOffset>0x0104</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DGEC0</name>
|
|
<description>Speed0</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DGEC1</name>
|
|
<description>Speed1</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DGEC2</name>
|
|
<description>Speed2</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DGEC3</name>
|
|
<description>Speed3</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DGEC4</name>
|
|
<description>Speed4</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DGEC5</name>
|
|
<description>Speed5</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POWER_CONTROL</name>
|
|
<description>Configures ADC power vs. speed, DC-in biasing, output format and power gating.</description>
|
|
<addressOffset>0x0108</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CRS</name>
|
|
<description>current setting for power versus speed programming</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DCINNEG</name>
|
|
<description>AC-DC coupling selection 0 = No dc bias 1 = DC bias on vin_neg side</description>
|
|
<bitRange>[9:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DCINPOS</name>
|
|
<description>AC-DC coupling selection 0 = No dc bias 1 = DC bias on vin_pos side</description>
|
|
<bitRange>[15:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TWOS</name>
|
|
<description>Output data format selection 0 = offset binary 1 = two's complement</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POWER_SWITCH</name>
|
|
<description>0 = ADC is powered down 1 = ADC is active</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BGAP_SWITCH</name>
|
|
<description>0 = ADC band gap reference is powered down 1 = ADC band gap reference is active</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:19]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>FIFO_OUTPUT[%s]</name>
|
|
<description>FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples</description>
|
|
<addressOffset>0x0200</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00008000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Value of first converted sample</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHAN_ID</name>
|
|
<description>Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error</description>
|
|
<bitRange>[14:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMPTY</name>
|
|
<description>0: FIFO not empty 1: FIFO empty</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE2</name>
|
|
<description>Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0</description>
|
|
<bitRange>[27:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHAN_ID2</name>
|
|
<description>Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0</description>
|
|
<bitRange>[30:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>EMPTY2</name>
|
|
<description>0: FIFO not empty 1: FIFO empty and PACKED_READ is set</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>DESCRIPTOR0_[%s]</name>
|
|
<description>Table 0 descriptor n, n= 0 to 7</description>
|
|
<addressOffset>0x0300</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000090E0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL_NR</name>
|
|
<description>0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HALT</name>
|
|
<description>0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRUPT</name>
|
|
<description>1: Raise interrupt when ADC result is available</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POWER_DOWN</name>
|
|
<description>1: Power down after this conversion.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BRANCH</name>
|
|
<description>00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top).</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MATCH_VALUE</name>
|
|
<description>Evaluate this descriptor when descriptor timer value is equal to match value.</description>
|
|
<bitRange>[21:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THRESHOLD_SEL</name>
|
|
<description>Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESET_TIMER</name>
|
|
<description>1: reset descriptor timer.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[30:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UPDATE_TABLE</name>
|
|
<description>1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>DESCRIPTOR1_[%s]</name>
|
|
<description>Table 1 descriptors n, n=0 to 7</description>
|
|
<addressOffset>0x0320</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000090E0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL_NR</name>
|
|
<description>0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>HALT</name>
|
|
<description>0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>INTERRUPT</name>
|
|
<description>1: Raise interrupt when ADC result is available</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POWER_DOWN</name>
|
|
<description>1: Power down after this conversion.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BRANCH</name>
|
|
<description>00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top).</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MATCH_VALUE</name>
|
|
<description>Evaluate this descriptor when descriptor timer value is equal to match value.</description>
|
|
<bitRange>[21:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THRESHOLD_SEL</name>
|
|
<description>Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved</description>
|
|
<bitRange>[23:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESET_TIMER</name>
|
|
<description>1: reset descriptor timer.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[30:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UPDATE_TABLE</name>
|
|
<description>1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_EN0</name>
|
|
<description>Interrupt 0 clear mask</description>
|
|
<addressOffset>0x0F00</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN0</name>
|
|
<description>Interrupt clear enable</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_EN0</name>
|
|
<description>Interrupt 0 set mask</description>
|
|
<addressOffset>0x0F04</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEN0</name>
|
|
<description>Interrupt set enable</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK0</name>
|
|
<description>Interrupt 0 mask</description>
|
|
<addressOffset>0x0F08</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M0</name>
|
|
<description>Interrupt enable</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS0</name>
|
|
<description>Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow</description>
|
|
<addressOffset>0x0F0C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFO_FULL</name>
|
|
<description>0: number of samples in FIFO less than or equal to FIFO_LEVEL 1: number of samples in FIFO is more than FIFO_LEVEL</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_EMPTY</name>
|
|
<description>0: FIFO is not empty 1: FIFO is empty</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FIFO_OVERFLOW</name>
|
|
<description>FIFO was full; conversion sample is not stored and lost</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DSCR_DONE</name>
|
|
<description>The descriptor INTERRUPT field was enabled and its sample is converted.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DSCR_ERROR</name>
|
|
<description>The ADC was not fully woken up when a sample was converted and the conversion results is unreliable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_OVF</name>
|
|
<description>Converted sample value was over range of the 12 bit output code.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_UNF</name>
|
|
<description>Converted sample value was under range of the 12 bit output code.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_STAT0</name>
|
|
<description>Interrupt 0 clear status</description>
|
|
<addressOffset>0x0F10</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSTAT0</name>
|
|
<description>Interrupt clear status</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_STAT0</name>
|
|
<description>Interrupt 0 set status</description>
|
|
<addressOffset>0x0F14</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSTAT0</name>
|
|
<description>Interrupt set status</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_EN1</name>
|
|
<description>Interrupt 1 mask clear enable.</description>
|
|
<addressOffset>0x0F20</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN1</name>
|
|
<description>Interrupt clear enable</description>
|
|
<bitRange>[29:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_EN1</name>
|
|
<description>Interrupt 1 mask set enable</description>
|
|
<addressOffset>0x0F24</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEN1</name>
|
|
<description>Interrupt set enable</description>
|
|
<bitRange>[29:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK1</name>
|
|
<description>Interrupt 1 mask</description>
|
|
<addressOffset>0x0F28</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M1</name>
|
|
<description>Interrupt enable</description>
|
|
<bitRange>[29:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS1</name>
|
|
<description>Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun.</description>
|
|
<addressOffset>0x0F2C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>THCMP_BRANGE0</name>
|
|
<description>Input channel 0 result below range</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_ARANGE0</name>
|
|
<description>Input channel 0 result above range</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_DCROSS0</name>
|
|
<description>Input channel 0 result downward threshold crossing detected</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_UCROSS0</name>
|
|
<description>Input channel 0 result upward threshold crossing detected</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN_0</name>
|
|
<description>A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [0] before it has been read</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_BRANGE1</name>
|
|
<description>Input channel 1 result below range</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_ARANGE1</name>
|
|
<description>Input channel 1 result above range</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_DCROSS1</name>
|
|
<description>Input channel 1 result downward threshold crossing detected</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_UCROSS1</name>
|
|
<description>Input channel 1 result upward threshold crossing detected</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN_1</name>
|
|
<description>A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [1] before it has been read</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_BRANGE2</name>
|
|
<description>Input channel 2 result below range</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_ARANGE2</name>
|
|
<description>Input channel 2 result above range</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_DCROSS2</name>
|
|
<description>Input channel 2 result downward threshold crossing detected</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_UCROSS2</name>
|
|
<description>Input channel 2 result upward threshold crossing detected</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN_2</name>
|
|
<description>A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [2] before it has been read</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_BRANGE3</name>
|
|
<description>Input channel 3 result below range</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_ARANGE3</name>
|
|
<description>Input channel 3 result above range</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_DCROSS3</name>
|
|
<description>Input channel 3 result downward threshold crossing detected</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_UCROSS3</name>
|
|
<description>Input channel 3 result upward threshold crossing detected</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN_3</name>
|
|
<description>A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [3] before it has been read</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_BRANGE4</name>
|
|
<description>Input channel 4 result below range</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_ARANGE4</name>
|
|
<description>Input channel 4 result above range</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_DCROSS4</name>
|
|
<description>Input channel 4 result downward threshold crossing detected</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_UCROSS4</name>
|
|
<description>Input channel 4 result upward threshold crossing detected</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN_4</name>
|
|
<description>A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [4] before it has been read</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_BRANGE5</name>
|
|
<description>Input channel 5 result below range</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_ARANGE5</name>
|
|
<description>Input channel 5 result above range</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_DCROSS5</name>
|
|
<description>Input channel 5 result downward threshold crossing detected</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>THCMP_UCROSS5</name>
|
|
<description>Input channel 5 result upward threshold crossing detected</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN_5</name>
|
|
<description>A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [5] before it has been read</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_STAT1</name>
|
|
<description>Interrupt 1 clear status</description>
|
|
<addressOffset>0x0F30</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CSTAT1</name>
|
|
<description>Interrupt clear status</description>
|
|
<bitRange>[29:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_STAT1</name>
|
|
<description>Interrupt 1 set status</description>
|
|
<addressOffset>0x0F34</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSTAT1</name>
|
|
<description>Interrupt set status</description>
|
|
<bitRange>[29:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:30]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
|
|
|
|
</peripheral>
|
|
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>GPIO_PORT</name>
|
|
<description>GPIO port </description>
|
|
<groupName>GPIO_PORT</groupName>
|
|
<baseAddress>0x400F4000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFfFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>256</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>0-255</dimIndex>
|
|
<name>B[%s]</name>
|
|
<description>Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31</description>
|
|
<addressOffset>0x0000</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PBYTE</name>
|
|
<description>Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<dim>256</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-255</dimIndex>
|
|
<name>W[%s]</name>
|
|
<description>Word pin registers port 0 to 5</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWORD</name>
|
|
<description>Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>DIR%s</name>
|
|
<description>Direction registers port m</description>
|
|
<addressOffset>0x2000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIRP0</name>
|
|
<description>Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP1</name>
|
|
<description>Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP2</name>
|
|
<description>Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP3</name>
|
|
<description>Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP4</name>
|
|
<description>Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP5</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP6</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP7</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP8</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP9</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP10</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP11</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP12</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP13</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP14</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP15</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP16</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP17</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP18</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP19</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP20</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP21</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP22</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP23</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP24</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP25</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP26</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP27</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP28</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP29</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP30</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DIRP31</name>
|
|
<description>Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>MASK%s</name>
|
|
<description>Mask register port m</description>
|
|
<addressOffset>0x2080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASKP0</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP1</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP2</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP3</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP4</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP5</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP6</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP7</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP8</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP9</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP10</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP11</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP12</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP13</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP14</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP15</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP16</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP17</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP18</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP19</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP20</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP21</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP22</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP23</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP24</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP25</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP26</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP27</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP28</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP29</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP30</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASKP31</name>
|
|
<description>Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>PIN%s</name>
|
|
<description>Port pin register port m</description>
|
|
<addressOffset>0x2100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PORT0</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT1</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT2</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT3</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT4</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT5</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT6</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT7</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT8</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT9</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT10</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT11</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT12</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT13</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT14</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT15</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT16</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT17</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT18</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT19</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT20</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT21</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT22</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT23</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT24</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT25</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT26</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT27</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT28</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT29</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT30</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PORT31</name>
|
|
<description>Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>MPIN%s</name>
|
|
<description>Masked port register port m</description>
|
|
<addressOffset>0x2180</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPORTP0</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP1</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP2</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP3</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP4</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP5</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP6</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP7</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP8</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP9</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP10</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP11</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP12</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP13</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP14</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP15</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP16</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP17</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP18</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP19</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP20</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP21</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP22</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP23</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP24</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP25</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP26</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP27</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP28</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP29</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP30</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MPORTP31</name>
|
|
<description>Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>SET%s</name>
|
|
<description>Write: Set register for port m Read: output bits for port m</description>
|
|
<addressOffset>0x2200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SETP0</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP1</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP2</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP3</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP4</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP5</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP6</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP7</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP8</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP9</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP10</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP11</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP12</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP13</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP14</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP15</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP16</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP17</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP18</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP19</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP20</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP21</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP22</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP23</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP24</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP25</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP26</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP27</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP28</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP29</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP30</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SETP31</name>
|
|
<description>Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>CLR%s</name>
|
|
<description>Clear port m</description>
|
|
<addressOffset>0x2280</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLRP00</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP01</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP02</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP03</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP04</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP05</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP06</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP07</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP08</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP09</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP010</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP011</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP012</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP013</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP014</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP015</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP016</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP017</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP018</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP019</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP020</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP021</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP022</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP023</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP024</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP025</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP026</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP027</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP028</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP029</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP030</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLRP031</name>
|
|
<description>Clear output bits: 0 = No operation. 1 = Clear output bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>NOT%s</name>
|
|
<description>Toggle port m</description>
|
|
<addressOffset>0x2300</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NOTP0</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP1</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP2</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP3</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP4</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP5</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP6</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP7</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP8</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP9</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP10</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP11</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP12</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP13</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP14</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP15</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP16</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP17</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP18</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP19</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP20</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP21</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP22</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP23</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP24</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP25</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP26</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP27</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP28</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP29</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP30</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NOTP31</name>
|
|
<description>Toggle output bits: 0 = no operation. 1 = Toggle output bit.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI</name>
|
|
<description>SPI </description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0x40100000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI_INT</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>SPI Control Register. This register controls the operation of the SPI.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BITENABLE</name>
|
|
<description>The SPI controller sends and receives 8 bits of data per transfer.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>THE_SPI_CONTROLLER_S</name>
|
|
<description>The SPI controller sends and receives the number of bits selected by bits 11:8.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FIRST_EDGE</name>
|
|
<description>Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SECOND_EDGE</name>
|
|
<description>Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock polarity control.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SCK_IS_ACTIVE_HIGH_</name>
|
|
<description>SCK is active high.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SCK_IS_ACTIVE_LOW_</name>
|
|
<description>SCK is active low.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>Master mode select.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLAVE</name>
|
|
<description>The SPI operates in Slave mode.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MASTER</name>
|
|
<description>The SPI operates in Master mode.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSBF</name>
|
|
<description>LSB First controls which direction each byte is shifted when transferred.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MSB</name>
|
|
<description>SPI data is transferred MSB (bit 7) first.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LSB</name>
|
|
<description>SPI data is transferred LSB (bit 0) first.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPIE</name>
|
|
<description>Serial peripheral interrupt enable.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTBLOCK</name>
|
|
<description>SPI interrupts are inhibited.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HWINT</name>
|
|
<description>A hardware interrupt is generated each time the SPIF or MODF bits are activated.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BITS</name>
|
|
<description>When bit 2 of this register is 1, this field controls the number of bits per transfer:</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>8_BITS_PER_TRANSFER</name>
|
|
<description>8 bits per transfer</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BITS_PER_TRANSFER</name>
|
|
<description>9 bits per transfer</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10_BITS_PER_TRANSFER</name>
|
|
<description>10 bits per transfer</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11_BITS_PER_TRANSFER</name>
|
|
<description>11 bits per transfer</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12_BITS_PER_TRANSFER</name>
|
|
<description>12 bits per transfer</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>13_BITS_PER_TRANSFER</name>
|
|
<description>13 bits per transfer</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>14_BITS_PER_TRANSFER</name>
|
|
<description>14 bits per transfer</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>15_BITS_PER_TRANSFER</name>
|
|
<description>15 bits per transfer</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BITS_PER_TRANSFER</name>
|
|
<description>16 bits per transfer</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>SPI Status Register. This register shows the status of the SPI.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABRT</name>
|
|
<description>Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROVR</name>
|
|
<description>Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WCOL</name>
|
|
<description>Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPIF</name>
|
|
<description>SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATALOW</name>
|
|
<description>SPI Bi-directional data port.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATAHIGH</name>
|
|
<description>If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>SPI Clock Counter Register. This register controls the frequency of a master's SCK0.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNTER</name>
|
|
<description>SPI0 Clock counter setting.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>SPI Test Control register. For functional testing only.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TEST</name>
|
|
<description>SPI test mode. When 0, the SPI operates normally. When 1, SCK will always be on, independent of master mode select and data availability setting.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSR</name>
|
|
<description>SPI Test Status register. For functional testing only.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ABRT</name>
|
|
<description>Slave abort.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>Mode fault.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ROVR</name>
|
|
<description>Read overrun.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>WCOL</name>
|
|
<description>Write collision.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SPIF</name>
|
|
<description>SPI transfer complete flag.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT</name>
|
|
<description>SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SPIF</name>
|
|
<description>SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>SGPIO</name>
|
|
<description>Serial GPIO (SGPIO)</description>
|
|
<groupName>SGPIO</groupName>
|
|
<baseAddress>0x40101000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SGPIO_IINT</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>OUT_MUX_CFG[%s]</name>
|
|
<description>Pin multiplexer configuration registers.</description>
|
|
<addressOffset>0x0000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>P_OUT_CFG</name>
|
|
<description>Output control of output SGPIOn. All other values are reserved.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DOUT_DOUTM1</name>
|
|
<description>dout_doutm1 (1-bit mode)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_DOUTM2A</name>
|
|
<description>dout_doutm2a (2-bit mode 2a)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_DOUTM2B</name>
|
|
<description>dout_doutm2b (2-bit mode 2b)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_DOUTM2C</name>
|
|
<description>dout_doutm2c (2-bit mode 2c)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>GPIO_OUT_LEVEL_SET</name>
|
|
<description>gpio_out (level set by GPIO_OUTREG)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_DOUTM4A</name>
|
|
<description>dout_doutm4a (4-bit mode 4a)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_DOUTM4B</name>
|
|
<description>dout_doutm4b (4-bit mode 4b)</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_DOUTM4C</name>
|
|
<description>dout_doutm4c (4-bit mode 4c)</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLK_OUT</name>
|
|
<description>clk_out</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_DOUTM8A</name>
|
|
<description>dout_doutm8a (8-bit mode 8a)</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_DOUTM8B</name>
|
|
<description>dout_doutm8b (8-bit mode 8b)</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_DOUTM8C</name>
|
|
<description>dout_doutm8c (8-bit mode 8c)</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>P_OE_CFG</name>
|
|
<description>Output enable source. All other values are reserved.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>GPIO_OE_STATE_SET_B</name>
|
|
<description>gpio_oe (state set by GPIO_OEREG)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_OEM1_1_BIT_MOD</name>
|
|
<description>dout_oem1 (1-bit mode)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_OEM2_2_BIT_MOD</name>
|
|
<description>dout_oem2 (2-bit mode)</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_OEM4_4_BIT_MOD</name>
|
|
<description>dout_oem4 (4-bit mode)</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DOUT_OEM8_8_BIT_MOD</name>
|
|
<description>dout_oem8 (8-bit mode)</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>SGPIO_MUX_CFG[%s]</name>
|
|
<description>SGPIO multiplexer configuration registers.</description>
|
|
<addressOffset>0x0040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EXT_CLK_ENABLE</name>
|
|
<description>Select clock signal.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INTERNAL_CLOCK_SIGNA</name>
|
|
<description>Internal clock signal (slice)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTERNAL_CLOCK_SIGNA</name>
|
|
<description>External clock signal (pin)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLK_SOURCE_PIN_MODE</name>
|
|
<description>Select source clock pin.</description>
|
|
<bitRange>[2:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SGPIO8</name>
|
|
<description>SGPIO8</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO9</name>
|
|
<description>SGPIO9</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO10</name>
|
|
<description>SGPIO10</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO11</name>
|
|
<description>SGPIO11</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLK_SOURCE_SLICE_MODE</name>
|
|
<description>Select clock source slice. Note that slices D, H, O and P do not support this mode.</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLICE_D</name>
|
|
<description>Slice D</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLICE_H</name>
|
|
<description>Slice H</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLICE_O</name>
|
|
<description>Slice O</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLICE_P</name>
|
|
<description>Slice P</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUALIFIER_MODE</name>
|
|
<description>Select qualifier mode.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLICE_SEE_BITS_QUAL</name>
|
|
<description>Slice (see bits QUALIFIER_SLICE_MODE in this register)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EXTERNAL_SGPIO_PIN</name>
|
|
<description>External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUALIFIER_PIN_MODE</name>
|
|
<description>Select qualifier pin.</description>
|
|
<bitRange>[8:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SGPIO8</name>
|
|
<description>SGPIO8</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO9</name>
|
|
<description>SGPIO9</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO10</name>
|
|
<description>SGPIO10</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SGPIO11</name>
|
|
<description>SGPIO11</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUALIFIER_SLICE_MODE</name>
|
|
<description>Select qualifier slice.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SLICE_A</name>
|
|
<description>Slice A, but for slice A slice D is used.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLICE_H</name>
|
|
<description>Slice H, but for slice H slice O is used.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLICE_I</name>
|
|
<description>Slice I, but for slice I slice D is used.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLICE_P</name>
|
|
<description>Slice P, but for slice P slice O is used.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONCAT_ENABLE</name>
|
|
<description>Enable concatenation.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EXTERNAL_DATA_PIN</name>
|
|
<description>External data pin</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CONCATENATE_DATA</name>
|
|
<description>Concatenate data</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONCAT_ORDER</name>
|
|
<description>Select concatenation order</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELF_LOOP</name>
|
|
<description>Self-loop</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_SLICES</name>
|
|
<description>2 slices</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_SLICES</name>
|
|
<description>4 slices</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_SLICES</name>
|
|
<description>8 slices</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:14]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>SLICE_MUX_CFG[%s]</name>
|
|
<description>Slice multiplexer configuration registers.</description>
|
|
<addressOffset>0x0080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH_MODE</name>
|
|
<description>Match mode. Selects whether the match filter is active or whether data is captured.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOT_MATCH_DATA</name>
|
|
<description>Do not match data.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MATCH_DATA</name>
|
|
<description>Match data.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLK_CAPTURE_MODE</name>
|
|
<description>Capture clock mode</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>USE_RISING_CLOCK_EDG</name>
|
|
<description>Use rising clock edge.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USE_FALLING_CLOCK_ED</name>
|
|
<description>Use falling clock edge.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKGEN_MODE</name>
|
|
<description>Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>USE_CLOCK_INTERNALLY</name>
|
|
<description>Use clock internally generated by COUNTER.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USE_EXTERNAL_CLOCK_F</name>
|
|
<description>Use external clock from a pin or other slice.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV_OUT_CLK</name>
|
|
<description>Invert output clock</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL_CLOCK</name>
|
|
<description>Normal clock.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INVERTED_CLOCK</name>
|
|
<description>Inverted clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATA_CAPTURE_MODE</name>
|
|
<description>Condition for input bit match interrupt</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DETECT_RISING_EDGE</name>
|
|
<description>Detect rising edge.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_FALLING_EDGE</name>
|
|
<description>Detect falling edge.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_LOW_LEVEL</name>
|
|
<description>Detect LOW level.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DETECT_HIGH_LEVEL</name>
|
|
<description>Detect HIGH level.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PARALLEL_MODE</name>
|
|
<description>Parallel mode</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SHIFT_1_BIT_PER_CLOC</name>
|
|
<description>Shift 1 bit per clock.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHIFT_2_BITS_PER_CLO</name>
|
|
<description>Shift 2 bits per clock.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHIFT_4_BITS_PER_CLO</name>
|
|
<description>Shift 4 bits per clock.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SHIFT_1_BYTE_PER_CLO</name>
|
|
<description>Shift 1 byte per clock.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV_QUALIFIER</name>
|
|
<description>Inversion qualifier</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>USE_NORMAL_QUALIFIER</name>
|
|
<description>Use normal qualifier.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USE_INVERTED_QUALIFI</name>
|
|
<description>Use inverted qualifier.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>REG[%s]</name>
|
|
<description>Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)</description>
|
|
<addressOffset>0x00C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG</name>
|
|
<description>At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0).</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>REG_SS[%s]</name>
|
|
<description>Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG</description>
|
|
<addressOffset>0x0100</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REG_SS</name>
|
|
<description>Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>PRESET[%s]</name>
|
|
<description>Reload value of COUNT0, loaded when COUNT0 reaches 0x0</description>
|
|
<addressOffset>0x0140</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRESET</name>
|
|
<description>Counter reload value; loaded when COUNT reaches 0x0.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>COUNT[%s]</name>
|
|
<description>Down counter, counts down each clock cycle.</description>
|
|
<addressOffset>0x0180</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET.</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-15</dimIndex>
|
|
<name>POS[%s]</name>
|
|
<description>Each time COUNT0 reaches 0x0 POS counts down.</description>
|
|
<addressOffset>0x01C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POS</name>
|
|
<description>Each time COUNT reaches 0x0 POS counts down.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>POS_RESET</name>
|
|
<description>Reload value for POS after POS reaches 0x0.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK_A</name>
|
|
<description>Mask for pattern match function of slice A</description>
|
|
<addressOffset>0x0200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK_A</name>
|
|
<description>Mask for pattern match function of slice A 0 = No effect. 1 = Mask this bit.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK_H</name>
|
|
<description>Mask for pattern match function of slice H</description>
|
|
<addressOffset>0x0204</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK_H</name>
|
|
<description>Mask for pattern match function of slice H 0 = No effect. 1 = Mask this bit.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK_I</name>
|
|
<description>Mask for pattern match function of slice I</description>
|
|
<addressOffset>0x0208</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK_I</name>
|
|
<description>Mask for pattern match function of slice I 0 = No effect . 1 = Mask this bit.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASK_P</name>
|
|
<description>Mask for pattern match function of slice P</description>
|
|
<addressOffset>0x020C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK_P</name>
|
|
<description>Mask for pattern match function of slice P 0 = No effect. 1 = Mask this bit.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO_INREG</name>
|
|
<description>GPIO input status register</description>
|
|
<addressOffset>0x0210</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_INi</name>
|
|
<description>Bit i reflects the input state of SGPIO pin i . 0 = LOW 1 = HIGH</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO_OUTREG</name>
|
|
<description>GPIO output control register</description>
|
|
<addressOffset>0x0214</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_OUT</name>
|
|
<description>GPIO output register. Bit i sets the output of SGPIO pin i. 0 = LOW 1 = HIGH</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO_OENREG</name>
|
|
<description>GPIO OE control register</description>
|
|
<addressOffset>0x0218</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPIO_OE</name>
|
|
<description>Bit i selects the output enable state of SGPIO pin i. 0 = GPIO output i is tri-stated . 1 = GPIO output i is active.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL_ENABLE</name>
|
|
<description>Enables the slice COUNT counter</description>
|
|
<addressOffset>0x021C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL_EN</name>
|
|
<description>Slice count enable. Bit n controls slice n (0 = slice A, ..., 15 = slice P). 0 = Disables slice shift clock. 1 = Starts COUNTn or external shift clock.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL_DISABLE</name>
|
|
<description>Disables the slice POS counter</description>
|
|
<addressOffset>0x0220</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTRL_DIS</name>
|
|
<description>Slice count disable. Bit n controls slice n, (0 = slice A, ..., 15 = slice P). 0 = Enables COUNT and POS counters. The counters start counting when the CTRL_EN bit or bits are set in the CTRL_ENABLED register. 1 = Disables POS counter of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_EN_0</name>
|
|
<description>Shift clock interrupt clear mask</description>
|
|
<addressOffset>0x0F00</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR_SCI</name>
|
|
<description>1 = Shift clock interrupt clear mask of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_EN_0</name>
|
|
<description>Shift clock interrupt set mask</description>
|
|
<addressOffset>0x0F04</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET_SCI</name>
|
|
<description>1 = Shift clock interrupt set mask of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENABLE_0</name>
|
|
<description>Shift clock interrupt enable</description>
|
|
<addressOffset>0x0F08</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_SCI</name>
|
|
<description>1 = Shift clock interrupt enable of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS_0</name>
|
|
<description>Shift clock interrupt status</description>
|
|
<addressOffset>0x0F0C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATUS_SCI</name>
|
|
<description>Shift clock interrupt status of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_STATUS_0</name>
|
|
<description>Shift clock interrupt clear status</description>
|
|
<addressOffset>0x0F10</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR_STATUS_SCI</name>
|
|
<description>Shift clock interrupt clear status of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_STATUS_0</name>
|
|
<description>Shift clock interrupt set status</description>
|
|
<addressOffset>0x0F14</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET_STATUS_SCI</name>
|
|
<description>Shift clock interrupt set status of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_EN_1</name>
|
|
<description>Exchange clock interrupt clear mask</description>
|
|
<addressOffset>0x0F20</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR_EN_CCI</name>
|
|
<description>1 = Exchange clock interrupt clear mask of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_EN_1</name>
|
|
<description>Exchange clock interrupt set mask</description>
|
|
<addressOffset>0x0F24</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET_EN_CCI</name>
|
|
<description>1 = Exchange clock interrupt set mask of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENABLE_1</name>
|
|
<description>Exchange clock interrupt enable</description>
|
|
<addressOffset>0x0F28</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_CCI</name>
|
|
<description>Exchange clock interrupt enable of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS_1</name>
|
|
<description>Exchange clock interrupt status</description>
|
|
<addressOffset>0x0F2C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATUS_CCI</name>
|
|
<description>Exchange clock interrupt status of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_STATUS_1</name>
|
|
<description>Exchange clock interrupt clear status</description>
|
|
<addressOffset>0x0F30</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR_STATUS_CCI</name>
|
|
<description>Exchange clock interrupt clear status of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_STATUS_1</name>
|
|
<description>Exchange clock interrupt set status</description>
|
|
<addressOffset>0x0F34</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET_STATUS_CCI</name>
|
|
<description>Exchange clock interrupt set status of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_EN_2</name>
|
|
<description>Pattern match interrupt clear mask</description>
|
|
<addressOffset>0x0F40</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR_EN2_PMI</name>
|
|
<description>1 = Match interrupt clear mask of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_EN_2</name>
|
|
<description>Pattern match interrupt set mask</description>
|
|
<addressOffset>0x0F44</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET_EN_PMI</name>
|
|
<description>1 = Match interrupt set mask of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENABLE_2</name>
|
|
<description>Pattern match interrupt enable</description>
|
|
<addressOffset>0x0F48</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE_PMI</name>
|
|
<description>Match interrupt enable of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS_2</name>
|
|
<description>Pattern match interrupt status</description>
|
|
<addressOffset>0x0F4C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATUS_PMI</name>
|
|
<description>Match interrupt status of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_STATUS_2</name>
|
|
<description>Pattern match interrupt clear status</description>
|
|
<addressOffset>0x0F50</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR_STATUS_PMI</name>
|
|
<description>Match interrupt clear status of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_STATUS_2</name>
|
|
<description>Pattern match interrupt set status</description>
|
|
<addressOffset>0x0F54</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET_STATUS_PMI</name>
|
|
<description>Match interrupt set status of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_EN_3</name>
|
|
<description>Input interrupt clear mask</description>
|
|
<addressOffset>0x0F60</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR_EN_INPI</name>
|
|
<description>1 = Input interrupt clear mask of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_EN_3</name>
|
|
<description>Input bit match interrupt set mask</description>
|
|
<addressOffset>0x0F64</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET_EN_INPI</name>
|
|
<description>1 = Input interrupt set mask of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENABLE_3</name>
|
|
<description>Input bit match interrupt enable</description>
|
|
<addressOffset>0x0F68</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE3_INPI</name>
|
|
<description>Input interrupt enable of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS_3</name>
|
|
<description>Input bit match interrupt status</description>
|
|
<addressOffset>0x0F6C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATUS_INPI</name>
|
|
<description>Input interrupt status of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLR_STATUS_3</name>
|
|
<description>Input bit match interrupt clear status</description>
|
|
<addressOffset>0x0F70</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR_STATUS_INPI</name>
|
|
<description>Input interrupt clear status of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SET_STATUS_3</name>
|
|
<description>Input bit match interrupt set status</description>
|
|
<addressOffset>0x0F74</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET_STATUS_INPI</name>
|
|
<description>Shift interrupt set status of slice n.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
|
|
|
|
|
|
|
|
</peripherals>
|
|
|
|
|
|
|
|
|
|
</device>
|