LPC43xx 10 Register cmsis file for LPC43xx parts CM4 r0p0 little 0 0 3 0 LPC_ 8 32 32 SCT State Configurable Timer (SCT) with dither engine SCT 0x40000000 0 0xFFF registers SCT 10 CONFIG SCT configuration register 0x000 read-write 0x00007E00 0xFFFFFFFF UNIFY SCT operation [0:0] ENUM 16_BIT 16-bit.The SCT operates as two 16-bit counters named L and H. 0 32_BIT 32-bit. The SCT operates as a unified 32-bit counter. 1 CLKMODE SCT clock mode [2:1] ENUM BUS_CLOCK Bus clock. The bus clock clocks the SCT and prescalers. 0x0 PRESCALED_BUS_CLOCK Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode. 0x1 SCT_INPUT SCT Input. The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode. 0x2 RESERVED Reserved. 0x3 CKSEL SCT clock select [6:3] ENUM RISING_EDGES_ON_INPU Rising edges on input 0. 0x0 FALLING_EDGES_ON_INP Falling edges on input 0. 0x1 RISING_EDGES_ON_INPU Rising edges on input 1. 0x2 FALLING_EDGES_ON_INP Falling edges on input 1. 0x3 RISING_EDGES_ON_INPU Rising edges on input 2. 0x4 FALLING_EDGES_ON_INP Falling edges on input 2. 0x5 RISING_EDGES_ON_INPU Rising edges on input 3. 0x6 FALLING_EDGES_ON_INP Falling edges on input 3. 0x7 RISING_EDGES_ON_INPU Rising edges on input 4. 0x8 FALLING_EDGES_ON_INP Falling edges on input 4. 0x9 RISING_EDGES_ON_INPU Rising edges on input 5. 0xA FALLING_EDGES_ON_INP Falling edges on input 5. 0xB RISING_EDGES_ON_INPU Rising edges on input 6. 0xC FALLING_EDGES_ON_INP Falling edges on input 6. 0xD RISING_EDGES_ON_INPU Rising edges on input 7. 0xE FALLING_EDGES_ON_INP Falling edges on input 7. 0xF NORELAOD_L A 1 in this bit prevents the lower match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. [7:7] NORELOAD_H A 1 in this bit prevents the higher match and fractional match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. [8:8] INSYNC Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used. [16:9] AUTOLIMIT_L A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. [17:17] AUTOLIMIT_H A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. [18:18] RESERVED Reserved [31:19] CTRL SCT control register 0x004 read-write 0x00040004 0xFFFFFFFF DOWN_L This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs. [0:0] STOP_L When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. [1:1] HALT_L When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation. [2:2] CLRCTR_L Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. [3:3] BIDIR_L L or unified counter direction select [4:4] ENUM UP Up. The counter counts up to its limit condition, then is cleared to zero. 0 UPDOWN Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0. 1 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. [12:5] RESERVED Reserved [15:13] DOWN_H This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs. [16:16] STOP_H When this bit is 1 and HALT is 0, the H counter does not run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. [17:17] HALT_H When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation. [18:18] CLRCTR_H Writing a 1 to this bit clears the H counter. This bit always reads as 0. [19:19] BIDIR_H Direction select [20:20] ENUM UP Up. The H counter counts up to its limit condition, then is cleared to zero. 0 UPDOWN Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0. 1 PRE_H Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. [28:21] RESERVED Reserved [31:29] LIMIT SCT limit register 0x008 read-write 0x00000000 0xFFFFFFFF LIMMSK_L If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). [15:0] LIMMSK_H If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). [31:16] HALT SCT halt condition register 0x00C read-write 0x00000000 0xFFFFFFFF HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). [15:0] HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). [31:16] STOP SCT stop condition register 0x010 read-write 0x00000000 0xFFFFFFFF STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). [15:0] STOPMSK_H If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). [31:16] START SCT start condition register 0x014 read-write 0x00000000 0xFFFFFFFF STARTMSK_L If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). [15:0] STARTMSK_H If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31). [31:16] DITHER SCT dither condition register 0x018 read-write 0 0x00000000 DITHMSK_L If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle. [15:0] DITHMSK_H If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle. [31:16] COUNT SCT counter register 0x040 read-write 0x00000000 0xFFFFFFFF CTR_L When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. [15:0] CTR_H When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. [31:16] STATE SCT state register 0x044 read-write 0x00000000 0xFFFFFFFF STATE_L State variable. [4:0] RESERVED Reserved. [15:5] STATE_H State variable. [20:16] RESERVED Reserved. [31:21] INPUT SCT input register 0x048 read-only 0x00000000 0xFFFFFFFF AIN0 Real-time status of input 0. [0:0] AIN1 Real-time status of input 1. [1:1] AIN2 Real-time status of input 2. [2:2] AIN3 Real-time status of input 3. [3:3] AIN4 Real-time status of input 4. [4:4] AIN5 Real-time status of input 5. [5:5] AIN6 Real-time status of input 6. [6:6] AIN7 Real-time status of input 7. [7:7] RESERVED Reserved. [15:8] SIN0 Input 0 state synchronized to the SCT clock. [16:16] SIN1 Input 1 state synchronized to the SCT clock. [17:17] SIN2 Input 2 state synchronized to the SCT clock. [18:18] SIN3 Input 3 state synchronized to the SCT clock. [19:19] SIN4 Input 4 state synchronized to the SCT clock. [20:20] SIN5 Input 5 state synchronized to the SCT clock. [21:21] SIN6 Input 6 state synchronized to the SCT clock. [22:22] SIN7 Input 7 state synchronized to the SCT clock. [23:23] RESERVED Reserved [31:24] REGMODE SCT match/capture registers mode register 0x04C read-write 0x00000000 0xFFFFFFFF REGMOD_L Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15). 0 = registers operate as match registers. 1 = registers operate as capture registers. [15:0] REGMOD_H Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers. [31:16] OUTPUT SCT output register 0x050 read-write 0x00000000 0xFFFFFFFF OUT Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [15:0] RESERVED Reserved [31:16] OUTPUTDIRCTRL SCT output counter direction control register 0x054 read-write 0x00000000 0xFFFFFFFF SETCLR0 Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. [1:0] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR1 Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. [3:2] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR2 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. [5:4] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR3 Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. [7:6] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR4 Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. [9:8] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR5 Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. [11:10] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR6 Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. [13:12] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR7 Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. [15:14] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR8 Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. [17:16] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR9 Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. [19:18] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR10 Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. [21:20] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR11 Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. [23:22] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR12 Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. [25:24] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR13 Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. [27:26] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR14 Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. [29:28] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 SETCLR15 Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. [31:30] ENUM INDEPENDENT Independent. Set and clear do not depend on any counter. 0x0 L_COUNTER L counter. Set and clear are reversed when counter L or the unified counter is counting down. 0x1 H_COUNTER H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. 0x2 RES SCT conflict resolution register 0x058 read-write 0x00000000 0xFFFFFFFF O0RES Effect of simultaneous set and clear on output 0. [1:0] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR0 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR0 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O1RES Effect of simultaneous set and clear on output 1. [3:2] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR1 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR1 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O2RES Effect of simultaneous set and clear on output 2. [5:4] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR2 field). 0x1 CLEAR_OUTPUT_N_OR_S Clear output n (or set based on the SETCLR2 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O3RES Effect of simultaneous set and clear on output 3. [7:6] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR3 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR3 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O4RES Effect of simultaneous set and clear on output 4. [9:8] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR4 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR4 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O5RES Effect of simultaneous set and clear on output 5. [11:10] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR5 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR5 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O6RES Effect of simultaneous set and clear on output 6. [13:12] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR6 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR6 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O7RES Effect of simultaneous set and clear on output 7. [15:14] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR7 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR7 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O8RES Effect of simultaneous set and clear on output 8. [17:16] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR8 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR8 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O9RES Effect of simultaneous set and clear on output 9. [19:18] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR9 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR9 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O10RES Effect of simultaneous set and clear on output 10. [21:20] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR10 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR10 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O11RES Effect of simultaneous set and clear on output 11. [23:22] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR11 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR11 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O12RES Effect of simultaneous set and clear on output 12. [25:24] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR12 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR12 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O13RES Effect of simultaneous set and clear on output 13. [27:26] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR13 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR13 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O14RES Effect of simultaneous set and clear on output 14. [29:28] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR14 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR14 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 O15RES Effect of simultaneous set and clear on output 15. [31:30] ENUM NO_CHANGE No change. 0x0 SET_OUTPUT_OR_CLEAR Set output (or clear based on the SETCLR15 field). 0x1 CLEAR_OUTPUT_OR_SET Clear output (or set based on the SETCLR15 field). 0x2 TOGGLE_OUTPUT Toggle output. 0x3 DMAREQ0 SCT DMA request 0 register 0x05C read-write 0x00000000 0xFFFFFFFF DEV_00 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [0:0] DEV_01 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [1:1] DEV_02 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [2:2] DEV_03 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [3:3] DEV_04 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [4:4] DEV_05 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [5:5] DEV_06 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [6:6] DEV_07 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [7:7] DEV_08 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [8:8] DEV_09 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [9:9] DEV_010 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [10:10] DEV_011 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [11:11] DEV_012 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [12:12] DEV_013 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [13:13] DEV_014 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [14:14] DEV_015 If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:15] RESERVED Reserved [29:16] DRL0 A 1 in this bit makes the SCT set DMA request 0 when it loads the Match_L/Unified registers from the Reload_L/Unified registers. [30:30] DRQ0 This read-only bit indicates the state of DMA Request 0 [31:31] DMAREQ1 SCT DMA request 1 register 0x060 read-write 0x00000000 0xFFFFFFFF DEV_10 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [0:0] DEV_11 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [1:1] DEV_12 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [2:2] DEV_13 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [3:3] DEV_14 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [4:4] DEV_15 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [5:5] DEV_16 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [6:6] DEV_17 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [7:7] DEV_18 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [8:8] DEV_19 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [9:9] DEV_110 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [10:10] DEV_111 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [11:11] DEV_112 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [12:12] DEV_113 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [13:13] DEV_114 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [14:14] DEV_115 If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:15] RESERVED Reserved [29:16] DRL1 A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. [30:30] DRQ1 This read-only bit indicates the state of DMA Request 1. [31:31] EVEN SCT event enable register 0x0F0 read-write 0x00000000 0xFFFFFFFF IEN0 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [0:0] IEN1 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [1:1] IEN2 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [2:2] IEN3 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [3:3] IEN4 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [4:4] IEN5 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [5:5] IEN6 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [6:6] IEN7 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [7:7] IEN8 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [8:8] IEN9 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [9:9] IEN10 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [10:10] IEN11 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [11:11] IEN12 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [12:12] IEN13 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [13:13] IEN14 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [14:14] IEN15 The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:15] RESERVED Reserved [31:16] EVFLAG SCT event flag register 0x0F4 read-write 0x00000000 0xFFFFFFFF FLAG0 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [0:0] FLAG1 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [1:1] FLAG2 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [2:2] FLAG3 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [3:3] FLAG4 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [4:4] FLAG5 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [5:5] FLAG6 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [6:6] FLAG7 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [7:7] FLAG8 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [8:8] FLAG9 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [9:9] FLAG10 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [10:10] FLAG11 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [11:11] FLAG12 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [12:12] FLAG13 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [13:13] FLAG14 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [14:14] FLAG15 Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:15] RESERVED Reserved [31:16] CONEN SCT conflict enable register 0x0F8 read-write 0x00000000 0xFFFFFFFF NCEN0 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [0:0] NCEN1 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [1:1] NCEN2 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [2:2] NCEN3 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [3:3] NCEN4 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [4:4] NCEN5 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [5:5] NCEN6 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [6:6] NCEN7 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [7:7] NCEN8 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [8:8] NCEN9 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [9:9] NCEN10 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [10:10] NCEN11 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [11:11] NCEN12 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [12:12] NCEN13 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [13:13] NCEN14 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [14:14] NCEN15 The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [15:15] RESERVED Reserved [31:16] CONFLAG SCT conflict flag register 0x0FC read-write 0x00000000 0xFFFFFFFF NCFLAG0 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [0:0] NCFLAG1 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [1:1] NCFLAG2 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [2:2] NCFLAG3 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [3:3] NCFLAG4 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [4:4] NCFLAG5 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [5:5] NCFLAG6 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [6:6] NCFLAG7 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [7:7] NCFLAG8 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [8:8] NCFLAG9 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [9:9] NCFLAG10 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [10:10] NCFLAG11 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [11:11] NCFLAG12 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [12:12] NCFLAG13 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [13:13] NCFLAG14 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [14:14] NCFLAG15 Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15). [15:15] RESERVED Reserved. [29:16] BUSERRL The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. [30:30] BUSERRH The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. [31:31] 16 0x4 0-15 MATCH%s SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 0x100 read-write 0x00000000 0xFFFFFFFF MATCH_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. [15:0] MATCH_H When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. [31:16] 6 0x4 0-5 FRACMAT%s Fractional match registers 0 to 5 for SCT match value registers 0 to 5. 0x140 read-write 0x00000000 0xFFFFFFFF FRACMAT_L When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register. [3:0] RESERVED Reserved. [15:4] FRACMAT_H When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5). [19:16] RESERVED Reserved. [31:20] 16 0x4 0-15 CAP%s SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 MATCH%s 0x100 read-write 0x00000000 0xFFFFFFFF CAP_L When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. [15:0] CAP_H When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. [31:16] 16 0x4 0-15 MATCHREL%s SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 0x200 read-write 0x00000000 0xFFFFFFFF RELOAD_L When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. [15:0] RELOAD_H When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. [31:16] 6 0x4 0-5 FRACMATREL%s Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5. 0x240 read-write 0x00000000 0xFFFFFFFF RELFRAC_L When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register. [3:0] RESERVED Reserved. [15:4] RELFRAC_H When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register. [19:16] RESERVED Reserved. [31:20] 16 0x4 0-15 CAPCTRL%s SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 MATCHREL%s 0x200 read-write 0x00000000 0xFFFFFFFF CAPCON_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15). [15:0] CAPCON_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31). [31:16] 16 0x8 0-15 EV%s_STATE SCT event state register 0 0x300 read-write 0x00000000 0xFFFFFFFF STATEMSK0 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [0:0] STATEMSK1 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [1:1] STATEMSK2 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [2:2] STATEMSK3 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [3:3] STATEMSK4 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [4:4] STATEMSK5 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [5:5] STATEMSK6 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [6:6] STATEMSK7 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [7:7] STATEMSK8 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [8:8] STATEMSK9 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [9:9] STATEMSK10 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [10:10] STATEMSK11 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [11:11] STATEMSK12 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [12:12] STATEMSK13 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [13:13] STATEMSK14 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [14:14] STATEMSK15 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [15:15] STATEMSK16 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [16:16] STATEMSK17 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [17:17] STATEMSK18 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [18:18] STATEMSK19 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [19:19] STATEMSK20 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [20:20] STATEMSK21 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [21:21] STATEMSK22 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [22:22] STATEMSK23 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [23:23] STATEMSK24 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [24:24] STATEMSK25 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [25:25] STATEMSK26 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [26:26] STATEMSK27 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [27:27] STATEMSK28 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [28:28] STATEMSK29 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [29:29] STATEMSK30 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [30:30] STATEMSK31 If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31). [31:31] 16 0x8 0-15 EV%s_CTRL SCT event control register 0 0x304 read-write 0x00000000 0xFFFFFFFF MATCHSEL Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running. [3:0] HEVENT Select L/H counter. Do not set this bit if UNIFY = 1. [4:4] ENUM L_STATE L state. Selects the L state and the L match register selected by MATCHSEL. 0 H_STATE H state. Selects the H state and the H match register selected by MATCHSEL. 1 OUTSEL Input/output select [5:5] ENUM INPUT Input. Selects the input selected by IOSEL. 0 OUTPUT Output. Selects the output selected by IOSEL. 1 IOSEL Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. [9:6] IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . [11:10] ENUM LOW LOW 0x0 RISE Rise 0x1 FALL Fall 0x2 HIGH HIGH 0x3 COMBMODE Selects how the specified match and I/O condition are used and combined. [13:12] ENUM OR OR. The event occurs when either the specified match or I/O condition occurs. 0x0 MATCH MATCH. Uses the specified match only. 0x1 IO IO. Uses the specified I/O condition only. 0x2 AND AND. The event occurs when the specified match and I/O condition occur simultaneously. 0x3 STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. [14:14] ENUM STATEV_VALUE_IS_ADDE STATEV value is added into STATE (the carry-out is ignored). 0 STATEV_VALUE_IS_LOAD STATEV value is loaded into STATE. 1 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. [19:15] MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. [20:20] DIRECTION Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. [22:21] ENUM DIRECTION_INDEPENDEN Direction independent. This event is triggered regardless of the count direction. 0x0 COUNTING_UP Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x1 COUNTING_DOWN Counting down. This event is triggered only during down-counting when BIDIR = 1. 0x2 RESERVED Reserved [31:23] 16 0x8 0-15 OUT%s_SET SCT output 0 set register 0x500 read-write 0x00000000 0xFFFFFFFF SET0 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [0:0] SET1 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [1:1] SET2 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [2:2] SET3 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [3:3] SET4 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [4:4] SET5 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [5:5] SET6 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [6:6] SET7 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [7:7] SET8 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [8:8] SET9 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [9:9] SET10 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [10:10] SET11 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [11:11] SET12 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [12:12] SET13 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [13:13] SET14 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [14:14] SET15 A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [15:15] RESERVED Reserved [31:16] 16 0x8 0-15 OUT%s_CLR SCT output 0 clear register 0x504 read-write 0x00000000 0xFFFFFFFF CLR0 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [0:0] CLR1 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [1:1] CLR2 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [2:2] CLR3 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [3:3] CLR4 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [4:4] CLR5 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [5:5] CLR6 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [6:6] CLR7 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [7:7] CLR8 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [8:8] CLR9 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [9:9] CLR10 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [10:10] CLR11 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [11:11] CLR12 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [12:12] CLR13 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [13:13] CLR14 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [14:14] CLR15 A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15. [15:15] RESERVED Reserved [31:16] GPDMA General Purpose DMA (GPDMA) GPDMA 0x40002000 0 0xFFF registers DMA 2 INTSTAT DMA Interrupt Status Register 0x000 read-only 0x00000000 0xFFFFFFFF INTSTAT0 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [0:0] INTSTAT1 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [1:1] INTSTAT2 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [2:2] INTSTAT3 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [3:3] INTSTAT4 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [4:4] INTSTAT5 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [5:5] INTSTAT6 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [6:6] INTSTAT7 Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. [7:7] RESERVED Reserved. Read undefined. [31:8] INTTCSTAT DMA Interrupt Terminal Count Request Status Register 0x004 read-only 0x00000000 0xFFFFFFFF INTTCSTAT0 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [0:0] INTTCSTAT1 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [1:1] INTTCSTAT2 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [2:2] INTTCSTAT3 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [3:3] INTTCSTAT4 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [4:4] INTTCSTAT5 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [5:5] INTTCSTAT6 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [6:6] INTTCSTAT7 Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [7:7] RESERVED Reserved. Read undefined. [31:8] INTTCCLEAR DMA Interrupt Terminal Count Request Clear Register 0x008 write-only 0 0x00000000 INTTCCLEAR0 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [0:0] INTTCCLEAR1 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [1:1] INTTCCLEAR2 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [2:2] INTTCCLEAR3 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [3:3] INTTCCLEAR4 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [4:4] INTTCCLEAR5 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [5:5] INTTCCLEAR6 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [6:6] INTTCCLEAR7 Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. [7:7] RESERVED Reserved. Read undefined. Write reserved bits as zero. [31:8] INTERRSTAT DMA Interrupt Error Status Register 0x00C read-only 0x00000000 0xFFFFFFFF INTERRSTAT0 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [0:0] INTERRSTAT1 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [1:1] INTERRSTAT2 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [2:2] INTERRSTAT3 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [3:3] INTERRSTAT4 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [4:4] INTERRSTAT5 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [5:5] INTERRSTAT6 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [6:6] INTERRSTAT7 Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [7:7] RESERVED Reserved. Read undefined. [31:8] INTERRCLR DMA Interrupt Error Clear Register 0x010 write-only 0 0x00000000 INTERRCLR0 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [0:0] INTERRCLR1 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [1:1] INTERRCLR2 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [2:2] INTERRCLR3 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [3:3] INTERRCLR4 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [4:4] INTERRCLR5 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [5:5] INTERRCLR6 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [6:6] INTERRCLR7 Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. [7:7] RESERVED Reserved. Read undefined. Write reserved bits as zero. [31:8] RAWINTTCSTAT DMA Raw Interrupt Terminal Count Status Register 0x014 read-only 0x00000000 0xFFFFFFFF RAWINTTCSTAT0 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [0:0] RAWINTTCSTAT1 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [1:1] RAWINTTCSTAT2 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [2:2] RAWINTTCSTAT3 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [3:3] RAWINTTCSTAT4 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [4:4] RAWINTTCSTAT5 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [5:5] RAWINTTCSTAT6 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [6:6] RAWINTTCSTAT7 Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. [7:7] RESERVED Reserved. Read undefined. [31:8] RAWINTERRSTAT DMA Raw Error Interrupt Status Register 0x018 read-only 0x00000000 0xFFFFFFFF RAWINTERRSTAT0 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [0:0] RAWINTERRSTAT1 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [1:1] RAWINTERRSTAT2 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [2:2] RAWINTERRSTAT3 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [3:3] RAWINTERRSTAT4 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [4:4] RAWINTERRSTAT5 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [5:5] RAWINTERRSTAT6 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [6:6] RAWINTERRSTAT7 Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. [7:7] RESERVED Reserved. Read undefined. [31:8] ENBLDCHNS DMA Enabled Channel Register 0x01C read-only 0x00000000 0xFFFFFFFF ENABLEDCHANNELS0 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [0:0] ENABLEDCHANNELS1 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [1:1] ENABLEDCHANNELS2 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [2:2] ENABLEDCHANNELS3 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [3:3] ENABLEDCHANNELS4 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [4:4] ENABLEDCHANNELS5 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [5:5] ENABLEDCHANNELS6 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [6:6] ENABLEDCHANNELS7 Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled. [7:7] RESERVED Reserved. Read undefined. [31:8] SOFTBREQ DMA Software Burst Request Register 0x020 read-write 0x00000000 0xFFFFFFFF SOFTBREQ0 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [0:0] SOFTBREQ1 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [1:1] SOFTBREQ2 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [2:2] SOFTBREQ3 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [3:3] SOFTBREQ4 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [4:4] SOFTBREQ5 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [5:5] SOFTBREQ6 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [6:6] SOFTBREQ7 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [7:7] SOFTBREQ8 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [8:8] SOFTBREQ9 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [9:9] SOFTBREQ10 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [10:10] SOFTBREQ11 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [11:11] SOFTBREQ12 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [12:12] SOFTBREQ13 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [13:13] SOFTBREQ14 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [14:14] SOFTBREQ15 Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line. [15:15] RESERVED Reserved. Read undefined. Write reserved bits as zero. [31:16] SOFTSREQ DMA Software Single Request Register 0x024 read-write 0x00000000 0xFFFFFFFF SOFTSREQ0 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [0:0] SOFTSREQ1 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [1:1] SOFTSREQ2 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [2:2] SOFTSREQ3 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [3:3] SOFTSREQ4 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [4:4] SOFTSREQ5 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [5:5] SOFTSREQ6 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [6:6] SOFTSREQ7 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [7:7] SOFTSREQ8 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [8:8] SOFTSREQ9 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [9:9] SOFTSREQ10 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [10:10] SOFTSREQ11 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [11:11] SOFTSREQ12 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [12:12] SOFTSREQ13 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [13:13] SOFTSREQ14 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [14:14] SOFTSREQ15 Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line. [15:15] RESERVED Reserved. Read undefined. Write reserved bits as zero. [31:16] SOFTLBREQ DMA Software Last Burst Request Register 0x028 read-write 0x00000000 0xFFFFFFFF SOFTLBREQ0 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [0:0] SOFTLBREQ1 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [1:1] SOFTLBREQ2 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [2:2] SOFTLBREQ3 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [3:3] SOFTLBREQ4 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [4:4] SOFTLBREQ5 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [5:5] SOFTLBREQ6 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [6:6] SOFTLBREQ7 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [7:7] SOFTLBREQ8 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [8:8] SOFTLBREQ9 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [9:9] SOFTLBREQ10 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [10:10] SOFTLBREQ11 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [11:11] SOFTLBREQ12 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [12:12] SOFTLBREQ13 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [13:13] SOFTLBREQ14 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [14:14] SOFTLBREQ15 Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line. [15:15] RESERVED Reserved. Read undefined. Write reserved bits as zero. [31:16] SOFTLSREQ DMA Software Last Single Request Register 0x02C read-write 0x00000000 0xFFFFFFFF SOFTLSREQ0 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [0:0] SOFTLSREQ1 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [1:1] SOFTLSREQ2 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [2:2] SOFTLSREQ3 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [3:3] SOFTLSREQ4 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [4:4] SOFTLSREQ5 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [5:5] SOFTLSREQ6 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [6:6] SOFTLSREQ7 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [7:7] SOFTLSREQ8 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [8:8] SOFTLSREQ9 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [9:9] SOFTLSREQ10 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [10:10] SOFTLSREQ11 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [11:11] SOFTLSREQ12 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [12:12] SOFTLSREQ13 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [13:13] SOFTLSREQ14 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [14:14] SOFTLSREQ15 Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line. [15:15] RESERVED Reserved. Read undefined. Write reserved bits as zero. [31:16] CONFIG DMA Configuration Register 0x030 read-write 0x00000000 0xFFFFFFFF E DMA Controller enable: [0:0] ENUM DISABLED__DEFAULT_ Disabled (default). Disabling the DMA Controller reduces power consumption. 0 ENABLED Enabled 1 M0 AHB Master 0 endianness configuration: [1:1] ENUM LITTLE_ENDIAN_MODE Little-endian mode (default). 0 BIG_ENDIAN_MODE_ Big-endian mode. 1 M1 AHB Master 1 endianness configuration: [2:2] ENUM LITTLE_ENDIAN_MODE Little-endian mode (default). 0 BIG_ENDIAN_MODE_ Big-endian mode. 1 RESERVED Reserved. Read undefined. Write reserved bits as zero. [31:3] SYNC DMA Synchronization Register 0x034 read-write 0x00000000 0xFFFFFFFF DMACSYNC0 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [0:0] DMACSYNC1 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [1:1] DMACSYNC2 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [2:2] DMACSYNC3 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [3:3] DMACSYNC4 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [4:4] DMACSYNC5 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [5:5] DMACSYNC6 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [6:6] DMACSYNC7 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [7:7] DMACSYNC8 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [8:8] DMACSYNC9 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [9:9] DMACSYNC10 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [10:10] DMACSYNC11 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [11:11] DMACSYNC12 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [12:12] DMACSYNC13 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [13:13] DMACSYNC14 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [14:14] DMACSYNC15 Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled. [15:15] RESERVED Reserved. Read undefined. Write reserved bits as zero. [31:16] 8 0x20 0-7 C%sSRCADDR DMA Channel Source Address Register 0x100 read-write 0x00000000 0xFFFFFFFF SRCADDR DMA source address. Reading this register will return the current source address. [31:0] 8 0x20 0-7 C%sDESTADDR DMA Channel Destination Address Register 0x104 read-write 0x00000000 0xFFFFFFFF DESTADDR DMA Destination address. Reading this register will return the current destination address. [31:0] 8 0x20 0-7 C%sLLI DMA Channel Linked List Item Register 0x108 read-write 0x00000000 0xFFFFFFFF LM AHB master select for loading the next LLI: [0:0] ENUM AHB_MASTER_0_ AHB Master 0. 0 AHB_MASTER_1_ AHB Master 1. 1 R Reserved, and must be written as 0, masked on read. [1:1] LLI Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. [31:2] 8 0x20 0-7 C%sCONTROL DMA Channel Control Register 0x10C read-write 0x00000000 0xFFFFFFFF TRANSFERSIZE Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller. [11:0] SBSIZE Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral. [14:12] ENUM SOURCE_BURST_1 Source burst size = 1 0x0 SOURCE_BURST_4 Source burst size = 4 0x1 SOURCE_BURST_8 Source burst size = 8 0x2 SOURCE_BURST_16 Source burst size = 16 0x3 SOURCE_BURST_32 Source burst size = 32 0x4 SOURCE_BURST_64 Source burst size = 64 0x5 SOURCE_BURST_128 Source burst size = 128 0x6 SOURCE_BURST_256 Source burst size = 256 0x7 DBSIZE Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral. [17:15] ENUM DESTINATION_BURST_1 Destination burst size = 1 0x0 DESTINATION_BURST_4 Destination burst size = 4 0x1 DESTINATION_BURST_8 Destination burst size = 8 0x2 DESTINATION_BURST_16 Destination burst size = 16 0x3 DESTINATION_BURST_32 Destination burst size = 32 0x4 DESTINATION_BURST_64 Destination burst size = 64 0x5 DESTINATION_BURST_128 Destination burst size = 128 0x6 DESTINATION_BURST_256 Destination burst size = 256 0x7 SWIDTH Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved. [20:18] ENUM BYTE_8_BIT Byte (8-bit) 0x0 HALFWORD_16_BIT Halfword (16-bit) 0x1 WORD_32_BIT Word (32-bit) 0x2 DWIDTH Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved. [23:21] ENUM BYTE_8_BIT Byte (8-bit) 0x0 HALFWORD_16_BIT Halfword (16-bit) 0x1 WORD_32_BIT Word (32-bit) 0x2 S Source AHB master select: [24:24] ENUM AHB_MASTER_0_SELECTE AHB Master 0 selected for source transfer. 0 AHB_MASTER_1_SELECTE AHB Master 1 selected for source transfer. 1 D Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory. [25:25] ENUM AHB_MASTER_0_SELECTE AHB Master 0 selected for destination transfer. 0 AHB_MASTER_1_SELECTE AHB Master 1 selected for destination transfer. 1 SI Source increment: [26:26] ENUM NOT_INCREMENT The source address is not incremented after each transfer. 0 INCREMENT The source address is incremented after each transfer. 1 DI Destination increment: [27:27] ENUM THE_DESTINATION_ADDR The destination address is not incremented after each transfer. 0 THE_DESTINATION_ADDR The destination address is incremented after each transfer. 1 PROT1 Indicates that the access is in user mode or privileged mode: [28:28] ENUM ACCESS_IS_IN_USER_MO Access is in user mode 0 ACCESS_IS_IN_PRIVILE Access is in privileged mode. 1 PROT2 Indicates that the access is bufferable or not bufferable: [29:29] ENUM ACCESS_IS_NOT_BUFFER Access is not bufferable. 0 ACCESS_IS_BUFFERABLE Access is bufferable. 1 PROT3 Indicates that the access is cacheable or not cacheable: [30:30] ENUM ACCESS_IS_NOT_CACHEA Access is not cacheable. 0 ACCESS_IS_CACHEABLE_ Access is cacheable. 1 I Terminal count interrupt enable bit. [31:31] ENUM THE_TERMINAL_COUNT_I The terminal count interrupt is disabled. 0 THE_TERMINAL_COUNT_I The terminal count interrupt is enabled. 1 8 0x20 0-7 C%sCONFIG DMA Channel Configuration Register 0x110 read-write 0x00000000 0xFFFFFFFF E Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared. [0:0] ENUM CHANNEL_DISABLED_ Channel disabled. 0 CHANNEL_ENABLED_ Channel enabled. 1 SRCPERIPHERAL Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details. [5:1] ENUM SOURCE_EQ_SPIFI Source = SPIFI 0x0 SOURCE_EQ_TIMER_0_MAT Source = Timer 0 match 0/UART0 transmit 0x1 SOURCE_EQ_TIMER_0_MAT Source = Timer 0 match 1/UART0 receive 0x2 SOURCE_EQ_TIMER_1_MAT Source = Timer 1 match 0/UART1 transmit 0x3 SOURCE_EQ_TIMER_1_MAT Source = Timer 1 match 1/UART 1 receive 0x4 SOURCE_EQ_TIMER_2_MAT Source = Timer 2 match 0/UART 2 transmit 0x5 SOURCE_EQ_TIMER_2_MAT Source = Timer 2 match 1/UART 2 receive 0x6 SOURCE_EQ_TIMER_3_MAT Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0 0x7 SOURCE_EQ_TIMER_3_MAT Source = Timer 3 match 1/UART3 receive/SCT DMA request 1 0x8 SOURCE_EQ_SSP0_RECEIV Source = SSP0 receive/I2S channel 0 0x9 SOURCE_EQ_SSP0_TRANSM Source = SSP0 transmit/I2S channel 1 0xA SOURCE_EQ_SSP1_RECEIV Source = SSP1 receive 0xB SOURCE_EQ_SSP1_TRANSM Source = SSP1 transmit 0xC SOURCE_EQ_ADC0 Source = ADC0 0xD SOURCE_EQ_ADC1 Source = ADC1 0xE SOURCE_EQ_DAC Source = DAC 0xF DESTPERIPHERAL Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details. [10:6] ENUM DESTINATION_EQ_SPIFI Destination = SPIFI 0x0 DESTINATION_EQ_TIMER_ Destination = Timer 0 match 0/UART0 transmit 0x1 DESTINATION_EQ_TIMER_ Destination = Timer 0 match 1/UART0 receive 0x2 DESTINATION_EQ_TIMER_ Destination = Timer 1 match 0/UART1 transmit 0x3 DESTINATION_EQ_TIMER_ Destination = Timer 1 match 1/UART 1 receive 0x4 DESTINATION_EQ_TIMER_ Destination = Timer 2 match 0/UART 2 transmit 0x5 DESTINATION_EQ_TIMER_ Destination = Timer 2 match 1/UART 2 receive 0x6 DESTINATION_EQ_TIMER_ Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0 0x7 DESTINATION_EQ_TIMER_ Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1 0x8 DESTINATION_EQ_SSP0_R Destination = SSP0 receive/I2S channel 0 0x9 DESTINATION_EQ_SSP0_T Destination = SSP0 transmit/I2S channel 1 0xA DESTINATION_EQ_SSP1_R Destination = SSP1 receive 0xB DESTINATION_EQ_SSP1_T Destination = SSP1 transmit 0xC DESTINATION_EQ_ADC0 Destination = ADC0 0xD DESTINATION_EQ_ADC1 Destination = ADC1 0xE DESTINATION_EQ_DAC Destination = DAC 0xF FLOWCNTRL Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field. [13:11] ENUM MEMORY_TO_MEMORY Memory to memory (DMA control) 0x0 MEMORY_TO_PERIPHERAL Memory to peripheral (DMA control) 0x1 PERIPHERAL_TO_MEMORY Peripheral to memory (DMA control) 0x2 SOURCE_PERIPHERAL_TO Source peripheral to destination peripheral (DMA control) 0x3 SOURCE_PERIPHERAL_TO Source peripheral to destination peripheral (destination control) 0x4 MEMORY_TO_PERIPHERAL Memory to peripheral (peripheral control) 0x5 PERIPHERAL_TO_MEMORY Peripheral to memory (peripheral control) 0x6 SOURCE_PERIPHERAL_TO Source peripheral to destination peripheral (source control) 0x7 IE Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. [14:14] ITC Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. [15:15] L Lock. When set, this bit enables locked transfers. [16:16] A Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit. [17:17] H Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel. [18:18] ENUM ENABLE_DMA_REQUESTS_ Enable DMA requests. 0 IGNORE_FURTHER_SOURC Ignore further source DMA requests. 1 RESERVED Reserved, do not modify, masked on read. [31:19] SPIFI SPI Flash Interface (SPIFI) SPIFI 0x40003000 0x0 0xFFF registers SPIFI 30 CTRL SPIFI control register 0x000 read-write 0x400FFFFF 0xFFFFFFFF TIMEOUT This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again. [15:0] CSHIGH This field controls the minimum CS high time, expressed as a number of serial clock periods minus one. [19:16] RESERVED Reserved. [20:20] D_PRFTCH_DIS This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses. [21:21] INTEN If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details. [22:22] MODE3 SPI Mode 3 select. [23:23] ENUM SCK_LOW SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH. 0 SCK_HIGH SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame. 1 RESERVED Reserved. [26:24] PRFTCH_DIS Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines. [27:27] ENUM ENABLE Enable. Cache prefetching enabled. 0 DISABLE Disable. Disables prefetching of cache lines. 1 DUAL Select dual protocol. [28:28] ENUM QUAD_PROTOCOL Quad protocol. This protocol uses IO3:0. 0 DUAL_PROTOCOL Dual protocol. This protocol uses IO1:0. 1 RFCLK Select active clock edge for input data. [29:29] ENUM RISING_EDGE Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation. 0 FALLING_EDGE Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame. 1 FBCLK Feedback clock select. [30:30] ENUM INTERNAL_CLOCK Internal clock. The SPIFI samples read data using an internal clock. 0 FEEDBACK_CLOCK Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame. 1 DMAEN A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode. [31:31] CMD SPIFI command register 0x004 read-write 0x00000000 0xFFFFFFFF DATALEN Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field. [13:0] POLL This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs [14:14] DOUT If the DATALEN field is not zero, this bit controls the direction of the data: [15:15] ENUM INPUT_FROM_SERIAL_FL Input from serial flash. 0 OUTPUT_TO_SERIAL_FLA Output to serial flash. 1 INTLEN This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes. [18:16] FIELDFORM This field controls how the fields of the command are sent. [20:19] ENUM ALL_SERIAL All serial. All fields of the command are serial. 0x0 QUADDUAL_DATA Quad/dual data. Data field is quad/dual, other fields are serial. 0x1 SERIAL_OPCODE Serial opcode. Opcode field is serial. Other fields are quad/dual. 0x2 ALL_QUADDUAL All quad/dual. All fields of the command are in quad/dual format. 0x3 FRAMEFORM This field controls the opcode and address fields. [23:21] ENUM RESERVED Reserved. 0x0 OPCODE Opcode. Opcode only, no address. 0x1 OPCODE_ONE_BYTE Opcode one byte. Opcode, least significant byte of address. 0x2 OPCODE_TWO_BYTES Opcode two bytes. Opcode, two least significant bytes of address. 0x3 OPCODE_THREE_BYTES Opcode three bytes. Opcode, three least significant bytes of address. 0x4 OPCODE_FOUR_BYTES Opcode four bytes. Opcode, 4 bytes of address. 0x5 NO_OPCODE_THREE_BYTE No opcode three bytes. No opcode, 3 least significant bytes of address. 0x6 NO_OPCODE_FOUR_BYTES No opcode four bytes. No opcode, 4 bytes of address. 0x7 OPCODE The opcode of the command (not used for some FRAMEFORM values). [31:24] ADDR SPIFI address register 0x008 read-write 0x00000000 0xFFFFFFFF ADDRESS Address. [31:0] IDATA SPIFI intermediate data register 0x00C read-write 0x00000000 0xFFFFFFFF IDATA Value of intermediate bytes. [31:0] CLIMIT SPIFI cache limit register 0x010 read-write 0x08000000 0xFFFFFFFF CLIMIT Zero-based upper limit of cacheable memory [31:0] DATA SPIFI data register 0x014 read-write 0x00000000 0xFFFFFFFF DATA Input or output data [31:0] MCMD SPIFI memory command register 0x018 read-write 0x00000000 0xFFFFFFFF RESERVED Reserved. [13:0] POLL This bit should be written as 0. [14:14] DOUT This bit should be written as 0. [15:15] INTLEN This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes. [18:16] FIELDFORM This field controls how the fields of the command are sent. [20:19] ENUM ALL_SERIAL All serial. All fields of the command are serial. 0x0 QUADDUAL_DATA Quad/dual data. Data field is quad/dual, other fields are serial. 0x1 SERIAL_OPCODE Serial opcode. Opcode field is serial. Other fields are quad/dual. 0x2 ALL_QUADDUAL All quad/dual. All fields of the command are in quad/dual format. 0x3 FRAMEFORM This field controls the opcode and address fields. [23:21] ENUM RESERVED Reserved. 0x0 RESERVED Reserved. 0x1 OPCODE_ONE_BYTE Opcode one byte. Opcode, least-significant byte of address. 0x2 OPCODE_TWO_BYTES Opcode two bytes. Opcode, 2 least-significant bytes of address. 0x3 OPCODE_THREE_BYTES Opcode three bytes. Opcode, 3 least-significant bytes of address. 0x4 OPCODE_FOUR_BYTES Opcode four bytes. Opcode, 4 bytes of address. 0x5 NO_OPCODE_THREE_BYTE No opcode three bytes. No opcode, 3 least-significant bytes of address. 0x6 NO_OPCODE_FOUR_BYTES No opcode, 4 bytes of address. 0x7 OPCODE The opcode of the command (not used for some FRAMEFORM values). [31:24] STAT SPIFI status register 0x01C read-write 0x02000000 0xFFFFFFFF MCINIT This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register. [0:0] CMD This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash. [1:1] RESET Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register. [4:4] INTRQ This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS. [5:5] RESERVED Reserved [23:6] VERSION The SPIFI hardware described in this chapter returns [31:24] SDMMC SD/MMC SDMMC 0x40004000 0x0 0xFFF registers SDIO 6 CTRL Control Register 0x000 read-write 0 0xFFFFFFFF CONTROLLER_RESET Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets: - BIU/CIU interface - CIU and state machines - abort_read_data, send_irq_response, and read_wait bits of Control register - start_cmd bit of Command register Does not affect any registers or DMA interface, or FIFO. or host interrupts. [0:0] ENUM NO_CHANGE No change. 0 RESET Reset. Reset SD/MMC controller 1 FIFO_RESET Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks. [1:1] ENUM NO_CHANGE No change. 0 RESET Reset. Reset to data FIFO To reset FIFO pointers 1 DMA_RESET Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks. [2:2] ENUM NO_CHANGE No change. 0 RESET Reset. Reset internal DMA interface control logic 1 RESERVED Reserved [3:3] INT_ENABLE Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set. [4:4] ENUM DISABLE_INTERRUPTS Disable interrupts 0 ENABLE_INTERRUPTS Enable interrupts 1 RESERVED Reserved. Always write this bit as 0. [5:5] READ_WAIT Read/wait. For sending read-wait to SDIO cards. [6:6] ENUM CLEAR_READ_WAIT Clear read wait 0 ASSERT_READ_WAIT Assert read wait 1 SEND_IRQ_RESPONSE Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state. [7:7] ENUM NO_CHANGE No change 0 SEND_AUTO_IRQ_RESPON Send auto IRQ response 1 ABORT_READ_DATA Abort read data. Used in SDIO card suspend sequence. [8:8] ENUM NO_CHANGE No change 0 ABORT Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence. 1 SEND_CCSD Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked. NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS. [9:9] ENUM CLEAR_BIT Clear bit if the SD/MMC controller does not reset the bit. 0 SEND_COMMAND_COMPLET Send Command Completion Signal Disable (CCSD) to CE-ATA device 1 SEND_AUTO_STOP Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit. [10:10] ENUM CLEAR_THIS_BIT_IF_TH Clear this bit if the SD/MMC controller does not reset the bit. 0 SEND_INTERNALLY_GENE Send internally generated STOP after sending CCSD to CE-ATA device. 1 CEATA_DEVICE_INTERRUPT_STATUS CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit. [11:11] ENUM DISABLED Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register) 0 ENABLED Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register) 1 RESERVED Reserved [15:12] CARD_VOLTAGE_A0 Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented. [16:16] CARD_VOLTAGE_A1 Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented. [17:17] CARD_VOLTAGE_A2 Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented. [18:18] RESERVED Reserved. [23:19] RESERVED Reserved. Always write this bit as 0. [24:24] USE_INTERNAL_DMAC SD/MMC DMA use. [25:25] ENUM HOST Host. The host performs data transfers through the slave interface 0 DMA DMA. Internal DMA used for data transfer 1 RESERVED Reserved [31:26] PWREN Power Enable Register 0x004 read-write 0 0xFFFFFFFF POWER_ENABLE Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card. 0 - power off 1 - power on Optional feature: port can be used as general-purpose output on the SD_POW pin. [0:0] RESERVED Reserved [31:1] CLKDIV Clock Divider Register 0x008 read-write 0 0xFFFFFFFF CLK_DIVIDER0 Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. [7:0] CLK_DIVIDER1 Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. [15:8] CLK_DIVIDER2 Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. [23:16] CLK_DIVIDER3 Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. [31:24] CLKSRC SD Clock Source Register 0x00C read-write 0 0xFFFFFFFF CLK_SOURCE Clock divider source for SD card. 00 - Clock divider 0 01 - Clock divider 1 10 - Clock divider 2 11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented. [1:0] RESERVED Reserved [31:1] CLKENA Clock Enable Register 0x010 read-write 0 0xFFFFFFFF CCLK_ENABLE Clock-enable control for SD card clock. One MMC card clock supported. 0 - Clock disabled 1 - Clock enabled [0:0] RESERVED Reserved [15:1] CCLK_LOW_POWER Low-power control for SD card clock. One MMC card clock supported. 0 - Non-low-power mode 1 - Low-power mode; stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped). [16:16] RESERVED Reserved [31:17] TMOUT Time-out Register 0x014 read-write 0 0x00000000 RESPONSE_TIMEOUT Response time-out value. Value is in number of card output clocks - cclk_out. [7:0] DATA_TIMEOUT Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. [31:8] CTYPE Card Type Register 0x018 read-write 0 0xFFFFFFFF CARD_WIDTH0 Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0). [0:0] RESERVED Reserved [15:1] CARD_WIDTH1 Indicates if card is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. [16:16] RESERVED Reserved [31:17] BLKSIZ Block Size Register 0x01C read-write 0x200 0xFFFFFFFF BLOCK_SIZE Block size [15:0] RESERVED Reserved [31:16] BYTCNT Byte Count Register 0x020 read-write 0x200 0xFFFFFFFF BYTE_COUNT Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer. [31:0] INTMASK Interrupt Mask Register 0x024 read-write 0 0x00000000 CDET Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [0:0] RE Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [1:1] CDONE Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [2:2] DTO Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [3:3] TXDR Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [4:4] RXDR Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [5:5] RCRC Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [6:6] DCRC Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [7:7] RTO Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [8:8] DRTO Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [9:9] HTO Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [10:10] FRUN FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [11:11] HLE Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [12:12] SBE Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [13:13] ACD Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [14:14] EBE End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt. [15:15] SDIO_INT_MASK Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0. [16:16] RESERVED Reserved [31:17] CMDARG Command Argument Register 0x028 read-write 0x00000000 0xFFFFFFFF CMD_ARG Value indicates command argument to be passed to card. [31:0] CMD Command Register 0x02C read-write 0x00000000 0xFFFFFFFF CMD_INDEX Command index [5:0] RESPONSE_EXPECT Response expect [6:6] ENUM NONE None. No response expected from card 0 EXPECTED Expected. Response expected from card 1 RESPONSE_LENGTH Response length [7:7] ENUM SHORT Short. Short response expected from card 0 LONG Long. Long response expected from card 1 CHECK_RESPONSE_CRC Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller. [8:8] ENUM DO_NOT_CHECK_RESPONS Do not check response CRC 0 CHECK_RESPONSE_CRC Check response CRC 1 DATA_EXPECTED Data expected [9:9] ENUM NONE None. No data transfer expected (read/write) 0 DATA Data. Data transfer expected (read/write) 1 READ_WRITE read/write. Don't care if no data expected from card. [10:10] ENUM READ_FROM_CARD Read from card 0 WRITE_TO_CARD Write to card 1 TRANSFER_MODE Transfer mode. Don't care if no data expected. [11:11] ENUM BLOCK_DATA_TRANSFER Block data transfer command 0 STREAM_DATA_TRANSFER Stream data transfer command 1 SEND_AUTO_STOP Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine: - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands - open-ended transfers that software should explicitly send to stop command Additionally, when resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card. [12:12] ENUM NO_STOP_COMMAND_SENT No stop command sent at end of data transfer 0 SEND_STOP_COMMAND_AT Send stop command at end of data transfer 1 WAIT_PRVDATA_COMPLETE Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command. [13:13] ENUM SEND Send. Send command at once, even if previous data transfer has not completed. 0 WAIT Wait. Wait for previous data transfer completion before sending command. 1 STOP_ABORT_CMD Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot. [14:14] ENUM DISABLED Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0. 0 ENABLED Enabled. Stop or abort command intended to stop current data transfer in progress. 1 SEND_INITIALIZATION Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory). [15:15] ENUM NO No. Do not send initialization sequence (80 clocks of 1) before sending this command. 0 SEND Send. Send initialization sequence before sending this command. 1 RESERVED Reserved. Always write as 0. [20:16] UPDATE_CLOCK_REGISTERS_ONLY Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. [21:21] ENUM NORMAL Normal. Normal command sequence 0 NO No. Do not send commands, just update clock register value into card clock domain 1 READ_CEATA_DEVICE Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device. [22:22] ENUM NO_READ No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device. 0 READ Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. 1 CCS_EXPECTED CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked. [23:23] ENUM DISABLED Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device. 0 ENABLED Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. 1 ENABLE_BOOT Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together. [24:24] EXPECT_BOOT_ACK Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card. [25:25] DISABLE_BOOT Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together. [26:26] BOOT_MODE Boot Mode [27:27] ENUM MANDATORY_BOOT_OPERA Mandatory Boot operation 0 ALTERNATE_BOOT_OPERA Alternate Boot operation 1 VOLT_SWITCH Voltage switch bit [28:28] ENUM DISABLED Disabled. No voltage switching 0 ENABLED Enabled. Voltage switching enabled; must be set for CMD11 only 1 RESERVED Reserved [30:29] START_CMD Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register. [31:31] RESP0 Response Register 0 0x030 read-only 0x00000000 0xFFFFFFFF RESPONSE0 Bit[31:0] of response [31:0] RESP1 Response Register 1 0x034 read-only 0x00000000 0xFFFFFFFF RESPONSE1 Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always short for them. For information on when CIU sends auto-stop commands, refer to Auto-Stop . [31:0] RESP2 Response Register 2 0x038 read-only 0 0xFFFFFFFF RESPONSE2 Bit[95:64] of long response [31:0] RESP3 Response Register 3 0x03C read-only 0 0xFFFFFFFF RESPONSE3 Bit[127:96] of long response [31:0] MINTSTS Masked Interrupt Status Register 0x040 read-only 0 0xFFFFFFFF CDET Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set. [0:0] RE Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set. [1:1] CDONE Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set. [2:2] DTO Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set. [3:3] TXDR Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set. [4:4] RXDR Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set. [5:5] RCRC Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set. [6:6] DCRC Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set. [7:7] RTO Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set. [8:8] DRTO Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set. [9:9] HTO Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set. [10:10] FRUN FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set. [11:11] HLE Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set. [12:12] SBE Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set. [13:13] ACD Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set. [14:14] EBE End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set. [15:15] SDIO_INTERRUPT Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt). 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, this bit is always 0. [16:16] RESERVED Reserved [31:17] RINTSTS Raw Interrupt Status Register 0x044 read-write 0 0xFFFFFFFF CDET Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [0:0] RE Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [1:1] CDONE Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [2:2] DTO Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [3:3] TXDR Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [4:4] RXDR Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [5:5] RCRC Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [6:6] DCRC Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [7:7] RTO_BAR Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [8:8] DRTO_BDS Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [9:9] HTO Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int [10:10] FRUN FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [11:11] HLE Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [12:12] SBE Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [13:13] ACD Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [14:14] EBE End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status. [15:15] SDIO_INTERRUPT Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact. 0 - No SDIO interrupt from card 1 - SDIO interrupt from card In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status. [16:16] RESERVED Reserved. [31:17] STATUS Status Register 0x048 read-only 0 0x00000000 FIFO_RX_WATERMARK FIFO reached Receive watermark level; not qualified with data transfer. [0:0] FIFO_TX_WATERMARK FIFO reached Transmit watermark level; not qualified with data transfer. [1:1] FIFO_EMPTY FIFO is empty status [2:2] FIFO_FULL FIFO is full status [3:3] CMDFSMSTATES Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are: - Bit 16 - Wait for CCS - Bit 17 - Send CCSD - Bit 18 - Boot Mode Due to this, while command FSM is in Wait for CCS state or Send CCSD or Boot Mode, the Status register indicates status as 0 for the bit field 7:4. [7:4] DATA_3_STATUS Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present [8:8] DATA_BUSY Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy [9:9] DATA_STATE_MC_BUSY Data transmit or receive state-machine is busy [10:10] RESPONSE_INDEX Index of previous response, including any auto-stop sent by core. [16:11] FIFO_COUNT FIFO count - Number of filled locations in FIFO [29:17] DMA_ACK DMA acknowledge signal state [30:30] DMA_REQ DMA request signal state [31:31] FIFOTH FIFO Threshold Watermark Register 0x04C read-write 0x0F800000 0xFFFFFFFF TX_WMARK FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark >= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2). [11:0] RESERVED Reserved. [15:12] RX_WMARK FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1) NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out. [27:16] DMA_MTS Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH Allowed combinations for MSize and TX_WMark are: MSize = 1, TX_WMARK = 1-15 MSize = 4, TX_WMark = 8 MSize = 4, TX_WMark = 4 MSize = 4, TX_WMark = 12 MSize = 8, TX_WMark = 8 MSize = 8, TX_WMark = 4. Allowed combinations for MSize and RX_WMark are: MSize = 1, RX_WMARK = 0-14 MSize = 4, RX_WMark = 3 MSize = 4, RX_WMark = 7 MSize = 4, RX_WMark = 11 MSize = 8, RX_WMark = 7 MSize = 8, RX_WMark = 11 Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7 [30:28] ENUM 1_TRANSFER 1 transfer 0x0 4_TRANSFERS 4 transfers 0x1 8_TRANSFERS 8 transfers 0x2 16_TRANSFERS 16 transfers 0x3 32_TRANSFERS 32 transfers 0x4 64_TRANSFERS 64 transfers 0x5 128_TRANSFERS 128 transfers 0x6 256_TRANSFERS 256 transfers 0x7 RESERVED Reserved [31:31] CDETECT Card Detect Register 0x050 read-only 0 0x00000000 CARD_DETECT Card detect. 0 represents presence of card. [0:0] RESERVED Reserved [31:1] WRTPRT Write Protect Register 0x054 read-only 0 0x00000000 WRITE_PROTECT Write protect. 1 represents write protection. [0:0] RESERVED Reserved [31:1] TCBCNT Transferred CIU Card Byte Count Register 0x05C read-only 0x00000000 0xFFFFFFFF TRANS_CARD_BYTE_COUNT Number of bytes transferred by CIU unit to card. Register should be read only after data transfer completes; during data transfer, register returns 0. [31:0] TBBCNT Transferred Host to BIU-FIFO Byte Count Register 0x060 read-only 0 0xFFFFFFFF TRANS_FIFO_BYTE_COUNT Number of bytes transferred between Host/DMA memory and BIU FIFO. [31:0] DEBNCE Debounce Count Register 0x064 read-write 0 0x00000000 DEBOUNCE_COUNT Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. [23:0] RESERVED Reserved [31:24] RST_N Hardware Reset 0x078 read-write 0 0x00000000 CARD_RESET Hardware reset. 1 - Active mode 0 - Reset Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized. [0:0] RESERVED Reserved [31:1] BMOD Bus Mode Register 0x080 read-write 0x00000000 0xFFFFFFFF SWR Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle. [0:0] FB Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write. [1:1] DSL Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write. [6:2] DE SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write. [7:7] PBL Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value. [10:8] ENUM 1_TRANSFER 1 transfer 0x0 4_TRANSFERS 4 transfers 0x1 8_TRANSFERS 8 transfers 0x2 16_TRANSFERS 16 transfers 0x3 32_TRANSFERS 32 transfers 0x4 64_TRANSFERS 64 transfers 0x5 128_TRANSFERS 128 transfers 0x6 256_TRANSFERS 256 transfers 0x7 RESERVED Reserved [31:11] PLDMND Poll Demand Register 0x084 write-only 0x00000000 0xFFFFFFFF PD Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only. [31:0] DBADDR Descriptor List Base Address Register 0x088 read-write 0x00000000 0xFFFFFFFF SDL Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only. [31:0] IDSTS Internal DMAC Status Register 0x08C read-write 0x00000000 0xFFFFFFFF TI Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit. [0:0] RI Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit. [1:1] FBE Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit. [2:2] RESERVED Reserved [3:3] DU Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit. [4:4] CES Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits: EBE - End Bit Error RTO - Response Time-out/Boot Ack Time-out RCRC - Response CRC SBE - Start Bit Error DRTO - Data Read Time-out/BDS time-out DCRC - Data CRC for Receive RE - Response Error Writing a 1 clears this bit. [5:5] RESERVED Reserved [7:6] NIS Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit. [8:8] AIS Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit. [9:9] EB Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt. 001 - Host Abort received during transmission 010 - Host Abort received during reception Others: Reserved EB is read-only. [12:10] FSM DMAC state machine present state. 0 - DMA_IDLE 1 - DMA_SUSPEND 2 - DESC_RD 3 - DESC_CHK 4 - DMA_RD_REQ_WAIT 5 - DMA_WR_REQ_WAIT 6 - DMA_RD 7 - DMA_WR 8 - DESC_CLOSE This bit is read-only. [16:13] RESERVED Reserved [31:17] IDINTEN Internal DMAC Interrupt Enable Register 0x090 read-write 0x00000000 0xFFFFFFFF TI Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. [0:0] RI Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. [1:1] FBE Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. [2:2] RESERVED Reserved [3:3] DU Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. [4:4] CES Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary. [5:5] RESERVED Reserved [7:6] NIS Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt [8:8] AIS Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt [9:9] RESERVED Reserved [31:10] DSCADDR Current Host Descriptor Address Register 0x094 read-only 0x00000000 0xFFFFFFFF HDA Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the SD/MMC DMA. [31:0] BUFADDR Current Buffer Descriptor Address Register 0x098 read-only 0x00000000 0xFFFFFFFF HBA Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the SD/MMC DMA. [31:0] EMC External Memory Controller (EMC) EMC 0x40005000 0 0xFFF registers CONTROL Controls operation of the memory controller. 0x000 read-write 0x3 0xFFFFFFFF E EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1] [0:0] ENUM DISABLED Disabled 0 ENABLED Enabled. (POR and warm reset value). 1 M Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed. [1:1] ENUM NORMAL Normal. Normal memory map. 0 RESET Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value). 1 L Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1] [2:2] ENUM NORMAL Normal. Normal mode (warm reset value). 0 LOW_POWER_MODE Low-power mode. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] STATUS Provides EMC status information. 0x004 read-only 0x5 0xFFFFFFFF B Busy indicator. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not: [0:0] ENUM IDLE Idle. EMC is idle (warm reset value). 0 BUSY Busy. EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value). 1 S Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly: [1:1] ENUM EMPTY Empty. Write buffers empty (POR reset value) 0 DATA Data. Write buffers contain data. 1 SA Self-refresh acknowledge. This bit indicates the operating mode of the EMC: [2:2] ENUM NORMAL_MODE Normal mode. 0 SELF_REFRESH_MODE Self-refresh mode. (POR reset value.) 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] CONFIG Configures operation of the memory controller. 0x008 read-write 0 0xFFFFFFFF EM Endian mode. [0:0] ENUM LITTLE_ENDIAN_MODE Little-endian mode. (POR reset value.) 0 BIG_ENDIAN_MODE Big-endian mode. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:1] RESERVED Reserved. Always write a 0 to this bit. [8:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:9] DYNAMICCONTROL Controls dynamic memory operation. 0x020 read-write 0x6 0xFFFFFFFF CE Dynamic memory clock enable. [0:0] ENUM DISABLED Disabled. Clock enable of idle devices are deasserted to save power (POR reset value). 0 ENABLED Enabled. All clock enables are driven HIGH continuously.[1] 1 CS Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode. [1:1] ENUM STOP Stop. CLKOUT stops when all SDRAMs are idle and during self-refresh mode. 0 RUN Run. CLKOUT runs continuously (POR reset value). 1 SR Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2] [2:2] ENUM NORMAL_MODE Normal mode. 0 SELF_REFRESH Self-refresh. Enter self-refresh mode (POR reset value). 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [4:3] MMC Memory clock control. [5:5] ENUM ENABLED Enabled. CLKOUT enabled (POR reset value). 0 DISABLED Disabled. CLKOUT disabled.[3] 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [6:6] I SDRAM initialization. [8:7] ENUM NORMAL Normal. Issue SDRAM NORMAL operation command (POR reset value). 0x0 MODE Mode. Issue SDRAM MODE command. 0x1 PALL PALL. Issue SDRAM PALL (precharge all) command. 0x2 NOP NOP. Issue SDRAM NOP (no operation) command) 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [13:9] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:14] DYNAMICREFRESH Configures dynamic memory refresh operation. 0x024 read-write 0 0xFFFFFFFF REFRESH Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles [10:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:11] DYNAMICREADCONFIG Configures the dynamic memory read strategy. 0x028 read-write 0 0xFFFFFFFF RD Read data strategy. [1:0] ENUM DO_NOT_USE Do not use. POR reset value. 0x0 HALF Command delayed by 1/2 EMC_CCLK. 0x1 HALFPLUSONE Command delayed by 1/2 EMC_CCLK plus one clock cycle. 0x2 HALFPLUSTWO Command delayed by1/2 EMC_CCLK plus two clock cycles, 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] DYNAMICRP Selects the precharge command period. 0x030 read-write 0xF 0xFFFFFFFF TRP Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICRAS Selects the active to precharge command period. 0x034 read-write 0xF 0xFFFFFFFF TRAS Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICSREX Selects the self-refresh exit time. 0x038 read-write 0xF 0xFFFFFFFF TSREX Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICAPR Selects the last-data-out to active command time. 0x03C read-write 0xF 0xFFFFFFFF TAPR Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICDAL Selects the data-in to active command time. 0x040 read-write 0xF 0xFFFFFFFF TDAL Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICWR Selects the write recovery time. 0x044 read-write 0xF 0xFFFFFFFF TWR Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICRC Selects the active to active command period. 0x048 read-write 0x1F 0xFFFFFFFF TRC Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] DYNAMICRFC Selects the auto-refresh period. 0x04C read-write 0x1F 0xFFFFFFFF TRFC Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] DYNAMICXSR Selects the exit self-refresh to active command time. 0x050 read-write 0x1F 0xFFFFFFFF TXSR Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] DYNAMICRRD Selects the active bank A to active bank B latency. 0x054 read-write 0xF 0xFFFFFFFF TRRD Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DYNAMICMRD Selects the load mode register to active command time. 0x058 read-write 0xF 0xFFFFFFFF TMRD Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] STATICEXTENDEDWAIT Selects time for long static memory read and write transfers. 0x080 read-write 0 0xFFFFFFFF EXTENDEDWAIT Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles. [9:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] 4 0x20 0-3 DYNAMICCONFIG%s Selects the configuration information for dynamic memory chip select 0. 0x100 read-write 0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [2:0] MD Memory device. [4:3] ENUM SDRAM SDRAM (POR reset value). 0x0 RESERVED Reserved. 0x1 RESERVED Reserved. 0x2 RESERVED Reserved. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [6:5] AM0 Address mapping. See Table 382. 000000 = reset value.[1] [12:7] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [13:13] AM1 Address mapping See Table 382. 0 = reset value. [14:14] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [18:15] B Buffer enable. [19:19] ENUM DISABLED Disabled. Buffer disabled for accesses to this chip select (POR reset value). 0 ENABLED Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2] 1 P Write protect. [20:20] ENUM NONE None. Writes not protected (POR reset value). 0 PROTECTED Protected. Writes protected. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:21] 4 0x20 0-3 DYNAMICRASCAS%s Selects the RAS and CAS latencies for dynamic memory chip select 0. 0x104 read-write 0x303 0xFFFFFFFF RAS RAS latency (active to read/write delay). [1:0] ENUM RESERVED Reserved. 0x0 ONE_EMC_CCLK_CYCLE One EMC_CCLK cycle. 0x1 TWO_EMC_CCLK_CYCLES Two EMC_CCLK cycles. 0x2 THREE_EMC_CCLK_CYCLE Three EMC_CCLK cycles (POR reset value). 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:2] CAS CAS latency. [9:8] ENUM RESERVED Reserved. 0x0 ONE_EMC_CCLK_CYCLE One EMC_CCLK cycle. 0x1 TWO_EMC_CCLK_CYCLES Two EMC_CCLK cycles. 0x2 THREE_EMC_CCLK_CYCLE Three EMC_CCLK cycles (POR reset value). 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] 4 0x20 0-3 STATICCONFIG%s Selects the memory configuration for static chip select 0. 0x200 read-write 0 0xFFFFFFFF MW Memory width. [1:0] ENUM 8_BIT 8 bit (POR reset value). 0x0 16_BIT 16 bit. 0x1 32_BIT 32 bit. 0x2 RESERVED Reserved. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [2:2] PM Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally. [3:3] ENUM DISABLED Disabled. (POR reset value.) 0 ENABLED Enabled. Async page mode enabled (page length four). 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] PC Chip select polarity. The value of the chip select polarity on power-on reset is 0. [6:6] ENUM ACTIVE_LOW Active LOW chip select. 0 ACTIVE_HIGH Active HIGH chip select. 1 PB Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal. [7:7] ENUM HIGH High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value). 0 LOW Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW. 1 EW Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1] [8:8] ENUM DISABLED Disabled. Extended wait disabled (POR reset value). 0 ENABLED Enabled. Extended wait enabled. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [18:9] B Buffer enable [2]. [19:19] ENUM DISABLED Disabled. Buffer disabled (POR reset value). 0 ENABLED Enabled. Buffer enabled. 1 P Write protect. [20:20] ENUM NONE None. Writes not protected (POR reset value). 0 PROTECT Protect. Write protected. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:21] 4 0x20 0-3 STATICWAITWEN%s Selects the delay from chip select 0 to write enable. 0x204 read-write 0 0xFFFFFFFF WAITWEN Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK. [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] 4 0x20 0-3 STATICWAITOEN%s Selects the delay from chip select 0 or address change, whichever is later, to output enable. 0x208 read-write 0 0xFFFFFFFF WAITOEN Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK. [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] 4 0x20 0-3 STATICWAITRD%s Selects the delay from chip select 0 to a read access. 0x20C read-write 0x1F 0xFFFFFFFF WAITRD Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] 4 0x20 0-3 STATICWAITPAGE%s Selects the delay for asynchronous page mode sequential accesses for chip select 0. 0x210 read-write 0x1F 0xFFFFFFFF WAITPAGE Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] 4 0x20 0-3 STATICWAITWR%s Selects the delay from chip select 0 to a write access. 0x214 read-write 0x1F 0xFFFFFFFF WAITWR Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] 4 0x20 0-3 STATICWAITTURN%s Selects the number of bus turnaround cycles for chip select 0. 0x218 read-write 0xF 0xFFFFFFFF WAITTURN Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value). [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] USB0 USB0 Host/Device/OTG controller USB0 0x40006000 0 0xFFF registers USB0 8 CAPLENGTH Capability register length 0x100 read-only 0x01000040 0xFFFFFFFF CAPLENGTH Indicates offset to add to the register base address at the beginning of the Operational Register [7:0] HCIVERSION BCD encoding of the EHCI revision number supported by this host controller. [23:8] RESERVED These bits are reserved and should be set to zero. [31:24] HCSPARAMS Host controller structural parameters 0x104 read-only 0x00010011 0xFFFFFFFF N_PORTS Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller. [3:0] PPC Port Power Control. This field indicates whether the host controller implementation includes port power control. [4:4] RESERVED These bits are reserved and should be set to zero. [7:5] N_PCC Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller. [11:8] N_CC Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller. [15:12] PI Port indicators. This bit indicates whether the ports support port indicator control. [16:16] RESERVED These bits are reserved and should be set to zero. [19:17] N_PTT Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller. [23:20] N_TT Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller. [27:24] RESERVED These bits are reserved and should be set to zero. [31:28] HCCPARAMS Host controller capability parameters 0x108 read-only 0x00000006 0xFFFFFFFF ADC 64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported. [0:0] PFL Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous. [1:1] ASP Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. [2:2] IST Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. [7:4] EECP EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list. [15:8] RESERVED These bits are reserved and should be set to zero. [31:16] DCIVERSION Device interface version number 0x120 read-only 0x00000001 0xFFFFFFFF DCIVERSION The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register. [15:0] USBCMD_D USB command (device mode) 0x140 read-write 0x00080000 0xFFFFFFFF RS Run/Stop [0:0] ENUM DETACH Writing a 0 to this bit will cause a detach event. 0 ATTACH Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized. 1 RST Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. [1:1] ENUM RESETCOMPLETE Set to 0 by hardware when the reset process is complete. 0 RESET When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. 1 RESERVED Not used in device mode. [3:2] RESERVED Not used in device mode. [4:4] RESERVED Not used in device mode. [5:5] RESERVED Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results. [6:6] RESERVED Reserved. These bits should be set to 0. [7:7] RESERVED Not used in Device mode. [9:8] RESERVED Reserved.These bits should be set to 0. [10:10] RESERVED Not used in Device mode. [11:11] RESERVED Reserved.These bits should be set to 0. [12:12] SUTW Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10). [13:13] ATDTW Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized. [14:14] RESERVED Not used in device mode. [15:15] ITC Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames. [23:16] RESERVED Reserved [31:24] USBCMD_H USB command (host mode) USBCMD_D 0x140 read-write 0x00080000 0xFFFFFFFF RS Run/Stop [0:0] ENUM HALT When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one). 0 PROCEED When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one. 1 RST Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. [1:1] ENUM RESETCOMPLETE This bit is set to zero by hardware when the reset process is complete. 0 RESET When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior. 1 FS0 Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2. [2:2] FS1 Bit 1 of the Frame List Size bits. See Table 220. [3:3] PSE This bit controls whether the host controller skips processing the periodic schedule. [4:4] ENUM DO_NOT_PROCESS_THE_P Do not process the periodic schedule. 0 USE_THE_PERIODICLIST Use the PERIODICLISTBASE register to access the periodic schedule. 1 ASE This bit controls whether the host controller skips processing the asynchronous schedule. [5:5] ENUM DO_NOT_PROCESS_THE_A Do not process the asynchronous schedule. 0 USE_THE_ASYNCLISTADD Use the ASYNCLISTADDR to access the asynchronous schedule. 1 IAA This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. [6:6] ENUM THE_HOST_CONTROLLER_ The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. 0 SOFTWARE_MUST_WRITE_ Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. 1 RESERVED Reserved [7:7] ASP1_0 Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior. [9:8] RESERVED Reserved. [10:10] ASPE Asynchronous Schedule Park Mode Enable [11:11] ENUM PARK_MODE_IS_DISABLE Park mode is disabled. 0 PARK_MODE_IS_ENABLED Park mode is enabled. 1 RESERVED Reserved. [12:12] RESERVED Not used in Host mode. [13:13] RESERVED Reserved. [14:14] FS2 Bit 2 of the Frame List Size bits. See Table 220. [15:15] ITC Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames. [23:16] RESERVED Reserved [31:24] USBSTS_D USB status (device mode) 0x144 read-write 0x00000000 0xFFFFFFFF UI USB interrupt [0:0] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. 1 UEI USB error interrupt [1:1] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6). 1 PCI Port change detect. [2:2] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively. 1 RESERVED Not used in Device mode. [3:3] RESERVED Reserved. [4:4] AAI Not used in Device mode. [5:5] URI USB reset received [6:6] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. 1 SRI SOF received [7:7] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. 1 SLI DCSuspend [8:8] ENUM ST The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it. 0 CLEAR When a device controller enters a suspend state from an active state, this bit will be set to a one. 1 RESERVED Reserved. Software should only write 0 to reserved bits. [11:9] RESERVED Not used in Device mode. [12:12] RESERVED Not used in Device mode. [13:13] RESERVED Not used in Device mode. [14:14] RESERVED Not used in Device mode. [15:15] NAKI NAK interrupt bit [16:16] ENUM ST This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared. 0 CLEAR It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set. 1 RESERVED Reserved. Software should only write 0 to reserved bits. [17:17] RESERVED Not used in Device mode. [18:18] RESERVED Not used in Device mode. [19:19] RESERVED Reserved. Software should only write 0 to reserved bits. [31:20] USBSTS_H USB status (host mode) USBSTS_D 0x144 read-write 0x00000000 0xFFFFFFFF UI USB interrupt (USBINT) [0:0] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. 1 UEI USB error interrupt (USBERRINT) [1:1] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. 1 PCI Port change detect. [2:2] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. 1 FRI Frame list roll-over [3:3] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6). 1 RESERVED Reserved. [4:4] AAI Interrupt on async advance [5:5] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source. 1 RESERVED Not used by the Host controller. [6:6] SRI SOF received [7:7] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base. 1 RESERVED Not used by the Host controller. [8:8] RESERVED Reserved. [11:9] HCH HCHalted [12:12] ENUM RS The RS bit in USBCMD is set to zero. Set by the host controller. 0 HALT The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error). 1 RCL Reclamation [13:13] ENUM NO_EMPTY_ASYNCHRONOU No empty asynchronous schedule detected. 0 EMPTY_ASYNCHRONOU An empty asynchronous schedule is detected. Set by the host controller. 1 PS Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0). [14:14] ENUM DISABLED The periodic schedule status is disabled. 0 DISABLED The periodic schedule status is enabled. 1 AS Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0). [15:15] ENUM DISABLED Asynchronous schedule status is disabled. 0 DISABLED Asynchronous schedule status is enabled. 1 RESERVED Not used on Host mode. [16:16] RESERVED Reserved. [17:17] UAI USB host asynchronous interrupt (USBHSTASYNCINT) [18:18] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. 1 UPI USB host periodic interrupt (USBHSTPERINT) [19:19] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. 1 RESERVED Reserved. [31:20] USBINTR_D USB interrupt enable (device mode) 0x148 read-write 0x00000000 0xFFFFFFFF UE USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS. [0:0] UEE USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register. [1:1] PCE Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS. [2:2] RESERVED Not used by the Device controller. [3:3] RESERVED Reserved [4:4] RESERVED Not used by the Device controller. [5:5] URE USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit. [6:6] SRE SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit. [7:7] SLE Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit. [8:8] RESERVED Reserved [15:9] NAKE NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated. [16:16] RESERVED Reserved [17:17] RESERVED Not used by the Device controller. [18:18] RESERVED Not used by the Device controller. [19:19] RESERVED Reserved [31:20] USBINTR_H USB interrupt enable (host mode) USBINTR_D 0x148 read-write 0x00000000 0xFFFFFFFF UE USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS. [0:0] UEE USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register. [1:1] PCE Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS. [2:2] FRE Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. [3:3] RESERVED Reserved [4:4] AAE Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit. [5:5] RESERVED Not used by the Host controller. [6:6] SRE If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register. [7:7] RESERVED Not used by the Host controller. [8:8] RESERVED Reserved [15:9] RESERVED Not used by the host controller. [16:16] RESERVED Reserved [17:17] UAIE USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit. [18:18] UPIA USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit. [19:19] RESERVED Reserved [31:20] FRINDEX_D USB frame index (device mode) 0x14C read-write 0x00000000 0xFFFFFFFF FRINDEX2_0 Current micro frame number [2:0] FRINDEX13_3 Current frame number of the last frame transmitted [13:3] RESERVED Reserved [31:14] FRINDEX_H USB frame index (host mode) FRINDEX_D 0x14C read-write 0x00000000 0xFFFFFFFF FRINDEX2_0 Current micro frame number [2:0] FRINDEX12_3 Frame list current index. [12:3] RESERVED Reserved [31:13] DEVICEADDR USB device address (device mode) 0x154 read-write 0x00000000 0xFFFFFFFF RESERVED Reserved [23:0] USBADRA Device address advance [24:24] ENUM INSTANTANEOUS Any write to USBADR are instantaneous. 0 DELAYED When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement. 1 USBADR USB device address [31:25] PERIODICLISTBASE Frame list base address (host mode) DEVICEADDR 0x154 read-write 0x00000000 0xFFFFFFFF RESERVED Reserved [11:0] PERBASE31_12 Base Address (Low) These bits correspond to the memory address signals 31:12. [31:12] ENDPOINTLISTADDR Address of endpoint list in memory 0x158 read-write 0x00000000 0xFFFFFFFF RESERVED reserved [10:0] EPBASE31_11 Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.) [31:11] ASYNCLISTADDR Address of endpoint list in memory ENDPOINTLISTADDR 0x158 read-write 0x00000000 0xFFFFFFFF RESERVED Reserved [4:0] ASYBASE31_5 Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH). [31:5] TTCTRL Asynchronous buffer status for embedded TT (host mode) 0x15C read-write 0x00000000 0xFFFFFFFF RESERVED Reserved. [23:0] TTHA Hub address when FS or LS device are connected directly. [30:24] RESERVED Reserved. [31:31] BURSTSIZE Programmable burst size 0x160 read-write 0x00000000 0xFFFFFFFF RXPBURST Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory. [7:0] TXPBURST Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus. [15:8] RESERVED Reserved. [31:16] TXFILLTUNING Host transmit pre-buffer packet tuning (host mode) 0x164 read-write 0x00000000 0xFFFFFFFF TXSCHOH FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set. [7:0] TXSCHEATLTH Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31. [12:8] RESERVED reserved [15:13] TXFIFOTHRES Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode for OTG and SPH. [21:16] RESERVED reserved [31:22] BINTERVAL Length of virtual frame 0x174 read-write 0x00000000 0xFFFFFFFF BINT bInterval value (see Section 18.7.7) [3:0] RESERVED reserved [31:4] ENDPTNAK Endpoint NAK (device mode) 0x178 read-write 0x00000000 0xFFFFFFFF EPRN0 Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [0:0] EPRN1 Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [1:1] EPRN2 Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [2:2] EPRN3 Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [3:3] EPRN4 Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [4:4] EPRN5 Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [5:5] RESERVED Reserved [15:6] EPTN0 Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [16:16] EPTN1 Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [17:17] EPTN2 Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [18:18] EPTN3 Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [19:19] EPTN4 Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [20:20] EPTN5 Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [21:21] RESERVED reserved [31:22] ENDPTNAKEN Endpoint NAK Enable (device mode) 0x17C read-write 0x00000000 0xFFFFFFFF EPRNE0 Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [0:0] EPRNE1 Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [1:1] EPRNE2 Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [2:2] EPRNE3 Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [3:3] EPRNE4 Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [4:4] EPRNE5 Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [5:5] RESERVED Reserved [15:6] EPTNE0 Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [16:16] EPTNE1 Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [17:17] EPTNE2 Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [18:18] EPTNE3 Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [19:19] EPTNE4 Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [20:20] EPTNE5 Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [21:21] RESERVED Reserved [31:22] PORTSC1_D Port 1 status/control (device mode) 0x184 read-write 0x00000000 0xFFFFFFFF CCS Current connect status [0:0] ENUM DEVICE_NOT_ATTACHED_ Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. 0 DEVICE_ATTACHED__A_ Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register. 1 RESERVED Not used in device mode [1:1] PE Port enable. This bit is always 1. The device port is always enabled. [2:2] PEC Port enable/disable change This bit is always 0. The device port is always enabled. [3:3] RESERVED Reserved [5:4] FPR Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well. [6:6] ENUM NO_RESUME No resume (K-state) detected/driven on port. 0 RESUME_DETECTED Resume detected/driven on port. 1 SUSP Suspend In device mode, this is a read-only status bit . [7:7] ENUM PORT_NOT_IN_SUSPEND_ Port not in suspend state 0 PORT_IN_SUSPEND_STAT Port in suspend state 1 PR Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register. [8:8] ENUM PORT_IS_NOT_IN_THE_R Port is not in the reset state. 0 PORT_IS_IN_THE_RESET Port is in the reset state. 1 HSP High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons. [9:9] ENUM NOT_HIGHSSPEED Host/device connected to the port is not in High-speed mode. 0 HIGHSPEED Host/device connected to the port is in High-speed mode. 1 RESERVED Not used in device mode. [11:10] RESERVED Not used in device mode. [12:12] RESERVED Reserved [13:13] PIC1_0 Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins. [15:14] ENUM OFF Port indicators are off. 0x0 AMBER amber 0x1 GREEN green 0x2 UNDEFINED undefined 0x3 PTC3_0 Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid. [19:16] ENUM TEST_MODE_DISABLE TEST_MODE_DISABLE 0x0 J_STATE J_STATE 0x1 K_STATE K_STATE 0x2 SE0_NAK SE0 (host)/NAK (device) 0x3 PACKET Packet 0x4 FORCE_ENABLE_HS FORCE_ENABLE_HS 0x5 FORCE_ENABLE_FS FORCE_ENABLE_FS 0x6 RESERVED Not used in device mode. This bit is always 0 in device mode. [20:20] RESERVED Not used in device mode. This bit is always 0 in device mode. [21:21] RESERVED Not used in device mode. This bit is always 0 in device mode. [22:22] PHCD PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit. [23:23] ENUM ENABLE Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled). 0 DISABLE Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled). 1 PFSC Port force full speed connect [24:24] ENUM ANYSPEED Port connects at any speed. 0 FULLSPEED Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device. 1 RESERVED reserved [25:25] PSPD Port speed This register field indicates the speed at which the port is operating. [27:26] ENUM FULL_SPEED Full-speed 0x0 INVALID_IN_DEVICE_MO invalid in device mode 0x1 HIGH_SPEED High-speed 0x2 RESERVED Reserved [31:28] PORTSC1_H Port 1 status/control (host mode) PORTSC1_D 0x184 read-write 0x00000000 0xFFFFFFFF CCS Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it. [0:0] ENUM NO_DEVICE_IS_PRESENT No device is present. 0 DEVICE_IS_PRESENT_ON Device is present on the port. 1 CSC Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0 [1:1] ENUM NO_CHANGE_IN_CURRENT No change in current status. 0 CHANGE_IN_CURRENT_ST Change in current status. 1 PE Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0. [2:2] ENUM PORT_DISABLED_ Port disabled. 0 PORT_ENABLED_ Port enabled. 1 PEC Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0, [3:3] ENUM NO_CHANGE_ No change. 0 CHANGED Port enabled/disabled status has changed. 1 OCA Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed. [4:4] ENUM THE_PORT_DOES_NOT_HA The port does not have an over-current condition. 0 THE_PORT_HAS_CURRENT The port has currently an over-current condition. 1 OCC Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position. [5:5] FPR Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0. [6:6] ENUM NO_RESUME No resume (K-state) detected/driven on port. 0 RESUME_DETECTED Resume detected/driven on port. 1 SUSP Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0. [7:7] ENUM PORT_NOT_IN_SUSPEND_ Port not in suspend state 0 PORT_IN_SUSPEND_STAT Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. 1 PR Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0. [8:8] ENUM PORT_IS_NOT_IN_THE_R Port is not in the reset state. 0 PORT_IS_IN_THE_RESET Port is in the reset state. 1 HSP High-speed status [9:9] ENUM NO_HISPEED Host/device connected to the port is not in High-speed mode. 0 HISPEED Host/device connected to the port is in High-speed mode. 1 LS Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS. [11:10] ENUM SE0 SE0 (USB_DP and USB_DM LOW) 0x0 J_STATE J-state (USB_DP HIGH and USB_DM LOW) 0x1 K_STATE K-state (USB_DP LOW and USB_DM HIGH) 0x2 UNDEFINED Undefined 0x3 PP Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port). [12:12] ENUM PORT_POWER_OFF_ Port power off. 0 PORT_POWER_ON_ Port power on. 1 RESERVED Reserved [13:13] PIC1_0 Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0. [15:14] ENUM PORT_INDICATORS_ARE_ Port indicators are off. 0x0 AMBER Amber 0x1 GREEN Green 0x2 UNDEFINED Undefined 0x3 PTC3_0 Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved. [19:16] ENUM TEST_MODE_DISABLE TEST_MODE_DISABLE 0x0 J_STATE J_STATE 0x1 K_STATE K_STATE 0x2 SE0_NAK SE0 (host)/NAK (device) 0x3 PACKET Packet 0x4 FORCE_ENABLE_HS FORCE_ENABLE_HS 0x5 FORCE_ENABLE_FS FORCE_ENABLE_FS 0x6 FORCE_ENABLE_LS FORCE_ENABLE_LS 0x7 WKCN Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0 [20:20] ENUM DISABLES_THE_PORT_TO Disables the port to wake up on device connects. 0 WRITING_THIS_BIT_TO_ Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. 1 WKDC Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0. [21:21] ENUM DISABLES_THE_PORT_TO Disables the port to wake up on device disconnects. 0 WRITING_THIS_BIT_TO_ Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. 1 WKOC Wake on over-current enable (WKOC_E) [22:22] ENUM DISABLES_THE_PORT_TO Disables the port to wake up on over-current events. 0 WRITING_A_ONE_TO_THI Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events. 1 PHCD PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. [23:23] ENUM WRITING_A_0_ENABLES_ Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled). 0 WRITING_A_1_DISABLES Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled). 1 PFSC Port force full speed connect [24:24] ENUM PORT_CONNECTS_AT_ANY Port connects at any speed. 0 WRITING_THIS_BIT_TO_ Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. 1 RESERVED Reserved [25:25] PSPD Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. [27:26] ENUM FULL_SPEED Full-speed 0x0 LOW_SPEED Low-speed 0x1 HIGH_SPEED High-speed 0x2 OTGSC OTG status and control 0x1A4 read-write 0x00000000 0xFFFFFFFF VD VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor. [0:0] VC VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP. [1:1] HAAR Hardware assist auto_reset [2:2] ENUM DISABLED Disabled 0 ENABLE_AUTOMATIC_RES Enable automatic reset after connect on host port. 1 OT OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM. [3:3] DP Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP. [4:4] IDPU ID pull-up. This bit provides control over the pull-up resistor. [5:5] ENUM PULL_UP_OFF_THE_ID_ Pull-up off. The ID bit will not be sampled. 0 PULL_UP_ON_ Pull-up on. 1 HADP Hardware assist data pulse Write a 1 to start data pulse sequence. [6:6] HABA Hardware assist B-disconnect to A-connect [7:7] ENUM DISABLED_ Disabled. 0 ENABLE_AUTOMATIC_B_D Enable automatic B-disconnect to A-connect sequence. 1 ID USB ID [8:8] ENUM A_DEVICE A-device 0 B_DEVICE B-device 1 AVV A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold. [9:9] ASV A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold. [10:10] BSV B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold. [11:11] BSE B-session end Reading 1 indicates that VBUS is below the B-session end threshold. [12:12] MS1T 1 millisecond timer toggle This bit toggles once per millisecond. [13:13] DPS Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port. [14:14] RESERVED reserved [15:15] IDIS USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it. [16:16] AVVIS A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it. [17:17] ASVIS A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it. [18:18] BSVIS B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it. [19:19] BSEIS B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold. Software must write a 1 to this bit to clear it. [20:20] ms1S 1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it. [21:21] DPIS Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it. [22:22] RESERVED reserved [23:23] IDIE USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt. [24:24] AVVIE A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt. [25:25] ASVIE A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt [26:26] BSVIE B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt. [27:27] BSEIE B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt. [28:28] MS1E 1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt. [29:29] DPIE Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt [30:30] RESERVED Reserved [31:31] USBMODE_D USB device mode (device mode) 0x1A8 read-write 0x00000000 0xFFFFFFFF CM1_0 Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. [1:0] ENUM IDLE Idle 0x0 RESERVED Reserved 0x1 DEVICE_CONTROLLER Device controller 0x2 HOST_CONTROLLER Host controller 0x3 ES Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words. [2:2] ENUM LITTLE_ENDIAN_FIRST Little endian: first byte referenced in least significant byte of 32-bit word. 0 BIG_ENDIAN_FIRST_BY Big endian: first byte referenced in most significant byte of 32-bit word. 1 SLOM Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8. [3:3] ENUM SETUP_LOCKOUTS_ON Setup Lockouts on 0 SETUP_LOCKOUTS_OFF Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD) 1 SDIS Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved. [4:4] ENUM NOT_DISABLED Not disabled 0 DISABLED_SETTING_TH Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active. 1 RESERVED Not used in device mode. [5:5] RESERVED reserved [31:6] USBMODE_H USB mode (host mode) USBMODE_D 0x1A8 read-write 0x00000000 0xFFFFFFFF CM Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. [1:0] ENUM IDLE Idle 0x0 RESERVED Reserved 0x1 DEVICE_CONTROLLER Device controller 0x2 HOST_CONTROLLER Host controller 0x3 ES Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words. [2:2] ENUM LITTLE_ENDIAN_FIRST Little endian: first byte referenced in least significant byte of 32-bit word. 0 BIG_ENDIAN_FIRST_BY Big endian: first byte referenced in most significant byte of 32-bit word. 1 RESERVED Not used in host mode [3:3] SDIS Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved. [4:4] ENUM NOT_DISABLED Not disabled 0 DISABLED_SETTING_TO Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature. 1 VBPS VBUS power select [5:5] ENUM LOW vbus_pwr_select is set LOW. 0 HIGH vbus_pwr_select is set HIGH 1 RESERVED reserved [31:6] ENDPTSETUPSTAT Endpoint setup status 0x1AC read-write 0x00000000 0xFFFFFFFF ENDPTSETUPSTAT0 Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged. [0:0] ENDPTSETUPSTAT1 Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged. [1:1] ENDPTSETUPSTAT2 Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged. [2:2] ENDPTSETUPSTAT3 Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged. [3:3] ENDPTSETUPSTAT4 Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged. [4:4] ENDPTSETUPSTAT5 Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged. [5:5] RESERVED reserved [31:6] ENDPTPRIME Endpoint initialization 0x1B0 read-write 0x00000000 0xFFFFFFFF PERB0 Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5 [0:0] PERB1 Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5 [1:1] PERB2 Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5 [2:2] PERB3 Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5 [3:3] PERB4 Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5 [4:4] PERB5 Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5 [5:5] RESERVED reserved [15:6] PETB0 Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5 [16:16] PETB1 Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5 [17:17] PETB2 Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5 [18:18] PETB3 Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5 [19:19] PETB4 Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5 [20:20] PETB5 Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB5 = endpoint 5 [21:21] RESERVED reserved [31:22] ENDPTFLUSH Endpoint de-initialization 0x1B4 read-write 0x00000000 0xFFFFFFFF FERB0 Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5 [0:0] FERB1 Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5 [1:1] FERB2 Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5 [2:2] FERB3 Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5 [3:3] FERB4 Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5 [4:4] FERB5 Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5 [5:5] RESERVED reserved [15:6] FETB0 Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5 [16:16] FETB1 Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5 [17:17] FETB2 Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5 [18:18] FETB3 Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5 [19:19] FETB4 Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5 [20:20] FETB5 Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB5 = endpoint 5 [21:21] RESERVED reserved [31:22] ENDPTSTAT Endpoint status 0x1B8 read-only 0x00000000 0xFFFFFFFF ERBR0 Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5 [0:0] ERBR1 Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5 [1:1] ERBR2 Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5 [2:2] ERBR3 Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5 [3:3] ERBR4 Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5 [4:4] ERBR5 Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5 [5:5] RESERVED reserved [15:6] ETBR0 Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5 [16:16] ETBR1 Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5 [17:17] ETBR2 Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5 [18:18] ETBR3 Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5 [19:19] ETBR4 Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5 [20:20] ETBR5 Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5 [21:21] RESERVED reserved [31:22] ENDPTCOMPLETE Endpoint complete 0x1BC read-write 0x00000000 0xFFFFFFFF ERCE0 Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5 [0:0] ERCE1 Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5 [1:1] ERCE2 Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5 [2:2] ERCE3 Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5 [3:3] ERCE4 Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5 [4:4] ERCE5 Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5 [5:5] RESERVED reserved [15:6] ETCE0 Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5 [16:16] ETCE1 Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5 [17:17] ETCE2 Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5 [18:18] ETCE3 Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5 [19:19] ETCE4 Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5 [20:20] ETCE5 Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5 [21:21] RESERVED reserved [31:22] ENDPTCTRL0 Endpoint control 0 0x1C0 read-write 0x00000000 0xFFFFFFFF RXS Rx endpoint stall [0:0] ENUM ENDPOINT_OK_ Endpoint ok. 0 ENDPOINT_STALLED_SOF Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1] 1 RESERVED reserved [1:1] RXT1_0 Endpoint type Endpoint 0 is always a control endpoint. [3:2] RESERVED reserved [6:4] RXE Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1. [7:7] RESERVED reserved [15:8] TXS Tx endpoint stall [16:16] ENUM ENDPOINT_OK_ Endpoint ok. 0 ENDPOINT_STALLED_SOF Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1] 1 RESERVED reserved [17:17] TXT1_0 Endpoint type Endpoint 0 is always a control endpoint. [19:18] RESERVED reserved [22:20] TXE Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1. [23:23] RESERVED reserved [31:24] 5 0x4 1-5 ENDPTCTRL%s Endpoint control 0x1C4 read-write 0x00000000 0xFFFFFFFF RXS Rx endpoint stall [0:0] ENUM ENDPOINT_OK_THIS_BI Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. 0 ENDPOINT_STALLED_SOF Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. 1 RESERVED Reserved [1:1] RXT Endpoint type [3:2] ENUM CONTROL Control 0x0 ISOCHRONOUS Isochronous 0x1 BULK Bulk 0x2 RESERVED Reserved 0x3 RESERVED Reserved [4:4] RXI Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID. [5:5] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RXR Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device. [6:6] RXE Rx endpoint enable An endpoint should be enabled only after it has been configured. [7:7] ENUM ENDPOINT_DISABLED_ Endpoint disabled. 0 ENDPOINT_ENABLED_ Endpoint enabled. 1 RESERVED reserved [15:8] TXS Tx endpoint stall [16:16] ENUM ENDPOINT_OK_THIS_BI Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. 0 ENDPOINT_STALLED_SOF Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. 1 RESERVED Reserved [17:17] TXT1_0 Tx endpoint type [19:18] ENUM CONTROL Control 0x0 ISOCHRONOUS Isochronous 0x1 BULK Bulk 0x2 INTERRUPT Interrupt 0x3 RESERVED reserved [20:20] TXI Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID. [21:21] ENUM ENABLED Enabled 0 DISABLED Disabled 1 TXR Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device. [22:22] TXE Tx endpoint enable An endpoint should be enabled only after it has been configured [23:23] ENUM ENDPOINT_DISABLED_ Endpoint disabled. 0 ENDPOINT_ENABLED_ Endpoint enabled. 1 RESERVED reserved [31:24] USB1 USB1 Host/Device controller 0x40007000 0 0xFFF registers USB1 9 CAPLENGTH Capability register length 0x100 read-only 0x00010040 0xFFFFFFFF CAPLENGTH Indicates offset to add to the register base address at the beginning of the Operational Register [7:0] HCIVERSION BCD encoding of the EHCI revision number supported by this host controller. [23:8] RESERVED These bits are reserved and should be set to zero. [31:24] HCSPARAMS Host controller structural parameters 0x104 read-only 0x00010011 0xFFFFFFFF N_PORTS Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller. [3:0] PPC Port Power Control. This field indicates whether the host controller implementation includes port power control. [4:4] RESERVED These bits are reserved and should be set to zero. [7:5] N_PCC Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller. [11:8] N_CC Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller. [15:12] PI Port indicators. This bit indicates whether the ports support port indicator control. [16:16] RESERVED These bits are reserved and should be set to zero. [19:17] N_PTT Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller. [23:20] N_TT Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller. [27:24] RESERVED These bits are reserved and should be set to zero. [31:28] HCCPARAMS Host controller capability parameters 0x108 read-only 0x00000005 0xFFFFFFFF ADC 64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported. [0:0] PFL Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous. [1:1] ASP Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. [2:2] IST Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. [7:4] EECP EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list. [15:8] RESERVED These bits are reserved and should be set to zero. [31:16] DCIVERSION Device interface version number 0x120 read-only 0x00000001 0xFFFFFFFF DCIVERSION The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register. [15:0] RESERVED These bits are reserved and should be set to zero. [31:16] USBCMD_D USB command (device mode) 0x140 read-write 0x00040000 0xFFFFFFFF RS Run/Stop [0:0] ENUM DETACH Writing a 0 to this bit will cause a detach event. 0 ATACH Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized. 1 RST Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. [1:1] ENUM RESETCOMPLETE Set to 0 by hardware when the reset process is complete. 0 RESET When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. 1 RESERVED Not used in device mode. [3:2] RESERVED Not used in device mode. [4:4] RESERVED Not used in device mode. [5:5] RESERVED Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results. [6:6] RESERVED Reserved. These bits should be set to 0. [7:7] RESERVED Not used in Device mode. [9:8] RESERVED Reserved.These bits should be set to 0. [10:10] RESERVED Not used in Device mode. [11:11] RESERVED Reserved.These bits should be set to 0. [12:12] SUTW Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10). [13:13] ATDTW Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized. [14:14] FS2 Not used in device mode. [15:15] ITC Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames. [23:16] RESERVED Reserved [31:24] USBCMD_H USB command (host mode) USBCMD_D 0x140 read-write 0x000400B0 0xFFFFFFFF RS Run/Stop [0:0] ENUM HALT When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one). 0 PROCEED When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one. 1 RST Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. [1:1] ENUM RESETCOMPLETE This bit is set to zero by hardware when the reset process is complete. 0 RESET When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior. 1 FS0 Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2. [2:2] FS1 Bit 1 of the Frame List Size bits. See Table 281 [3:3] PSE This bit controls whether the host controller skips processing the periodic schedule. [4:4] ENUM DO_NOT_PROCESS_THE_P Do not process the periodic schedule. 0 USE_THE_PERIODICLIST Use the PERIODICLISTBASE register to access the periodic schedule. 1 ASE This bit controls whether the host controller skips processing the asynchronous schedule. [5:5] ENUM DO_NOT_PROCESS_THE_A Do not process the asynchronous schedule. 0 USE_THE_ASYNCLISTADD Use the ASYNCLISTADDR to access the asynchronous schedule. 1 IAA This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. [6:6] ENUM ST The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. 0 DOORBELL Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. 1 RESERVED Reserved [7:7] ASP1_0 Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior. [9:8] RESERVED Reserved. [10:10] ASPE Asynchronous Schedule Park Mode Enable [11:11] ENUM PARK_MODE_IS_DISABLE Park mode is disabled. 0 PARK_MODE_IS_ENABLED Park mode is enabled. 1 RESERVED Reserved. [12:12] RESERVED Not used in Host mode. [13:13] RESERVED Reserved. [14:14] FS2 Bit 2 of the Frame List Size bits. See Table 281. [15:15] ITC Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames. [23:16] RESERVED Reserved [31:24] USBSTS_D USB status (device mode) 0x144 read-write 0x00000000 0xFFFFFFFF UI USB interrupt [0:0] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. 1 UEI USB error interrupt [1:1] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6). 1 PCI Port change detect. [2:2] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively. 1 RESERVED Not used in Device mode. [3:3] RESERVED Reserved. [4:4] RESERVED Not used in Device mode. [5:5] URI USB reset received [6:6] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. 1 SRI SOF received [7:7] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. 1 SLI DCSuspend [8:8] ENUM ST The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it. 0 CLEAR When a device controller enters a suspend state from an active state, this bit will be set to a one. 1 RESERVED Reserved. Software should only write 0 to reserved bits. [11:9] RESERVED Not used in Device mode. [12:12] RESERVED Not used in Device mode. [13:13] RESERVED Not used in Device mode. [14:14] RESERVED Not used in Device mode. [15:15] NAKI NAK interrupt bit [16:16] ENUM ENDPCLEAR This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared. 0 SET It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set. 1 RESERVED Reserved. Software should only write 0 to reserved bits. [17:17] RESERVED Not used in Device mode. [18:18] RESERVED Not used in Device mode. [19:19] RESERVED Reserved. Software should only write 0 to reserved bits. [31:20] USBSTS_H USB status (host mode) USBSTS_D 0x144 read-write 0x00001000 0xFFFFFFFF UI USB interrupt (USBINT) [0:0] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. 1 UEI USB error interrupt (USBERRINT) [1:1] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. 1 PCI Port change detect. [2:2] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. 1 FRI Frame list roll-over [3:3] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5). 1 RESERVED Reserved. [4:4] AAI Interrupt on async advance [5:5] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source. 1 RESERVED Not used by the Host controller. [6:6] SRI SOF received [7:7] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base. 1 SLI Not used by the Host controller. [8:8] RESERVED Reserved. [11:9] HCH HCHalted [12:12] ENUM RS The RS bit in USBCMD is set to zero. Set by the host controller. 0 STOP The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error). 1 RCL Reclamation [13:13] ENUM NO_EMPTY_ASYNCHRONOU No empty asynchronous schedule detected. 0 EMPTY_ASYNCHRONOU An empty asynchronous schedule is detected. Set by the host controller. 1 PS Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0). [14:14] ENUM DISABLED The periodic schedule status is disabled. 0 ENABLED The periodic schedule status is enabled. 1 AS Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0). [15:15] ENUM DISABLED Asynchronous schedule status is disabled. 0 ENABLED Asynchronous schedule status is enabled. 1 RESERVED Not used on Host mode. [16:16] RESERVED Reserved. [17:17] UAI USB host asynchronous interrupt (USBHSTASYNCINT) [18:18] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. 1 UPI USB host periodic interrupt (USBHSTPERINT) [19:19] ENUM ST This bit is cleared by software writing a one to it. 0 CLEAR This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. 1 RESERVED Reserved. [31:20] USBINTR_D USB interrupt enable (device mode) 0x148 read-write 0x00000000 0xFFFFFFFF UE USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS. [0:0] UEE USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register. [1:1] PCE Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS. [2:2] RESERVED Not used by the Device controller. [3:3] RESERVED Reserved [4:4] RESERVED Not used by the Device controller. [5:5] URE USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit. [6:6] SRE SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit. [7:7] SLE Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit. [8:8] RESERVED Reserved [15:9] NAKE NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated. [16:16] RESERVED Reserved [17:17] UAIE Not used by the Device controller. [18:18] UPIA Not used by the Device controller. [19:19] RESERVED Reserved [31:20] USBINTR_H USB interrupt enable (host mode) USBINTR_D 0x148 read-write 0x00000000 0xFFFFFFFF UE USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS. [0:0] UEE USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register. [1:1] PCE Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS. [2:2] FRE Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. [3:3] RESERVED Reserved [4:4] AAE Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit. [5:5] RESERVED Not used by the Host controller. [6:6] SRE If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register. [7:7] RESERVED Not used by the Host controller. [8:8] RESERVED Reserved [15:9] RESERVED Not used by the host controller. [16:16] RESERVED Reserved [17:17] UAIE USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit. [18:18] UPIA USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit. [19:19] RESERVED Reserved [31:20] FRINDEX_D USB frame index (device mode) 0x14C read-only 0x00000000 0xFFFFFFFF FRINDEX2_0 Current micro frame number [2:0] FRINDEX13_3 Current frame number of the last frame transmitted [13:3] RESERVED Reserved [31:14] FRINDEX_H USB frame index (host mode) FRINDEX_D 0x14C read-write 0x00000000 0xFFFFFFFF FRINDEX2_0 Current micro frame number [2:0] FRINDEX12_3 Frame list current index for 1024 elements. [12:3] RESERVED Reserved [31:13] DEVICEADDR USB device address 0x154 read-write 0x00000000 0xFFFFFFFF RESERVED reserved [23:0] USBADRA Device address advance [24:24] ENUM ADVANCE Any write to USBADR are instantaneous. 0 HOLD When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement. 1 USBADR USB device address [31:25] PERIODICLISTBASE Frame list base address DEVICEADDR 0x154 read-write 0x00000000 0xFFFFFFFF RESERVED Reserved [11:0] PERBASE31_12 Base Address (Low) These bits correspond to the memory address signals[31:12]. [31:12] ENDPOINTLISTADDR Address of endpoint list in memory (device mode) 0x158 read-write 0x00000000 0xFFFFFFFF RESERVED reserved [10:0] EPBASE31_11 Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.) [31:11] ASYNCLISTADDR Address of endpoint list in memory (host mode) ENDPOINTLISTADDR 0x158 read-write 0x00000000 0xFFFFFFFF RESERVED Reserved [4:0] ASYBASE31_5 Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH). [31:5] TTCTRL Asynchronous buffer status for embedded TT (host mode) 0x15C read-write 0x00000000 0xFFFFFFFF RESERVED Reserved. [23:0] TTHA Hub address when FS or LS device are connected directly. [30:24] RESERVED Reserved. [31:31] BURSTSIZE Programmable burst size 0x160 read-write 0x00000000 0xFFFFFFFF RXPBURST Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory. [7:0] TXPBURST Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus. [15:8] RESERVED reserved [31:16] TXFILLTUNING Host transmit pre-buffer packet tuning (host mode) 0x164 read-write 0x00000000 0xFFFFFFFF TXSCHOH FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set. [7:0] TXSCHEATLTH Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31. [12:8] RESERVED Reserved [15:13] TXFIFOTHRES Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267 ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333 ms when a device is connected in Low/Full Speed Mode. [21:16] RESERVED Reserved [31:22] ULPIVIEWPORT ULPI viewport 0x170 read-write 0x00000000 0xFFFFFFFF ULPIDATWR When a write operation is commanded, the data to be sent is written to this field. [7:0] ULPIDATRD After a read operation completes, the result is placed in this field. [15:8] ULPIADDR When a read or write operation is commanded, the address of the operation is written to this field. [23:16] ULPIPORT For the wakeup or read/write operation to be executed, this value must be written as 0. [26:24] ULPISS ULPI sync state. This bit represents the state of the ULPI interface. [27:27] ENUM IN_ANOTHER_STATE In another state (ie. carkit, serial, low power) 0 NORMAL_SYNC_STATE_ Normal Sync. State. 1 RESERVED Reserved [28:28] ULPIRW ULPI Read/Write control. This bit selects between running a read or write operation. [29:29] ENUM READ Read 0 WRITE Write 1 ULPIRUN ULPI Read/Write Run. Writing the 1 to this bit will begin the read/write operation. The bit will automatically transition to 0 after the read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time. [30:30] ULPIWU ULPI Wake-up. Writing the 1 to this bit will begin the wakeup operation. The bit will automatically transition to 0 after the wakeup is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at the same time. [31:31] BINTERVAL Length of virtual frame 0x174 read-write 0x00000000 0xFFFFFFFF BINT bInterval value [3:0] RESERVED Reserved [31:4] ENDPTNAK Endpoint NAK (device mode) 0x178 read-write 0x00000000 0xFFFFFFFF EPRN0 Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [0:0] EPRN1 Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [1:1] EPRN2 Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [2:2] EPRN3 Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [3:3] RESERVED Reserved [15:4] EPTN16 Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [16:16] EPTN17 Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [17:17] EPTN18 Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [18:18] EPTN19 Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [19:19] RESERVED Reserved [31:20] ENDPTNAKEN Endpoint NAK Enable (device mode) 0x17C read-write 0x00000000 0xFFFFFFFF EPRNE0 Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [0:0] EPRNE1 Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [1:1] EPRNE2 Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [2:2] EPRNE3 Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [3:3] RESERVED Reserved [15:4] EPTNE16 Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [16:16] EPTNE17 Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [17:17] EPTNE18 Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [18:18] EPTNE19 Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0. [19:19] RESERVED Reserved [31:20] PORTSC1_D Port 1 status/control (device mode) 0x184 read-write 0x00000000 0xFFFFFFFF CCS Current connect status [0:0] ENUM DEVICE_NOT_ATTACHED_ Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. 0 DEVICE_ATTACHED__A_ Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register. 1 CSC Not used in device mode [1:1] PE Port enable. This bit is always 1. The device port is always enabled. [2:2] PEC Port enable/disable change This bit is always 0. The device port is always enabled. [3:3] RESERVED Reserved [5:4] FPR Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well. [6:6] ENUM NO_RESUME No resume (K-state) detected/driven on port. 0 RESUME_DETECTED Resume detected/driven on port. 1 SUSP Suspend In device mode, this is a read-only status bit . [7:7] ENUM PORT_NOT_IN_SUSPEND_ Port not in suspend state 0 PORT_IN_SUSPEND_STAT Port in suspend state 1 PR Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register. [8:8] ENUM PORT_IS_NOT_IN_THE_R Port is not in the reset state. 0 PORT_IS_IN_THE_RESET Port is in the reset state. 1 HSP High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons. [9:9] ENUM NOHISPEED Host/device connected to the port is not in High-speed mode. 0 HISPEED Host/device connected to the port is in High-speed mode. 1 LS Not used in device mode. [11:10] PP Not used in device mode. [12:12] RESERVED Reserved [13:13] PIC1_0 Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins. [15:14] ENUM OFF Port indicators are off. 0x0 AMBER amber 0x1 GREEN green 0x2 UNDEFINED undefined 0x3 PTC3_0 Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved. [19:16] ENUM TEST_MODE_DISABLE TEST_MODE_DISABLE 0x0 J_STATE J_STATE 0x1 K_STATE K_STATE 0x2 SE0 SE0 (host)/NAK (device) 0x3 PACKET Packet 0x4 FORCE_ENABLE_HS FORCE_ENABLE_HS 0x5 FORCE_ENABLE_FS FORCE_ENABLE_FS 0x6 RESERVED Not used in device mode. This bit is always 0 in device mode. [20:20] RESERVED Not used in device mode. This bit is always 0 in device mode. [21:21] RESERVED Not used in device mode. This bit is always 0 in device mode. [22:22] PHCD PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit. [23:23] ENUM ENABLED Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled). 0 DISABLED Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled). 1 PFSC Port force full speed connect [24:24] ENUM ANYSPEED Port connects at any speed. 0 FULLSPEED Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device. 1 RESERVED Reserved [25:25] PSPD Port speed This register field indicates the speed at which the port is operating. [27:26] ENUM FULL_SPEED Full-speed 0x1 INVALID_IN_DEVICE_MO invalid in device mode 0x2 HIGH_SPEED High-speed 0x3 RESERVED Reserved [29:28] PTS Parallel transceiver select. All other values are reserved. [31:30] ENUM ULPI ULPI 0x2 SERIAL Serial/ 1.1 PHY (Full-speed only) 0x3 PORTSC1_H Port 1 status/control (host mode) PORTSC1_D 0x184 read-write 0x00000000 0xFFFFFFFF CCS Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it. [0:0] ENUM NO_DEVICE_IS_PRESENT No device is present. 0 DEVICE_IS_PRESENT_ON Device is present on the port. 1 CSC Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0 [1:1] ENUM NO_CHANGE_IN_CURRENT No change in current status. 0 CHANGE_IN_CURRENT_ST Change in current status. 1 PE Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0. [2:2] ENUM PORT_DISABLED_ Port disabled. 0 PORT_ENABLED_ Port enabled. 1 PEC Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0, [3:3] ENUM NO_CHANGE_ No change. 0 CHANGED Port enabled/disabled status has changed. 1 OCA Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed. [4:4] ENUM THE_PORT_DOES_NOT_HA The port does not have an over-current condition. 0 THE_PORT_HAS_CURRENT The port has currently an over-current condition. 1 OCC Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position. [5:5] FPR Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0. [6:6] ENUM NO_RESUME No resume (K-state) detected/driven on port. 0 RESUME_DETECTED Resume detected/driven on port. 1 SUSP Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0. [7:7] ENUM PORT_NOT_IN_SUSPEND_ Port not in suspend state 0 PORT_IN_SUSPEND_STAT Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. 1 PR Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0. [8:8] ENUM NOT_IN_RESET Port is not in the reset state. 0 PORT_IS_IN_THE_RESET Port is in the reset state. 1 HSP High-speed status [9:9] ENUM NOHIGHSPEED Host/device connected to the port is not in High-speed mode. 0 HIGHSPEED Host/device connected to the port is in High-speed mode. 1 LS Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS. [11:10] ENUM SE0 SE0 (USB_DP and USB_DM LOW) 0x0 J_STATE J-state (USB_DP HIGH and USB_DM LOW) 0x1 K_STATE K-state (USB_DP LOW and USB_DM HIGH) 0x2 UNDEFINED Undefined 0x3 PP Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port). [12:12] ENUM PORT_POWER_OFF_ Port power off. 0 PORT_POWER_ON_ Port power on. 1 RESERVED Reserved [13:13] PIC1_0 Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0. [15:14] ENUM OFF Port indicators are off. 0x0 AMBER Amber 0x1 GREEN Green 0x2 UNDEFINED Undefined 0x3 PTC3_0 Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved. [19:16] ENUM TEST_MODE_DISABLE TEST_MODE_DISABLE 0x0 J_STATE J_STATE 0x1 K_STATE K_STATE 0x2 SE0_NAK SE0 (host)/NAK (device) 0x3 PACKET Packet 0x4 FORCE_ENABLE_HS FORCE_ENABLE_HS 0x5 FORCE_ENABLE_FS FORCE_ENABLE_FS 0x6 FORCE_ENABLE_LS FORCE_ENABLE_LS 0x7 WKCN Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0 [20:20] ENUM DISABLES_THE_PORT_TO Disables the port to wake up on device connects. 0 ENABLE_DEVICE_CON Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. 1 WKDC Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0. [21:21] ENUM DISABLES_THE_PORT_TO Disables the port to wake up on device disconnects. 0 ENABLE_DEVICE_CON Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. 1 WKOC Wake on over-current enable (WKOC_E) [22:22] ENUM DISABLES_OVERCURRENT Disables the port to wake up on over-current events. 0 ENABLE_OVERCURRENT Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events. 1 PHCD PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. [23:23] ENUM ENABLE_PHY_CLK Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled). 0 DISABLE_PHY_CLK Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled). 1 PFSC Port force full speed connect [24:24] ENUM ANYSPEED Port connects at any speed. 0 FULLSPEED Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. 1 RESERVED Reserved [25:25] PSPD Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. [27:26] ENUM FULL_SPEED Full-speed 0x0 LOW_SPEED Low-speed 0x1 HIGH_SPEED High-speed 0x2 RESERVED Reserved [29:28] PTS Parallel transceiver select. All other values are reserved. [31:30] ENUM ULPI ULPI 0x2 SERIAL Serial/ 1.1 PHY (Full-speed only) 0x3 USBMODE_D USB mode (device mode) 0x1A8 read-write 0x00000000 0xFFFFFFFF CM1_0 Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. [1:0] ENUM IDLE Idle 0x0 RESERVED Reserved 0x1 DEVICE_CONTROLLER Device controller 0x2 HOST_CONTROLLER Host controller 0x3 ES Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words. [2:2] ENUM LITTLE_ENDIAN_FIRST Little endian: first byte referenced in least significant byte of 32-bit word. 0 BIG_ENDIAN_FIRST_BY Big endian: first byte referenced in most significant byte of 32-bit word. 1 SLOM Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8. [3:3] ENUM SETUP_LOCKOUTS_ON Setup Lockouts on 0 SETUP_LOCKOUTS_OFF Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD) 1 SDIS Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved. [4:4] ENUM NOT_DISABLED Not disabled 0 DISABLED_SETTING_TH Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active. 1 RESERVED Not used in device mode. [5:5] RESERVED Reserved [31:6] USBMODE_H USB mode (host mode) USBMODE_D 0x1A8 read-write 0x00000000 0xFFFFFFFF CM1_0 Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. [1:0] ENUM IDLE Idle 0x0 RESERVED Reserved 0x1 DEVICE_CONTROLLER Device controller 0x2 HOST_CONTROLLER Host controller 0x3 ES Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words. [2:2] ENUM LITTLE_ENDIAN_FIRST Little endian: first byte referenced in least significant byte of 32-bit word. 0 BIG_ENDIAN_FIRST_BY Big endian: first byte referenced in most significant byte of 32-bit word. 1 RESERVED Not used in host mode [3:3] SDIS Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved. [4:4] ENUM NOT_DISABLED Not disabled 0 DISABLED_SETTING_TO Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature. 1 VBPS VBUS power select [5:5] ENUM LOW vbus_pwr_select is set LOW. 0 HIGH vbus_pwr_select is set HIGH 1 RESERVED Reserved [31:6] ENDPTSETUPSTAT Endpoint setup status 0x1AC read-write 0x00000000 0xFFFFFFFF ENDPTSETUPSTAT0 Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged. [0:0] ENDPTSETUPSTAT1 Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged. [1:1] ENDPTSETUPSTAT2 Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged. [2:2] ENDPTSETUPSTAT3 Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged. [3:3] RESERVED Reserved [31:4] ENDPTPRIME Endpoint initialization 0x1B0 read-write 0x00000000 0xFFFFFFFF PERB0 Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3 [0:0] PERB1 Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3 [1:1] PERB2 Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3 [2:2] PERB3 Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3 [3:3] RESERVED Reserved [15:4] PETB0 Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3 [16:16] PETB1 Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3 [17:17] PETB2 Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3 [18:18] PETB3 Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB0 = endpoint 0 ... PETB3 = endpoint 3 [19:19] RESERVED Reserved [31:20] ENDPTFLUSH Endpoint de-initialization 0x1B4 read-write 0x00000000 0xFFFFFFFF FERB0 Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3 [0:0] FERB1 Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3 [1:1] FERB2 Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3 [2:2] FERB3 Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3 [3:3] RESERVED Reserved [15:4] FETB0 Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3 [16:16] FETB1 Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3 [17:17] FETB2 Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3 [18:18] FETB3 Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers. FETB0 = endpoint 0 ... FETB3 = endpoint 3 [19:19] RESERVED Reserved [31:20] ENDPTSTAT Endpoint status 0x1B8 read-only 0x00000000 0xFFFFFFFF ERBR0 Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3 [0:0] ERBR1 Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3 [1:1] ERBR2 Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3 [2:2] ERBR3 Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3 [3:3] RESERVED Reserved [15:4] ETBR0 Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3 [16:16] ETBR1 Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3 [17:17] ETBR2 Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3 [18:18] ETBR3 Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3 [19:19] RESERVED Reserved [31:20] ENDPTCOMPLETE Endpoint complete 0x1BC read-write 0x00000000 0xFFFFFFFF ERCE0 Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3 [0:0] ERCE1 Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3 [1:1] ERCE2 Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3 [2:2] ERCE3 Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3 [3:3] RESERVED Reserved [15:4] ETCE0 Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3 [16:16] ETCE1 Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3 [17:17] ETCE2 Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3 [18:18] ETCE3 Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3 [19:19] RESERVED Reserved [31:20] ENDPTCTRL0 Endpoint control 0 0x1C0 read-write 0x00000000 0xFFFFFFFF RXS Rx endpoint stall [0:0] ENUM ENDPOINT_OK_ Endpoint ok. 0 ENDPOINT_STALLED_SOF Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1] 1 RESERVED Reserved [1:1] RXT Endpoint type Endpoint 0 is always a control endpoint. [3:2] RESERVED Reserved [6:4] RXE Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1. [7:7] RESERVED Reserved [15:8] TXS Tx endpoint stall [16:16] ENUM ENDPOINT_OK_ Endpoint ok. 0 ENDPOINT_STALLED_SOF Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1] 1 RESERVED Reserved [17:17] TXT Endpoint type Endpoint 0 is always a control endpoint. [19:18] RESERVED Reserved [22:20] TXE Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1. [23:23] RESERVED Reserved [31:24] 3 0x4 1-3 ENDPTCTRL%s Endpoint control 0x1C4 read-write 0x00000000 0xFFFFFFFF RXS Rx endpoint stall [0:0] ENUM ENDPOINT_OK_THIS_BI Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. 0 ENDPOINT_STALLED_SOF Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1] 1 RESERVED Reserved [1:1] RXT Endpoint type [3:2] ENUM CONTROL Control 0x0 ISOCHRONOUS Isochronous 0x1 BULK Bulk 0x2 RESERVED Reserved 0x3 RESERVED Reserved [4:4] RXI Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID. [5:5] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RXR Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device. [6:6] RXE Rx endpoint enable An endpoint should be enabled only after it has been configured. [7:7] ENUM ENDPOINT_DISABLED_ Endpoint disabled. 0 ENDPOINT_ENABLED_ Endpoint enabled. 1 RESERVED Reserved [15:8] TXS Tx endpoint stall [16:16] ENUM ENDPOINT_OK_THIS_BI Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. 0 ENDPOINT_STALLED_SOF Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1] 1 RESERVED Reserved [17:17] TXT Tx endpoint type [19:18] ENUM CONTROL Control 0x0 ISOCHRONOUS Isochronous 0x1 BULK Bulk 0x2 INTERRUPT Interrupt 0x3 RESERVED Reserved [20:20] TXI Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID. [21:21] ENUM ENABLED Enabled 0 DISABLED Disabled 1 TXR Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device. [22:22] TXE Tx endpoint enable An endpoint should be enabled only after it has been configured [23:23] ENUM ENDPOINT_DISABLED_ Endpoint disabled. 0 ENDPOINT_ENABLED_ Endpoint enabled. 1 RESERVED Reserved [31:24] LCD LCD controller LCD 0x40008000 0 0xFFFF registers LCD 7 TIMH Horizontal Timing Control register 0x000 read-write 0x0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] PPL Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19. [7:2] HSW Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1. [15:8] HFP Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1. [23:16] HBP Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1. [31:24] TIMV Vertical Timing Control register 0x004 read-write 0x0 0xFFFFFFFF LPP Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels. [9:0] VSW Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs. [15:10] VFP Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast. [23:16] VBP Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast. [31:24] POL Clock and Signal Polarity Control register 0x008 read-write 0x0 0xFFFFFFFF PCD_LO Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16). [4:0] CLKSEL Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD). [5:5] ACB AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal. [10:6] IVS Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH. [11:11] IHS Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH. [12:12] IPC Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK. [13:13] IOE Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode. [14:14] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:15] CPL Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly. [25:16] BCD Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays. [26:26] PCD_HI Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register. [31:27] LE Line End Control register 0x00C read-write 0x0 0xFFFFFFFF LED Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1. [6:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:7] LEE LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active. [16:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:17] UPBASE Upper Panel Frame Base Address register 0x010 read-write 0x0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [2:0] LCDUPBASE LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned. [31:3] LPBASE Lower Panel Frame Base Address register 0x014 read-write 0x0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [2:0] LCDLPBASE LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned. [31:3] CTRL LCD Control register 0x018 read-write 0x0 0xFFFFFFFF LCDEN LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing. [0:0] LCDBPP LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode. [3:1] LCDBW STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode. [4:4] LCDTFT LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler. [5:5] LCDMONO8 Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface. [6:6] LCDDUAL Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel. [7:7] BGR Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped. [8:8] BEBO Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order. [9:9] BEPO Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format. [10:10] LCDPWR LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active). See LCD power-up and power-down sequence for details on LCD power sequencing. [11:11] LCDVCOMP LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch. [13:12] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:14] WATERMARK LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations. [16:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:17] INTMSK Interrupt Mask register 0x01C read-write 0x0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [0:0] FUFIM FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows. [1:1] LNBUIM LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers. [2:2] VCOMPIM Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached. [3:3] BERIM AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs. [4:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] INTRAW Raw Interrupt Status register 0x020 read-only 0x0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [0:0] FUFRIS FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the INTMSK register is set. [1:1] LNBURIS LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the INTMSK register is set. [2:2] VCOMPRIS Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. Generates an interrupt if the VCompIM bit in the INTMSK register is set. [3:3] BERRAW AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the INTMSK register is set. [4:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] INTSTAT Masked Interrupt Status register 0x024 read-only 0x0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [0:0] FUFMIS FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the INTRAW register and the FUFIM bit in the INTMSK register are set. [1:1] LNBUMIS LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the INTRAW register and the LNBUIM bit in the INTMSK register are set. [2:2] VCOMPMIS Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the INTRAW register and the VCompIM bit in the INTMSK register are set. [3:3] BERMIS AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the INTRAW register and the BERIM bit in the INTMSK register are set. [4:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] INTCLR Interrupt Clear register 0x028 write-only 0x0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [0:0] FUFIC FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt. [1:1] LNBUIC LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt. [2:2] VCOMPIC Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt. [3:3] BERIC AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt. [4:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] UPCURR Upper Panel Current Address Value register 0x02C read-only 0x0 0xFFFFFFFF LCDUPCURR LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address. [31:0] LPCURR Lower Panel Current Address Value register 0x030 read-only 0x0 0xFFFFFFFF LCDLPCURR LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address. [31:0] 256 0x4 0-255 PAL[%s] 256x16-bit Color Palette registers 0x200 read-write 0x0 0xFFFFFFFF R04_0 Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields. [4:0] G04_0 Green palette data. [9:5] B04_0 Blue palette data. [14:10] I0 Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities. [15:15] R14_0 Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields. [20:16] G14_0 Green palette data. [25:21] B14_0 Blue palette data. [30:26] I1 Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities. [31:31] 256 0x4 0-255 CRSR_IMG[%s] Cursor Image registers 0x800 read-write 0x0 0xFFFFFFFF CRSR_IMG Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors. [31:0] CRSR_CTRL Cursor Control register 0xC00 read-write 0x0 0xFFFFFFFF CrsrOn Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed. [0:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:1] CRSRNUM1_0 Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3. [5:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] CRSR_CFG Cursor Configuration register 0xC04 read-write 0x0 0xFFFFFFFF CrsrSize Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor. [0:0] FRAMESYNC Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] CRSR_PAL0 Cursor Palette register 0 0xC08 read-write 0x0 0xFFFFFFFF RED Red color component [7:0] GREEN Green color component [15:8] BLUE Blue color component. [23:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] CRSR_PAL1 Cursor Palette register 1 0xC0C read-write 0x0 0xFFFFFFFF RED Red color component [7:0] GREEN Green color component [15:8] BLUE Blue color component. [23:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] CRSR_XY Cursor XY Position register 0xC10 read-write 0x0 0xFFFFFFFF CRSRX X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display. [9:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:10] CRSRY Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display. [25:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:26] CRSR_CLIP Cursor Clip Position register 0xC14 read-write 0x0 0xFFFFFFFF CRSRCLIPX Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed. [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:6] CRSRCLIPY Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image. [13:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:14] CRSR_INTMSK Cursor Interrupt Mask register 0xC20 read-write 0x0 0xFFFFFFFF CRSRIM Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image. [0:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:1] CRSR_INTCLR Cursor Interrupt Clear register 0xC24 write-only 0x0 0xFFFFFFFF CRSRIC Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared. [0:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:1] CRSR_INTRAW Cursor Raw Interrupt Status register 0xC28 read-only 0x0 0xFFFFFFFF CRSRRIS Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register. [0:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:1] CRSR_INTSTAT Cursor Masked Interrupt Status register 0xC2C read-only 0x0 0xFFFFFFFF CRSRMIS Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register. [0:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:1] EEPROM EEPROM EEPROM 0x4000E000 0x0 0xFFF registers FLASH 4 CMD EEPROM command register 0x000 read-write 0 0xFFFFFFFF CMD Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved. [2:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] RWSTATE EEPROM read wait state register 0x008 read-write 0x00000905 0xFFFFFFFF RPHASE2 Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration. [7:0] RPHASE1 Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1. [15:8] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] AUTOPROG EEPROM auto programming register 0x00C read-write 0 0xFFFFFFFF AUTOPROG Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with ......1111100 (last word of a page) [1:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:2] WSTATE EEPROM wait state register 0x010 read-write 0x00020602 0xFFFFFFFF PHASE3 Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3. [7:0] PHASE2 Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2. [15:8] PHASE1 Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1. [23:16] RESERVED Reserved. Read value is undefined, only zero should be written. [30:24] LCK_PARWEP Lock timing parameters for write, erase and program operation 0 = WSTATE and CLKDIV registers have R/W access 1 = WSTATE and CLKDIV registers have R only access [31:31] CLKDIV EEPROM clock divider register 0x014 read-write 0x00000063 0xFFFFFFFF CLKDIV Division factor (minus 1 encoded). [15:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:16] PWRDWN EEPROM power-down register 0x018 read-write 0 0xFFFFFFFF PWRDWN Power down mode bit. 0 = not in power down mode. 1 = power down mode. [0:0] RESERVED Reserved. Read value is undefined, only zero should be written. [31:1] INTENCLR EEPROM interrupt enable clear 0xFD8 write-only 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [1:0] PROG_CLR_EN Clear program operation finished interrupt enable bit for EEPROM. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit. [2:2] RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] INTENSET EEPROM interrupt enable set 0xFDC write-only 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [1:0] PROG_SET_EN Set program operation finished interrupt enable bit for EEPROM device 1. 0 = leave corresponding bit unchanged. 1 = set corresponding bit. [2:2] RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] INTSTAT EEPROM interrupt status 0xFE0 read-only 0 0xFFFFFFFF RESERVED Reserved. The value read from a reserved bit is not defined. [1:0] END_OF_PROG EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when one is written to the corresponding bit of the INTSTATSET register. - cleared when one is written to the corresponding bit of the INTSTATCLR register. [2:2] RESERVED Reserved. The value read from a reserved bit is not defined. [31:3] INTEN EEPROM interrupt enable 0xFE4 read-only 0 0xFFFFFFFF RESERVED Reserved. The value read from a reserved bit is not defined. [1:0] EE_PROG_DONE EEPROM program operation finished interrupt enable bit. Bit is: - set when one is written in the corresponding bit of the INTENSET register. - cleared when one is written to the corresponding bit of the INTENCLR register. [2:2] RESERVED Reserved. The value read from a reserved bit is not defined. [31:3] INTSTATCLR EEPROM interrupt status clear 0xFE8 write-only 0 0xFFFFFFFF RESERVED Reserved. Read value is undefined, only zero should be written. [1:0] PROG_CLR_ST Clear program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit. [2:2] RESERVED Reserved. Read value is undefined, only zero should be written. [31:3] ETHERNET Ethernet ETHERNET 0x40010000 0x0 0xFFFFF registers ETHERNET 5 MAC_CONFIG MAC configuration register 0x0000 read-write 0x00008000 0xFFFFFFFF RESERVED Reserved [1:0] RE Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII. [2:2] TE Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames. [3:3] DF Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration. [4:4] BL Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration. 00: k = min (n, 10) 01: k = min (n, 8) 10: k = min (n, 4) 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 <= r <= 2k. [6:5] ACS Automatic Pad/CRC Stripping When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field. When this bit is reset, the MAC will pass all incoming frames to the Host unmodified. [7:7] RESERVED Link Up/Down Indicates whether the link is up or down during the transmission of configuration in SMII interface: 0 = Link down 1 = Link up [8:8] DR Disable Retry When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration. [9:9] RESERVED Reserved [10:10] DM Duplex Mode When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously. [11:11] LM Loopback Mode When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally. [12:12] DO Disable Receive Own When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in Full-Duplex mode. [13:13] FES Speed Indicates the speed in Fast Ethernet (MII) mode: 0 = 10 Mbps 1 = 100 Mbps [14:14] PS Port select 1 = MII (100 Mbp) - this is the only allowed value. [15:15] DCRS Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions. [16:16] IFG Inter-frame gap These bits control the minimum IFG between frames during transmission. 000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered [19:17] JE Jumbo Frame Enable When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. [20:20] RESERVED Reserved. [21:21] JD Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. [22:22] WD Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes. When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that. [23:23] RESERVED Reserved. [31:24] MAC_FRAME_FILTER MAC frame filter 0x0004 read-write 0x00000000 0xFFFFFFFF PR Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set. [0:0] HUC Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. [1:1] HMC Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. [2:2] DAIF DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed. [3:3] PM Pass All Multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit. [4:4] DBF Disable Broadcast Frames When this bit is set, the AFM module filters all incoming broadcast frames. When this bit is reset, the AFM module passes all received broadcast frames. [5:5] PCF Pass Control Frames These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register. 00 = MAC filters all control frames from reaching the application. 01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter. 10 = MAC forwards all control frames to application even if they fail the Address Filter. 11 = MAC forwards control frames that pass the Address Filter. [7:6] RESERVED Reserved. [8:8] RESERVED Reserved. [9:9] HPF Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter. [10:10] RESERVED Reserved [30:11] RA Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter. [31:31] MAC_HASHTABLE_HIGH Hash table high register 0x0008 read-write 0x00000000 0xFFFFFFFF HTH Hash table high This field contains the upper 32 bits of Hash table. [31:0] MAC_HASHTABLE_LOW Hash table low register 0x000C read-write 0x00000000 0xFFFFFFFF HTL Hash table low This field contains the upper 32 bits of Hash table. [31:0] MAC_MII_ADDR MII address register 0x0010 read-write 0x00000000 0xFFFFFFFF GB MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared. [0:0] W MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register. [1:1] CR CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M4_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks. See Table 554 for bit values. [5:2] GR MII register These bits select the desired MII register in the selected PHY device. [10:6] PA Physical layer address This field tells which of the 32 possible PHY devices are being accessed. [15:11] RESERVED Reserved [31:16] MAC_MII_DATA MII data register 0x0014 read-write 0x00000000 0xFFFFFFFF GD MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation. [15:0] RESERVED Reserved [31:16] MAC_FLOW_CTRL Flow control register 0x0018 read-write 0x00000000 0xFFFFFFFF FCB Flow Control Busy/Backpressure Activate This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled. [0:0] TFE Transmit Flow Control Enable In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled. [1:1] RFE Receive Flow Control Enable When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled. [2:2] UP Unicast Pause Frame Detect When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard. [3:3] PLT Pause Low Threshold This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted. [5:4] RESERVED Reserved [6:6] DZPQ Disable Zero-Quanta Pause When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled. [7:7] RESERVED Reserved [15:8] PT Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain. [31:16] MAC_VLAN_TAG VLAN tag register 0x001C read-write 0x00000000 0xFFFFFFFF VL VLAN Tag Identifier for Receive Frames This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames. [15:0] ETV Enable 12-Bit VLAN Tag Comparison When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison. [16:16] RESERVED Reserved [31:17] MAC_DEBUG Debug register 0x0024 read-only 0x00000000 0xFFFFFFFF RXIDLESTAT When high, it indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state. [0:0] FIFOSTAT0 When high, it indicates the active state of the small FIFO Read and Write controllers respectively of the MAC receive Frame Controller module. [2:1] RESERVED Reserved [3:3] RXFIFOSTAT1 When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO. [4:4] RXFIFOSTAT State of the RxFIFO read Controller: 00 = idle state 01 = reading frame data 10 = reading frame status (or Time stamp) 11 = flushing the frame data and status [6:5] RESERVED Reserved [7:7] RXFIFOLVL Status of the RxFIFO Fill-level 00 = RxFIFO Empty 01 = RxFIFO fill-level below flow-control de-activate threshold 10 = RxFIFO fill-level above flow-control activate threshold 11 = RxFIFO Full [9:8] RESERVED Reserved [15:10] TXIDLESTAT When high, it indicates that the MAC MII transmit protocol engine is actively transmitting data and not in IDLE state. [16:16] TXSTAT State of the MAC Transmit Frame Controller module: 00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over 10 = Generating and transmitting a PAUSE control frame (in full duplex mode) 11 = Transferring input frame for transmission [18:17] PAUSE When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission. [19:19] TXFIFOSTAT State of the TxFIFO read Controller 00 = idle state 01 = READ state (transferring data to MAC transmitter) 10 = Waiting for TxStatus from MAC transmitter 11 = Writing the received TxStatus or flushing the TxFIFO [21:20] TXFIFOSTAT1 When high, it indicates that the TxFIFO Write Controller is active and transferring data to the TxFIFO. [22:22] RESERVED Reserved [23:23] TXFIFOLVL When high, it indicates that the TxFIFO is not empty and has some data left for transmission. [24:24] TXFIFOFULL When high, it indicates that the TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission. [25:25] RESERVED Reserved [31:26] MAC_RWAKE_FRFLT Remote wake-up frame filter 0x0028 read-write 0x00000000 0xFFFFFFFF ADDR WKUPFMFILTER address [31:0] MAC_PMT_CTRL_STAT PMT control and status 0x002C read-write 0x00000000 0xFFFFFFFF PD Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high. [0:0] MPE Magic packet enable When set, enables generation of a power management event due to Magic Packet reception. [1:1] WFE Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception. [2:2] RESERVED Reserved [4:3] MPR Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register. [5:5] WFR Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register. [6:6] RESERVED Reserved [8:7] GU Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame. [9:9] RESERVED Reserved [30:10] WFFRPR Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle. [31:31] MAC_INTR Interrupt status register 0x0038 read-only 0x00000000 0xFFFFFFFF RESERVED Reserved. [2:0] PMT PMT Interrupt Status This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power- Down mode (See bits 5 and 6 in Table 560). This bit is cleared when both bits[6:5] are cleared because of a read operation to the PMT Control and Status register. [3:3] RESERVED Reserved. [8:4] TS Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers - There is an overflow in the seconds register This bit is cleared on reading the byte 0 of the Timestamp Status register (Table 576). Otherwise, when default Time stamping is enabled, this bit when set indicates that the system time value equals or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this Interrupt Status Register[9]. In all other modes, this bit is reserved. [9:9] RESERVED Reserved. [10:10] RESERVED Reserved [31:11] MAC_INTR_MASK Interrupt mask register 0x003C read-write 0x00000000 0xFFFFFFFF RESERVED Reserved [2:0] PMTIM PMT Interrupt Mask This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561. [3:3] RESERVED Reserved. [8:4] TSIM Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561 [9:9] RESERVED Reserved. [10:10] MAC_ADDR0_HIGH MAC address 0 high register 0x0040 read-write 0x8000FFFF 0xFFFFFFFF A47_32 MAC Address0 [47:32] This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames. [15:0] RESERVED Reserved [30:16] MO Always 1 [31:31] MAC_ADDR0_LOW MAC address 0 low register 0x0044 read-write 0xFFFFFFFF 0xFFFFFFFF A31_0 MAC Address0 [31:0] This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames. [31:0] MAC_TIMESTP_CTRL Time stamp control register 0x0700 read-write 0x00002000 0xFFFFFFFF TSENA Time stamp Enable When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode. [0:0] TSCFUPDT Time stamp Fine or Coarse Update When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled. [1:1] TSINIT Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete. [2:2] TSUPDT Time stamp Update This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware. [3:3] TSTRIG Time stamp Interrupt Trigger Enable This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear). When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt. [4:4] TSADDREG Addend Reg Update When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected. [5:5] RESERVED Reserved [7:6] TSENALL Enable Time stamp for All Frames When set, the Time stamp snapshot is enabled for all frames received by the core. [8:8] TSCTRLSSR Time stamp Digital or Binary rollover control When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value. [9:9] TSVER2ENA Enable PTP packet snooping for version 2 format When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format. [10:10] TSIPENA Enable Time stamp Snapshot for PTP over Ethernet frames When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets. [11:11] TSIPV6ENA Enable Time stamp Snapshot for IPv6 frames When set, the Time stamp snapshot is taken for IPv6 frames. [12:12] TSIPV4ENA Enable Time stamp Snapshot for IPv4 frames When set, the Time stamp snapshot is taken for IPv4 frames. [13:13] TSEVNTENA Enable Time stamp Snapshot for Event Messages When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling. [14:14] TSMSTRENA Enable Snapshot for Messages Relevant to Master When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node. [15:15] TSCLKTYPE Select the type of clock node The following are the options to select the type of clock node: 00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock [17:16] TSENMACADDR Enable MAC address for PTP frame filtering When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet. [18:18] SUBSECOND_INCR Sub-second increment register 0x0704 read-write 0x00000000 0xFFFFFFFF SSINC Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.) [7:0] RESERVED Reserved. [31:8] SECONDS System time seconds register 0x0708 read-only 0x00000000 0xFFFFFFFF TSS Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the core. [31:0] NANOSECONDS System time nanoseconds register 0x070C read-only 0x00000000 0xFFFFFFFF TSSS Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR in the MAC_TIMESTAMP_CTRL register is set, each bit represents 1 ns and the maximum value will be 0x3B9A_C9FF, after which it rolls-over to zero). [30:0] PSNT Positive or negative time This bit indicates positive or negative time value. If the bit is reset, it indicates that the time representation is positive, and if it is set, it indicates negative time value. (This bit represents the 32nd bit of the nanoseconds value when the Advance Time stamp feature is enabled). [31:31] SECONDSUPDATE System time seconds update register 0x0710 read-write 0x00000000 0xFFFFFFFF TSS Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time. [31:0] NANOSECONDSUPDATE System time nanoseconds update register 0x0714 read-write 0x00000000 0xFFFFFFFF TSSS Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.) [30:0] ADDSUB Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. [31:31] ADDEND Time stamp addend register 0x0718 read-write 0x00000000 0xFFFFFFFF TSAR Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. [31:0] TARGETSECONDS Target time seconds register 0x071C read-write 0x00000000 0xFFFFFFFF TSTR Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt. [31:0] TARGETNANOSECONDS Target time nanoseconds register 0x0720 read-write 0x00000000 0xFFFFFFFF TSTR Target Time stamp low This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.) [30:0] RESERVED Reserved. [31:31] HIGHWORD System time higher word seconds register 0x0724 read-write 0x00000000 0xFFFFFFFF TSHWR Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. [15:0] RESERVED Reserved. [31:16] TIMESTAMPSTAT Time stamp status register 0x0728 read-only 0x00000000 0xFFFFFFFF TSSOVF Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF. [0:0] TSTARGT Time stamp target reached When set, indicates the value of system time is greater or equal to the value specified in the Target Time High and Low registers [1:1] RESERVED Reserved. [31:2] DMA_BUS_MODE Bus Mode Register 0x1000 read-write 0x00020100 0xFFFFFFFF SWR Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core. The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. [0:0] DA DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14] 1 = Rx has priority over Tx [1:1] DSL Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode. [6:2] ATDS Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). [7:7] PBL Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only. The PBL values have the following limitations. The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly. [13:8] PR Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset. 00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1 [15:14] FB Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. [16:16] RPBL RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high. [22:17] USP Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines. [23:23] PBL8X 8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL. [24:24] AAL Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address. [25:25] MB Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below. [26:26] TXPR When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. [27:27] RESERVED Reserved [31:28] DMA_TRANS_POLL_DEMAND Transmit poll demand register 0x1004 read-write 0x00000000 0xFFFFFFFF TPD Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered. When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes. [31:0] DMA_REC_POLL_DEMAND Receive poll demand register 0x1008 read-write 0x00000000 0xFFFFFFFF RPD Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered. When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state. [31:0] DMA_REC_DES_ADDR Receive descriptor list address register 0x100C read-write 0x00000000 0xFFFFFFFF SRL Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only. [31:0] DMA_TRANS_DES_ADDR Transmit descriptor list address register 0x1010 read-write 0x00000000 0xFFFFFFFF SRL Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only. [31:0] DMA_STAT Status register 0x1014 read-write 0x00000000 0xFFFFFFFF TI Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor. [0:0] TPS Transmit process stopped This bit is set when the transmission is stopped. [1:1] TU Transmit buffer unavailable This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command. [2:2] TJT Transmit jabber timeout This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. [3:3] OVF Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]. [4:4] UNF Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. [5:5] RI Receive interrupt This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state. [6:6] RU Receive buffer unavailable This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA. [7:7] RPS Received process stopped This bit is asserted when the Receive Process enters the Stopped state. [8:8] RWT Receive watchdog timeout This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled). [9:9] ETI Early transmit interrupt This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO. [10:10] RESERVED Reserved [12:11] FBI Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses. [13:13] ERI Early receive interrupt This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit. [14:14] AIE Abnormal interrupt summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. [15:15] NIS Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared. [16:16] RS Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued. 001 = Running: Fetching Receive Transfer Descriptor. 010 = Reserved. 011 = Running: Waiting for receive packet. 100 = Suspended: Receive Descriptor Unavailable. 101 = Running: Closing Receive Descriptor. 110 = TIME_STAMP write state. 111 = Running: Transferring the receive packet data from receive buffer to host memory. [19:17] TS Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued. 001 = Running; Fetching Transmit Transfer Descriptor. 010 = Running; Waiting for status. 011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO). 100 = TIME_STAMP write state. 101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow. 111 = Running; Closing Transmit Descriptor. [22:20] EB1 Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA. [23:23] EB2 Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during read transfer. 0 = Error during write transfer. [24:24] EB3 Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during descriptor access. 0 = Error during data buffer access. [25:25] RESERVED Reserved [31:26] DMA_OP_MODE Operation mode register 0x1018 read-write 0x00000000 0xFFFFFFFF RESERVED Reserved [0:0] SR Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable. [1:1] OSF Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained. [2:2] RTC Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. 00 = 64 01 = 32 10 = 96 11 = 128 [4:3] RESERVED Reserved [5:5] FUF Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC). When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01). [6:6] FEF Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set. [7:7] RESERVED Reserved [12:8] ST Start/Stop Transmission Command When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state. [13:13] TTC Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16 [16:14] RESERVED Reserved [19:17] FTF Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission. The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active. [20:20] RESERVED Reserved [21:21] RESERVED Reserved [23:22] DFF Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See). [24:24] RESERVED Reserved [25:25] RESERVED Reserved [26:26] RESERVED Reserved [31:27] DMA_INT_EN Interrupt enable register 0x101C read-write 0x00000000 0xFFFFFFFF TIE Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled. [0:0] TSE Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled. [1:1] TUE Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled. [2:2] TJE Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled. [3:3] OVE Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled. [4:4] UNE Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled. [5:5] RIE Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled. [6:6] RUE Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. [7:7] RSE Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled. [8:8] RWE Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled. [9:9] ETE Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled. [10:10] RESERVED Reserved [12:11] FBE Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled. [13:13] ERE Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled. [14:14] AIE Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error [15:15] NIE Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt [16:16] RESERVED Reserved [31:17] DMA_MFRM_BUFOF Missed frame and buffer overflow register 0x1020 read-only 0x00000000 0xFFFFFFFF FMC Number of frames missed This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with. [15:0] OC Overflow bit for missed frame counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. [16:16] FMA Number of frames missed by the application This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. Indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal. The counter is cleared when this register is read with . [27:17] OF Overflow bit for FIFO overflow counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. [28:28] RESERVED Reserved [31:29] DMA_REC_INT_WDT Receive interrupt watchdog timer register 0x1024 read-write 0x00000000 0xFFFFFFFF RIWT RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame. [7:0] RESERVED Reserved [31:8] DMA_CURHOST_TRANS_DES Current host transmit descriptor register 0x1048 read-only 0x00000000 0xFFFFFFFF HTD Host Transmit Descriptor Address Pointer Cleared on Reset. Pointer updated by DMA during operation. [31:0] DMA_CURHOST_REC_DES Current host receive descriptor register 0x104C read-only 0x00000000 0xFFFFFFFF HRD Host Receive Descriptor Address Pointer Cleared on Reset. Pointer updated by DMA during operation. [31:0] DMA_CURHOST_TRANS_BUF Current host transmit buffer address register 0x1050 read-only 0x00000000 0xFFFFFFFF HTB Host Transmit Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation. [31:0] DMA_CURHOST_REC_BUF Current host receive buffer address register 0x1054 read-only 0x00000000 0xFFFFFFFF HRB Host Receive Buffer Address Pointer Cleared on Reset. Pointer updated by DMA during operation. [31:0] ATIMER Alarm timer ATIMER 0x40040000 0 0xFFFF registers ATIMER 46 DOWNCOUNTER Downcounter register 0x000 read-write 0x000 0xFFFFFFFF CVAL When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues. [15:0] RESERVED Reserved. [31:16] PRESET Preset value register 0x004 read-write 0x000 0xFFFFFFFF PRESETVAL Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero [15:0] RESERVED Reserved. [31:16] CLR_EN Interrupt clear enable register 0xFD8 write-only 0x0 0xFFFFFFFF CLR_EN Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register. [0:0] RESERVED Reserved. [31:1] SET_EN Interrupt set enable register 0xFDC write-only 0x0 0xFFFFFFFF SET_EN Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register. [0:0] RESERVED Reserved. [31:1] STATUS Status register 0xFE0 read-only 0x0 0xFFFFFFFF STAT A 1 in this bit shows that the STATUS interrupt has been raised. [0:0] RESERVED Reserved. [31:1] ENABLE Enable register 0xFE4 read-only 0x0 0xFFFFFFFF EN A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register. [0:0] RESERVED Reserved. [31:1] CLR_STAT Clear register 0xFE8 write-only 0x0 0xFFFFFFFF CSTAT Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register. [0:0] RESERVED Reserved. [31:1] SET_STAT Set register 0xFEC write-only 0x0 0xFFFFFFFF SSTAT Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register. [0:0] RESERVED Reserved. [31:1] REGFILE RTC REGFILE REGFILE 0x40041000 0 0xFFFF registers 64 0x4 0-63 REGFILE[%s] General purpose storage register 0x000 read-write 0 0xFFFFFFFF REGVAL General purpose storage. [31:0] PMC Power Management Controller (PMC) PMC 0x40042000 0 0xFFFF registers PD0_SLEEP0_HW_ENA Hardware sleep event enable register 0x000 read-write 0x00000001 0xFFFFFFFF ENA_EVENT0 Writing a 1 enables the Cortex-M4 core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register. [0:0] ENA_EVENT1 Writing a 1 enables the Cortex-M0 core and the Cortex-M0 subsystem core to put the part into any of the Power-down modes Deep-sleep, Power-down, or Deep power-down depending on the value in the PD0_SLEEP0_MODE register. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] PD0_SLEEP0_MODE Sleep power mode register 0x01C read-write 0x003FFF7F 0xFFFFFFFF PWR_STATE Selects between Deep-sleep, Power-down, and Deep power-down modes. Only one of the following three values can be programmed in this register: 0x0030 00AA = Deep-sleep mode 0x0030 FCBA = Power-down mode 0x0030 3CBA = Power-down mode with M0SUB SRAM maintained 0x0030 FF7F = Deep power-down mode [31:0] CREG Configuration Registers (CREG) CREG 0x40043000 0x0 0xFFF registers CREG0 Chip configuration register 32 kHz oscillator output and BOD control register. 0x004 read-write 0 0x00000000 EN1KHZ Enable 1 kHz output. [0:0] ENUM 1_KHZ_OUTPUT_DISABLE 1 kHz output disabled. 0 1_KHZ_OUTPUT_ENABLED 1 kHz output enabled. 1 EN32KHZ Enable 32 kHz output [1:1] ENUM 32_KHZ_OUTPUT_DISABL 32 kHz output disabled. 0 32_KHZ_OUTPUT_ENABLE 32 kHz output enabled. 1 RESET32KHZ 32 kHz oscillator reset [2:2] ENUM CLEAR_RESET Clear reset. 0 RESET_ACTIVE Reset active. 1 PD32KHZ 32 kHz power control. [3:3] ENUM POWERED Powered. 0 POWERED_DOWN Powered-down. 1 RESERVED Reserved [4:4] USB0PHY USB0 PHY power control. [5:5] ENUM ENABLE_USB0_PHY_POWE Enable USB0 PHY power. 0 DISABLE_USB0_PHY Disable USB0 PHY. PHY powered down. 1 ALARMCTRL RTC_ALARM pin output control [7:6] ENUM RTC_ALARM RTC alarm. 0x0 EVENT_ROUTER_EVENT Event router event. 0x1 RESERVED Reserved. 0x2 INACTIVE Inactive. 0x3 BODLVL1 BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values. [9:8] ENUM LEVEL_0_INTERRUPT Level 0 interrupt 0x0 LEVEL_1_INTERRUPT Level 1 interrupt 0x1 LEVEL_2_INTERRUPT Level 2 interrupt 0x2 LEVEL_3_INTERRUPT Level 3 interrupt 0x3 BODLVL2 BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values. [11:10] ENUM LEVEL_0_RESET Level 0 reset 0x0 LEVEL_1_RESET Level 1 reset 0x1 LEVEL_2_RESET Level 2 reset 0x2 LEVEL_3_RESET Level 3 reset 0x3 SAMPLECTRL SAMPLE pin input/output control [13:12] ENUM RESERVED Reserved 0x0 SAMPLE_OUTPUT_FROM_T Sample output from the event monitor/recorder. 0x1 OUTPUT_FROM_THE_EVEN Output from the event router. 0x2 RESERVED Reserved. 0x3 WAKEUP0CTRL WAKEUP0 pin input/output control [15:14] ENUM INPUT_TO_THE_EVENT_R Input to the event router. 0x0 OUTPUT_FROM_THE_EVEN Output from the event router. 0x1 RESERVED Reserved. 0x2 INPUT_TO_THE_EVENT_R Input to the event router. 0x3 WAKEUP1CTRL WAKEUP1 pin input/output control [17:16] ENUM INPUT_TO_EVENT_ROUTE Input to event router. 0x0 OUTPUT_FROM_THE_EVEN Output from the event router. 0x1 RESERVED Reserved 0x2 INPUT_TO_EVENT_ROUTE Input to event router. 0x3 RESERVED Reserved [31:18] M4MEMMAP ARM Cortex-M4 memory mapping 0x100 read-write 0x10400000 0xFFFFFFFF M4MAP Shadow address when accessing memory at address 0x0000 0000 [31:12] CREG5 Chip configuration register 5. Controls JTAG access. 0x118 read-write 0 0x00000000 RESERVED Reserved. [9:0] M0SUBTAPSEL JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset. [10:10] ENUM NO_EFFECT No effect. 0 DISABLE_JTAG_DEBUG Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source. 1 M4TAPSEL JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset. [11:11] ENUM NO_EFFECT No effect. 0 DISABLE_JTAG_DEBUG Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source. 1 M0APPTAPSEL JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset. [12:12] ENUM NO_EFFECT No effect. 0 DISABLE_JTAG_DEBUG Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source. 1 RESERVED Reserved. [31:13] DMAMUX DMA mux control 0x11C read-write 0 0x00000000 DMAMUXPER0 Select DMA to peripheral connection for DMA peripheral 0. [1:0] ENUM SPIFI SPIFI 0x0 SCT_CTOUT_2 SCT CTOUT_2 0x1 SGPIO14 SGPIO14 0x2 TIMER3_MATCH_1 Timer3 match 1 0x3 DMAMUXPER1 Select DMA to peripheral connection for DMA peripheral 1 [3:2] ENUM TIMER0_MATCH_0 Timer0 match 0 0x0 USART0_TRANSMIT USART0 transmit 0x1 RESERVED Reserved 0x2 RESERVED Reserved 0x3 DMAMUXPER2 Select DMA to peripheral connection for DMA peripheral 2. [5:4] ENUM TIMER0_MATCH_1 Timer0 match 1 0x0 USART0_RECEIVE USART0 receive 0x1 RESERVED Reserved 0x2 RESERVED Reserved 0x3 DMAMUXPER3 Select DMA to peripheral connection for DMA peripheral 3. [7:6] ENUM TIMER1_MATCH_0 Timer1 match 0 0x0 UART1_TRANSMIT UART1 transmit 0x1 I2S1_DMA_REQUEST_1 I2S1 DMA request 1 0x2 SSP1_TRANSMIT SSP1 transmit 0x3 DMAMUXPER4 Select DMA to peripheral connection for DMA peripheral 4. [9:8] ENUM TIMER1_MATCH_1 Timer1 match 1 0x0 UART1_RECEIVE UART1 receive 0x1 I2S1_DMA_REQUEST_2 I2S1 DMA request 2 0x2 SSP1_RECEIVE SSP1 receive 0x3 DMAMUXPER5 Select DMA to peripheral connection for DMA peripheral 5. [11:10] ENUM TIMER2_MATCH_0 Timer2 match 0 0x0 USART2_TRANSMIT USART2 transmit 0x1 SSP1_TRANSMIT SSP1 transmit 0x2 SGPIO15 SGPIO15 0x3 DMAMUXPER6 Selects DMA to peripheral connection for DMA peripheral 6. [13:12] ENUM TIMER2_MATCH_1 Timer2 match 1 0x0 USART2_RECEIVE USART2 receive 0x1 SSP1_RECEIVE SSP1 receive 0x2 SGPIO14 SGPIO14 0x3 DMAMUXPER7 Selects DMA to peripheral connection for DMA peripheral 7. [15:14] ENUM TIMER3_MATCH_0 Timer3 match 0 0x0 USART3_TRANSMIT USART3 transmit 0x1 SCT_DMA_REQUEST_0 SCT DMA request 0 0x2 ADCHS_WRITE ADCHS write 0x3 DMAMUXPER8 Select DMA to peripheral connection for DMA peripheral 8. [17:16] ENUM TIMER3_MATCH_1 Timer3 match 1 0x0 USART3_RECEIVE USART3 receive 0x1 SCT_DMA_REQUEST_1 SCT DMA request 1 0x2 ADCHS_READ ADCHS read 0x3 DMAMUXPER9 Select DMA to peripheral connection for DMA peripheral 9. [19:18] ENUM SSP0_RECEIVE SSP0 receive 0x0 I2S0_DMA_REQUEST_1 I2S0 DMA request 1 0x1 SCT_DMA_REQUEST_1 SCT DMA request 1 0x2 RESERVED Reserved 0x3 DMAMUXPER10 Select DMA to peripheral connection for DMA peripheral 10. [21:20] ENUM SSP0_TRANSMIT SSP0 transmit 0x0 I2S0_DMA_REQUEST_2 I2S0 DMA request 2 0x1 SCT_DMA_REQUEST_0 SCT DMA request 0 0x2 RESERVED Reserved 0x3 DMAMUXPER11 Selects DMA to peripheral connection for DMA peripheral 11. [23:22] ENUM SSP1_RECEIVE SSP1 receive 0x0 SGPIO14 SGPIO14 0x1 USART0_TRANSMIT USART0 transmit 0x2 RESERVED Reserved 0x3 DMAMUXPER12 Select DMA to peripheral connection for DMA peripheral 12. [25:24] ENUM SSP1_TRANSMIT SSP1 transmit 0x0 SGPIO15 SGPIO15 0x1 USART0_RECEIVE USART0 receive 0x2 RESERVED Reserved 0x3 DMAMUXPER13 Select DMA to peripheral connection for DMA peripheral 13. [27:26] ENUM ADC0 ADC0 0x0 RESERVED Reserved 0x1 SSP1_RECEIVE SSP1 receive 0x2 USART3_RECEIVE USART3 receive 0x3 DMAMUXPER14 Select DMA to peripheral connection for DMA peripheral 14. [29:28] ENUM ADC1 ADC1 0x0 RESERVED Reserved 0x1 SSP1_TRANSMIT SSP1 transmit 0x2 USART3_TRANSMIT USART3 transmit 0x3 DMAMUXPER15 Select DMA to peripheral connection for DMA peripheral 15. [31:30] ENUM DAC DAC 0x0 SCT_CTOUT_3 SCT CTOUT_3 0x1 SGPIO15 SGPIO15 0x2 TIMER3_MATCH_0 Timer3 match 0 0x3 FLASHCFGA Flash accelerator configuration register for flash bank A 0x120 read-write 0x8000F03A 0xFFFFFFFF RESERVED Reserved. Do not change these bits from the reset value. [11:0] FLASHTIM Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies. [15:12] ENUM 1_BASE_M4_CLK_CLOCK 1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz. 0x0 2_BASE_M4_CLK_CLOCKS 2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz. 0x1 3_BASE_M4_CLK_CLOCKS 3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz. 0x2 4_BASE_M4_CLK_CLOCKS 4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz. 0x3 5_BASE_M4_CLK_CLOCKS 5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz. 0x4 6_BASE_M4_CLK_CLOCKS 6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz. 0x5 7_BASE_M4_CLK_CLOCKS 7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz. 0x6 8_BASE_M4_CLK_CLOCKS 8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz. 0x7 9_BASE_M4_CLK_CLOCKS 9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz. 0x8 10_BASE_M4_CLK_CLOCK 10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions. 0x9 RESERVED Reserved. Write zeros only to these bits. [30:16] POW Flash bank A power control [31:31] ENUM POWER_DOWN Power-down 0 ACTIVE Active (Default) 1 FLASHCFGB Flash accelerator configuration register for flash bank B 0x124 read-write 0x8000F03A 0xFFFFFFFF RESERVED Reserved. Do not change these bits from the reset value. [11:0] FLASHTIM Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies. [15:12] ENUM 1_BASE_M4_CLK_CLOCK 1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz. 0x0 2_BASE_M4_CLK_CLOCKS 2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz. 0x1 3_BASE_M4_CLK_CLOCKS 3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz. 0x2 4_BASE_M4_CLK_CLOCKS 4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz. 0x3 5_BASE_M4_CLK_CLOCKS 5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz. 0x4 6_BASE_M4_CLK_CLOCKS 6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz. 0x5 7_BASE_M4_CLK_CLOCKS 7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz. 0x6 8_BASE_M4_CLK_CLOCKS 8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz. 0x7 9_BASE_M4_CLK_CLOCKS 9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz. 0x8 10_BASE_M4_CLK_CLOCK 10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions. 0x9 RESERVED Reserved. Write zeros only to these bits. [30:16] POW Flash bank A power control [31:31] ENUM POWER_DOWN Power-down 0 ACTIVE Active (Default) 1 ETBCFG ETB RAM configuration 0x128 read-write 0x1 0xFFFFFFFF ETB Select SRAM interface [0:0] ENUM ETB_ACCESSES_SRAM_AT ETB accesses SRAM at address 0x2000 C000. 0 AHB_ACCESSES_SRAM_AT AHB accesses SRAM at address 0x2000 C000. 1 RESERVED Reserved. [31:1] CREG6 Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock. 0x12C read-write 0 0xFFFFFFFF ETHMODE Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved. [2:0] ENUM MII MII 0x0 RMII RMII 0x4 RESERVED Reserved. [3:3] CTOUTCTRL Selects the functionality of the SCT outputs. [4:4] ENUM COMBINE_SCT_AND_TIME Combine SCT and timer match outputs. SCT outputs are Red with timer outputs. 0 SCT_OUTPUTS_ONLY SCT outputs only. SCT outputs are used without timer match outputs. 1 RESERVED Reserved. [11:5] I2S0_TX_SCK_IN_SEL I2S0_TX_SCK input select [12:12] ENUM I2S_REGISTER I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960. 0 BASE_AUDIO_CLK_FOR_I BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode. 1 I2S0_RX_SCK_IN_SEL I2S0_RX_SCK input select [13:13] ENUM I2S_REGISTER I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961. 0 BASE_AUDIO_CLK_FOR_I BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode. 1 I2S1_TX_SCK_IN_SEL I2S1_TX_SCK input select [14:14] ENUM I2S_REGISTER I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960. 0 BASE_AUDIO_CLK_FOR_I BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode. 1 I2S1_RX_SCK_IN_SEL I2S1_RX_SCK input select [15:15] ENUM I2S_REGISTER I2S register. I2S clock selected as defined by the I2S receive mode register Table 961. 0 BASE_AUDIO_CLK_FOR_I BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode. 1 EMC_CLK_SEL EMC_CLK divided clock select (see Section 21.1). [16:16] ENUM DIVIDE_BY_1 Divide by 1. EMC_CLK_DIV not divided. 0 DIVIDE_BY_2 Divide by 2. EMC_CLK_DIV divided by 2. 1 RESERVED Reserved. [31:17] M4TXEVENT Cortex-M4 TXEV event clear 0x130 read-write 0 0xFFFFFFFF TXEVCLR Cortex-M4 TXEV event. [0:0] ENUM CLEAR_THE_TXEV_EVENT Clear the TXEV event. 0 NO_EFFECT No effect. 1 RESERVED Reserved. [31:1] CHIPID Part ID 0x200 read-only 0 0x00000000 ID Boundary scan ID code 0x5906 002B or 0x6906 002B = LPC4350/30/20/10 (flashless parts) 0x4906 002B = LPC4357/53 (parts with on-chip flash) [31:0] M0SUBMEMMAP ARM Cortex-M0SUB memory mapping 0x308 read-write 0x18400000 0xFFFFFFFF M0SUBMAP Shadow address when accessing memory at address 0x0000 0000 [31:12] M0SUBTXEVENT Cortex-M0SUB TXEV event clear 0x314 read-write 0 0xFFFFFFFF TXEVCLR Cortex-M0SUB TXEV event handling. [0:0] ENUM CLEAR_THE_TXEV_EVENT Clear the TXEV event. 0 NO_EFFECT No effect. 1 RESERVED Reserved. [31:1] M0APPTXEVENT Cortex-M0APP TXEV event clear 0x400 read-write 0 0xFFFFFFFF TXEVCLR Cortex-M0APP TXEV event handling. [0:0] ENUM CLEAR_THE_TXEV_EVENT Clear the TXEV event. 0 NO_EFFECT No effect. 1 RESERVED Reserved. [31:1] M0APPMEMMAP ARM Cortex-M0APP memory mapping 0x404 read-write 0x20000000 0xFFFFFFFF M0APPMAP Shadow address when accessing memory at address 0x0000 0000 [31:12] USB0FLADJ USB0 frame length adjust register 0x500 read-write 0x20 0xFFFFFFFF FLTV Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16) [5:0] RESERVED Reserved [31:6] USB1FLADJ USB1 frame length adjust register 0x600 read-write 0x20 0xFFFFFFFF FLTV Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16) [5:0] RESERVED Reserved [31:6] EVENTROUTER Event router EVENTROUTER 0x40044000 0x0 0xFFF registers EVENTROUTER 42 HILO Level configuration register 0x000 read-write 0x000 0xFFFFFFFF WAKEUP0_L Level detect mode for WAKEUP0 event. [0:0] ENUM DETECT_LOW_LEVEL Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1. 1 WAKEUP1_L Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0. [1:1] ENUM DETECT_LOW_LEVEL Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. 0 DETECT_HIGH_LEVEL Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1. 1 WAKEUP2_L Level detect mode for WAKEUP2 event. [2:2] ENUM DETECT_LOW_LEVEL Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1. 1 WAKEUP3_L Level detect mode for WAKEUP3 event. [3:3] ENUM DETECT_LOW_LEVEL Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1. 1 ATIMER_L Level detect mode for alarm timer event. [4:4] ENUM DETECT_LOW_LEVEL Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1. 1 RTC_L Level detect mode for RTC event. [5:5] ENUM DETECT_LOW_LEVEL Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1. 1 BOD_L Level detect mode for BOD event. [6:6] ENUM DETECT_LOW_LEVEL Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1. 1 WWDT_L Level detect mode for WWDT event. [7:7] ENUM DETECT_LOW_LEVEL Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1. 1 ETH_L Level detect mode for Ethernet event [8:8] ENUM DETECT_LOW_LEVEL Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1. 1 USB0_L Level detect mode for USB0 event [9:9] ENUM DETECT_LOW_LEVEL Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1. 1 USB1_L Level detect mode for USB1 event [10:10] ENUM DETECT_LOW_LEVEL Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1. 1 SDMMC_L Level detect mode for SD/MMC event [11:11] ENUM DETECT_LOW_LEVEL Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1. 1 CAN_L Level detect mode for C_CAN event. [12:12] ENUM DETECT_LOW_LEVEL Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1. 1 TIM2_L Level detect mode for combined timer output 2 event. [13:13] ENUM DETECT_LOW_LEVEL Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1. 1 TIM6_L Level detect mode for combined timer output 6 event. [14:14] ENUM DETECT_LOW_LEVEL Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1. 1 QEI_L Level detect mode for QEI event. [15:15] ENUM DETECT_LOW_LEVEL Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1. 1 TIM14_L Level detect mode for combined timer output 14 event. [16:16] ENUM DETECT_LOW_LEVEL Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1. 1 RESERVED Reserved. [18:17] RESET_L Level detect mode for Reset [19:19] ENUM DETECT_LOW_LEVEL_IF Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL_IF Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1. 1 BODRESET_L Level detect mode for BOD Reset [20:20] ENUM DETECT_LOW_LEVEL_IF Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL_IF Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1. 1 DPDRESET_L Level detect mode for Deep power-down Reset [21:21] ENUM DETECT_LOW_LEVEL_IF Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1. 0 DETECT_HIGH_LEVEL_IF Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1. 1 RESERVED Reserved. [31:22] EDGE Edge configuration 0x004 read-write 0x000 0xFFFFFFFF WAKEUP0_E Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0. [0:0] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_WAKEU Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1. 1 WAKEUP1_E Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0. [1:1] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_WAKEU Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1. 1 WAKEUP2_E Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0. [2:2] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_WAKEU Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1. 1 WAKEUP3_E Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0. [3:3] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_WAKEU Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1. 1 ATIMER_E Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0. [4:4] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_THE_A Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1. 1 RTC_E Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0. [5:5] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_THE_R Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1. 1 BOD_E Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0. [6:6] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_THE_B Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1. 1 WWDT_E Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0. [7:7] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_THE_W Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1. 1 ETH_E Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0. [8:8] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_THE_E Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1. 1 USB0_E Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0. [9:9] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_THE_U Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1. 1 USB1_E Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0. [10:10] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_THE_U Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1. 1 SDMMC_E Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0. [11:11] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_THE_S Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1. 1 CAN_E Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0. [12:12] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_THE_C Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1. 1 TIM2_E Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0. [13:13] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_GIMA Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1. 1 TIM6_E Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0. [14:14] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_GIMA Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1. 1 QEI_E Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0. [15:15] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_QEI_I Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1. 1 TIM14_E Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0. [16:16] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_GIMA Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1. 1 RESERVED Reserved. [18:17] RESET_E Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0. [19:19] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_THE_R Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1. 1 BODRESET_E Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0. [20:20] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_THE_R Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1. 1 DPDRESET_E Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0. [21:21] ENUM LEVEL_DETECT Level detect. 0 EDGE_DETECT_OF_THE_R Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1. 1 RESERVED Reserved. [31:22] CLR_EN Clear event enable register 0xFD8 write-only 0x0 0xFFFFFFFF WAKEUP0_CLREN Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register. [0:0] WAKEUP1_CLREN Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register. [1:1] WAKEUP2_CLREN Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register. [2:2] WAKEUP3_CLREN Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register. [3:3] ATIMER_CLREN Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register. [4:4] RTC_CLREN Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register. [5:5] BOD_CLREN Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register. [6:6] WWDT_CLREN Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register. [7:7] ETH_CLREN Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register. [8:8] USB0_CLREN Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register. [9:9] USB1_CLREN Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register. [10:10] SDMMC_CLREN Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register. [11:11] CAN_CLREN Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register. [12:12] TIM2_CLREN Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register. [13:13] TIM6_CLREN Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register. [14:14] QEI_CLREN Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register. [15:15] TIM14_CLREN Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register. [16:16] RESERVED Reserved. [18:17] RESET_CLREN Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register. [19:19] BODRESET_CLREN Writing a 1 to this bit clears the event enable bit 20 in the ENABLE register. [20:20] DPDRESET_CLREN Writing a 1 to this bit clears the event enable bit 21 in the ENABLE register. [21:21] RESERVED Reserved. [31:22] SET_EN Set event enable register 0xFDC write-only 0x0 0xFFFFFFFF WAKEUP0_SETEN Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register. [0:0] WAKEUP1_SETEN Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register. [1:1] WAKEUP2_SETEN Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register. [2:2] WAKEUP3_SETEN Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register. [3:3] ATIMER_SETEN Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register. [4:4] RTC_SETEN Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register. [5:5] BOD_SETEN Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register. [6:6] WWDT_SETEN Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register. [7:7] ETH_SETEN Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register. [8:8] USB0_SETEN Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register. [9:9] USB1_SETEN Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register. [10:10] SDMMC_SETEN Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register. [11:11] CAN_SETEN Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register. [12:12] TIM2_SETEN Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register. [13:13] TIM6_SETEN Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register. [14:14] QEI_SETEN Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register. [15:15] TIM14_SETEN Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register. [16:16] RESERVED Reserved. [18:17] RESET_SETEN Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register. [19:19] BODRESET_SETEN Writing a 1 to this bit sets the event enable bit 20 in the ENABLE register. [20:20] DPDRESET_SETEN Writing a 1 to this bit sets the event enable bit 21 in the ENABLE register. [21:21] RESERVED Reserved. [31:22] STATUS Event Status register 0xFE0 read-only 0x03FDFFFF 0xFFFFFFFF WAKEUP0_ST A 1 in this bit shows that the WAKEUP0 event has been raised. [0:0] WAKEUP1_ST A 1 in this bit shows that the WAKEUP1 event has been raised. [1:1] WAKEUP2_ST A 1 in this bit shows that the WAKEUP2 event has been raised. [2:2] WAKEUP3_ST A 1 in this bit shows that the WAKEUP3 event has been raised. [3:3] ATIMER_ST A 1 in this bit shows that the ATIMER event has been raised. [4:4] RTC_ST A 1 in this bit shows that the RTC event has been raised. [5:5] BOD_ST A 1 in this bit shows that the BOD event has been raised. [6:6] WWDT_ST A 1 in this bit shows that the WWDT event has been raised. [7:7] ETH_ST A 1 in this bit shows that the ETHERNET event has been raised. [8:8] USB0_ST A 1 in this bit shows that the USB0 event has been raised. [9:9] USB1_ST A 1 in this bit shows that the USB1 event has been raised. [10:10] SDMMC_ST A 1 in this bit indicates that the SDMMC event has been raised. [11:11] CAN_ST A 1 in this bit shows that the C_CAN event has been raised. [12:12] TIM2_ST A 1 in this bit shows that the combined timer 2 output event has been raised. [13:13] TIM6_ST A 1 in this bit shows that the combined timer 6 output event has been raised. [14:14] QEI_ST A 1 in this bit shows that the QEI event has been raised. [15:15] TIM14_ST A 1 in this bit shows that the combined timer 14 output event has been raised. [16:16] RESERVED Reserved. [18:17] RESET_ST A 1 in this bit shows that the reset event has been raised. [19:19] BODRESET_ST A 1 in this bit indicates that the reset event has been raised. [20:20] DPDRESET_ST A 1 in this bit indicates that the reset event has been raised. [21:21] RESERVED Reserved. [31:22] ENABLE Event Enable register 0xFE4 read-only 0x0 0xFFFFFFFF WAKEUP0_EN A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [0:0] WAKEUP1_EN A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [1:1] WAKEUP2_EN A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [2:2] WAKEUP3_EN A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [3:3] ATIMER_EN A 1 in this bit shows that the ATIMER event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [4:4] RTC_EN A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [5:5] BOD_EN A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [6:6] WWDT_EN A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [7:7] ETH_EN A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [8:8] USB0_EN A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [9:9] USB1_EN A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [10:10] SDMMC_EN A 1 in this bit indicates that the SDMMC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [11:11] CAN_EN A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [12:12] TIM2_EN A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [13:13] TIM6_EN A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [14:14] QEI_EN A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [15:15] TIM14_EN A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [16:16] RESERVED Reserved [18:17] RESET_EN A 1 in this bit shows that the RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [19:19] BODRESET_EN A 1 in this bit indicates that the BOD RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [20:20] DPDRESET_EN A 1 in this bit indicates that the deep power-down RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register. [21:21] RESERVED Reserved. [31:22] CLR_STAT Clear event status register 0xFE8 write-only 0x0 0xFFFFFFFF WAKEUP0_CLRST Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register. [0:0] WAKEUP1_CLRST Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register. [1:1] WAKEUP2_CLRST Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register. [2:2] WAKEUP3_CLRST Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register. [3:3] ATIMER_CLRST Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register. [4:4] RTC_CLRST Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register. [5:5] BOD_CLRST Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register. [6:6] WWDT_CLRST Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register. [7:7] ETH_CLRST Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register. [8:8] USB0_CLRST Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register. [9:9] USB1_CLRST Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register. [10:10] SDMMC_CLRST Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register. [11:11] CAN_CLRST Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register. [12:12] TIM2_CLRST Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register. [13:13] TIM6_CLRST Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register. [14:14] QEI_CLRST Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register. [15:15] TIM14_CLRST Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register. [16:16] RESERVED Reserved. [18:17] RESET_CLRST Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register. [19:19] BODRESET_CLRST Writing a 1 to this bit clears the STATUS event bit 20 in the STATUS register. [20:20] DPDRESET_CLRST Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register. [21:21] RESERVED Reserved. [31:22] SET_STAT Set event status register 0xFEC write-only 0x0 0xFFFFFFFF WAKEUP0_SETST Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register. [0:0] WAKEUP1_SETST Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register. [1:1] WAKEUP2_SETST Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register. [2:2] WAKEUP3_SETST Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register. [3:3] ATIMER_SETST Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register. [4:4] RTC_SETST Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register. [5:5] BOD_SETST Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register. [6:6] WWDT_SETST Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register. [7:7] ETH_SETST Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register. [8:8] USB0_SETST Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register. [9:9] USB1_SETST Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register. [10:10] SDMMC_SETST Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register. [11:11] CAN_SETST Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register. [12:12] TIM2_SETST Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register. [13:13] TIM6_SETST Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register. [14:14] QEI_SETST Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register. [15:15] TIM14_SETST Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register. [16:16] RESERVED Reserved. [18:17] RESET_SETST Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register. [19:19] BODRESET_SETST Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register. [20:20] DPDRESET_SETST Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register. [21:21] RESERVED Reserved. [31:22] RTC Real-Time Clock (RTC) and event recorder RTC 0x40046000 0 0xFFFF registers RTC 47 ILR Interrupt Location Register 0x000 write-only 0x0 0xFFFFFFFF RTCCIF When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt. [0:0] RTCALF When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] CCR Clock Control Register 0x008 read-write 0x00 0xFFFFFFFF CLKEN Clock Enable. [0:0] ENUM DISABLED The time counters are disabled so that they may be initialized. 0 ENABLED The time counters are enabled. 1 CTCRST CTC Reset. [1:1] ENUM NO_EFFECT No effect. 0 RESET When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software. 1 RESERVED Internal test mode controls. These bits must be 0 for normal RTC operation. [3:2] CCALEN Calibration counter enable. [4:4] ENUM ENABLED The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and Section 29.7.1. 0 DISABLED The calibration counter is disabled and reset to zero. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] CIIR Counter Increment Interrupt Register 0x00C read-write 0x00 0xFFFFFFFF IMSEC When 1, an increment of the Second value generates an interrupt. [0:0] IMMIN When 1, an increment of the Minute value generates an interrupt. [1:1] IMHOUR When 1, an increment of the Hour value generates an interrupt. [2:2] IMDOM When 1, an increment of the Day of Month value generates an interrupt. [3:3] IMDOW When 1, an increment of the Day of Week value generates an interrupt. [4:4] IMDOY When 1, an increment of the Day of Year value generates an interrupt. [5:5] IMMON When 1, an increment of the Month value generates an interrupt. [6:6] IMYEAR When 1, an increment of the Year value generates an interrupt. [7:7] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] AMR Alarm Mask Register 0x010 read-write 0 0xFFFFFFFF AMRSEC When 1, the Second value is not compared for the alarm. [0:0] AMRMIN When 1, the Minutes value is not compared for the alarm. [1:1] AMRHOUR When 1, the Hour value is not compared for the alarm. [2:2] AMRDOM When 1, the Day of Month value is not compared for the alarm. [3:3] AMRDOW When 1, the Day of Week value is not compared for the alarm. [4:4] AMRDOY When 1, the Day of Year value is not compared for the alarm. [5:5] AMRMON When 1, the Month value is not compared for the alarm. [6:6] AMRYEAR When 1, the Year value is not compared for the alarm. [7:7] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] CTIME0 Consolidated Time Register 0 0x014 read-only 0 0xFFFFFFFF SECONDS Seconds value in the range of 0 to 59 [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:6] MINUTES Minutes value in the range of 0 to 59 [13:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:14] HOURS Hours value in the range of 0 to 23 [20:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [23:21] DOW Day of week value in the range of 0 to 6 [26:24] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:27] CTIME1 Consolidated Time Register 1 0x018 read-only 0 0xFFFFFFFF DOM Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:5] MONTH Month value in the range of 1 to 12. [11:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:12] YEAR Year value in the range of 0 to 4095. [27:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:28] CTIME2 Consolidated Time Register 2 0x01C read-only 0 0xFFFFFFFF DOY Day of year value in the range of 1 to 365 (366 for leap years). [11:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] SEC Seconds Register 0x020 read-write 0 0xFFFFFFFF SECONDS Seconds value in the range of 0 to 59 [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] MIN Minutes Register 0x024 read-write 0 0xFFFFFFFF MINUTES Minutes value in the range of 0 to 59 [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] HRS Hours Register 0x028 read-write 0 0xFFFFFFFF HOURS Hours value in the range of 0 to 23 [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] DOM Day of Month Register 0x02C read-write 0 0xFFFFFFFF DOM Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] DOW Day of Week Register 0x030 read-write 0 0xFFFFFFFF DOW Day of week value in the range of 0 to 6. [2:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] DOY Day of Year Register 0x034 read-write 0 0xFFFFFFFF DOY Day of year value in the range of 1 to 365 (366 for leap years). [8:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:9] MONTH Months Register 0x038 read-write 0 0xFFFFFFFF MONTH Month value in the range of 1 to 12. [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] YEAR Years Register 0x03C read-write 0 0xFFFFFFFF YEAR Year value in the range of 0 to 4095. [11:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CALIBRATION Calibration Value Register 0x040 read-write 0 0xFFFFFFFF CALVAL If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0. [16:0] CALDIR Calibration direction [17:17] ENUM FORWARD_CALIBRATION_ Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds. 0 BACKWARD_CALIBRATION Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second. 1 ASEC Alarm value for Seconds 0x060 read-write 0 0xFFFFFFFF SECONDS Seconds value in the range of 0 to 59 [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] AMIN Alarm value for Minutes 0x064 read-write 0 0xFFFFFFFF MINUTES Minutes value in the range of 0 to 59 [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] AHRS Alarm value for Hours 0x068 read-write 0 0xFFFFFFFF HOURS Hours value in the range of 0 to 23 [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] ADOM Alarm value for Day of Month 0x6C read-write 0 0xFFFFFFFF DOM Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). [4:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] ADOW Alarm value for Day of Week 0x070 read-write 0 0xFFFFFFFF DOW Day of week value in the range of 0 to 6. [2:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:3] ADOY Alarm value for Day of Year 0x074 read-write 0 0xFFFFFFFF DOY Day of year value in the range of 1 to 365 (366 for leap years). [8:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:9] AMON Alarm value for Months 0x078 read-write 0 0xFFFFFFFF MONTH Month value in the range of 1 to 12. [3:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] AYRS Alarm value for Year 0x07C read-write 0 0xFFFFFFFF YEAR Year value in the range of 0 to 4095. [11:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] ERCONTRO Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup. 0x084 read-write 0 0xFFFFFFFF INTWAKE_EN0 Interrupt and wake-up enable for channel 0. [0:0] ENUM DISABLED No interrupt or wake-up will be generated by event channel 0. 0 ENABLED An event in channel 0 will trigger an (RTC) interrupt and a wake-up request. 1 GPCLEAR_EN0 Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0. [1:1] ENUM DISABLED Channel 0 has no influence on the general purpose registers. 0 ENABLED An event in channel 0 will clear the general purpose registers asynchronously. 1 POL0 Selects the polarity of an event on input pin WAKEUP0. [2:2] ENUM NEGATIVE A channel 0 event is defined as a negative edge on WAKEUP0. 0 POSITIVE A channel 0 event is defined as a positive edge on WAKEUP0. 1 EV0_INPUT_EN Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function. [3:3] ENUM DISABLED Event 0 input is disabled and forced high internally. 0 ENABLED Event 0 input is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [9:4] INTWAKE_EN1 Interrupt and wake-up enable for channel 1. [10:10] ENUM DISABLED No interrupt or wake-up will be generated by event channel 1. 0 ENABLED An event in channel 1 will trigger an (RTC) interrupt and a wake-up request. 1 GPCLEAR_EN1 Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1. [11:11] ENUM DISABLED Channel 1 has no influence on the general purpose registers. 0 ENABLED A n event in channel 1 will clear the general purpose registers asynchronously. 1 POL1 Selects the polarity of an event on input pin WAKEUP1. [12:12] ENUM NEGATIVE A channel 1 event is defined as a negative edge on WAKEUP1. 0 POSITIVE A channel 1 event is defined as a positive edge on WAKEUP1. 1 EV1_INPUT_EN Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function. [13:13] ENUM DISABLED Event 1 input is disabled and forced high internally. 0 ENABLED Event 1 input is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [19:14] INTWAKE_EN2 Interrupt and wake-up enable for channel 2. [20:20] ENUM DISABLED No interrupt or wake-up will be generated by event channel 2. 0 ENABLED An event in channel 2 will trigger an (RTC) interrupt and a wake-up request. 1 GPCLEAR_EN2 Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2. [21:21] ENUM DISABLED Channel 2 has no influence on the general purpose registers. 0 ENABLED An event in channel 2 will clear the general purpose registers asynchronously. 1 POL2 Selects the polarity of an event on input pin WAKEUP2. [22:22] ENUM NEGATIVE A channel 2 event is defined as a negative edge on WAKEUP2. 0 POSITIVE A channel 2 event is defined as a positive edge on WAKEUP2. 1 EV2_INPUT_EN Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function. [23:23] ENUM DISABLED Event 2 input is disabled and forced high internally. 0 ENABLED Event 2 input is enabled. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [29:24] ERMODE Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized. [31:30] ENUM DISABLE_EVENT_MONITO Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected. 0x0 16_HZ_SAMPLE_CLOCK 16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out. 0x1 64_HZ_SAMPLE_CLOCK 64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out. 0x2 1_KHZ_SAMPLE_CLOCK 1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out. 0x3 ERSTATUS Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions. 0x080 read-write 0 0xFFFFFFFF EV0 Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect. [0:0] ENUM NO_CHANGE No event change on channel 0. 0 EVENT At least one event has occurred on channel 0. 1 EV1 Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect. [1:1] ENUM NO_CHANGE No event change on channel 1. 0 EVENT At least one event has occurred on channel 1. 1 EV2 Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect. [2:2] ENUM NO_CHANGE No event change on channel 2. 0 EVENT At least one event has occurred on channel 2. 1 GP_CLEARED General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect. [3:3] ENUM NO_CHANGE General purpose registers have not been asynchronous cleared. 0 EVENT General purpose registers have been asynchronous cleared. 1 RESERVED Reserved. Read value is undefined, only zero should be written. [30:4] WAKEUP Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect. [31:31] ENUM NOINTERRUPTWAKEUP No interrupt/wake-up request is pending 0 INTERRUPTWAKEUP An interrupt/wake-up request is pending. 1 ERCOUNTERS Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels. 0x088 read-only 0 0xFFFFFFFF COUNTER0 Value of the counter for Event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software. [2:0] RESERVED Reserved. The value read from a reserved bit is not defined. [7:3] COUNTER1 Value of the counter for event 1. See description for COUNTER0. [10:8] RESERVED Reserved. The value read from a reserved bit is not defined. [15:11] COUNTER2 Value of the counter for event 2. See description for COUNTER0. [18:16] RESERVED Reserved. The value read from a reserved bit is not defined. [31:19] 3 0x4 0-2 ERFIRSTSTAMP%s Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0. 0x090 read-only 0 0x00000000 SEC Seconds value in the range of 0 to 59. [5:0] MIN Minutes value in the range of 0 to 59. [11:6] HOUR Hours value in the range of 0 to 23. [16:12] DOY Day of Year value in the range of 1 to 366. [25:17] RESERVED Reserved. The value read from a reserved bit is not defined. [31:26] 3 0x4 0-2 ERLASTSTAMP%s Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0. 0x0A0 read-only 0 0x00000000 SEC Seconds value in the range of 0 to 59. [5:0] MIN Minutes value in the range of 0 to 59. [11:6] HOUR Hours value in the range of 0 to 23. [16:12] DOY Day of Year value in the range of 1 to 366. [25:17] RESERVED Reserved. The value read from a reserved bit is not defined. [31:26] CGU Clock Generation Unit (CGU) CGU 0x40050000 0x0 0xFFF registers FREQ_MON Frequency monitor register 0x014 read-write 0 0xFFFFFFFF RCNT 9-bit reference clock-counter value [8:0] FCNT 14-bit selected clock-counter value [22:9] MEAS Measure frequency [23:23] ENUM RCNT_AND_FCNT_DISABL RCNT and FCNT disabled 0 FREQUENCY_COUNTERS_S Frequency counters started 1 CLK_SEL Clock-source selection for the clock to be measured. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR_D 32 kHz oscillator (default) 0x00 IRC IRC 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 RESERVED Reserved 0x05 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0USB PLL0USB 0x07 PLL0AUDIO PLL0AUDIO 0x08 PLL1 PLL1 0x09 RESERVED Reserved 0x0A RESERVED Reserved 0x0B IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] XTAL_OSC_CTRL Crystal oscillator control register 0x018 read-write 0x00000005 0xFFFFFFFF ENABLE Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation! [0:0] ENUM ENABLE Enable 0 POWER_DOWN Power-down (default) 1 BYPASS Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation! [1:1] ENUM CRYSTAL Crystal. Operation with crystal connected (default). 0 BYPASS_MODE Bypass mode. Use this mode when an external clock source is used instead of a crystal. 1 HF Select frequency range [2:2] ENUM LOW Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care. 0 HIGH High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care. 1 RESERVED Reserved [31:3] PLL0USB_STAT PLL0USB status register 0x01C read-only 0x01000000 0xFFFFFFFF LOCK PLL0 lock indicator [0:0] FR PLL0 free running indicator [1:1] RESERVED Reserved [31:2] PLL0USB_CTRL PLL0USB control register 0x020 read-write 0x01000003 0xFFFFFFFF PD PLL0 power down [0:0] ENUM PLL0_ENABLED PLL0 enabled 0 PLL0_POWERED_DOWN PLL0 powered down 1 BYPASS Input clock bypass control [1:1] ENUM CCO_CLOCK_SENT_TO_PO CCO clock sent to post-dividers. Use this in normal operation. 0 PLL0_INPUT_CLOCK_SEN PLL0 input clock sent to post-dividers (default). 1 DIRECTI PLL0 direct input [2:2] DIRECTO PLL0 direct output [3:3] CLKEN PLL0 clock enable [4:4] RESERVED Reserved [5:5] FRM Free running mode [6:6] RESERVED Reserved [7:7] RESERVED Reserved. Reads as zero. Do not write one to this register. [8:8] RESERVED Reserved. Reads as zero. Do not write one to this register. [9:9] RESERVED Reserved. Reads as zero. Do not write one to this register. [10:10] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] PLL0USB_MDIV PLL0USB M-divider register 0x024 read-write 0x05F85B6A 0xFFFFFFFF MDEC Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071. [16:0] SELP Bandwidth select P value [21:17] SELI Bandwidth select I value [27:22] SELR Bandwidth select R value; SELR = 0. [31:28] PLL0USB_NP_DIV PLL0USB N/P-divider register 0x028 read-write 0x000B1002 0xFFFFFFFF PDEC Decoded P-divider coefficient value [6:0] RESERVED Reserved [11:7] NDEC Decoded N-divider coefficient value [21:12] RESERVED Reserved [31:22] PLL0AUDIO_STAT PLL0AUDIO status register 0x02C read-only 0x01000000 0xFFFFFFFF LOCK PLL0 lock indicator [0:0] FR PLL0 free running indicator [1:1] RESERVED Reserved [31:2] PLL0AUDIO_CTRL PLL0AUDIO control register 0x030 read-write 0x01004003 0xFFFFFFFF PD PLL0 power down [0:0] ENUM PLL0_ENABLED PLL0 enabled 0 PLL0_POWERED_DOWN PLL0 powered down 1 BYPASS Input clock bypass control [1:1] ENUM CCO_CLOCK_SENT_TO_PO CCO clock sent to post-dividers. Use this in normal operation. 0 PLL0_INPUT_CLOCK_SEN PLL0 input clock sent to post-dividers (default). 1 DIRECTI PLL0 direct input [2:2] DIRECTO PLL0 direct output [3:3] CLKEN PLL0 clock enable [4:4] RESERVED Reserved [5:5] FRM Free running mode [6:6] RESERVED Reserved [7:7] RESERVED Reserved. Reads as zero. Do not write one to this register. [8:8] RESERVED Reserved. Reads as zero. Do not write one to this register. [9:9] RESERVED Reserved. Reads as zero. Do not write one to this register. [10:10] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 PLLFRACT_REQ Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit. [12:12] SEL_EXT Select fractional divider. [13:13] ENUM FRAC_ENABLED FRAC Enabled. Enable fractional divider. 0 MDEC_ENABLED MDEC enabled. Fractional divider not used. 1 MOD_PD Sigma-Delta modulator power-down [14:14] ENUM ENABLED Enabled. Sigma-Delta modulator enabled 0 DISABLED Disabled. Sigma-Delta modulator powered down 1 RESERVED Reserved [23:15] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] PLL0AUDIO_MDIV PLL0AUDIO M-divider register 0x034 read-write 0x05F85B6A 0xFFFFFFFF MDEC Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071. [16:0] RESERVED Reserved [31:17] PLL0AUDIO_NP_DIV PLL0AUDIO N/P-divider register 0x038 read-write 0x000B1002 0xFFFFFFFF PDEC Decoded P-divider coefficient value [6:0] RESERVED Reserved [11:7] NDEC Decoded N-divider coefficient value [21:12] RESERVED Reserved [31:22] PLL0AUDIO_FRAC PLL0AUDIO fractional divider register 0x03C read-write 0x00200000 0xFFFFFFFF PLLFRACT_CTRL PLL fractional divider control word [21:0] RESERVED Reserved [31:22] PLL1_STAT PLL1 status register 0x040 read-only 0x01000000 0xFFFFFFFF LOCK PLL1 lock indicator [0:0] RESERVED Reserved [31:1] PLL1_CTRL PLL1 control register 0x044 read-write 0x01000003 0xFFFFFFFF PD PLL1 power down [0:0] ENUM PLL1_ENABLED PLL1 enabled 0 PLL1_POWERED_DOWN PLL1 powered down 1 BYPASS Input clock bypass control [1:1] ENUM NORMAL Normal. CCO clock sent to post-dividers. Use for normal operation. 0 INPUT_CLOCK Input clock. PLL1 input clock sent to post-dividers (default). 1 RESERVED Reserved. Do not write one to this bit. [2:2] RESERVED Reserved. Do not write one to these bits. [5:3] FBSEL PLL feedback select. [6:6] ENUM CCO_OUT CCO out. CCO output is used as feedback divider input clock. 0 PLL_OUT PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation. 1 DIRECT PLL direct CCO output [7:7] ENUM DISABLED Disabled 0 ENABLED Enabled 1 PSEL Post-divider division ratio P. The value applied is 2xP. [9:8] ENUM 1 1 0x0 PEQ2 2 (default) 0x1 PEQ4 4 0x2 8 8 0x3 RESERVED Reserved [10:10] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 NSEL Pre-divider division ratio N [13:12] ENUM 1 1 0x0 NEQ2 2 0x1 NEQ3 3 (default) 0x2 4 4 0x3 RESERVED Reserved [15:14] MSEL Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2 ... 11111111 = 256 [23:16] CLK_SEL Clock-source selection. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 RESERVED Reserved 0x05 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0USB PLL0USB 0x07 PLL0AUDIO PLL0AUDIO 0x08 RESERVED Reserved 0x09 RESERVED Reserved 0x0A IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] IDIVA_CTRL Integer divider A control register 0x048 read-write 0x01000000 0xFFFFFFFF PD Integer divider A power down [0:0] ENUM ENABLED Enabled. IDIVA enabled (default) 0 POWER_DOWN Power-down 1 RESERVED Reserved [1:1] IDIV Integer divider A divider values (1/(IDIV + 1)) [3:2] ENUM DIV1 1 (default) 0x0 DIV2 2 0x1 DIV3 3 0x2 DIV4 4 0x3 RESERVED Reserved [10:4] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0USB PLL0USB 0x07 PLL0AUDIO PLL0AUDIO 0x08 PLL1 PLL1 0x09 RESERVED Reserved [31:29] IDIVB_CTRL Integer divider B control register 0x04C read-write 0x01000000 0xFFFFFFFF PD Integer divider power down [0:0] ENUM ENABLED Enabled. IDIV enabled (default) 0 POWER_DOWN Power-down 1 RESERVED Reserved [1:1] IDIV Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16 [5:2] RESERVED Reserved [10:6] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock-source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0AUDIO PLL0AUDIO 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C RESERVED Reserved [31:29] IDIVC_CTRL Integer divider C control register 0x050 read-write 0x01000000 0xFFFFFFFF PD Integer divider power down [0:0] ENUM ENABLED Enabled. IDIV enabled (default) 0 POWER_DOWN Power-down 1 RESERVED Reserved [1:1] IDIV Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16 [5:2] RESERVED Reserved [10:6] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock-source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0AUDIO PLL0AUDIO 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C RESERVED Reserved [31:29] IDIVD_CTRL Integer divider D control register 0x054 read-write 0x01000000 0xFFFFFFFF PD Integer divider power down [0:0] ENUM ENABLED Enabled. IDIV enabled (default) 0 POWER_DOWN Power-down 1 RESERVED Reserved [1:1] IDIV Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16 [5:2] RESERVED Reserved [10:6] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock-source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0AUDIO PLL0AUDIO 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C RESERVED Reserved [31:29] IDIVE_CTRL Integer divider E control register 0x058 read-write 0x01000000 0xFFFFFFFF PD Integer divider power down [0:0] ENUM ENABLED Enabled. IDIV enabled (default) 0 POWER_DOWN Power-down 1 RESERVED Reserved [1:1] IDIV Integer divider E divider values (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2 ... 111111111 = 256 [9:2] RESERVED Reserved [10:10] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock-source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0AUDIO PLL0AUDIO 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C RESERVED Reserved [31:29] BASE_SAFE_CLK Output stage 0 control register for base clock BASE_SAFE_CLK 0x05C read-only 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM ENABLED Enabled. Output stage enabled (default) 0 POWER_DOWN Power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM IRC_DEFAULT IRC (default) 0x01 RESERVED Reserved [31:29] BASE_USB0_CLK Output stage 1 control register for base clock BASE_USB0_CLK 0x060 read-write 0x07000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM ENABLED Enabled. Output stage enabled (default) 0 POWER_DOWN Power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock-source selection. [28:24] ENUM PLL0USB PLL0USB (default) 0x07 RESERVED Reserved [31:29] BASE_PERIPH_CLK Output stage 2 control register for base clock BASE_PERIPH_CLK 0x064 read-write 0x07000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM ENABLED Enabled. Output stage enabled (default) 0 POWER_DOWN Power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0AUDIO PLL0AUDIO 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_USB1_CLK Output stage 3 control register for base clock BASE_USB1_CLK 0x068 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM ENABLED Enabled. Output stage enabled (default) 0 POWER_DOWN Power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0USB PLL0USB 0x07 PLL0AUDIO PLL0AUDIO 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_M4_CLK Output stage BASE_M4_CLK control register 0x06C read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_SPIFI_CLK Output stage BASE_SPIFI_CLK control register 0x070 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_SPI_CLK Output stage BASE_SPI_CLK control register 0x074 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_PHY_RX_CLK Output stage BASE_PHY_RX_CLK control register 0x078 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_PHY_TX_CLK Output stage BASE_PHY_TX_CLK control register 0x07C read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_APB1_CLK Output stage BASE_APB1_CLK control register 0x080 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_APB3_CLK Output stage BASE_APB3_CLK control register 0x084 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_LCD_CLK Output stage BASE_LCD_CLK control register 0x088 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_SDIO_CLK Output stage BASE_SDIO_CLK control register 0x090 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_SSP0_CLK Output stage BASE_SSP0_CLK control register 0x094 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_SSP1_CLK Output stage BASE_SSP1_CLK control register 0x098 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_UART0_CLK Output stage BASE_UART0_CLK control register 0x09C read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_UART1_CLK Output stage BASE_UART1_CLK control register 0x0A0 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_UART2_CLK Output stage BASE_UART2_CLK control register 0x0A4 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_UART3_CLK Output stage BASE_UART3_CLK control register 0x0A8 read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM DISABLED Disabled. Autoblocking disabled 0 ENABLED Enabled. Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock source selection. All other values are reserved. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_OUT_CLK Output stage 20 control register for base clock BASE_OUT_CLK 0x0AC read-write 0x01000000 0xFFFFFFFF PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM AUTOBLOCKING_DISABLE Autoblocking disabled 0 AUTOBLOCKING_ENABLED Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock-source selection. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 RESERVED Reserved 0x05 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 PLL0_FOR_USB PLL0 (for USB) 0x07 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_AUDIO_CLK Output stage 25 control register for base clock BASE_AUDIO_CLK 0x0C0 read-write 0 0x00000000 PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM AUTOBLOCKING_DISABLE Autoblocking disabled 0 AUTOBLOCKING_ENABLED Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock-source selection. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 RESERVED Reserved 0x05 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 RESERVED Reserved 0x07 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_CGU_OUT0_CLK Output stage 25 control register for base clock BASE_CGU_OUT0_CLK 0x0C4 read-write 0 0x00000000 PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM AUTOBLOCKING_DISABLE Autoblocking disabled 0 AUTOBLOCKING_ENABLED Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock-source selection. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 RESERVED Reserved 0x05 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 RESERVED Reserved 0x07 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] BASE_CGU_OUT1_CLK Output stage 25 control register for base clock BASE_CGU_OUT1_CLK 0x0C8 read-write 0 0x00000000 PD Output stage power down [0:0] ENUM OUTPUT_STAGE_ENABLED Output stage enabled (default) 0 POWER_DOWN power-down 1 RESERVED Reserved [10:1] AUTOBLOCK Block clock automatically during frequency change [11:11] ENUM AUTOBLOCKING_DISABLE Autoblocking disabled 0 AUTOBLOCKING_ENABLED Autoblocking enabled 1 RESERVED Reserved [23:12] CLK_SEL Clock-source selection. [28:24] ENUM 32_KHZ_OSCILLATOR 32 kHz oscillator 0x00 IRC_DEFAULT IRC (default) 0x01 ENET_RX_CLK ENET_RX_CLK 0x02 ENET_TX_CLK ENET_TX_CLK 0x03 GP_CLKIN GP_CLKIN 0x04 RESERVED Reserved 0x05 CRYSTAL_OSCILLATOR Crystal oscillator 0x06 RESERVED Reserved 0x07 PLL0_FOR_AUDIO PLL0 (for audio) 0x08 PLL1 PLL1 0x09 IDIVA IDIVA 0x0C IDIVB IDIVB 0x0D IDIVC IDIVC 0x0E IDIVD IDIVD 0x0F IDIVE IDIVE 0x10 RESERVED Reserved [31:29] CCU1 Clock Control Unit (CCU) CCU1 0x40051000 0 0xFFFF registers PM CCU1 power mode register 0x000 read-write 0x00000000 0xFFFFFFFF PD Initiate power-down mode [0:0] ENUM NORMAL_OPERATION_ Normal operation. 0 CLOCKS_WITH_WAKE_UP_ Clocks with wake-up mode enabled (W = 1) are disabled. 1 RESERVED Reserved. [31:1] BASE_STAT CCU1 base clocks status register 0x004 read-only 0x00000FFF 0xFFFFFFFF BASE_APB3_CLK_IND Base clock indicator for BASE_APB3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. [0:0] BASE_APB1_CLK_IND Base clock indicator for BASE_APB1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. [1:1] BASE_SPIFI_CLK_IND Base clock indicator for BASE_SPIFI_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. [2:2] BASE_M3_CLK_IND Base clock indicator for BASE_M3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. [3:3] RESERVED Reserved [6:4] BASE_USB0_CLK_IND Base clock indicator for BASE_USB0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. [7:7] BASE_USB1_CLK_IND Base clock indicator for BASE_USB1_CLK 0 = All branch clocks switched off. 1 = at least one branch clock running. [8:8] RESERVED Reserved [31:9] CLK_APB3_BUS_CFG CLK_APB3_BUS clock configuration register 0x100 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_APB3_I2C1_CFG CLK_APB3_I2C1 clock configuration register 0x0108 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_APB3_DAC_CFG CLK_APB3_DAC clock configuration register 0x0110 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_APB3_ADC0_CFG CLK_APB3_ADC0 clock configuration register 0x0118 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_APB3_ADC1_CFG CLK_APB3_ADC1 clock configuration register 0x0120 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_APB3_CAN0_CFG CLK_APB3_CAN0 clock configuration register 0x0128 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_APB1_BUS_CFG CLK_APB1_BUS clock configuration register 0x200 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_APB1_MOTOCONPWM_CFG CLK_APB1_MOTOCONPWM clock configuration register 0x0208 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_APB1_I2C0_CFG CLK_ABP1_I2C0 clock configuration register 0x0210 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_APB1_I2S_CFG CLK_APB1_I2S clock configuration register 0x0218 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_APB1_CAN1_CFG CLK_APB1_CAN1 clock configuration register 0x0220 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_SPIFI_CFG CLK_SPIFI clock configuration register 0x300 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_BUS_CFG CLK_M4_BUS clock configuration register 0x400 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_SPIFI_CFG CLK_M4_SPIFI clock configuration register 0x0408 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_GPIO_CFG CLK_M4_GPIO clock configuration register 0x0410 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_LCD_CFG CLK_M4_LCD clock configuration register 0x0418 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_ETHERNET_CFG CLK_M4_ETHERNET clock configuration register 0x0420 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_USB0_CFG CLK_M4_USB0 clock configuration register 0x0428 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_EMC_CFG CLK_M4_EMC clock configuration register 0x0430 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_SDIO_CFG CLK_M4_SDIO clock configuration register 0x0438 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_DMA_CFG CLK_M4_DMA clock configuration register 0x0440 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_M4CORE_CFG CLK_M4_M4CORE clock configuration register 0x0448 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_SCT_CFG CLK_M4_SCT clock configuration register 0x0468 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_USB1_CFG CLK_M4_USB1 clock configuration register 0x0470 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_EMCDIV_CFG CLK_M4_EMCDIV clock configuration register 0x0478 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [4:3] DIV Clock divider value [7:5] DIVIDEBY1 No division. Divide by 1. 0x0 DIVIDEBY2 Divide by 2. 0x1 RESERVED Reserved [31:8] CLK_M4_FLASHA_CFG CLK_M4_FLASHA clock configuration register 0x0480 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_FLASHB_CFG CLK_M4_FLASHB clock configuration register 0x0488 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_M0APP_CFG CLK_M0APP_CFG clock configuration register 0x0490 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_ADCHS_CFG CLK_ADCHS_CFG clock configuration register 0x0498 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_EEPROM_CFG CLK_EEPROM_CFG clock configuration register 0x04A0 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_WWDT_CFG CLK_M4_WWDT clock configuration register 0x500 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_USART0_CFG CLK_M4_USART0 clock configuration register 0x0508 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_UART1_CFG CLK_M4_UART1 clock configuration register 0x0510 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_SSP0_CFG CLK_M4_SSP0 clock configuration register 0x0518 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_TIMER0_CFG CLK_M4_TIMER0 clock configuration register 0x0520 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_TIMER1_CFG CLK_M4_TIMER1clock configuration register 0x0528 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_SCU_CFG CLK_M4_SCU clock configuration register 0x0530 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_CREG_CFG CLK_M4_CREGclock configuration register 0x0538 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_RITIMER_CFG CLK_M4_RITIMER clock configuration register 0x600 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_USART2_CFG CLK_M4_USART2 clock configuration register 0x0608 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_USART3_CFG CLK_M4_USART3 clock configuration register 0x0610 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_TIMER2_CFG CLK_M4_TIMER2 clock configuration register 0x0618 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_TIMER3_CFG CLK_M4_TIMER3 clock configuration register 0x0620 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_SSP1_CFG CLK_M4_SSP1 clock configuration register 0x0628 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_M4_QEI_CFG CLK_M4_QEIclock configuration register 0x0630 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_PERIPH_BUS_CFG CLK_PERIPH_BUS_CFG clock configuration register 0x0700 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_PERIPH_CORE_CFG CLK_PERIPH_CORE_CFG clock configuration register 0x0710 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_PERIPH_SGPIO_CFG CLK_PERIPH_SGPIO_CFG clock configuration register 0x0718 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_USB0_CFG CLK_M4_USB0 clock configuration register 0x800 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM AUTO_IS_DISABLED_ Auto is disabled. 0 AUTO_IS_ENABLED_ Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM WAKE_UP_IS_DISABLED_ Wake-up is disabled. 0 WAKE_UP_IS_ENABLED_ Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_USB1_CFG CLK_USB1 clock configuration register 0x900 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM AUTO_IS_DISABLED_ Auto is disabled. 0 AUTO_IS_ENABLED_ Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM WAKE_UP_IS_DISABLED_ Wake-up is disabled. 0 WAKE_UP_IS_ENABLED_ Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_SPI_CFG CLK_SPI clock configuration register 0xA00 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM AUTO_IS_DISABLED_ Auto is disabled. 0 AUTO_IS_ENABLED_ Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM WAKE_UP_IS_DISABLED_ Wake-up is disabled. 0 WAKE_UP_IS_ENABLED_ Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_ADCHS_CFG CLK_ADCHS clock configuration register 0xB00 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM AUTO_IS_DISABLED_ Auto is disabled. 0 AUTO_IS_ENABLED_ Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM WAKE_UP_IS_DISABLED_ Wake-up is disabled. 0 WAKE_UP_IS_ENABLED_ Wake-up is enabled. 1 RESERVED Reserved [31:3] CLK_APB3_BUS_STAT CLK_APB3_BUS clock status register 0x104 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB3_I2C1_STAT CLK_APB3_I2C1 clock status register 0x010C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB3_DAC_STAT CLK_APB3_DAC clock status register 0x0114 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB3_ADC0_STAT CLK_APB3_ADC0 clock status register 0x011C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB3_ADC1_STAT CLK_APB3_ADC1 clock status register 0x0124 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB3_CAN0_STAT CLK_APB3_CAN0 clock status register 0x012C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB1_BUS_STAT CLK_APB1_BUS clock status register 0x204 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB1_MOTOCONPWM_STAT CLK_APB1_MOTOCONPWM clock status register 0x020C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB1_I2C0_STAT CLK_APB1_I2C0 clock status register 0x0214 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB1_I2S_STAT CLK_APB1_I2S clock status register 0x021C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB1_CAN1_STAT CLK_APB1_CAN1 clock status register 0x0224 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_SPIFI_STAT CLK_APB1_SPIFI clock status register 0x304 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_BUS_STAT CLK_M4_BUSclock status register 0x404 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_SPIFI_STAT CLK_M4_SPIFI clock status register 0x040C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_GPIO_STAT CLK_M4_GPIO clock status register 0x0414 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_LCD_STAT CLK_M4_LCD clock status register 0x041C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_ETHERNET_STAT CLK_M4_ETHERNET clock status register 0x0424 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_USB0_STAT CLK_M4_USB0 clock status register 0x042C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_EMC_STAT CLK_M4_EMC clock status register 0x0434 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_SDIO_STAT CLK_M4_SDIO clock status register 0x043C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_DMA_STAT CLK_M4_DMA clock status register 0x0444 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_M4CORE_STAT CLK_M4_M3CORE clock status register 0x044C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_SCT_STAT CLK_M4_SCT clock status register 0x046C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_USB1_STAT CLK_M4_USB1 clock status register 0x0474 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_EMCDIV_STAT CLK_M4_EMCDIV clock status register 0x047C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_FLASHA_STAT CLK_M4_FLASHA clock status register 0x0484 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_FLASHB_STAT CLK_M4_FLASHB clock status register 0x048C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_M0APP_STAT CLK_M4_MOAPP clock status register 0x0494 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_ADCHS_STAT CLK_M4_ADCHS clock status register 0x049C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_EEPROM_STAT CLK_M4_EEPROM clock status register 0x04A4 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_WWDT_STAT CLK_M4_WWDT clock status register 0x504 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_USART0_STAT CLK_M4_USART0 clock status register 0x050C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_UART1_STAT CLK_M4_UART1 clock status register 0x0514 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_SSP0_STAT CLK_M4_SSP0 clock status register 0x051C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_TIMER0_STAT CLK_M4_TIMER0 clock status register 0x0524 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_TIMER1_STAT CLK_M4_TIMER1 clock status register 0x052C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_SCU_STAT CLK_SCU_XXX clock status register 0x0534 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_CREG_STAT CLK_M4_CREG clock status register 0x053C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_RITIMER_STAT CLK_M4_RITIMER clock status register 0x604 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_USART2_STAT CLK_M4_USART2 clock status register 0x060C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_USART3_STAT CLK_M4_USART3 clock status register 0x0614 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_TIMER2_STAT CLK_M4_TIMER2 clock status register 0x061C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_TIMER3_STAT CLK_M4_TIMER3 clock status register 0x0624 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_SSP1_STAT CLK_M4_SSP1 clock status register 0x062C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_M4_QEI_STAT CLK_M4_QEI clock status register 0x0634 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_PERIPH_BUS_STAT CLK_PERIPH_BUS_STAT clock status register 0x0704 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_PERIPH_CORE_STAT CLK_CORE_BUS_STAT clock status register 0x0714 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_PERIPH_SGPIO_STAT CLK_CORE_SGPIO_STAT clock status register 0x071C read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_USB0_STAT CLK_USB0 clock status register 0x804 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_USB1_STAT CLK_USB1 clock status register 0x904 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_SPI_STAT CLK_SPI clock status register 0xA04 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_ADCHS_STAT CLK_ADCHS clock status register 0xB04 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CCU2 Clock Control Unit (CCU2) CCU2 0x40052000 0 0xFFFF registers PM Power mode register 0x000 read-write 0x00000000 0xFFFFFFFF PD Initiate power-down mode [0:0] ENUM NORMAL_OPERATION_ Normal operation. 0 CLOCKS_WITH_WAKE_UP_ Clocks with wake-up mode enabled (W = 1) are disabled. 1 RESERVED Reserved. [31:1] BASE_STAT CCU base clocks status register 0x004 read-only 0x00000FFF 0xFFFFFFFF RESERVED Reserved. [0:0] BASE_UART3_CLK Base clock indicator for BASE_UART3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. [1:1] BASE_UART2_CLK Base clock indicator for BASE_UART2_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. [2:2] BASE_UART1_CLK Base clock indicator for BASE_UART1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. [3:3] BASE_UART0_CLK Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. [4:4] BASE_SSP1_CLK Base clock indicator for BASE_SSP1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. [5:5] BASE_SSP0_CLK Base clock indicator for BASE_SSP0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running. [6:6] RESERVED Reserved. [7:7] RESERVED Reserved. [31:8] CLK_AUDIO_CFG CLK_AUDIO clock configuration register 0x100 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved. [31:3] CLK_APB2_USART3_CFG CLK_APB2_USART3 clock configuration register 0x200 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved. [31:3] CLK_APB2_USART2_CFG CLK_APB2_USART2 clock configuration register 0x300 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved. [31:3] CLK_APB0_UART1_BUS_CFG CLK_APB2_UART1 clock configuration register 0x400 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved. [31:3] CLK_APB0_USART0_CFG CLK_APB2_USART0 clock configuration register 0x500 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved. [31:3] CLK_APB0_SSP0_CFG CLK_APB0_SSP0 clock configuration register 0x700 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved. [31:3] CLK_APB2_SSP1_CFG CLK_APB2_SSP1 clock configuration register 0x600 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved. [31:3] CLK_SDIO_CFG CLK_SDIO clock configuration register 0x800 read-write 0x00000001 0xFFFFFFFF RUN Run enable [0:0] ENUM DISABLED Clock is disabled. 0 ENABLED Clock is enabled. 1 AUTO Auto (AHB disable mechanism) enable [1:1] ENUM DISABLED_ Auto is disabled. 0 ENABLED Auto is enabled. 1 WAKEUP Wake-up mechanism enable [2:2] ENUM DISABLED Wake-up is disabled. 0 ENABLED Wake-up is enabled. 1 RESERVED Reserved. [31:3] CLK_AUDIO_STAT CLK_AUDIO clock status register 0x104 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB2_USART3_STAT CLK_APB2_USART3 clock status register 0x204 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB2_USART2_STAT CLK_APB2_USART clock status register 0x0304 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB0_UART1_STAT CLK_APB0_UART1 clock status register 0x0404 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB0_USART0_STAT CLK_APB0_USART0 clock status register 0x0504 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB2_SSP1_STAT CLK_APB2_SSP1 clock status register 0x0604 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_APB0_SSP0_STAT CLK_APB0_SSP0 clock status register 0x0704 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] CLK_SDIO_STAT CLK_SDIO clock status register 0x0804 read-only 0x00000001 0xFFFFFFFF RUN Run enable status 0 = clock is disabled. 1 = clock is enabled. [0:0] AUTO Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled. [1:1] WAKEUP Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled. [2:2] RESERVED Reserved [31:3] RGU Reset Generation Unit (RGU) RGU 0x40053000 0x0 0xFFF registers RESET_CTRL0 Reset control register 0 0x100 write-only 0 0x00000000 CORE_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [0:0] PERIPH_RST Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles. [1:1] MASTER_RST Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles. [2:2] RESERVED Reserved [3:3] WWDT_RST Writing a one to this bit has no effect. [4:4] CREG_RST Writing a one to this bit has no effect. [5:5] RESERVED Reserved [6:6] RESERVED Reserved [7:7] BUS_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation [8:8] SCU_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [9:9] RESERVED Reserved [10:10] RESERVED Reserved [11:11] M0_SUB_RST Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software. [12:12] M4_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [13:13] RESERVED Reserved [14:14] RESERVED Reserved [15:15] LCD_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [16:16] USB0_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [17:17] USB1_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [18:18] DMA_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [19:19] SDIO_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [20:20] EMC_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [21:21] ETHERNET_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [22:22] RESERVED Reserved [23:23] RESERVED Reserved [24:24] FLASHA_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [25:25] RESERVED Reserved [26:26] EEPROM_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [27:27] GPIO_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [28:28] FLASHB_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [29:29] RESERVED Reserved [30:30] RESERVED Reserved [31:31] RESET_CTRL1 Reset control register 1 0x104 write-only 0 0x00000000 TIMER0_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [0:0] TIMER1_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [1:1] TIMER2_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [2:2] TIMER3_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [3:3] RITIMER_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [4:4] SCT_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [5:5] MOTOCONPWM_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [6:6] QEI_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [7:7] ADC0_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [8:8] ADC1_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [9:9] DAC_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [10:10] RESERVED Reserved [11:11] UART0_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [12:12] UART1_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [13:13] UART2_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [14:14] UART3_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [15:15] I2C0_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [16:16] I2C1_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [17:17] SSP0_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [18:18] SSP1_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [19:19] I2S_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [20:20] SPIFI_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [21:21] CAN1_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [22:22] CAN0_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [23:23] M0APP_RST Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software. [24:24] SGPIO_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [25:25] SPI_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [26:26] RESERVED Reserved [27:27] ADCHS_RST Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. [28:28] RESERVED Reserved [29:29] RESERVED Reserved [30:30] RESERVED Reserved [31:31] RESET_STATUS0 Reset status register 0 0x110 read-write 0x55550050 0xFFFFFFFF RESERVED Reserved [1:0] PERIPH_RST Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [3:2] MASTER_RST Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [5:4] RESERVED Reserved [7:6] WWDT_RST Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved [9:8] CREG_RST Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved [11:10] RESERVED Reserved [13:12] RESERVED Reserved [15:14] BUS_RST Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [17:16] SCU_RST Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [19:18] RESERVED Reserved [21:20] RESERVED Reserved [23:22] M0SUB_RST Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [25:24] M4_RST Status of the M4_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [27:26] RESERVED Reserved [29:28] RESERVED Reserved [31:30] RESET_STATUS1 Reset status register 1 0x114 read-write 0x55555555 0xFFFFFFFF LCD_RST Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [1:0] USB0_RST Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [3:2] USB1_RST Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [5:4] DMA_RST Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [7:6] SDIO_RST Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [9:8] EMC_RST Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [11:10] ETHERNET_RST Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [13:12] RESERVED Reserved [15:14] RESERVED Reserved [17:16] FLASHA_RST Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [19:18] RESERVED Reserved [21:20] EEPROM_RST Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [23:22] GPIO_RST Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [25:24] FLASHB_RST Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [27:26] RESERVED Reserved [29:28] RESERVED Reserved [31:30] RESET_STATUS2 Reset status register 2 0x118 read-write 0x55555555 0xFFFFFFFF TIMER0_RST Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [1:0] TIMER1_RST Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [3:2] TIMER2_RST Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [5:4] TIMER3_RST Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [7:6] RITIMER_RST Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [9:8] SCT_RST Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [11:10] MOTOCONPWM_RST Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [13:12] QEI_RST Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [15:14] ADC0_RST Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [17:16] ADC1_RST Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [19:18] DAC_RST Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [21:20] RESERVED Reserved [23:22] UART0_RST Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [25:24] UART1_RST Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [27:26] UART2_RST Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [29:28] UART3_RST Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [31:30] RESET_STATUS3 Reset status register 3 0x11C read-write 0x55555555 0xFFFFFFFF I2C0_RST Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [1:0] I2C1_RST Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [3:2] SSP0_RST Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [5:4] SSP1_RST Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [7:6] I2S_RST Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [9:8] SPIFI_RST Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [11:10] CAN1_RST Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [13:12] CAN0_RST Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [15:14] M0APP_RST Status of the M0APP_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [17:16] SGPIO_RST Status of the SGPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [19:18] SPI_RST Status of the SPI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [21:20] RESERVED Reserved [23:22] ADCHS_RST Status of the ADCHS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register [25:24] RESERVED Reserved [27:26] RESERVED Reserved [29:28] RESERVED Reserved [31:30] RESET_ACTIVE_STATUS0 Reset active status register 0 0x150 read-only 0xFFFFEFFF 0xFFFFFFFF CORE_RST Current status of the CORE_RST 0 = Reset asserted 1 = No reset [0:0] PERIPH_RST Current status of the PERIPH_RST 0 = Reset asserted 1 = No reset [1:1] MASTER_RST Current status of the MASTER_RST 0 = Reset asserted 1 = No reset [2:2] RESERVED Reserved [3:3] WWDT_RST Current status of the WWDT_RS 0 = Reset asserted 1 = No reset [4:4] CREG_RST Current status of the CREG_RST 0 = Reset asserted 1 = No reset [5:5] RESERVED Reserved [6:6] RESERVED Reserved [7:7] BUS_RST Current status of the BUS_RST 0 = Reset asserted 1 = No reset [8:8] SCU_RST Current status of the SCU_RST 0 = Reset asserted 1 = No reset [9:9] RESERVED Reserved [10:10] RESERVED Reserved [11:11] M0SUB_RST Current status of the M0SUB_RST 0 = Reset asserted 1 = No reset [12:12] M4_RST Current status of the M4_RST 0 = Reset asserted 1 = No reset [13:13] RESERVED Reserved [14:14] RESERVED Reserved [15:15] LCD_RST Current status of the LCD_RST 0 = Reset asserted 1 = No reset [16:16] USB0_RST Current status of the USB0_RST 0 = Reset asserted 1 = No reset [17:17] USB1_RST Current status of the USB1_RST 0 = Reset asserted 1 = No reset [18:18] DMA_RST Current status of the DMA_RST 0 = Reset asserted 1 = No reset [19:19] SDIO_RST Current status of the SDIO_RST 0 = Reset asserted 1 = No reset [20:20] EMC_RST Current status of the EMC_RST 0 = Reset asserted 1 = No reset [21:21] ETHERNET_RST Current status of the ETHERNET_RST 0 = Reset asserted 1 = No reset [22:22] RESERVED Reserved [23:23] RESERVED Reserved [24:24] FLASHA_RST Current status of the FLASHA_RST 0 = Reset asserted 1 = No reset [25:25] RESERVED Reserved [26:26] EEPROM_RST Current status of the EEPROM_RST 0 = Reset asserted 1 = No reset [27:27] GPIO_RST Current status of the GPIO_RST 0 = Reset asserted 1 = No reset [28:28] FLASHB_RST Current status of the FLASHB_RST 0 = Reset asserted 1 = No reset [29:29] RESERVED Reserved [30:30] RESERVED Reserved [31:31] RESET_ACTIVE_STATUS1 Reset active status register 1 0x154 read-only 0xFEFFFFFF 0xFFFFFFFF TIMER0_RST Current status of the TIMER0_RST 0 = Reset asserted 1 = No reset [0:0] TIMER1_RST Current status of the TIMER1_RST 0 = Reset asserted 1 = No reset [1:1] TIMER2_RST Current status of the TIMER2_RST 0 = Reset asserted 1 = No reset [2:2] TIMER3_RST Current status of the TIMER3_RST 0 = Reset asserted 1 = No reset [3:3] RITIMER_RST Current status of the RITIMER_RST 0 = Reset asserted 1 = No reset [4:4] SCT_RST Current status of the SCT_RST 0 = Reset asserted 1 = No reset [5:5] MOTOCONPWM_RST Current status of the MOTOCONPWM_RST 0 = Reset asserted 1 = No reset [6:6] QEI_RST Current status of the QEI_RST 0 = Reset asserted 1 = No reset [7:7] ADC0_RST Current status of the ADC0_RST 0 = Reset asserted 1 = No reset [8:8] ADC1_RST Current status of the ADC1_RST 0 = Reset asserted 1 = No reset [9:9] DAC_RST Current status of the DAC_RST 0 = Reset asserted 1 = No reset [10:10] RESERVED Reserved. [11:11] UART0_RST Current status of the UART0_RST 0 = Reset asserted 1 = No reset [12:12] UART1_RST Current status of the UART1_RST 0 = Reset asserted 1 = No reset [13:13] UART2_RST Current status of the UART2_RST 0 = Reset asserted 1 = No reset [14:14] UART3_RST Current status of the UART3_RST 0 = Reset asserted 1 = No reset [15:15] I2C0_RST Current status of the I2C0_RST 0 = Reset asserted 1 = No reset [16:16] I2C1_RST Current status of the I2C1_RST 0 = Reset asserted 1 = No reset [17:17] SSP0_RST Current status of the SSP0_RST 0 = Reset asserted 1 = No reset [18:18] SSP1_RST Current status of the SSP1_RST 0 = Reset asserted 1 = No reset [19:19] I2S_RST Current status of the I2S_RST 0 = Reset asserted 1 = No reset [20:20] SPIFI_RST Current status of the SPIFI_RST 0 = Reset asserted 1 = No reset [21:21] CAN1_RST Current status of the CAN1_RST 0 = Reset asserted 1 = No reset [22:22] CAN0_RST Current status of the CAN0_RST 0 = Reset asserted 1 = No reset [23:23] M0APP_RST Current status of the M0APP_RST 0 = Reset asserted 1 = No reset [24:24] SGPIO_RST Current status of the SGPIO_RST 0 = Reset asserted 1 = No reset [25:25] SPI_RST Current status of the SPI_RST 0 = Reset asserted 1 = No reset [26:26] RESERVED Reserved. [27:27] ADCHS_RST Current status of the ADCHS_RST 0 = Reset asserted 1 = No reset [28:28] RESERVED Reserved. [29:29] RESERVED Reserved. [30:30] RESERVED Reserved. [31:31] RESET_EXT_STAT1 Reset external status register 1 for PERIPH_RST 0x404 read-write 0x0 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [0:0] CORE_RESET Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [1:1] RESERVED Reserved. Do not modify; read as logic 0. [31:2] RESET_EXT_STAT2 Reset external status register 2 for MASTER_RST 0x408 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT5 Reset external status register 5 for CREG_RST 0x414 read-write 0x0 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [0:0] CORE_RESET Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [1:1] RESERVED Reserved. Do not modify; read as logic 0. [31:2] RESET_EXT_STAT8 Reset external status register 0x420 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT9 Reset external status register 0x0424 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT12 Reset external status register 0x430 read-write 0x8 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [2:0] MASTER_RESET Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [3:3] RESERVED Reserved. Do not modify; read as logic 0. [31:4] RESET_EXT_STAT13 Reset external status register 0x434 read-write 0x8 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [2:0] MASTER_RESET Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [3:3] RESERVED Reserved. Do not modify; read as logic 0. [31:4] RESET_EXT_STAT16 Reset external status register 0x440 read-write 0x8 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [2:0] MASTER_RESET Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [3:3] RESERVED Reserved. Do not modify; read as logic 0. [31:4] RESET_EXT_STAT17 Reset external status register 0x0444 read-write 0x8 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [2:0] MASTER_RESET Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [3:3] RESERVED Reserved. Do not modify; read as logic 0. [31:4] RESET_EXT_STAT18 Reset external status register 0x0448 read-write 0x8 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [2:0] MASTER_RESET Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [3:3] RESERVED Reserved. Do not modify; read as logic 0. [31:4] RESET_EXT_STAT19 Reset external status register 0x044C read-write 0x8 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [2:0] MASTER_RESET Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [3:3] RESERVED Reserved. Do not modify; read as logic 0. [31:4] RESET_EXT_STAT20 Reset external status register 0x0450 read-write 0x8 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [2:0] MASTER_RESET Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [3:3] RESERVED Reserved. Do not modify; read as logic 0. [31:4] RESET_EXT_STAT21 Reset external status register 0x0454 read-write 0x8 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [2:0] MASTER_RESET Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [3:3] RESERVED Reserved. Do not modify; read as logic 0. [31:4] RESET_EXT_STAT22 Reset external status register 0x0458 read-write 0x8 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [2:0] MASTER_RESET Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [3:3] RESERVED Reserved. Do not modify; read as logic 0. [31:4] RESET_EXT_STAT25 Reset external status register 0x0464 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [2:0] MASTER_RESET Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [3:3] RESERVED Reserved. Do not modify; read as logic 0. [31:4] RESET_EXT_STAT27 Reset external status register 0x046C read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [2:0] MASTER_RESET Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [3:3] RESERVED Reserved. Do not modify; read as logic 0. [31:4] RESET_EXT_STAT28 Reset external status register 0x470 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT29 Reset external status register 0x0474 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [2:0] MASTER_RESET Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [3:3] RESERVED Reserved. Do not modify; read as logic 0. [31:4] RESET_EXT_STAT32 Reset external status register 0x480 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT33 Reset external status register 0x0484 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT34 Reset external status register 0x0488 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT35 Reset external status register 0x048C read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT36 Reset external status register 0x0490 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT37 Reset external status register 0x0494 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT38 Reset external status register 0x0498 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT39 Reset external status register 0x049C read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT40 Reset external status register 0x04A0 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT41 Reset external status register 0x04A4 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT42 Reset external status register 0x04A8 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT44 Reset external status register 0x04B0 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT45 Reset external status register 0x04B4 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT46 Reset external status register 0x04B8 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT47 Reset external status register 0x04BC read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT48 Reset external status register 0x04C0 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT49 Reset external status register 0x04C4 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT50 Reset external status register 0x04C8 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT51 Reset external status register 0x04CC read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT52 Reset external status register 0x04D0 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT53 Reset external status register 0x04D4 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT54 Reset external status register 0x04D8 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT55 Reset external status register 0x04DC read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT56 Reset external status register 0x04E0 read-write 0x8 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT57 Reset external status register 0x04E4 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT58 Reset external status register 0x04E8 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] RESET_EXT_STAT60 Reset external status register 0x04F0 read-write 0x4 0xFFFFFFFF RESERVED Reserved. Do not modify; read as logic 0. [1:0] PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated [2:2] RESERVED Reserved. Do not modify; read as logic 0. [31:3] WWDT Windowed Watchdog timer (WWDT) WWDT 0x40080000 0 0x300 registers WWDT 49 MOD Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. 0x000 read-write 0 0xFFFFFFFF WDEN Watchdog enable bit. This bit is Set Only. [0:0] ENUM WWDTSTOPPED The watchdog timer is stopped. 0 WWDTRUN The watchdog timer is running. 1 WDRESET Watchdog reset enable bit. This bit is Set Only. [1:1] ENUM WWDTINT A watchdog time-out will not cause a chip reset. 0 WWDTRESET A watchdog time-out will cause a chip reset. 1 WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit. [2:2] WDINT Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit. [3:3] WDPROTECT Watchdog update mode. This bit is Set Only. [4:4] ENUM NO_LOCK The watchdog time-out value (WDTC) can be changed at any time. 0 LOCK The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:5] TC Watchdog timer constant register. This register determines the time-out value. 0x004 read-write 0xFF 0xFFFFFFFF WDTC Watchdog time-out value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] FEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. 0x008 write-only 0 0x00000000 Feed Feed value should be 0xAA followed by 0x55. [7:0] TV Watchdog timer value register. This register reads out the current value of the Watchdog timer. 0x00C read-only 0xFF 0xFFFFFFFF Count Counter timer value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] WARNINT Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. 0x014 read-write 0 0xFFFFFFFF WDWARNINT Watchdog warning interrupt compare value. [9:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] WINDOW Watchdog timer window register. This register contains the Watchdog window value. 0x018 read-write 0x00FFFFFF 0xFFFFFFFF WDWINDOW Watchdog window value. [23:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:24] USART0 USART0_2_3 USART 0x40081000 0 0x300 registers USART0 24 RBR Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). 0x000 read-only 0 0x00000000 modify RBR Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO. [7:0] RESERVED Reserved [31:8] THR Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). RBR 0x000 write-only 0 0x00000000 modify THR Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. [7:0] RESERVED Reserved [31:8] DLL Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). RBR 0x000 read-write 0x01 0xFFFFFFFF DLLSB Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART. [7:0] RESERVED Reserved [31:8] DLM Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). 0x004 read-write 0x00 0xFFFFFFFF DLMSB Divisor latch MSB. The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART. [7:0] RESERVED Reserved [31:8] IER Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0). DLM 0x004 read-write 0x00 0xFFFFFFFF RBRIE RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt. [0:0] ENUM DISABLE Disable. Disable the RDA interrupt. 0 ENABLE Enable. Enable the RDA interrupt. 1 THREIE THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5]. [1:1] ENUM DISABLE Disable. Disable the THRE interrupt. 0 ENABLE Enable. Enable the THRE interrupt. 1 RXIE RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. [2:2] ENUM DISABLE Disable. Disable the RX line status interrupts. 0 ENABLE Enable. Enable the RX line status interrupts. 1 RESERVED Reserved [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [6:4] RESERVED Reserved [7:7] ABEOINTEN Enables the end of auto-baud interrupt. [8:8] ENUM DISABLE Disable. Disable end of auto-baud Interrupt. 0 ENABLE Enable. Enable end of auto-baud Interrupt. 1 ABTOINTEN Enables the auto-baud time-out interrupt. [9:9] ENUM DISABLE Disable. Disable auto-baud time-out Interrupt. 0 ENABLE Enable. Enable auto-baud time-out Interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] IIR Interrupt ID Register. Identifies which interrupt(s) are pending. 0x008 read-only 0x01 0xFFFFFFFF INTSTATUS Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. [0:0] ENUM INTERRUPT_PENDING Interrupt pending. At least one interrupt is pending. 0 NOT_PENDING Not pending. No interrupt is pending. 1 INTID Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111). [3:1] ENUM RLS RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS). 0x3 RDA RDA. Priority 2 - Receive Data Available (RDA). 0x2 CTI CTI. Priority 2 - Character Time-out Indicator (CTI). 0x6 THRE THRE. Priority 3 - THRE Interrupt. 0x1 RESERVED Reserved. Priority 4 (lowest) - Reserved. 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] FIFOENABLE Copies of FCR[0]. [7:6] ABEOINT End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. [8:8] ABTOINT Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. [9:9] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] FCR FIFO Control Register. Controls USART FIFO usage and modes. 0x008 write-only 0x00 0xFFFFFFFF FIFOEN FIFO Enable. [0:0] ENUM DISABLED Disabled. USART FIFOs are disabled. Must not be used in the application. 0 ENABLED Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs. 1 RXFIFORES RX FIFO Reset. [1:1] ENUM NO_EFFECT No effect. No impact on either of USART FIFOs. 0 CLEAR Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing. 1 TXFIFORES TX FIFO Reset. [2:2] ENUM NO_EFFECT No effect. No impact on either of USART FIFOs. 0 CLEAR Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing. 1 DMAMODE DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] RXTRIGLVL RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated. [7:6] ENUM LEVEL_0 Level 0. Trigger level 0 (1 character or 0x01). 0x0 LEVEL_1 Level 1. Trigger level 1 (4 characters or 0x04). 0x1 LEVEL_2 Level 2. Trigger level 2 (8 characters or 0x08). 0x2 LEVEL_3 Level 3. Trigger level 3 (14 characters or 0x0E). 0x3 RESERVED Reserved [31:8] LCR Line Control Register. Contains controls for frame formatting and break generation. 0x00C read-write 0x00 0xFFFFFFFF WLS Word Length Select. [1:0] ENUM 5_BIT_CHARACTER_LENG 5-bit character length. 0x0 6_BIT_CHARACTER_LENG 6-bit character length. 0x1 7_BIT_CHARACTER_LENG 7-bit character length. 0x2 8_BIT_CHARACTER_LENG 8-bit character length. 0x3 SBS Stop Bit Select. [2:2] ENUM 1_STOP_BIT 1 stop bit. 0 2_STOP_BITS_1 2 stop bits (1.5 if LCR[1:0]=00). 1 PE Parity Enable [3:3] ENUM DISABLE_PARITY_GENER Disable parity generation and checking. 0 ENABLE_PARITY_GENERA Enable parity generation and checking. 1 PS Parity Select. [5:4] ENUM ODD_PARITY Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x0 EVEN_PARITY Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x1 FORCE_HIGH Force HIGH. Forced 1 stick parity. 0x2 FORCE_LOW Force LOW. Forced 0 stick parity. 0x3 BC Break Control. [6:6] ENUM DISABLED Disabled. Disable break transmission. 0 ENABLED Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high. 1 DLAB Divisor Latch Access Bit. [7:7] ENUM DISABLED Disabled. Disable access to Divisor Latches. 0 ENABLED Enabled. Enable access to Divisor Latches. 1 RESERVED Reserved [31:8] LSR Line Status Register. Contains flags for transmit and receive status, including line errors. 0x014 read-only 0x60 0xFFFFFFFF modify RDR Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty. [0:0] ENUM EMPTY Empty. RBR is empty. 0 DATA Data. RBR contains valid data. 1 OE Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost. [1:1] ENUM INACTIVE Inactive. Overrun error status is inactive. 0 ACTIVE Active. Overrun error status is active. 1 PE Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO. [2:2] ENUM INACTIVE Inactive. Parity error status is inactive. 0 ACTIVE Active. Parity error status is active. 1 FE Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO. [3:3] ENUM INACTIVE Inactive. Framing error status is inactive. 0 ACTIVE Active. Framing error status is active. 1 BI Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO. [4:4] ENUM INACTIVE Inactive. Break interrupt status is inactive. 0 ACTIVE Active. Break interrupt status is active. 1 THRE Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write. [5:5] ENUM NOT_EMPTY Not empty. THR contains valid data. 0 EMPTY Empty. THR is empty. 1 TEMT Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. [6:6] ENUM NOT_EMPTY Not empty. THR and/or the TSR contains valid data. 0 EMPTY Empty. THR and the TSR are empty. 1 RXFE Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO. [7:7] ENUM NO_ERROR No error. RBR contains no USART RX errors or FCR[0]=0. 0 ERROR Error. USART RBR contains at least one USART RX error. 1 TXERR Error in transmitted character. A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read. [8:8] ENUM NO_ERROR No error. No error (normal default condition). 0 NACK NACK. A NACK response is received during Smart card T=0 operation. 1 RESERVED Reserved [31:9] SCR Scratch Pad Register. Eight-bit temporary storage for software. 0x01C read-write 0x00 0xFFFFFFFF PAD Scratch pad. A readable, writable byte. [7:0] RESERVED Reserved [31:8] ACR Auto-baud Control Register. Contains controls for the auto-baud feature. 0x020 read-write 0x00 0xFFFFFFFF START Start bit. This bit is automatically cleared after auto-baud completion. [0:0] ENUM STOP Stop. Auto-baud stop (auto-baud is not running). 0 START Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 MODE Auto-baud mode select bit. [1:1] ENUM MODE_0 Mode 0. 0 MODE_1 Mode 1. 1 AUTORESTART Restart bit. [2:2] ENUM NO_RESTART No restart. 0 RESTART Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge) 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:3] ABEOINTCLR End of auto-baud interrupt clear bit (write-only). [8:8] ENUM NO_EFFECT No effect. Writing a 0 has no impact. 0 CLEAR Clear. Writing a 1 will clear the corresponding interrupt in the IIR. 1 ABTOINTCLR Auto-baud time-out interrupt clear bit (write-only). [9:9] ENUM NO_EFFECT No effect. Writing a 0 has no impact. 0 CLEAR Clear. Writing a 1 will clear the corresponding interrupt in the IIR. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] ICR IrDA control register (USART3 only) 0x024 read-write 0x00 0xFFFFFFFF IRDAEN IrDA mode enable. [0:0] ENUM DISABLED Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART. 0 ENABLED Enabled. IrDA mode on USART3 is enabled. 1 IRDAINV Serial input direction. [1:1] ENUM NOT_INVERTED Not inverted. The serial input is not inverted. 0 INVERTED Inverted. The serial input is inverted. This has no effect on the serial output. 1 FIXPULSEEN IrDA fixed pulse width mode. [2:2] ENUM DISABLED Disabled. IrDA fixed pulse width mode disabled. 0 ENABLED Enabled. IrDA fixed pulse width mode enabled. 1 PULSEDIV Configures the pulse when FixPulseEn = 1. See Table 885 for details. [5:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] FDR Fractional Divider Register. Generates a clock input for the baud rate divider. 0x028 read-write 0x10 0xFFFFFFFF DIVADDVAL Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate. [3:0] MULVAL Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not. [7:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] OSR Oversampling Register. Controls the degree of oversampling during each bit time. 0x02C read-write 0xF0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [0:0] OSFRAC Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875) [3:1] OSINT Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time. [7:4] FDINT In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372. [14:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:15] HDEN Half-duplex enable Register 0x040 read-write 0 0x00000000 HDEN Half-duplex mode enable [0:0] ENUM DISABLED Disabled. Disable half-duplex mode. 0 ENABLED Enabled. Enable half-duplex mode. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:1] SCICTRL Smart card interface control register 0x048 read-write 0x00 0xFFFFFFFF SCIEN Smart Card Interface Enable. [0:0] ENUM DISABLED Disabled. Smart card interface disabled. 0 ENABLED Enabled. synchronous half duplex smart card interface is enabled. 1 NACKDIS NACK response disable. Only applicable in T=0. [1:1] ENUM ENABLED Enabled. A NACK response is enabled. 0 DISABLED Disabled. A NACK response is inhibited. 1 PROTSEL Protocol selection as defined in the ISO7816-3 standard. [2:2] ENUM T_EQ_0 T = 0 0 T_EQ_1 T = 1 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [4:3] TXRETRY Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled. [7:5] GUARDTIME Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol. [15:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] RS485CTRL RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. 0x04C read-write 0x00 0xFFFFFFFF NMMEN NMM enable. [0:0] ENUM DISABLED Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0 ENABLED Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt. 1 RXDIS Receiver enable. [1:1] ENUM ENABLED Enabled. The receiver is enabled. 0 DISABLED Disabled.The receiver is disabled. 1 AADEN AAD enable [2:2] ENUM DISABLED Disabled. Auto Address Detect (AAD) is disabled. 0 ENABLED Enabled. Auto Address Detect (AAD) is enabled. 1 RESERVED Reserved. [3:3] DCTRL Direction control for DIR pin. [4:4] ENUM DISABLED Disabled. Disable Auto Direction Control. 0 ENABLED Enabled. Enable Auto Direction Control. 1 OINV Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin. [5:5] ENUM LOW Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. 0 HIGH High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] RS485ADRMATCH RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. 0x050 read-write 0x00 0xFFFFFFFF ADRMATCH Contains the address match value. [7:0] RESERVED Reserved [31:8] RS485DLY RS-485/EIA-485 direction control delay. 0x054 read-write 0x00 0xFFFFFFFF DLY Contains the direction control delay value. This register works in conjunction with an 8-bit counter. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] SYNCCTRL Synchronous mode control register. 0x058 read-write 0x00 0xFFFFFFFF SYNC Enables synchronous mode. [0:0] ENUM DISABLED Disabled. 0 ENABLED Enabled. 1 CSRC Clock source select. [1:1] ENUM SLAVE_MODE Slave mode. Synchronous slave mode (SCLK in) 0 MASTER_MODE Master mode. Synchronous master mode (SCLK out) 1 FES Edge sampling. [2:2] ENUM RISING Rising. RxD is sampled on the rising edge of SCLK. 0 FALLING Falling. RxD is sampled on the falling edge of SCLK. 1 TSBYPASS Transmit synchronization bypass in synchronous slave mode. [3:3] ENUM SYNCHRONIZED Synchronized. The input clock is synchronized prior to being used in clock edge detection logic. 0 NOT_SYNCHRONIZED Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability. 1 CSCEN Continuous master clock enable (used only when CSRC is 1) [4:4] ENUM ON_CHARACTER On character. SCLK cycles only when characters are being sent on TxD. 0 CONTINUOUSLY Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD). 1 SSSDIS Start/stop bits [5:5] ENUM SEND Send. Send start and stop bits as in other modes. 0 DO_NOT_SEND Do not send. Do not send start/stop bits. 1 CCCLR Continuous clock clear [6:6] ENUM SOFTWARE Software. CSCEN is under software control. 0 HARDWARE Hardware. Hardware clears CSCEN after each character is received. 1 RESERVED Reserved. The value read from a reserved bit is not defined. [31:7] TER Transmit Enable Register. Turns off USART transmitter for use with software flow control. 0x05C read-write 0x01 0xFFFFFFFF TXEN Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR. [0:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:1] USART2 0x400C1000 USART2 26 USART3 0x400C2000 USART3 27 UART1 UART1 UART1 0x40082000 0 0x300 registers UART1 25 RBR Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) 0x000 read-only 0 0x00000000 modify RBR Receiver Buffer. Contains the oldest received byte in the UART1 RX FIFO. [7:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] THR Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) RBR 0x000 write-only 0 0x00000000 THR Transmit Holding Register. Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. [31:8] DLL Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) RBR 0x000 read-write 0x01 0xFFFFFFFF DLLSB Divisor Latch LSB. The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] DLM Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) 0x004 read-write 0x00 0xFFFFFFFF DLMSB Divisor Latch MSB. The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] IER Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) DLM 0x004 read-write 0x00 0xFFFFFFFF RBRIE RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt. [0:0] ENUM DISABLE Disable. Disable the RDA interrupts. 0 ENABLE Enable. Enable the RDA interrupts. 1 THREIE THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5]. [1:1] ENUM DISABLE Disable. Disable the THRE interrupts. 0 ENABLE Enable. Enable the THRE interrupts. 1 RXIE RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. [2:2] ENUM DISABLE Disable. Disable the RX line status interrupts. 0 ENABLE Enable. Enable the RX line status interrupts. 1 MSIE Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0]. [3:3] ENUM DISABLE Disable. Disable the modem interrupt. 0 ENABLE Enable. Enable the modem interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [6:4] CTSIE CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set. [7:7] ENUM DISABLE Disable. Disable the CTS interrupt. 0 ENABLE Enable. Enable the CTS interrupt. 1 ABEOIE Enables the end of auto-baud interrupt. [8:8] ENUM DISABLE Disable. Disable end of auto-baud Interrupt. 0 ENABLE Enable. Enable end of auto-baud Interrupt. 1 ABTOIE Enables the auto-baud time-out interrupt. [9:9] ENUM DISABLE Disable. Disable auto-baud time-out Interrupt. 0 ENABLE Enable. Enable auto-baud time-out Interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] IIR Interrupt ID Register. Identifies which interrupt(s) are pending. 0x008 read-only 0x01 0xFFFFFFFF INTSTATUS Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. [0:0] ENUM INTERRUPT_PENDING Interrupt pending. At least one interrupt is pending. 0 NOT_PENDING Not pending. No interrupt is pending. 1 INTID Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111). [3:1] ENUM RLS RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS). 0x3 RDA RDA. Priority 2 - Receive Data Available (RDA). 0x2 CTI CTI. Priority 2 - Character Time-out Indicator (CTI). 0x6 THRE THRE. Priority 3 - THRE Interrupt. 0x1 RESERVED Reserved. Priority 4 (lowest) - Reserved. 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] FIFOENABLE Copies of FCR[0]. [7:6] ABEOINT End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. [8:8] ABTOINT Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. [9:9] RESERVED Reserved, the value read from a reserved bit is not defined. [31:10] FCR FIFO Control Register. Controls UART1 FIFO usage and modes. 0x008 write-only 0x00 0xFFFFFFFF FIFOEN FIFO enable. [0:0] ENUM DISABLED Disabled. Must not be used in the application. 0 ENABLED Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs. 1 RXFIFORES RX FIFO Reset. [1:1] ENUM NO_EFFECT No effect. No impact on either of UART1 FIFOs. 0 CLEAR Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing. 1 TXFIFORES TX FIFO Reset. [2:2] ENUM NO_EFFECT No effect. No impact on either of UART1 FIFOs. 0 CLEAR Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing. 1 DMAMODE DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 39.6.6.1. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:4] RXTRIGLVL RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated. [7:6] ENUM LEVEL_0 Level 0. Trigger level 0 (1 character or 0x01). 0x0 LEVEL_1 Level 1. Trigger level 1 (4 characters or 0x04). 0x1 LEVEL_2 Level 2. Trigger level 2 (8 characters or 0x08). 0x2 LEVEL_3 Level 3. Trigger level 3 (14 characters or 0x0E). 0x3 RESERVED Reserved, user software should not write ones to reserved bits. [31:8] LCR Line Control Register. Contains controls for frame formatting and break generation. 0x00C read-write 0x00 0xFFFFFFFF WLS Word Length Select. [1:0] ENUM 5_BIT_CHARACTER_LENG 5-bit character length. 0x0 6_BIT_CHARACTER_LENG 6-bit character length. 0x1 7_BIT_CHARACTER_LENG 7-bit character length. 0x2 8_BIT_CHARACTER_LENG 8-bit character length. 0x3 SBS Stop Bit Select. [2:2] ENUM 1_STOP_BIT 1 stop bit. 0 2_STOP_BITS 2 stop bits. (1.5 if LCR[1:0]=00). 1 PE Parity Enable. [3:3] ENUM DISABLE_PARITY_GENER Disable parity generation and checking. 0 ENABLE_PARITY_GENERA Enable parity generation and checking. 1 PS Parity Select. [5:4] ENUM ODD_PARITY Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x0 EVEN_PARITY Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x1 FORCE_HIGH Force HIGH. Forced 1 stick parity. 0x2 FORCE_LOW Force LOW. Forced 0 stick parity. 0x3 BC Break Control. [6:6] ENUM DISABLED Disabled. Disable break transmission. 0 ENABLED Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high. 1 DLAB Divisor Latch Access Bit (DLAB) [7:7] ENUM DISABLED Disabled. Disable access to Divisor Latches. 0 ENABLED Enabled. Enable access to Divisor Latches. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] MCR Modem Control Register. Contains controls for flow control handshaking and loopback mode. 0x010 read-write 0x00 0xFFFFFFFF DTRCTRL DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active. [0:0] RTSCTRL RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [3:2] LMS Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR. [4:4] ENUM DISABLED Disabled. Disable modem loopback mode. 0 ENABLED Enabled. Enable modem loopback mode. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:5] RTSEN RTS enable. [6:6] ENUM DISABLED Disabled. Disable auto-rts flow control. 0 ENABLED Enabled. Enable auto-rts flow control. 1 CTSEN CTS enable. [7:7] ENUM DISABLED Disabled. Disable auto-cts flow control. 0 ENABLED Enabled. Enable auto-cts flow control. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] LSR Line Status Register. Contains flags for transmit and receive status, including line errors. 0x014 read-only 0x60 0xFFFFFFFF modify RDR Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty. [0:0] ENUM EMPTY Empty. The UART1 receiver FIFO is empty. 0 DATA Data. The UART1 receiver FIFO is not empty. 1 OE Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost. [1:1] ENUM INACTIVE Inactive. Overrun error status is inactive. 0 ACTIVE Active. Overrun error status is active. 1 PE Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO. [2:2] ENUM INACTIVE Inactive. Parity error status is inactive. 0 ACTIVE Active. Parity error status is active. 1 FE Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO. [3:3] ENUM INACTIVE Inactive. Framing error status is inactive. 0 ACTIVE Active. Framing error status is active. 1 BI Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO. [4:4] ENUM BREAK_INTERRUPT_STAT Break interrupt status is inactive. 0 BREAK_INTERRUPT_STAT Break interrupt status is active. 1 THRE Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write. [5:5] ENUM NOT_EMPTY Not empty. THR contains valid data. 0 EMPTY Empty. THR is empty. 1 TEMT Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data. [6:6] ENUM NOT_EMPTY Not empty. THR and/or the TSR contains valid data. 0 EMPTY Empty. THR and the TSR are empty. 1 RXFE Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO. [7:7] ENUM NO_ERROR No error. RBR contains no UART1 RX errors or FCR[0]=0. 0 ERROR Error. UART1 RBR contains at least one UART1 RX error. 1 RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] MSR Modem Status Register. Contains handshake signal status flags. 0x018 read-only 0x00 0xFFFFFFFF modify DCTS Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. [0:0] ENUM NO_CHANGE No change. No change detected on modem input, CTS. 0 STATE_CHANGE State change. State change detected on modem input, CTS. 1 DDSR Delta DSR. Set upon state change of input DSR. Cleared on an MSR read. [1:1] ENUM NO_CHANGE No change. No change detected on modem input, DSR. 0 STATE_CHANGE State change. State change detected on modem input, DSR. 1 TERI Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read. [2:2] ENUM NO_CHANGE No change. No change detected on modem input, RI. 0 RISING Rising. Low-to-high transition detected on RI. 1 DDCD Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. [3:3] ENUM NO_CHANGE No change. No change detected on modem input, DCD. 0 STATE_CHANGE State change. State change detected on modem input, DCD. 1 CTS Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode. [4:4] DSR Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode. [5:5] RI Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode. [6:6] DCD Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode. [7:7] RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] SCR Scratch Pad Register. 8-bit temporary storage for software. 0x01C read-write 0x00 0xFFFFFFFF Pad Scratch pad. A readable, writable byte. [7:0] RESERVED Reserved, the value read from a reserved bit is not defined. [31:8] ACR Auto-baud Control Register. Contains controls for the auto-baud feature. 0x020 read-write 0x00 0xFFFFFFFF START Auto-baud start bit. This bit is automatically cleared after auto-baud completion. [0:0] ENUM STOP Stop. Auto-baud stop (auto-baud is not running). 0 START Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 MODE Auto-baud mode select bit. [1:1] ENUM MODE_0 Mode 0. 0 MODE_1 Mode 1. 1 AUTORESTART Auto-baud restart bit. [2:2] ENUM NO_RESTART No restart 0 RESTART Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge) 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:3] ABEOINTCLR End of auto-baud interrupt clear bit (write-only). [8:8] ENUM NO_EFFECT No effect. Writing a 0 has no impact. 0 CLEAR Clear. Writing a 1 will clear the corresponding interrupt in the IIR. 1 ABTOINTCLR Auto-baud time-out interrupt clear bit (write-only). [9:9] ENUM NO_EFFECT No effect. Writing a 0 has no impact. 0 CLEAR Clear. Writing a 1 will clear the corresponding interrupt in the IIR. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:10] FDR Fractional Divider Register. Generates a clock input for the baud rate divider. 0x028 read-write 0x10 0xFFFFFFFF DIVADDVAL Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate. [3:0] MULVAL Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not. [7:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] RS485CTRL RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. 0x04C read-write 0x00 0xFFFFFFFF NMMEN Multidrop mode select. [0:0] ENUM DISABLED Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0 ENABLED Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt. 1 RXDIS Receive enable. [1:1] ENUM ENABLED Enabled. The receiver is enabled. 0 DISABLED Disabled.The receiver is disabled. 1 AADEN Auto Address Detect enable. [2:2] ENUM DISABLED Disabled. Auto Address Detect (AAD) is disabled. 0 ENABLED Enabled. Auto Address Detect (AAD) is enabled. 1 SEL Direction control. [3:3] ENUM RTS RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. 0 DTR DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. 1 DCTRL Direction control enable. [4:4] ENUM DISABLED Disabled. Disable Auto Direction Control. 0 ENABLED Enabled. Enable Auto Direction Control. 1 OINV Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. [5:5] ENUM LOW Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. 0 HIGH High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] RS485ADRMATCH RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. 0x050 read-write 0x00 0xFFFFFFFF ADRMATCH Contains the address match value. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] RS485DLY RS-485/EIA-485 direction control delay. 0x054 read-write 0x00 0xFFFFFFFF DLY Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] TER Transmit Enable Register. Turns off UART transmitter for use with software flow control. 0x05C read-write 0x80 0xFFFFFFFF TXEN Transmit enable. After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR. [0:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:1] SSP0 SSP0/1 SSP 0x40083000 0 0x300 registers SSP0 22 CR0 Control Register 0. Selects the serial clock rate, bus type, and data size. 0x000 read-write 0 0xFFFFFFFF DSS Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. [3:0] ENUM 4_BIT_TRANSFER 4-bit transfer 0x3 5_BIT_TRANSFER 5-bit transfer 0x4 6_BIT_TRANSFER 6-bit transfer 0x5 7_BIT_TRANSFER 7-bit transfer 0x6 8_BIT_TRANSFER 8-bit transfer 0x7 9_BIT_TRANSFER 9-bit transfer 0x8 10_BIT_TRANSFER 10-bit transfer 0x9 11_BIT_TRANSFER 11-bit transfer 0xA 12_BIT_TRANSFER 12-bit transfer 0xB 13_BIT_TRANSFER 13-bit transfer 0xC 14_BIT_TRANSFER 14-bit transfer 0xD 15_BIT_TRANSFER 15-bit transfer 0xE 16_BIT_TRANSFER 16-bit transfer 0xF FRF Frame Format. [5:4] ENUM SPI SPI 0x0 TI TI 0x1 MICROWIRE Microwire 0x2 THIS_COMBINATION_IS_ This combination is not supported and should not be used. 0x3 CPOL Clock Out Polarity. This bit is only used in SPI mode. [6:6] ENUM BUS_LOW SSP controller maintains the bus clock low between frames. 0 BUS_HIGH SSP controller maintains the bus clock high between frames. 1 CPHA Clock Out Phase. This bit is only used in SPI mode. [7:7] ENUM FIRST_CLOCK SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. 0 SECOND_CLOCK SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. 1 SCR Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]). [15:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] CR1 Control Register 1. Selects master/slave and other modes. 0x004 read-write 0 0xFFFFFFFF LBM Loop Back Mode. [0:0] ENUM NORMAL During normal operation. 0 OUPTU Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). 1 SSE SSP Enable. [1:1] ENUM DISABLED The SSP controller is disabled. 0 ENABLED The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. 1 MS Master/Slave Mode.This bit can only be written when the SSE bit is 0. [2:2] ENUM MASTER The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. 0 SLAVE The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. 1 SOD Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] DR Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. 0x008 read-write 0 0xFFFFFFFF modify DATA Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. [15:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] SR Status Register 0x00C read-only 0x00000003 0xFFFFFFFF TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. [0:0] TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. [1:1] RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. [2:2] RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. [3:3] BSY Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. [4:4] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:5] CPSR Clock Prescale Register 0x010 read-write 0 0xFFFFFFFF CPSDVSR This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] IMSC Interrupt Mask Set and Clear Register 0x014 read-write 0 0xFFFFFFFF RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. [0:0] RTIM Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXIM Software should set this bit to enable interrupt when the Rx FIFO is at least half full. [2:2] TXIM Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] RIS Raw Interrupt Status Register 0x018 read-only 0x00000008 0xFFFFFFFF RORRIS This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. [0:0] RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXRIS This bit is 1 if the Rx FIFO is at least half full. [2:2] TXRIS This bit is 1 if the Tx FIFO is at least half empty. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] MIS Masked Interrupt Status Register 0x01C read-only 0 0xFFFFFFFF RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. [0:0] RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]). [1:1] RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. [2:2] TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] ICR SSPICR Interrupt Clear Register 0x020 write-only 0 0x00000000 RORIC Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. [0:0] RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]). [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] DMACR SSP0 DMA control register 0x024 read-write 0 0xFFFFFFFF RXDMAE Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled. [0:0] TXDMAE Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] SSP1 0x400C5000 SSP1 23 TIMER0 Timer0/1/2/3 TIMER 0x40084000 0 0x300 registers TIMER0 12 IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. 0x000 read-write 0 0xFFFFFFFF MR0INT Interrupt flag for match channel 0. [0:0] MR1INT Interrupt flag for match channel 1. [1:1] MR2INT Interrupt flag for match channel 2. [2:2] MR3INT Interrupt flag for match channel 3. [3:3] CR0INT Interrupt flag for capture channel 0 event. [4:4] CR1INT Interrupt flag for capture channel 1 event. [5:5] CR2INT Interrupt flag for capture channel 2 event. [6:6] CR3INT Interrupt flag for capture channel 3 event. [7:7] RESERVED Reserved. [31:8] TCR Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x004 read-write 0 0xFFFFFFFF CEN When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. [0:0] CRST When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:2] TC Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x008 read-write 0 0xFFFFFFFF TC Timer counter value. [31:0] PR Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. 0x00C read-write 0 0xFFFFFFFF PM Prescale counter maximum value. [31:0] PC Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x010 read-write 0 0xFFFFFFFF PC Prescale counter value. [31:0] MCR Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x014 read-write 0 0xFFFFFFFF MR0I Interrupt on MR0 [0:0] ENUM DISABLED Disabled. Interrupt is disabled 0 ENABLED Enabled. Interrupt is generated when MR0 matches the value in the TC. 1 MR0R Reset on MR0 [1:1] ENUM DISABLED Disabled. Feature disabled. 0 RESET Reset. TC will be reset if MR0 matches it. 1 MR0S Stop on MR0 [2:2] ENUM DISABLED Disabled. Feature disabled. 0 MATCH Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 1 MR1I Interrupt on MR1 [3:3] ENUM DISABLED Disabled. Interrupt is disabled. 0 MATCH Match. Interrupt is generated when MR1 matches the value in the TC. 1 MR1R Reset on MR1 [4:4] ENUM DISABLED Disabled. Feature disabled. 0 RESET Reset. TC will be reset if MR1 matches it. 1 MR1S Stop on MR1 [5:5] ENUM DISABLED Disabled. Feature disabled. 0 STOP Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 1 MR2I Interrupt on MR2 [6:6] ENUM DISABLED Disabled. Interrupt is disabled 0 MATCH Match. Interrupt is generated when MR2 matches the value in the TC. 1 MR2R Reset on MR2 [7:7] ENUM DISABLED Disabled. Feature disabled. 0 MATCH Match. TC will be reset if MR2 matches it. 1 MR2S Stop on MR2. [8:8] ENUM DISABLED Disabled. Feature disabled. 0 STOP Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 1 MR3I Interrupt on MR3 [9:9] ENUM DISABLED Disabled. This interrupt is disabled. 0 INTERRUPT Interrupt. Interrupt is generated when MR3 matches the value in the TC. 1 MR3R Reset on MR3 [10:10] ENUM DISABLED Disabled. Feature disabled. 0 MATCH Match. TC will be reset if MR3 matches it. 1 MR3S Stop on MR3 [11:11] ENUM DISABLED Disabled. Feature disabled. 0 STOP Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 MR%s Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x018 read-write 0 0xFFFFFFFF MATCH Timer counter match value. [31:0] CCR Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x028 read-write 0 0xFFFFFFFF CAP0RE Capture on CAPn.0 rising edge [0:0] ENUM DISABLED Disabled. This feature is disabled. 0 LOW_TO_HIGH Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC. 1 CAP0FE Capture on CAPn.0 falling edge [1:1] ENUM DISABLED Disabled. This feature is disabled. 0 HIGH_TO_LOW High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC. 1 CAP0I Interrupt on CAPn.0 event [2:2] ENUM DISABLED Disabled. This feature is disabled. 0 LOAD Load. A CR0 load due to a CAPn.0 event will generate an interrupt. 1 CAP1RE Capture on CAPn.1 rising edge [3:3] ENUM DISABLED Disabled. This feature is disabled. 0 LOW_TO_HIGH Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC. 1 CAP1FE Capture on CAPn.1 falling edge [4:4] ENUM DISABLED Disabled. This feature is disabled. 0 HIGH_TO_LOW High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC. 1 CAP1I Interrupt on CAPn.1 event [5:5] ENUM DISABLED Disabled. This feature is disabled. 0 LOAD Load. A CR1 load due to a CAPn.1 event will generate an interrupt. 1 CAP2RE Capture on CAPn.2 rising edge [6:6] ENUM DISABLED Disabled. This feature is disabled. 0 LOW_TO_HIGH Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC. 1 CAP2FE Capture on CAPn.2 falling edge: [7:7] ENUM DISABLED Disabled. This feature is disabled. 0 HIGH_TO_LOW High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC. 1 CAP2I Interrupt on CAPn.2 event [8:8] ENUM DISABLED Disabled. This feature is disabled. 0 LOAD Load. A CR2 load due to a CAPn.2 event will generate an interrupt. 1 CAP3RE Capture on CAPn.3 rising edge [9:9] ENUM DISABLED Disabled. This feature is disabled. 0 LOW_TO_HIGH Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC. 1 CAP3FE High to low. Capture on CAPn.3 falling edge [10:10] ENUM DISABLED Disabled. This feature is disabled. 0 HIGH_TO_LOW A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC. 1 CAP3I Interrupt on CAPn.3 event: [11:11] ENUM DISABLED Disabled. This feature is disabled. 0 LOAD Load. A CR3 load due to a CAPn.3 event will generate an interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] 4 0x4 0-3 CR%s Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. 0x02C read-only 0 0xFFFFFFFF CAP Timer counter capture value. [31:0] EMR External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). 0x03C read-write 0 0xFFFFFFFF EM0 External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). [0:0] EM1 External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high). [1:1] EM2 External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). [2:2] EM3 External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high). [3:3] EMC0 External Match Control 0. Determines the functionality of External Match 0. [5:4] ENUM NOP Do Nothing. 0x0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. [7:6] ENUM NOP Do Nothing. 0x0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. [9:8] ENUM NOP Do Nothing. 0x0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. [11:10] ENUM NOP Do Nothing. 0x0 CLEAR Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out). 0x1 SET Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out). 0x2 TOGGLE Toggle. Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] CTCR Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x070 read-write 0 0xFFFFFFFF CTMODE Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. [1:0] ENUM TIMER_MODE Timer Mode. Counts every rising PCLK edge 0x0 COUNTER_MODE_RISING Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 COUNTER_MODE_FALLING Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 COUNTER_MODE_EDGES Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 CINSEL Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. [3:2] ENUM CAP0 CAP0. CAPn.0 for TIMERn 0x0 CAP1 CAP1. CAPn.1 for TIMERn 0x1 CAP2 CAP2. CAPn.2 for TIMERn 0x2 CAP3 CAP3. CAPn.3 for TIMERn 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] TIMER1 0x40085000 TIMER1 13 TIMER2 0x400C3000 TIMER2 14 TIMER3 0x400C4000 TIMER3 15 SCU System Control Unit (SCU) I/O configuration SCU 0x40086000 0x0 0xFFF registers 2 0x4 0-1 SFSP0_%s Pin configuration register for pins P0 0x000 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 17 0x4 0-16 SFSP1_%s Pin configuration register for pins P1 0x080 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] SFSP1_17 Pin configuration register for pins P1_17 0x0C4 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up 1 RESERVED Reserved [5:5] EZI Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 EHD Select drive strength. [9:8] ENUM NORMAL_DRIVE_4_MA_D Normal-drive: 4 mA drive strength 0x0 MEDIUM_DRIVE_8_MA_D Medium-drive: 8 mA drive strength 0x1 HIGH_DRIVE_14_MA_DR High-drive: 14 mA drive strength 0x2 ULTRA_HIGH_DRIVE_20 Ultra high-drive: 20 mA drive strength 0x3 RESERVED Reserved [31:10] 3 0x4 18-20 SFSP1_%s Pin configuration register for pins P1 0x0C8 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 3 0x4 0-2 SFSP2_%s Pin configuration register for pins P2 0x100 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 3 0x4 3-5 SFSP2_%s Pin configuration register for pins P2 0x10C read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up 1 RESERVED Reserved [5:5] EZI Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 EHD Select drive strength. [9:8] ENUM NORMAL_DRIVE_4_MA_D Normal-drive: 4 mA drive strength 0x0 MEDIUM_DRIVE_8_MA_D Medium-drive: 8 mA drive strength 0x1 HIGH_DRIVE_14_MA_DR High-drive: 14 mA drive strength 0x2 ULTRA_HIGH_DRIVE_20 Ultra high-drive: 20 mA drive strength 0x3 RESERVED Reserved [31:10] 7 0x4 6-12 SFSP2_%s Pin configuration register for pins P2 0x118 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 3 0x4 0-2 SFSP3_%s Pin configuration register for pins P3 0x180 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] SFSP3_3 Pin configuration register for pins P3 0x18C read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Slew rate [5:5] ENUM FAST_LOW_NOISE_WITH Fast (low noise with fast speed) 0 HIGH_SPEED_MEDIUM_N High-speed (medium noise with high speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_FILTER Enable input filter 0 DISABLE_INPUT_FILTER Disable input filter 1 RESERVED Reserved [31:8] 5 0x4 4-8 SFSP3_%s Pin configuration register for pins P3 0x190 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 11 0x4 0-10 SFSP4_%s Pin configuration register for pins P4 0x200 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 8 0x4 0-7 SFSP5_%s Pin configuration register for pins P5 0x280 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 13 0x4 0-12 SFSP6_%s Pin configuration register for pins P6 0x300 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 8 0x4 0-7 SFSP7_%s Pin configuration register for pins P7 0x380 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 3 0x4 0-2 SFSP8_%s Pin configuration register for pins P8 0x400 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 6 0x4 3-8 SFSP8_%s Pin configuration register for pins P8 0x40C read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 7 0x4 0-6 SFSP9_%s Pin configuration register for pins P9 0x480 read-write 0 0xFFFFFFFF MODE Select pin function [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad [3:3] ENUM DISABLE_PULL_DOWN_ Disable pull-down. 0 ENABLE_PULL_DOWN_ Enable pull-down. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up 0 DISABLE_PULL_UP Disable pull-up 1 EHS Slew rate [5:5] ENUM SLOW Slow 0 FAST Fast 1 EZI Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 RESERVED Reserved [7:7] EHD Select drive strength [9:8] ENUM STANDARD_DRIVE_4_MA Standard drive: 4 mA drive strength 0x0 MEDIUM_DRIVE_8_MA_D Medium drive: 8 mA drive strength 0x1 HIGH_DRIVE_14_MA_DR High drive: 14 mA drive strength 0x2 ULTRA_HIGH_DRIVE_20 Ultra-high drive: 20 mA drive strength 0x3 RESERVED Reserved [31:10] SFSPA_0 Pin configuration register for pins PA 0x500 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 3 0x4 1-3 SFSPA_%s Pin configuration register for pins PA 0x504 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up 1 RESERVED Reserved [5:5] EZI Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 EHD Select drive strength. [9:8] ENUM NORMAL_DRIVE_4_MA_D Normal-drive: 4 mA drive strength 0x0 MEDIUM_DRIVE_8_MA_D Medium-drive: 8 mA drive strength 0x1 HIGH_DRIVE_14_MA_DR High-drive: 14 mA drive strength 0x2 ULTRA_HIGH_DRIVE_20 Ultra high-drive: 20 mA drive strength 0x3 RESERVED Reserved [31:10] SFSPA_4 Pin configuration register for pins PA 0x510 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 7 0x4 0-6 SFSPB_%s Pin configuration register for pins PB 0x580 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 15 0x4 0-14 SFSPC_%s Pin configuration register for pins PC 0x600 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 17 0x4 0-16 SFSPD_%s Pin configuration register for pins PD 0x680 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 16 0x4 0-15 SFSPE_%s Pin configuration register for pins PE 0x700 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 12 0x4 0-11 SFSPF_%s Pin configuration register for pins PF 0x780 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Select Slew rate. [5:5] ENUM SLOW_LOW_NOISE_WITH Slow (low noise with medium speed) 0 FAST_MEDIUM_NOISE_W Fast (medium noise with fast speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_GLITCH Enable input glitch filter 0 DISABLE_INPUT_GLITCH Disable input glitch filter 1 RESERVED Reserved [31:8] 4 0x4 0-3 SFSCLK_%s Pin configuration register for pins CLK 0xC00 read-write 0 0xFFFFFFFF MODE Select pin function. [2:0] ENUM FUNCTION_0_DEFAULT Function 0 (default) 0x0 FUNCTION_1 Function 1 0x1 FUNCTION_2 Function 2 0x2 FUNCTION_3 Function 3 0x3 FUNCTION_4 Function 4 0x4 FUNCTION_5 Function 5 0x5 FUNCTION_6 Function 6 0x6 FUNCTION_7 Function 7 0x7 EPD Enable pull-down resistor at pad. [3:3] ENUM DISABLE_PULL_DOWN Disable pull-down. 0 ENABLE_PULL_DOWN Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode. 1 EPUN Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. [4:4] ENUM ENABLE_PULL_UP Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. 0 DISABLE_PULL_UP Disable pull-up. 1 EHS Slew rate [5:5] ENUM FAST_LOW_NOISE_WITH Fast (low noise with fast speed) 0 HIGH_SPEED_MEDIUM_N High-speed (medium noise with high speed) 1 EZI Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. [6:6] ENUM DISABLE_INPUT_BUFFER Disable input buffer 0 ENABLE_INPUT_BUFFER Enable input buffer 1 ZIF Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. [7:7] ENUM ENABLE_INPUT_FILTER Enable input filter 0 DISABLE_INPUT_FILTER Disable input filter 1 RESERVED Reserved [31:8] SFSUSB Pin configuration register for pins USB1_DM and USB1_DP 0xC80 read-write 0x02 0xFFFFFFFF USB_AIM Differential data input AIP/AIM. [0:0] ENUM GOING_LOW_WITH_FULL Going LOW with full speed edge rate 0 GOING_HIGH_WITH_FULL Going HIGH with full speed edge rate 1 USB_ESEA Control signal for differential input or single input. [1:1] ENUM RESERVED Reserved. Do not use. 0 SINGLE_INPUT Single input. Enables USB1. Use with the on-chip full-speed PHY. 1 USB_EPD Enable pull-down connect. [2:2] ENUM PULL_DOWN_DISCONNECT Pull-down disconnected 0 PULL_DOWN_CONNECTED Pull-down connected 1 RESERVED Reserved [3:3] USB_EPWR Power mode. [4:4] ENUM POWER_SAVING_MODE_S Power saving mode (Suspend mode) 0 NORMAL_MODE Normal mode 1 USB_VBUS Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register. The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register. [5:5] ENUM VBUS_SIGNAL_LOW_OR_I VBUS signal LOW or inactive 0 VBUS_SIGNAL_HIGH_OR VBUS signal HIGH or active 1 RESERVED Reserved [31:6] SFSI2C0 Pin configuration register for I2C0-bus pins 0xC84 read-write 0x00 0xFFFFFFFF SCL_EFP Select input glitch filter time constant for the SCL pin. [0:0] ENUM 50_NS_GLITCH_FILTER 50 ns glitch filter 0 3_NS_GLITCH_FILTER 3 ns glitch filter 1 RESERVED Reserved. Always write a 0 to this bit. [1:1] SCL_EHD Select I2C mode for the SCL pin. [2:2] ENUM STANDARDFAST_MODE Standard/Fast mode transmit 0 FAST_MODE_PLUS_TRANS Fast-mode Plus transmit 1 SCL_EZI Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0. [3:3] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved [6:4] SCL_ZIF Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP. [7:7] ENUM ENABLE_INPUT_FILTER Enable input filter 0 DISABLE_INPUT_FILTER Disable input filter 1 SDA_EFP Select input glitch filter time constant for the SDA pin. [8:8] ENUM 50_NS_GLITCH_FILTER 50 ns glitch filter 0 3_NS_GLITCH_FILTER 3 ns glitch filter 1 RESERVED Reserved. Always write a 0 to this bit. [9:9] SDA_EHD Select I2C mode for the SDA pin. [10:10] ENUM STANDARDFAST_MODE Standard/Fast mode transmit 0 FAST_MODE_PLUS_TRANS Fast-mode Plus transmit 1 SDA_EZI Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0. [11:11] ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved [14:12] SDA_ZIF Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP. [15:15] ENUM ENABLE_INPUT_FILTER Enable input filter 0 DISABLE_INPUT_FILTER Disable input filter 1 RESERVED Reserved [31:16] ENAIO0 ADC0 function select register 0xC88 read-write 0x00 0xFFFFFFFF ADC0_0 Select ADC0_0 [0:0] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin P4_3. 0 ANALOG_FUNCTION_ADC0 Analog function ADC0_0 selected on pin P4_3 1 ADC0_1 Select ADC0_1 [1:1] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin P4_1. 0 ANALOG_FUNCTION_ADC0 Analog function ADC0_1 selected on pin P4_1. 1 ADC0_2 Select ADC0_2 [2:2] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin PF_8. 0 ANALOG_FUNCTION_ADC0 Analog function ADC0_2 selected on pin PF_8. 1 ADC0_3 Select ADC0_3 [3:3] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin P7_5. 0 ANALOG_FUNCTION_ADC0 Analog function ADC0_3 selected on pin P7_5. 1 ADC0_4 Select ADC0_4 [4:4] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin P7_4. 0 ANALOG_FUNCTION_ADC0 Analog function ADC0_4 selected on pin P7_4. 1 ADC0_5 Select ADC0_5 [5:5] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin PF_10. 0 ANALOG_FUNCTION_ADC0 Analog function ADC0_5 selected on pin PF_10. 1 ADC0_6 Select ADC0_6 [6:6] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin PB_6. 0 ANALOG_FUNCTION_ADC0 Analog function ADC0_6 selected on pin PB_6. 1 ENAIO1 ADC1 function select register 0xC8C read-write 0x00 0xFFFFFFFF ADC1_0 Select ADC1_0 [0:0] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin PC_3. 0 ANALOG_FUNCTION_ADC1 Analog function ADC1_0 selected on pin PC_3. 1 ADC1_1 Select ADC1_1 [1:1] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin PC_0. 0 ANALOG_FUNCTION_ADC1 Analog function ADC1_1 selected on pin PC_0. 1 ADC1_2 Select ADC1_2 [2:2] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin PF_9. 0 ANALOG_FUNCTION_ADC1 Analog function ADC1_2 selected on pin PF_9. 1 ADC1_3 Select ADC1_3 [3:3] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin PF_6. 0 ANALOG_FUNCTION_ADC1 Analog function ADC1_3 selected on pin PF_6. 1 ADC1_4 Select ADC1_4 [4:4] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin PF_5. 0 ANALOG_FUNCTION_ADC1 Analog function ADC1_4 selected on pin PF_5. 1 ADC1_5 Select ADC1_5 [5:5] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin PF_11. 0 ANALOG_FUNCTION_ADC1 Analog function ADC1_5 selected on pin PF_11. 1 ADC1_6 Select ADC1_6 [6:6] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin P7_7. 0 ANALOG_FUNCTION_ADC1 Analog function ADC1_6 selected on pin P7_7. 1 ADC1_7 Select ADC1_7. [7:7] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin PF_7. 0 ANALOG_FUNCTION_ADC1 Analog function ADC1_7 selected on pin PF_7. 1 ENAIO2 Analog function select register 0xC90 read-write 0x00 0xFFFFFFFF DAC Select DAC [0:0] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin P4_4. 0 ANALOG_FUNCTION_DAC Analog function DAC selected on pin P4_4. 1 BG Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1). [4:4] ENUM DIGITAL_FUNCTION_SEL Digital function selected on pin PF_7. 0 BAND_GAP_OUTPUT_SELE Band gap output selected for pin PF_7. 1 EMCDELAYCLK EMC clock delay register 0xD00 read-write 0x00 0xFFFFFFFF CLK_DELAY EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay [15:0] RESERVED Reserved. Do not write ones to reserved register bits. [31:16] SDDELAY SD/MMC sample and drive delay register 0xD80 read-write 0x00 0xFFFFFFFF SAMPLE_DELAY SD/MMC sample delay. The delay value is SAMPLE_DELAY x 0.5 ns. [3:0] RESERVED Reserved. Do not write ones to reserved register bits. [7:4] DRV_DELAY SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed. [11:8] RESERVED Reserved. Do not write ones to reserved register bits. [31:12] PINTSEL0 Pin interrupt select register for pin interrupts 0 to 3. 0xE00 read-write 0x00 0xFFFFFFFF INTPIN0 Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register. [4:0] PORTSEL0 Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register. [7:5] ENUM GPIO_PORT_0 GPIO Port 0 0x0 GPIO_PORT_1 GPIO Port 1 0x1 GPIO_PORT_2 GPIO Port 2 0x2 GPIO_PORT_3 GPIO Port 3 0x3 GPIO_PORT_4 GPIO Port 4 0x4 GPIO_PORT_5 GPIO Port 5 0x5 GPIO_PORT_6 GPIO Port 6 0x6 GPIO_PORT_7 GPIO Port 7 0x7 INTPIN1 Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register. [12:8] PORTSEL1 Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register. [15:13] ENUM GPIO_PORT_0 GPIO Port 0 0x0 GPIO_PORT_1 GPIO Port 1 0x1 GPIO_PORT_2 GPIO Port 2 0x2 GPIO_PORT_3 GPIO Port 3 0x3 GPIO_PORT_4 GPIO Port 4 0x4 GPIO_PORT_5 GPIO Port 5 0x5 GPIO_PORT_6 GPIO Port 6 0x6 GPIO_PORT_7 GPIO Port 7 0x7 INTPIN2 Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register. [20:16] PORTSEL2 Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register. [23:21] ENUM GPIO_PORT_0 GPIO Port 0 0x0 GPIO_PORT_1 GPIO Port 1 0x1 GPIO_PORT_2 GPIO Port 2 0x2 GPIO_PORT_3 GPIO Port 3 0x3 GPIO_PORT_4 GPIO Port 4 0x4 GPIO_PORT_5 GPIO Port 5 0x5 GPIO_PORT_6 GPIO Port 6 0x6 GPIO_PORT_7 GPIO Port 7 0x7 INTPIN3 Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register. [28:24] PORTSEL3 Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register. [31:29] ENUM GPIO_PORT_0 GPIO Port 0 0x0 GPIO_PORT_1 GPIO Port 1 0x1 GPIO_PORT_2 GPIO Port 2 0x2 GPIO_PORT_3 GPIO Port 3 0x3 GPIO_PORT_4 GPIO Port 4 0x4 GPIO_PORT_5 GPIO Port 5 0x5 GPIO_PORT_6 GPIO Port 6 0x6 GPIO_PORT_7 GPIO Port 7 0x7 PINTSEL1 Pin interrupt select register for pin interrupts 4 to 7. 0xE04 read-write 0x00 0xFFFFFFFF INTPIN4 Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register. [4:0] PORTSEL4 Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register. [7:5] ENUM GPIO_PORT_0 GPIO Port 0 0x0 GPIO_PORT_1 GPIO Port 1 0x1 GPIO_PORT_2 GPIO Port 2 0x2 GPIO_PORT_3 GPIO Port 3 0x3 GPIO_PORT_4 GPIO Port 4 0x4 GPIO_PORT_5 GPIO Port 5 0x5 GPIO_PORT_6 GPIO Port 6 0x6 GPIO_PORT_7 GPIO Port 7 0x7 INTPIN5 Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register. [12:8] PORTSEL5 Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register. [15:13] ENUM GPIO_PORT_0 GPIO Port 0 0x0 GPIO_PORT_1 GPIO Port 1 0x1 GPIO_PORT_2 GPIO Port 2 0x2 GPIO_PORT_3 GPIO Port 3 0x3 GPIO_PORT_4 GPIO Port 4 0x4 GPIO_PORT_5 GPIO Port 5 0x5 GPIO_PORT_6 GPIO Port 6 0x6 GPIO_PORT_7 GPIO Port 7 0x7 INTPIN6 Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register. [20:16] PORTSEL6 Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register. [23:21] ENUM GPIO_PORT_0 GPIO Port 0 0x0 GPIO_PORT_1 GPIO Port 1 0x1 GPIO_PORT_2 GPIO Port 2 0x2 GPIO_PORT_3 GPIO Port 3 0x3 GPIO_PORT_4 GPIO Port 4 0x4 GPIO_PORT_5 GPIO Port 5 0x5 GPIO_PORT_6 GPIO Port 6 0x6 GPIO_PORT_7 GPIO Port 7 0x7 INTPIN7 Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register. [28:24] PORTSEL7 Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register. [31:29] ENUM GPIO_PORT_0 GPIO Port 0 0x0 GPIO_PORT_1 GPIO Port 1 0x1 GPIO_PORT_2 GPIO Port 2 0x2 GPIO_PORT_3 GPIO Port 3 0x3 GPIO_PORT_4 GPIO Port 4 0x4 GPIO_PORT_5 GPIO Port 5 0x5 GPIO_PORT_6 GPIO Port 6 0x6 GPIO_PORT_7 GPIO Port 7 0x7 GPIO_PIN_INT GPIO pin interrupt GPIO_PIN_INT 0x40087000 0 0xFFF registers PIN_INT0 32 PIN_INT1 33 PIN_INT2 34 PIN_INT3 35 PIN_INT4 36 PIN_INT5 37 PIN_INT6 38 PIN_INT7 39 ISEL Pin Interrupt Mode register 0x000 read-write 0 0xFFFFFFFF PMODE0 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [0:0] PMODE1 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [1:1] PMODE2 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [2:2] PMODE3 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [3:3] PMODE4 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [4:4] PMODE5 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [5:5] PMODE6 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [6:6] PMODE7 Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive [7:7] RESERVED Reserved. [31:8] IENR Pin Interrupt Enable (Rising) register 0x004 read-write 0 0xFFFFFFFF ENRL0 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [0:0] ENRL1 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [1:1] ENRL2 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [2:2] ENRL3 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [3:3] ENRL4 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [4:4] ENRL5 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [5:5] ENRL6 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [6:6] ENRL7 Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] SIENR Set Pin Interrupt Enable (Rising) register 0x008 write-only 0 0x00000000 SETENRL0 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [0:0] SETENRL1 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [1:1] SETENRL2 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [2:2] SETENRL3 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [3:3] SETENRL4 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [4:4] SETENRL5 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [5:5] SETENRL6 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [6:6] SETENRL7 Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] CIENR Clear Pin Interrupt Enable (Rising) register 0x00C write-only 0 0x00000000 CENRL0 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [0:0] CENRL1 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [1:1] CENRL2 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [2:2] CENRL3 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [3:3] CENRL4 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [4:4] CENRL5 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [5:5] CENRL6 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [6:6] CENRL7 Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. [7:7] RESERVED Reserved. [31:8] IENF Pin Interrupt Enable Falling Edge / Active Level register 0x010 read-write 0 0xFFFFFFFF ENAF0 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [0:0] ENAF1 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [1:1] ENAF2 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [2:2] ENAF3 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [3:3] ENAF4 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [4:4] ENAF5 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [5:5] ENAF6 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [6:6] ENAF7 Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. [7:7] RESERVED Reserved. [31:8] SIENF Set Pin Interrupt Enable Falling Edge / Active Level register 0x014 write-only 0 0x00000000 SETENAF0 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [0:0] SETENAF1 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [1:1] SETENAF2 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [2:2] SETENAF3 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [3:3] SETENAF4 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [4:4] SETENAF5 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [5:5] SETENAF6 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [6:6] SETENAF7 Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. [7:7] RESERVED Reserved. [31:8] CIENF Clear Pin Interrupt Enable Falling Edge / Active Level address 0x018 write-only 0 0x00000000 CENAF0 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [0:0] CENAF1 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [1:1] CENAF2 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [2:2] CENAF3 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [3:3] CENAF4 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [4:4] CENAF5 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [5:5] CENAF6 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [6:6] CENAF7 Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. [7:7] RESERVED Reserved. [31:8] RISE Pin Interrupt Rising Edge register 0x01C read-write 0 0xFFFFFFFF RDET0 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [0:0] RDET1 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [1:1] RDET2 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [2:2] RDET3 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [3:3] RDET4 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [4:4] RDET5 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [5:5] RDET6 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [6:6] RDET7 Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. [7:7] RESERVED Reserved. [31:8] FALL Pin Interrupt Falling Edge register 0x020 read-write 0 0xFFFFFFFF FDET0 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [0:0] FDET1 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [1:1] FDET2 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [2:2] FDET3 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [3:3] FDET4 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [4:4] FDET5 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [5:5] FDET6 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [6:6] FDET7 Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. [7:7] RESERVED Reserved. [31:8] IST Pin Interrupt Status register 0x024 read-write 0 0xFFFFFFFF PSTAT0 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [0:0] PSTAT1 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [1:1] PSTAT2 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [2:2] PSTAT3 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [3:3] PSTAT4 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [4:4] PSTAT5 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [5:5] PSTAT6 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [6:6] PSTAT7 Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register). [7:7] RESERVED Reserved. [31:8] GPIO_GROUP_INT0 GPIO group interrupt 0 GPIO_GROUP_INT0 0x40088000 0 0xFFF registers GINT0 40 CTRL GPIO grouped interrupt control register 0x000 read-write 0 0xFFFFFFFF INT Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. [0:0] ENUM NO_INTERRUPT_REQUEST No interrupt request is pending. 0 INTERRUPT_REQUEST_IS Interrupt request is active. 1 COMB Combine enabled inputs for group interrupt [1:1] ENUM OR_FUNCTIONALITY_A_ OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). 0 AND_FUNCTIONALITY_A AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). 1 TRIG Group interrupt trigger [2:2] ENUM EDGE_TRIGGERED Edge-triggered 0 LEVEL_TRIGGERED Level-triggered 1 RESERVED Reserved [31:3] 8 0x4 0-7 PORT_POL%s GPIO grouped interrupt port polarity register 0x020 read-write 0xFFFFFFFF 0xFFFFFFFF POL_0 Configure pin polarity of port pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [0:0] POL_1 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [1:1] POL_2 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [2:2] POL_3 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [3:3] POL_4 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [4:4] POL_5 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [5:5] POL_6 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [6:6] POL_7 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [7:7] POL_8 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [8:8] POL_9 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [9:9] POL_10 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [10:10] POL_11 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [11:11] POL_12 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [12:12] POL_13 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [13:13] POL_14 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [14:14] POL_15 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [15:15] POL_16 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [16:16] POL_17 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [17:17] POL_18 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [18:18] POL_19 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [19:19] POL_20 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [20:20] POL_21 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [21:21] POL_22 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [22:22] POL_23 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [23:23] POL_24 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [24:24] POL_25 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [25:25] POL_26 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [26:26] POL_27 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [27:27] POL_28 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [28:28] POL_29 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [29:29] POL_30 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [30:30] POL_31 Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt. [31:31] 8 0x4 0-7 PORT_ENA%s GPIO grouped interrupt port m enable register 0x040 read-write 0 0xFFFFFFFF ENA_0 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [0:0] ENA_1 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [1:1] ENA_2 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [2:2] ENA_3 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [3:3] ENA_4 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [4:4] ENA_5 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [5:5] ENA_6 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [6:6] ENA_7 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [7:7] ENA_8 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [8:8] ENA_9 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [9:9] ENA_10 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [10:10] ENA_11 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [11:11] ENA_12 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [12:12] ENA_13 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [13:13] ENA_14 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [14:14] ENA_15 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [15:15] ENA_16 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [16:16] ENA_17 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [17:17] ENA_18 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [18:18] ENA_19 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [19:19] ENA_20 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [20:20] ENA_21 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [21:21] ENA_22 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [22:22] ENA_23 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [23:23] ENA_24 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [24:24] ENA_25 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [25:25] ENA_26 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [26:26] ENA_27 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [27:27] ENA_28 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [28:28] ENA_29 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [29:29] ENA_30 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [30:30] ENA_31 Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt. [31:31] GPIO_GROUP_INT1 0x40089000 0 0xFFF registers GINT1 41 MCPWM Motor Control PWM (MOTOCONPWM) MCPWM 0x400A0000 0 0xFFF registers MCPWM 16 CON PWM Control read address 0x000 read-only 0 0xFFFFFFFF RUN0 Stops/starts timer channel 0. [0:0] ENUM STOP_ Stop. 0 RUN_ Run. 1 CENTER0 Edge/center aligned operation for channel 0. [1:1] ENUM EDGE_ALIGNED_ Edge-aligned. 0 CENTER_ALIGNED_ Center-aligned. 1 POLA0 Selects polarity of the MCOA0 and MCOB0 pins. [2:2] ENUM PASSIVE_STATE_IS_LOW Passive state is LOW, active state is HIGH. 0 PASSIVE_STATE_IS_HIG Passive state is HIGH, active state is LOW. 1 DTE0 Controls the dead-time feature for channel 0. [3:3] ENUM DEAD_TIME_DISABLED_ Dead-time disabled. 0 DEAD_TIME_ENABLED_ Dead-time enabled. 1 DISUP0 Enable/disable updates of functional registers for channel 0 (see Section 24.8.2). [4:4] ENUM UPDATE Functional registers are updated from the write registers at the end of each PWM cycle. 0 NOUPDATE Functional registers remain the same as long as the timer is running. 1 RESERVED Reserved. [7:5] RUN1 Stops/starts timer channel 1. [8:8] ENUM STOP_ Stop. 0 RUN_ Run. 1 CENTER1 Edge/center aligned operation for channel 1. [9:9] ENUM EDGE_ALIGNED_ Edge-aligned. 0 CENTER_ALIGNED_ Center-aligned. 1 POLA1 Selects polarity of the MCOA1 and MCOB1 pins. [10:10] ENUM PASSIVE_STATE_IS_LOW Passive state is LOW, active state is HIGH. 0 PASSIVE_STATE_IS_HIG Passive state is HIGH, active state is LOW. 1 DTE1 Controls the dead-time feature for channel 1. [11:11] ENUM DEAD_TIME_DISABLED_ Dead-time disabled. 0 DEAD_TIME_ENABLED_ Dead-time enabled. 1 DISUP1 Enable/disable updates of functional registers for channel 1 (see Section 24.8.2). [12:12] ENUM UPDATE Functional registers are updated from the write registers at the end of each PWM cycle. 0 NOUPDATE Functional registers remain the same as long as the timer is running. 1 RESERVED Reserved. [15:13] RUN2 Stops/starts timer channel 2. [16:16] ENUM STOP_ Stop. 0 RUN_ Run. 1 CENTER2 Edge/center aligned operation for channel 2. [17:17] ENUM EDGE_ALIGNED_ Edge-aligned. 0 CENTER_ALIGNED_ Center-aligned. 1 POLA2 Selects polarity of the MCOA2 and MCOB2 pins. [18:18] ENUM PASSIVE_STATE_IS_LOW Passive state is LOW, active state is HIGH. 0 PASSIVE_STATE_IS_HIG Passive state is HIGH, active state is LOW. 1 DTE2 Controls the dead-time feature for channel 1. [19:19] ENUM DEAD_TIME_DISABLED_ Dead-time disabled. 0 DEAD_TIME_ENABLED_ Dead-time enabled. 1 DISUP2 Enable/disable updates of functional registers for channel 2 (see Section 24.8.2). [20:20] ENUM UPDATE Functional registers are updated from the write registers at the end of each PWM cycle. 0 NOUPDATE Functional registers remain the same as long as the timer is running. 1 RESERVED Reserved. [28:21] INVBDC Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode. [29:29] ENUM OPPOSITE The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time). 0 SAME The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6) 1 ACMODE 3-phase AC mode select (see Section 24.8.7). [30:30] ENUM 3_PHASE_AC_MODE_OFF 3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register. 0 3_PHASE_AC_MODE_ON_ 3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0. 1 DCMODE 3-phase DC mode select (see Section 24.8.6). [31:31] ENUM 3_PHASE_DC_MODE_OFF 3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1) 0 3_PHASE_DC_MODE_ON_ 3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs. 1 CON_SET PWM Control set address 0x004 write-only 0 0x00000000 RUN0_SET Writing a one sets the corresponding bit in the CON register. [0:0] CENTER0_SET Writing a one sets the corresponding bit in the CON register. [1:1] POLA0_SET Writing a one sets the corresponding bit in the CON register. [2:2] DTE0_SET Writing a one sets the corresponding bit in the CON register. [3:3] DISUP0_SET Writing a one sets the corresponding bit in the CON register. [4:4] RESERVED Writing a one sets the corresponding bit in the CON register. [7:5] RUN1_SET Writing a one sets the corresponding bit in the CON register. [8:8] CENTER1_SET Writing a one sets the corresponding bit in the CON register. [9:9] POLA1_SET Writing a one sets the corresponding bit in the CON register. [10:10] DTE1_SET Writing a one sets the corresponding bit in the CON register. [11:11] DISUP1_SET Writing a one sets the corresponding bit in the CON register. [12:12] RESERVED Writing a one sets the corresponding bit in the CON register. [15:13] RUN2_SET Writing a one sets the corresponding bit in the CON register. [16:16] CENTER2_SET Writing a one sets the corresponding bit in the CON register. [17:17] POLA2_SET Writing a one sets the corresponding bit in the CON register. [18:18] DTE2_SET Writing a one sets the corresponding bit in the CON register. [19:19] DISUP2_SET Writing a one sets the corresponding bit in the CON register. [20:20] RESERVED Writing a one sets the corresponding bit in the CON register. [28:21] INVBDC_SET Writing a one sets the corresponding bit in the CON register. [29:29] ACMODE_SET Writing a one sets the corresponding bit in the CON register. [30:30] DCMODE_SET Writing a one sets the corresponding bit in the CON register. [31:31] CON_CLR PWM Control clear address 0x008 write-only 0 0x00000000 RUN0_CLR Writing a one clears the corresponding bit in the CON register. [0:0] CENTER0_CLR Writing a one clears the corresponding bit in the CON register. [1:1] POLA0_CLR Writing a one clears the corresponding bit in the CON register. [2:2] DTE0_CLR Writing a one clears the corresponding bit in the CON register. [3:3] DISUP0_CLR Writing a one clears the corresponding bit in the CON register. [4:4] RESERVED Writing a one clears the corresponding bit in the CON register. [7:5] RUN1_CLR Writing a one clears the corresponding bit in the CON register. [8:8] CENTER1_CLR Writing a one clears the corresponding bit in the CON register. [9:9] POLA1_CLR Writing a one clears the corresponding bit in the CON register. [10:10] DTE1_CLR Writing a one clears the corresponding bit in the CON register. [11:11] DISUP1_CLR Writing a one clears the corresponding bit in the CON register. [12:12] RESERVED Writing a one clears the corresponding bit in the CON register. [15:13] RUN2_CLR Writing a one clears the corresponding bit in the CON register. [16:16] CENTER2_CLR Writing a one clears the corresponding bit in the CON register. [17:17] POLA2_CLR Writing a one clears the corresponding bit in the CON register. [18:18] DTE2_CLR Writing a one clears the corresponding bit in the CON register. [19:19] DISUP2_CLR Writing a one clears the corresponding bit in the CON register. [20:20] RESERVED Writing a one clears the corresponding bit in the CON register. [28:21] INVBDC_CLR Writing a one clears the corresponding bit in the CON register. [29:29] ACMOD_CLR Writing a one clears the corresponding bit in the CON register. [30:30] DCMODE_CLR Writing a one clears the corresponding bit in the CON register. [31:31] CAPCON Capture Control read address 0x00C read-only 0 0xFFFFFFFF CAP0MCI0_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. [0:0] CAP0MCI0_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. [1:1] CAP0MCI1_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. [2:2] CAP0MCI1_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. [3:3] CAP0MCI2_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. [4:4] CAP0MCI2_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. [5:5] CAP1MCI0_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. [6:6] CAP1MCI0_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. [7:7] CAP1MCI1_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. [8:8] CAP1MCI1_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. [9:9] CAP1MCI2_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. [10:10] CAP1MCI2_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. [11:11] CAP2MCI0_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. [12:12] CAP2MCI0_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. [13:13] CAP2MCI1_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. [14:14] CAP2MCI1_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. [15:15] CAP2MCI2_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. [16:16] CAP2MCI2_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. [17:17] RT0 If this bit is 1, TC0 is reset by a channel 0 capture event. [18:18] RT1 If this bit is 1, TC1 is reset by a channel 1 capture event. [19:19] RT2 If this bit is 1, TC2 is reset by a channel 2 capture event. [20:20] RESERVED Reserved. [31:21] CAPCON_SET Capture Control set address 0x010 write-only 0 0x00000000 CAP0MCI0_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [0:0] CAP0MCI0_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [1:1] CAP0MCI1_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [2:2] CAP0MCI1_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [3:3] CAP0MCI2_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [4:4] CAP0MCI2_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [5:5] CAP1MCI0_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [6:6] CAP1MCI0_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [7:7] CAP1MCI1_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [8:8] CAP1MCI1_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [9:9] CAP1MCI2_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [10:10] CAP1MCI2_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [11:11] CAP2MCI0_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [12:12] CAP2MCI0_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [13:13] CAP2MCI1_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [14:14] CAP2MCI1_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [15:15] CAP2MCI2_RE_SET Writing a one sets the corresponding bits in the CAPCON register. [16:16] CAP2MCI2_FE_SET Writing a one sets the corresponding bits in the CAPCON register. [17:17] RT0_SET Writing a one sets the corresponding bits in the CAPCON register. [18:18] RT1_SET Writing a one sets the corresponding bits in the CAPCON register. [19:19] RT2_SET Writing a one sets the corresponding bits in the CAPCON register. [20:20] RESERVED Reserved. [31:21] CAPCON_CLR Event Control clear address 0x014 write-only 0 0x00000000 CAP0MCI0_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [0:0] CAP0MCI0_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [1:1] CAP0MCI1_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [2:2] CAP0MCI1_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [3:3] CAP0MCI2_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [4:4] CAP0MCI2_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [5:5] CAP1MCI0_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [6:6] CAP1MCI0_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [7:7] CAP1MCI1_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [8:8] CAP1MCI1_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [9:9] CAP1MCI2_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [10:10] CAP1MCI2_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [11:11] CAP2MCI0_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [12:12] CAP2MCI0_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [13:13] CAP2MCI1_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [14:14] CAP2MCI1_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [15:15] CAP2MCI2_RE_CLR Writing a one clears the corresponding bits in the CAPCON register. [16:16] CAP2MCI2_FE_CLR Writing a one clears the corresponding bits in the CAPCON register. [17:17] RT0_CLR Writing a one clears the corresponding bits in the CAPCON register. [18:18] RT1_CLR Writing a one clears the corresponding bits in the CAPCON register. [19:19] RT2_CLR Writing a one clears the corresponding bits in the CAPCON register. [20:20] RESERVED Reserved. [31:21] 3 0x4 0-2 TC%s Timer Counter register 0x018 read-write 0 0xFFFFFFFF MCTC Timer/Counter value. [31:0] 3 0x4 0-2 LIM%s Limit register 0x024 read-write 0 0xFFFFFFFF MCLIM Limit value. [31:0] 3 0x4 0-2 MAT%s Match register 0x030 read-write 0 0xFFFFFFFF MCMAT Match value. [31:0] DT Dead time register 0x03C read-write 0x3FFFFFFF 0xFFFFFFFF DT0 Dead time for channel 0.[1] [9:0] DT1 Dead time for channel 1.[2] [19:10] DT2 Dead time for channel 2.[2] [29:20] RESERVED reserved [31:30] CCP Communication Pattern register 0x040 read-write 0 0xFFFFFFFF CCPA0 Communication pattern output A, channel 0. [0:0] ENUM MCOA0_PASSIVE_ MCOA0 passive. 0 INTERNAL_MCOA0_ internal MCOA0. 1 CCPB0 Communication pattern output B, channel 0. [1:1] ENUM MCOB0_PASSIVE_ MCOB0 passive. 0 MCOB0_TRACKS_INTERNA MCOB0 tracks internal MCOA0. 1 CCPA1 Communication pattern output A, channel 1. [2:2] ENUM MCOA1_PASSIVE_ MCOA1 passive. 0 MCOA1_TRACKS_INTERNA MCOA1 tracks internal MCOA0. 1 CCPB1 Communication pattern output B, channel 1. [3:3] ENUM MCOB1_PASSIVE_ MCOB1 passive. 0 MCOB1_TRACKS_INTERNA MCOB1 tracks internal MCOA0. 1 CCPA2 Communication pattern output A, channel 2. [4:4] ENUM MCOA2_PASSIVE_ MCOA2 passive. 0 MCOA2_TRACKS_INTERNA MCOA2 tracks internal MCOA0. 1 CCPB2 Communication pattern output B, channel 2. [5:5] ENUM MCOB2_PASSIVE_ MCOB2 passive. 0 MCOB2_TRACKS_INTERNA MCOB2 tracks internal MCOA0. 1 RESERVED Reserved. [31:6] 3 0x4 0-2 CAP%s Capture register 0x044 read-only 0 0xFFFFFFFF CAP Current TC value at a capture event. [31:0] INTEN Interrupt Enable read address 0x050 read-only 0 0xFFFFFFFF ILIM0 Limit interrupt for channel 0. [0:0] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 IMAT0 Match interrupt for channel 0. [1:1] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 ICAP0 Capture interrupt for channel 0. [2:2] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 RESERVED Reserved. [3:3] ILIM1 Limit interrupt for channel 1. [4:4] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 IMAT1 Match interrupt for channel 1. [5:5] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 ICAP1 Capture interrupt for channel 1. [6:6] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 RESERVED Reserved. [7:7] ILIM2 Limit interrupt for channel 2. [8:8] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 IMAT2 Match interrupt for channel 2. [9:9] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 ICAP2 Capture interrupt for channel 2. [10:10] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 RESERVED Reserved. [14:11] ABORT Fast abort interrupt. [15:15] ENUM INTERRUPT_DISABLED_ Interrupt disabled. 0 INTERRUPT_ENABLED_ Interrupt enabled. 1 RESERVED Reserved. [31:16] INTEN_SET Interrupt Enable set address 0x054 write-only 0 0x00000000 ILIM0_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [0:0] IMAT0_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [1:1] ICAP0_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [2:2] RESERVED Reserved. [3:3] ILIM1_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [4:4] IMAT1_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [5:5] ICAP1_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [6:6] RESERVED Reserved. [7:7] ILIM2_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [9:9] IMAT2_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [10:10] ICAP2_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [11:11] RESERVED Reserved. [14:12] ABORT_SET Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt. [15:15] RESERVED Reserved. [31:16] INTEN_CLR Interrupt Enable clear address 0x058 write-only 0 0x00000000 ILIM0_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [0:0] IMAT0_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [1:1] ICAP0_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [2:2] RESERVED Reserved. [3:3] ILIM1_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [4:4] IMAT1_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [5:5] ICAP1_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [6:6] RESERVED Reserved. [7:7] ILIM2_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [8:8] IMAT2_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [9:9] ICAP2_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [10:10] RESERVED Reserved. [14:11] ABORT_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [15:15] RESERVED Reserved. [31:16] INTF Interrupt flags read address 0x068 read-only 0 0xFFFFFFFF ILIM0_F Limit interrupt flag for channel 0. [0:0] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 IMAT0_F Match interrupt flag for channel 0. [1:1] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 ICAP0_F Capture interrupt flag for channel 0. [2:2] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 RESERVED Reserved. [3:3] ILIM1_F Limit interrupt flag for channel 1. [4:4] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 IMAT1_F Match interrupt flag for channel 1. [5:5] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 ICAP1_F Capture interrupt flag for channel 1. [6:6] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 RESERVED Reserved. [7:7] ILIM2_F Limit interrupt flag for channel 2. [8:8] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 IMAT2_F Match interrupt flag for channel 2. [9:9] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 ICAP2_F Capture interrupt flag for channel 2. [10:10] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 RESERVED Reserved. [14:11] ABORT_F Fast abort interrupt flag. [15:15] ENUM THIS_INTERRUPT_SOURC This interrupt source is not contributing to the MCPWM interrupt request. 0 IF_THE_CORRESPONDING If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller. 1 RESERVED Reserved. [31:16] INTF_SET Interrupt flags set address 0x06C write-only 0 0x00000000 ILIM0_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [0:0] IMAT0_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [1:1] ICAP0_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [2:2] RESERVED Reserved. [3:3] ILIM1_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [4:4] IMAT1_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [5:5] ICAP1_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [6:6] RESERVED Reserved. [7:7] ILIM2_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [8:8] IMAT2_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [9:9] ICAP2_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [10:10] RESERVED Reserved. [14:11] ABORT_F_SET Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt. [15:15] RESERVED Reserved. [31:16] INTF_CLR Interrupt flags clear address 0x070 write-only 0 0x00000000 ILIM0_F_CLR Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request. [0:0] IMAT0_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [1:1] ICAP0_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [2:2] RESERVED Reserved. [3:3] ILIM1_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [4:4] IMAT1_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [5:5] ICAP1_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [6:6] RESERVED Reserved. [7:7] ILIM2_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [8:8] IMAT2_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [9:9] ICAP2_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [10:10] RESERVED Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [14:11] ABORT_F_CLR Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt. [15:15] RESERVED Reserved. [31:16] CNTCON Count Control read address 0x05C read-only 0 0xFFFFFFFF TC0MCI0_RE Counter 0 rising edge mode, channel 0. [0:0] ENUM NOEFFECT A rising edge on MCI0 does not affect counter 0. 0 RISING If MODE0 is 1, counter 0 advances on a rising edge on MCI0. 1 TC0MCI0_FE Counter 0 falling edge mode, channel 0. [1:1] ENUM NOEFECT A falling edge on MCI0 does not affect counter 0. 0 FALLING If MODE0 is 1, counter 0 advances on a falling edge on MCI0. 1 TC0MCI1_RE Counter 0 rising edge mode, channel 1. [2:2] ENUM NOEFFECT A rising edge on MCI1 does not affect counter 0. 0 RISING If MODE0 is 1, counter 0 advances on a rising edge on MCI1. 1 TC0MCI1_FE Counter 0 falling edge mode, channel 1. [3:3] ENUM NOEFFECT A falling edge on MCI1 does not affect counter 0. 0 FALLING If MODE0 is 1, counter 0 advances on a falling edge on MCI1. 1 TC0MCI2_RE Counter 0 rising edge mode, channel 2. [4:4] ENUM NOEFFECT A rising edge on MCI0 does not affect counter 0. 0 RISING If MODE0 is 1, counter 0 advances on a rising edge on MCI2. 1 TC0MCI2_FE Counter 0 falling edge mode, channel 2. [5:5] ENUM NOEFFECT A falling edge on MCI0 does not affect counter 0. 0 FALLING If MODE0 is 1, counter 0 advances on a falling edge on MCI2. 1 TC1MCI0_RE Counter 1 rising edge mode, channel 0. [6:6] ENUM NOEFFECT A rising edge on MCI0 does not affect counter 1. 0 RISING If MODE1 is 1, counter 1 advances on a rising edge on MCI0. 1 TC1MCI0_FE Counter 1 falling edge mode, channel 0. [7:7] ENUM RISING A falling edge on MCI0 does not affect counter 1. 0 FALLING If MODE1 is 1, counter 1 advances on a falling edge on MCI0. 1 TC1MCI1_RE Counter 1 rising edge mode, channel 1. [8:8] ENUM NOEFFECT A rising edge on MCI1 does not affect counter 1. 0 RISING If MODE1 is 1, counter 1 advances on a rising edge on MCI1. 1 TC1MCI1_FE Counter 1 falling edge mode, channel 1. [9:9] ENUM NOEFFECT A falling edge on MCI0 does not affect counter 1. 0 FALLING If MODE1 is 1, counter 1 advances on a falling edge on MCI1. 1 TC1MCI2_RE Counter 1 rising edge mode, channel 2. [10:10] ENUM NOEFFECT A rising edge on MCI2 does not affect counter 1. 0 RISING If MODE1 is 1, counter 1 advances on a rising edge on MCI2. 1 TC1MCI2_FE Counter 1 falling edge mode, channel 2. [11:11] ENUM NOEFFECT A falling edge on MCI2 does not affect counter 1. 0 RISING If MODE1 is 1, counter 1 advances on a falling edge on MCI2. 1 TC2MCI0_RE Counter 2 rising edge mode, channel 0. [12:12] ENUM NOEFFECT A rising edge on MCI0 does not affect counter 2. 0 FALLING If MODE2 is 1, counter 2 advances on a rising edge on MCI0. 1 TC2MCI0_FE Counter 2 falling edge mode, channel 0. [13:13] ENUM NOEFFECT A falling edge on MCI0 does not affect counter 2. 0 FALLING If MODE2 is 1, counter 2 advances on a falling edge on MCI0. 1 TC2MCI1_RE Counter 2 rising edge mode, channel 1. [14:14] ENUM NOEFFECT A rising edge on MCI1 does not affect counter 2. 0 FALLING If MODE2 is 1, counter 2 advances on a rising edge on MCI1. 1 TC2MCI1_FE Counter 2 falling edge mode, channel 1. [15:15] ENUM NOEFFECT A falling edge on MCI1 does not affect counter 2. 0 FALLING If MODE2 is 1, counter 2 advances on a falling edge on MCI1. 1 TC2MCI2_RE Counter 2 rising edge mode, channel 2. [16:16] ENUM NOEFFECT A rising edge on MCI2 does not affect counter 2. 0 FALLING If MODE2 is 1, counter 2 advances on a rising edge on MCI2. 1 TC2MCI2_FE Counter 2 falling edge mode, channel 2. [17:17] ENUM NOEFFECT A falling edge on MCI2 does not affect counter 2. 0 FALLING If MODE2 is 1, counter 2 advances on a falling edge on MCI2. 1 RESERVED Reserved. [28:18] CNTR0 Channel 0 counter/timer mode. [29:29] ENUM CHANNEL_0_IS_IN_TIME Channel 0 is in timer mode. 0 CHANNEL_0_IS_IN_COUN Channel 0 is in counter mode. 1 CNTR1 Channel 1 counter/timer mode. [30:30] ENUM CHANNEL_1_IS_IN_TIME Channel 1 is in timer mode. 0 CHANNEL_1_IS_IN_COUN Channel 1 is in counter mode. 1 CNTR2 Channel 2 counter/timer mode. [31:31] ENUM CHANNEL_2_IS_IN_TIME Channel 2 is in timer mode. 0 CHANNEL_2_IS_IN_COUN Channel 2 is in counter mode. 1 CNTCON_SET Count Control set address 0x060 write-only 0 0x00000000 TC0MCI0_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [0:0] TC0MCI0_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [1:1] TC0MCI1_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [2:2] TC0MCI1_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [3:3] TC0MCI2_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [4:4] TC0MCI2_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [5:5] TC1MCI0_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [6:6] TC1MCI0_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [7:7] TC1MCI1_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [8:8] TC1MCI1_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [9:9] TC1MCI2_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [10:10] TC1MCI2_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [11:11] TC2MCI0_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [12:12] TC2MCI0_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [13:13] TC2MCI1_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [14:14] TC2MCI1_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [15:15] TC2MCI2_RE_SET Writing a one sets the corresponding bit in the CNTCON register. [16:16] TC2MCI2_FE_SET Writing a one sets the corresponding bit in the CNTCON register. [17:17] RESERVED Reserved. [28:18] CNTR0_SET Writing a one sets the corresponding bit in the CNTCON register. [29:29] CNTR1_SET Writing a one sets the corresponding bit in the CNTCON register. [30:30] CNTR2_SET Writing a one sets the corresponding bit in the CNTCON register. [31:31] CNTCON_CLR Count Control clear address 0x064 write-only 0 0x00000000 TC0MCI0_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [0:0] TC0MCI0_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [1:1] TC0MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [2:2] TC0MCI1_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [3:3] TC0MCI2_RE Writing a one clears the corresponding bit in the CNTCON register. [4:4] TC0MCI2_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [5:5] TC1MCI0_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [6:6] TC1MCI0_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [7:7] TC1MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [8:8] TC1MCI1_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [9:9] TC1MCI2_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [10:10] TC1MCI2_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [11:11] TC2MCI0_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [12:12] TC2MCI0_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [13:13] TC2MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [14:14] TC2MCI1_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [15:15] TC2MCI2_RE_CLR Writing a one clears the corresponding bit in the CNTCON register. [16:16] TC2MCI2_FE_CLR Writing a one clears the corresponding bit in the CNTCON register. [17:17] RESERVED Reserved. [28:18] CNTR0_CLR Writing a one clears the corresponding bit in the CNTCON register. [29:29] CNTR1_CLR Writing a one clears the corresponding bit in the CNTCON register. [30:30] CNTR2_CLR Writing a one clears the corresponding bit in the CNTCON register. [31:31] CAP_CLR Capture clear address 0x074 write-only 0 0x00000000 CAP_CLR0 Writing a 1 to this bit clears the CAP0 register. [0:0] CAP_CLR1 Writing a 1 to this bit clears the CAP1 register. [1:1] CAP_CLR2 Writing a 1 to this bit clears the CAP2 register. [2:2] RESERVED Reserved [31:3] I2C0 I2C-bus interface I2C 0x400A1000 0 0xFFF registers I2C0 18 CONSET I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. 0x000 read-write 0x00 0xFFFFFFFF RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] AA Assert acknowledge flag. [2:2] SI I2C interrupt flag. [3:3] STO STOP flag. [4:4] STA START flag. [5:5] I2EN I2C interface enable. [6:6] RESERVED Reserved. The value read from a reserved bit is not defined. [31:7] STAT I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. 0x004 read-only 0xF8 0xFFFFFFFF RESERVED These bits are unused and are always 0. [2:0] Status These bits give the actual status information about the I 2C interface. [7:3] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] DAT I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. 0x008 read-write 0x00 0xFFFFFFFF Data This register holds data values that have been received or are to be transmitted. [7:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] ADR0 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x00C read-write 0x00 0xFFFFFFFF GC General Call enable bit. [0:0] Address The I2C device address for slave mode. [7:1] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] SCLH SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. 0x010 read-write 0x04 0xFFFFFFFF SCLH Count for SCL HIGH time period selection. [15:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:16] SCLL SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. 0x014 read-write 0x04 0xFFFFFFFF SCLL Count for SCL low time period selection. [15:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:16] CONCLR I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. 0x018 write-only 0 0x00000000 RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] AAC Assert acknowledge Clear bit. [2:2] SIC I2C interrupt Clear bit. [3:3] RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [4:4] STAC START flag Clear bit. [5:5] I2ENC I2C interface Disable bit. [6:6] RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:7] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] MMCTRL Monitor mode control register. 0x01C read-write 0x00 0xFFFFFFFF MM_ENA Monitor mode enable. [0:0] ENUM MONITOR_MODE_DISABLE Monitor mode disabled. 0 THE_I_2C_MODULE_WILL The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. 1 ENA_SCL SCL output enable. [1:1] ENUM WHEN_THIS_BIT_IS_CLE When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. 0 WHEN_THIS_BIT_IS_SET When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] 1 MATCH_ALL Select interrupt register match. [2:2] ENUM WHEN_THIS_BIT_IS_CLE When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. 0 WHEN_THIS_BIT_IS_SET When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. 1 RESERVED Reserved. The value read from reserved bits is not defined. [31:3] 3 0x4 1-3 ADR%s I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x020 read-write 0x00 0xFFFFFFFF GC General Call enable bit. [0:0] Address The I2C device address for slave mode. [7:1] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] DATA_BUFFER Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. 0x02C read-only 0x00 0xFFFFFFFF Data This register holds contents of the 8 MSBs of the DAT shift register. [7:0] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] 4 0x4 0-3 MASK%s I2C Slave address mask register 0x030 read-write 0x00 0xFFFFFFFF RESERVED Reserved. User software should not write ones to reserved bits. This bit reads always back as 0. [0:0] MASK Mask bits. [7:1] RESERVED Reserved. The value read from a reserved bit is not defined. [31:8] I2C1 0x400E0000 I2C1 19 I2S0 I2S interface I2S 0x400A2000 0 0xFFF registers I2S0 28 DAO I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. 0x000 read-write 0x87E1 0xFFFFFFFF WORDWIDTH Selects the number of bytes in data as follows: [1:0] ENUM 8_BIT_DATA 8-bit data 0x0 16_BIT_DATA 16-bit data 0x1 RESERVED Reserved, do not use this setting 0x2 32_BIT_DATA 32-bit data 0x3 MONO When 1, data is of monaural format. When 0, the data is in stereo format. [2:2] STOP When 1, disables accesses on FIFOs, places the transmit channel in mute mode. [3:3] RESET When 1, asynchronously resets the transmit channel and FIFO. [4:4] WS_SEL When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE. [5:5] WS_HALFPERIOD Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. [14:6] MUTE When 1, the transmit channel sends only zeroes. [15:15] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] DAI I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. 0x004 read-write 0x07E1 0xFFFFFFFF WORDWIDTH Selects the number of bytes in data as follows: [1:0] ENUM 8_BIT_DATA 8-bit data 0x0 16_BIT_DATA 16-bit data 0x1 RESERVED Reserved, do not use this setting 0x2 32_BIT_DATA 32-bit data 0x3 MONO When 1, data is of monaural format. When 0, the data is in stereo format. [2:2] STOP When 1, disables accesses on FIFOs, places the transmit channel in mute mode. [3:3] RESET When 1, asynchronously reset the transmit channel and FIFO. [4:4] WS_SEL When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE. [5:5] WS_HALFPERIOD Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. [14:6] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:15] TXFIFO I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. 0x008 write-only 0 0xFFFFFFFF I2STXFIFO 8 x 32-bit transmit FIFO. [31:0] RXFIFO I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. 0x00C read-only 0 0xFFFFFFFF modify I2SRXFIFO 8 x 32-bit transmit FIFO. [31:0] STATE I2S Status Feedback Register. Contains status information about the I2S interface. 0x010 read-only 0x7 0xFFFFFFFF IRQ This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register. [0:0] DMAREQ1 This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register. [1:1] DMAREQ2 This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register. [2:2] RESERVED Reserved. [7:3] RX_LEVEL Reflects the current level of the Receive FIFO. [11:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:12] TX_LEVEL Reflects the current level of the Transmit FIFO. [19:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:20] DMA1 I2S DMA Configuration Register 1. Contains control information for DMA request 1. 0x014 read-write 0 0xFFFFFFFF RX_DMA1_ENABLE When 1, enables DMA1 for I2S receive. [0:0] TX_DMA1_ENABLE When 1, enables DMA1 for I2S transmit. [1:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:2] RX_DEPTH_DMA1 Set the FIFO level that triggers a receive DMA request on DMA1. [11:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:12] TX_DEPTH_DMA1 Set the FIFO level that triggers a transmit DMA request on DMA1. [19:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:20] DMA2 I2S DMA Configuration Register 2. Contains control information for DMA request 2. 0x018 read-write 0 0xFFFFFFFF RX_DMA2_ENABLE When 1, enables DMA1 for I2S receive. [0:0] TX_DMA2_ENABLE When 1, enables DMA1 for I2S transmit. [1:1] RESERVED Reserved. [7:2] RX_DEPTH_DMA2 Set the FIFO level that triggers a receive DMA request on DMA2. [11:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:12] TX_DEPTH_DMA2 Set the FIFO level that triggers a transmit DMA request on DMA2. [19:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:20] IRQ I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. 0x01C read-write 0 0xFFFFFFFF RX_IRQ_ENABLE When 1, enables I2S receive interrupt. [0:0] TX_IRQ_ENABLE When 1, enables I2S transmit interrupt. [1:1] RESERVED Reserved. [7:2] RX_DEPTH_IRQ Set the FIFO level on which to create an irq request. [11:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [15:12] TX_DEPTH_IRQ Set the FIFO level on which to create an irq request. [19:16] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:20] TXRATE I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. 0x020 read-write 0 0xFFFFFFFF Y_DIVIDER I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. [7:0] X_DIVIDER I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. [15:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] RXRATE I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. 0x024 read-write 0 0xFFFFFFFF Y_DIVIDER I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock. [7:0] X_DIVIDER I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2. [15:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] TXBITRATE I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. 0x028 read-write 0 0xFFFFFFFF TX_BITRATE I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock. [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] RXBITRATE I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. 0x02C read-write 0 0xFFFFFFFF RX_BITRATE I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock. [5:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:6] TXMODE I2S Transmit mode control. 0x030 read-write 0 0xFFFFFFFF TXCLKSEL Clock source selection for the transmit bit clock divider. [1:0] ENUM SELECT_THE_TX_FRACTI Select the TX fractional rate divider clock output as the source 0x0 RESERVED Reserved 0x1 SELECT_THE_RX_MCLK_S Select the RX_MCLK signal as the TX_MCLK clock source 0x2 RESERVED Reserved 0x3 TX4PIN Transmit 4-pin mode selection. When 1, enables 4-pin mode. [2:2] TXMCENA Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] RXMODE I2S Receive mode control. 0x034 read-write 0 0xFFFFFFFF RXCLKSEL Clock source selection for the receive bit clock divider. [1:0] ENUM SELECT_THE_RX_FRACTI Select the RX fractional rate divider clock output as the source 0x0 RESERVED Reserved 0x1 SELECT_THE_TX_MCLK_S Select the TX_MCLK signal as the RX_MCLK clock source 0x2 RESERVED Reserved 0x3 RX4PIN Receive 4-pin mode selection. When 1, enables 4-pin mode. [2:2] RXMCENA Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled. [3:3] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] I2S1 0x400A3000 I2S1 29 C_CAN1 C_CAN C_CAN1 0x400A4000 0 0xFFF registers C_CAN1 43 CNTL CAN control 0x000 read-write 0x0001 0xFFFFFFFF INIT Initialization [0:0] ENUM INITIALIZATION_IS_ST Initialization is started. On reset, software needs to initialize the CAN controller. 1 NORMAL_OPERATION_ Normal operation. 0 IE Module interrupt enable [1:1] ENUM ENABLE_CAN_INTERRUPT Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared. 1 DISABLE_CAN_INTERRUP Disable CAN interrupts. The interrupt line is always HIGH. 0 SIE Status change interrupt enable [2:2] ENUM ENABLE_STATUS_CHANGE Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. 1 DISABLE_STATUS_CHANG Disable status change interrupts. No status change interrupt will be generated. 0 EIE Error interrupt enable [3:3] ENUM ENABLE_ERROR_INTERRU Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt. 1 DISABLE_ERROR_INTERR Disable error interrupt. No error status interrupt will be generated. 0 RESERVED reserved [4:4] DAR Disable automatic retransmission [5:5] ENUM DISABLED Automatic retransmission disabled. 1 ENABLED Automatic retransmission of disturbed messages enabled. 0 CCE Configuration change enable [6:6] ENUM THE_CPU_HAS_WRITE_AC The CPU has write access to the CANBT register while the INIT bit is one. 1 THE_CPU_HAS_NO_WRITE The CPU has no write access to the bit timing register. 0 TEST Test mode enable [7:7] ENUM TEST_MODE_ Test mode. 1 NORMAL_OPERATION_ Normal operation. 0 RESERVED reserved [31:8] STAT Status register 0x004 read-write 0x0000 0xFFFFFFFF LEC Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates. [2:0] ENUM NO_ERROR_ No error. 0x0 STUFF_ERROR_MORE_TH Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x1 FORM_ERROR_A_FIXED_ Form error: A fixed format part of a received frame has the wrong format. 0x2 ACKERROR_THE_MESSAG AckError: The message this CAN core transmitted was not acknowledged. 0x3 BIT1ERROR_DURING_TH Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant. 0x4 BIT0ERROR_DURING_TH Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed). 0x5 CRCERROR_THE_CRC_CH CRCError: The CRC checksum was incorrect in the message received. 0x6 UNUSED_NO_CAN_BUS_E Unused: No CAN bus event was detected (written by the CPU). 0x7 TXOK Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller. [3:3] ENUM MSGTRANSFER Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node). 1 NOMSGTRANSFER Since this bit was reset by the CPU, no message has been successfully transmitted. 0 RXOK Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller. [4:4] ENUM MSGTRANSFER Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering. 1 NOMSGTRANSFER Since this bit was last reset by the CPU, no message has been successfully transmitted. 0 EPASS Error passive [5:5] ENUM PASSIVE The CAN controller is in the error passive state as defined in the CAN 2.0 specification. 1 ACTIVE The CAN controller is in the error active state. 0 EWARN Warning status [6:6] ENUM AT_LEAST_ONE_OF_THE_ At least one of the error counters in the EML has reached the error warning limit of 96. 1 BOTH_ERROR_COUNTERS_ Both error counters are below the error warning limit of 96. 0 BOFF Busoff status [7:7] ENUM BUSOFF The CAN controller is in busoff state. 1 NOBUSOFF The CAN module is not in busoff. 0 RESERVED reserved [31:8] EC Error counter 0x008 read-only 0x0000 0xFFFFFFFF TEC_7_0 Transmit error counter Current value of the transmit error counter (maximum value 127) [7:0] REC_6_0 Receive error counter Current value of the receive error counter (maximum value 255). [14:8] RP Receive error passive [15:15] ENUM PASSIVE The receive counter has reached the error passive level as defined in the CAN2.0 specification. 1 BELOWPASSIVE The receive counter is below the error passive level. 0 RESERVED Reserved [31:16] BT Bit timing register 0x00C read-write 0x2301 0xFFFFFFFF BRP Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1]. Valid programmed values are 0x01 - 0x3F[1]. [5:0] SJW (Re)synchronization jump width Valid programmed values are 0 to 3[1]. [7:6] TSEG1 Time segment after the sample point Valid values are 0 to 7[1]. [11:8] TSEG2 Time segment before the sample point Valid values are 1 to 15[1]. [14:12] RESERVED Reserved [31:15] INT Interrupt register 0x010 read-only 0x0000 0xFFFFFFFF INTID15_0 0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused [15:0] RESERVED Reserved [31:16] TEST Test register 0x014 read-write 0 0x00000000 RESERVED tbd. [1:0] BASIC Basic mode [2:2] ENUM IF1_TX_if2_rx IF1 registers used as TX buffer, IF2 registers used as RX buffer. 1 BASIC_MODE_DISABLED_ Basic mode disabled. 0 SILENT Silent mode [3:3] ENUM SILENT The module is in silent mode. 1 NORMAL_OPERATION_ Normal operation. 0 LBACK Loop back mode [4:4] ENUM ENABLED Loop back mode is enabled. 1 DISABLED Loop back mode is disabled. 0 TX1_0 Control of TD pins [6:5] ENUM LEVEL_AT_THE_TD_PIN_ Level at the TD pin is controlled by the CAN controller. This is the value at reset. 0x0 THE_SAMPLE_POINT_CAN The sample point can be monitored at the TD pin. 0x1 TD_PIN_IS_DRIVEN_LOW TD pin is driven LOW/dominant. 0x2 TD_PIN_IS_DRIVEN_HIG TD pin is driven HIGH/recessive. 0x3 RX Monitors the actual value of the RD Pin [7:7] ENUM THE_CAN_BUS_IS_RECES The CAN bus is recessive (RD = 1). 1 THE_CAN_BUS_IS_DOMIN The CAN bus is dominant (RD = 0). 0 RESERVED Reserved [31:8] BRPE Baud rate prescaler extension register 0x018 read-write 0x0000 0xFFFFFFFF BRPE Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F [3:0] RESERVED Reserved [31:4] 2 0x60 1-2 IF%s_CMDREQ Message interface command request 0x020 read-write 0x0001 0xFFFFFFFF MESSNUM Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1] [5:0] RESERVED Reserved [14:6] BUSY BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished. [15:15] RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_CMDMSK_W Message interface command mask (write direction) 0x024 read-write 0x0000 0xFFFFFFFF DATA_B Access data bytes 4-7 [0:0] ENUM TRANSFER_DATA_BYTES_ Transfer data bytes 4-7 to message object. 1 DATA_BYTES_4_7_UNCHA data bytes 4-7 unchanged. 0 DATA_A Access data bytes 0-3 [1:1] ENUM TRANSFER_DATA_BYTES_ Transfer data bytes 0-3 to message object. 1 DATA_BYTES_0_3_UNCHA data bytes 0-3 unchanged. 0 TXRQST Access transmission request bit [2:2] ENUM REQUEST_A_TRANSMISSI Request a transmission. Set the TXRQST bit IF1/2_MCTRL. 1 NO_TRANSMISSION_REQU No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored. 0 CLRINTPND This bit is ignored in the write direction. [3:3] CTRL Access control bits [4:4] ENUM TRANSFER_CONTROL_BIT Transfer control bits to message object 1 CONTROL_BITS_UNCHANG Control bits unchanged. 0 ARB Access arbitration bits [5:5] ENUM TRANSFER_IDENTIFIER Transfer Identifier, DIR, XTD, and MSGVAL bits to message object. 1 ARBITRATION_BITS_UNC Arbitration bits unchanged. 0 MASK Access mask bits [6:6] ENUM TRANSFER_IDENTIFIER_ Transfer Identifier MASK + MDIR + MXTD to message object. 1 MASK_BITS_UNCHANGED_ Mask bits unchanged. 0 WR_RD Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ. [7:7] RESERVED reserved [31:8] 2 0x60 1-2 IF%s_CMDMSK_R Message interface command mask (read direction) IF%s_CMDMSK_W 0x024 read-write 0x0000 0xFFFFFFFF DATA_B Access data bytes 4-7 [0:0] ENUM TRANSFER_DATA_BYTES_ Transfer data bytes 4-7 to IFx message buffer register. 1 DATA_BYTES_4_7_UNCHA data bytes 4-7 unchanged. 0 DATA_A Access data bytes 0-3 [1:1] ENUM TRANSFER_DATA_BYTES_ Transfer data bytes 0-3 to IFx message buffer. 1 DATA_BYTES_0_3_UNCHA data bytes 0-3 unchanged. 0 NEWDAT Access new data bit [2:2] ENUM CLEAR_NEWDAT_BIT_IN_ Clear NEWDAT bit in the message object. 1 NEWDAT_BIT_REMAINS_U NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits. 0 CLRINTPND Clear interrupt pending bit. [3:3] ENUM CLEAR_INTPND_BIT_IN_ Clear INTPND bit in the message object. 1 INTPND_BIT_REMAINS_U INTPND bit remains unchanged. 0 CTRL Access control bits [4:4] ENUM TRANSFER_CONTROL_BIT Transfer control bits to IFx message buffer. 1 CONTROL_BITS_UNCHANG Control bits unchanged. 0 ARB Access arbitration bits [5:5] ENUM TRANSFER_IDENTIFIER Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register. 1 ARBITRATION_BITS_UNC Arbitration bits unchanged. 0 MASK Access mask bits [6:6] ENUM TRANSFER_IDENTIFIER_ Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register. 1 MASK_BITS_UNCHANGED_ Mask bits unchanged. 0 WR_RD Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ. [7:7] RESERVED reserved [31:8] 2 0x60 1-2 IF%s_MSK1 Message interface mask 1 0x028 read-write 0xFFFF 0xFFFFFFFF MSK15_0 Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering. [15:0] RESERVED reserved [31:16] 2 0x60 1-2 IF%s_MSK2 Message interface 1 mask 2 0x02C read-write 0xFFFF 0xFFFFFFFF MSK28_16 Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering. [12:0] RESERVED Reserved [13:13] MDIR Mask message direction [14:14] ENUM THE_MESSAGE_DIRECTIO The message direction bit (DIR) is used for acceptance filtering. 1 THE_MESSAGE_DIRECTIO The message direction bit (DIR) has no effect on acceptance filtering. 0 MXTD Mask extend identifier [15:15] ENUM THE_EXTENDED_IDENTIF The extended identifier bit (IDE) is used for acceptance filtering. 1 THE_EXTENDED_IDENTIF The extended identifier bit (IDE) has no effect on acceptance filtering. 0 RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_ARB1 Message interface 1 arbitration 1 0x030 read-write 0x0000 0xFFFFFFFF ID15_0 Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame) [15:0] RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_ARB2 Message interface 1 arbitration 2 0x034 read-write 0x0000 0xFFFFFFFF ID28_16 Message identifier 29-bit identifier (extended frame) 11-bit identifier (standard frame) [12:0] DIR Message direction [13:13] ENUM DIRECTION_EQ_TRANSMIT Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one). 1 DIRECTION_EQ_RECEIVE_ Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object. 0 XTD Extend identifier [14:14] ENUM THE_29_BIT_EXTENDED_ The 29-bit extended identifier will be used for this message object. 1 THE_11_BIT_STANDARD_ The 11-bit standard identifier will be used for this message object. 0 MSGVAL Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required. [15:15] ENUM THE_MESSAGE_OBJECT_I The message object is configured and should be considered by the message handler. 1 THE_MESSAGE_OBJECT_I The message object is ignored by the message handler. 0 RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_MCTRL Message interface 1 message control 0x038 read-write 0x0000 0xFFFFFFFF DLC3_0 Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes. [3:0] RESERVED reserved [6:4] EOB End of buffer [7:7] ENUM SINGLE_MESSAGE_OBJEC Single message object or last message object of a FIFO buffer. 1 MESSAGE_OBJECT_BELON Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer. 0 TXRQST Transmit request [8:8] ENUM REQUEST The transmission of this message object is requested and is not yet done 1 WAIT This message object is not waiting for transmission. 0 RMTEN Remote enable [9:9] ENUM TXRQSTSET At the reception of a remote frame, TXRQST is set. 1 UNCHANGED At the reception of a remote frame, TXRQST is left unchanged. 0 RXIE Receive interrupt enable [10:10] ENUM INTPNDSET INTPND will be set after successful reception of a frame. 1 UNCHANGED INTPND will be left unchanged after successful reception of a frame. 0 TXIE Transmit interrupt enable [11:11] ENUM INTPNDSET INTPND will be set after a successful reception of a frame. 1 UNCHANGED The INTPND bit will be left unchanged after a successful reception of a frame. 0 UMASK Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1. [12:12] ENUM USE_MASK Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering. 1 MASK_IGNORED_ Mask ignored. 0 INTPND Interrupt pending [13:13] ENUM INTSOURCE This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority. 1 NOINTSOURCE This message object is not the source of an interrupt. 0 MSGLST Message lost (only valid for message objects in the direction receive). [14:14] ENUM THE_MESSAGE_HANDLER_ The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message. 1 NO_MESSAGE_LOST_SINC No message lost since this bit was reset last by the CPU. 0 NEWDAT New data [15:15] ENUM THE_MESSAGE_HANDLER_ The message handler or the CPU has written new data into the data portion of this message object. 1 NO_NEW_DATA_HAS_BEEN No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU. 0 RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_DA1 Message interface data A1 0x03C read-write 0x0000 0xFFFFFFFF DATA0 Data byte 0 [7:0] DATA1 Data byte 1 [15:8] RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_DA2 Message interface 1 data A2 0x040 read-write 0x0000 0xFFFFFFFF DATA2 Data byte 2 [7:0] DATA3 Data byte 3 [15:8] RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_DB1 Message interface 1 data B1 0x044 read-write 0x0000 0xFFFFFFFF DATA4 Data byte 4 [7:0] DATA5 Data byte 5 [15:8] RESERVED Reserved [31:16] 2 0x60 1-2 IF%s_DB2 Message interface 1 data B2 0x048 read-write 0x0000 0xFFFFFFFF DATA6 Data byte 6 [7:0] DATA7 Data byte 7 [15:8] RESERVED Reserved [31:16] TXREQ1 Transmission request 1 0x100 read-only 0x0000 0xFFFFFFFF TXRQST16_1 Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. [15:0] RESERVED Reserved [31:16] TXREQ2 Transmission request 2 0x104 read-only 0x0000 0xFFFFFFFF TXRQST32_17 Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done. [15:0] RESERVED Reserved [31:16] ND1 New data 1 0x120 read-only 0x0000 0xFFFFFFFF NEWDAT16_1 New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object. [15:0] RESERVED Reserved [31:16] ND2 New data 2 0x124 read-only 0x0000 0xFFFFFFFF NEWDAT32_17 New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object. [15:0] RESERVED Reserved [31:16] IR1 Interrupt pending 1 0x140 read-only 0x0000 0xFFFFFFFF INTPND16_1 Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt. [15:0] RESERVED Reserved [31:16] IR2 Interrupt pending 2 0x144 read-only 0x0000 0xFFFFFFFF INTPND32_17 Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt. [15:0] RESERVED Reserved [31:16] MSGV1 Message valid 1 0x160 read-only 0x0000 0xFFFFFFFF MSGVAL16_1 Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. [15:0] RESERVED Reserved [31:16] MSGV2 Message valid 2 0x164 read-only 0x0000 0xFFFFFFFF MSGVAL32_17 Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler. [15:0] RESERVED Reserved [31:16] CLKDIV CAN clock divider register 0x180 read-write 0x0001 0xFFFFFFFF CLKDIVVAL Clock divider value CAN_CLK = PCLK/(CLKDIVVAL +1) 0000: CAN_CLK = PCLK divided by 1. 0001: CAN_CLK = PCLK divided by 2. 0010: CAN_CLK = PCLK divided by 3. 0011: CAN_CLK = PCLK divided by 4. 0100: CAN_CLK = PCLK divided by 5. ... 1111: CAN_CLK = PCLK divided by 16. [3:0] RESERVED reserved [31:4] RITIMER Repetitive Interrupt Timer (RIT) RITIMER 0x400C0000 0 0xFFF registers RITIMER 11 COMPVAL Compare register 0x000 read-write 0xFFFFFFFF 0xFFFFFFFF RICOMP Compare register. Holds the compare value which is compared to the counter. [31:0] MASK Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. 0x004 read-write 0 0xFFFFFFFF RIMASK Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true). [31:0] CTRL Control register. 0x008 read-write 0xC 0xFFFFFFFF RITINT Interrupt flag [0:0] ENUM THIS_BIT_IS_SET_TO_1 This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect. 1 THE_COUNTER_VALUE_DO The counter value does not equal the masked compare value. 0 RITENCLR Timer enable clear [1:1] ENUM THE_TIMER_WILL_BE_CL The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag. 1 THE_TIMER_WILL_NOT_B The timer will not be cleared to 0. 0 RITENBR Timer enable for debug [2:2] ENUM THE_TIMER_IS_HALTED_ The timer is halted when the processor is halted for debugging. 1 DEBUG_HAS_NO_EFFECT_ Debug has no effect on the timer operation. 0 RITEN Timer enable. [3:3] ENUM TIMER_ENABLED_THIS_ Timer enabled. This can be overruled by a debug halt if enabled in bit 2. 1 TIMER_DISABLED_ Timer disabled. 0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] COUNTER 32-bit counter 0x00C read-write 0 0xFFFFFFFF RICOUNTER 32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software. [31:0] QEI Quadrature Encoder Interface (QEI) QEI 0x400C6000 0 0xFFF registers QEI 52 CON Control register 0x000 write-only 0 0xFFFFFFFF RESP Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared. [0:0] RESPI Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared. [1:1] RESV Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared. [2:2] RESI Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared. [3:3] RESERVED reserved [31:4] CONF Configuration register 0x008 read-write 0x000F0000 0xFFFFFFFF DIRINV Direction invert. When = 1, complements the DIR bit. [0:0] SIGMODE Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal. [1:1] CAPMODE Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range. [2:2] INVINX Invert Index. When set, inverts the sense of the index input. [3:3] CRESPI Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared. [4:4] RESERVED Reserved [15:5] INXGATE Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block. [19:16] RESERVED reserved [31:20] STAT Encoder status register 0x004 read-only 0 0xFFFFFFFF DIR Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 516. [0:0] RESERVED reserved [31:1] POS Position register 0x00C read-only 0 0xFFFFFFFF POS Current position value. [31:0] MAXPOS Maximum position register 0x010 read-write 0 0xFFFFFFFF MAXPOS Maximum position value. [31:0] CMPOS0 position compare register 0 0x014 read-write 0xFFFFFFFF 0xFFFFFFFF PCMP0 Position compare value 0. [31:0] CMPOS1 position compare register 1 0x018 read-write 0xFFFFFFFF 0xFFFFFFFF PCMP1 Position compare value 1. [31:0] CMPOS2 position compare register 2 0x01C read-write 0xFFFFFFFF 0xFFFFFFFF PCMP2 Position compare value 2. [31:0] INXCNT Index count register 0x020 read-only 0 0xFFFFFFFF ENCPOS Current encoder position value. [31:0] INXCMP0 Index compare register 0 0x024 read-write 0xFFFFFFFF 0xFFFFFFFF ICMP0 Index compare value. [31:0] LOAD Velocity timer reload register 0x028 read-write 0xFFFFFFFF 0xFFFFFFFF VELLOAD Current velocity timer load value. [31:0] TIME Velocity timer register 0x02C read-only 0xFFFFFFFF 0xFFFFFFFF VELVAL Current velocity timer value. [31:0] VEL Velocity counter register 0x030 read-only 0 0xFFFFFFFF VELPC Current velocity pulse count. [31:0] CAP Velocity capture register 0x034 read-only 0xFFFFFFFF 0xFFFFFFFF VELCAP Velocity capture value. [31:0] VELCOMP Velocity compare register 0x038 read-write 0 0xFFFFFFFF VELCMP Velocity compare value. [31:0] FILTERPHA Digital filter register on input phase A (QEI_A) 0x03C read-write 0 0xFFFFFFFF FILTA Digital filter sampling delay [31:0] FILTERPHB Digital filter register on input phase B (QEI_B) 0x040 read-write 0 0xFFFFFFFF FILTB Digital filter sampling delay [31:0] FILTERINX Digital filter register on input index (QEI_IDX) 0x044 read-write 0 0xFFFFFFFF FITLINX Digital filter sampling delay [31:0] WINDOW Index acceptance window register 0x048 read-write 0x00000000 0xFFFFFFFF WINDOW Index acceptance window width [31:0] INXCMP1 Index compare register 1 0x04C read-write 0xFFFFFFFF 0xFFFFFFFF ICMP1 Index compare value 1. [31:0] INXCMP2 Index compare register 2 0x050 read-write 0xFFFFFFFF 0xFFFFFFFF ICMP2 Index compare value 2. [31:0] IEC Interrupt enable clear register 0xFD8 write-only 0 0xFFFFFFFF INX_EN Indicates that an index pulse was detected. [0:0] TIM_EN Indicates that a velocity timer overflow occurred [1:1] VELC_EN Indicates that captured velocity is less than compare velocity. [2:2] DIR_EN Indicates that a change of direction was detected. [3:3] ERR_EN Indicates that an encoder phase error was detected. [4:4] ENCLK_EN Indicates that and encoder clock pulse was detected. [5:5] POS0_Int Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_Int Indicates that the position 1compare value is equal to the current position. [7:7] POS2_Int Indicates that the position 2 compare value is equal to the current position. [8:8] REV_Int Indicates that the index compare value is equal to the current index count. [9:9] POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. [10:10] POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. [11:11] POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set. [12:12] REV1_Int Indicates that the index 1 compare value is equal to the current index count. [13:13] REV2_Int Indicates that the index 2 compare value is equal to the current index count. [14:14] MAXPOS_Int Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. [15:15] RESERVED Reserved [31:16] IES Interrupt enable set register 0xFDC write-only 0 0xFFFFFFFF INX_EN Indicates that an index pulse was detected. [0:0] TIM_EN Indicates that a velocity timer overflow occurred [1:1] VELC_EN Indicates that captured velocity is less than compare velocity. [2:2] DIR_EN Indicates that a change of direction was detected. [3:3] ERR_EN Indicates that an encoder phase error was detected. [4:4] ENCLK_EN Indicates that and encoder clock pulse was detected. [5:5] POS0_Int Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_Int Indicates that the position 1compare value is equal to the current position. [7:7] POS2_Int Indicates that the position 2 compare value is equal to the current position. [8:8] REV_Int Indicates that the index compare value is equal to the current index count. [9:9] POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. [10:10] POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. [11:11] POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set. [12:12] REV1_Int Indicates that the index 1 compare value is equal to the current index count. [13:13] REV2_Int Indicates that the index 2 compare value is equal to the current index count. [14:14] MAXPOS_Int Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. [15:15] RESERVED Reserved [31:16] INTSTAT Interrupt status register 0xFE0 read-only 0 0xFFFFFFFF INX_Int Indicates that an index pulse was detected. [0:0] TIM_Int Indicates that a velocity timer overflow occurred [1:1] VELC_Int Indicates that captured velocity is less than compare velocity. [2:2] DIR_Int Indicates that a change of direction was detected. [3:3] ERR_Int Indicates that an encoder phase error was detected. [4:4] ENCLK_Int Indicates that and encoder clock pulse was detected. [5:5] POS0_Int Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_Int Indicates that the position 1compare value is equal to the current position. [7:7] POS2_Int Indicates that the position 2 compare value is equal to the current position. [8:8] REV_Int Indicates that the index compare value is equal to the current index count. [9:9] POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. [10:10] POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. [11:11] POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set. [12:12] REV1_Int Indicates that the index 1 compare value is equal to the current index count. [13:13] REV2_Int Indicates that the index 2 compare value is equal to the current index count. [14:14] MAXPOS_Int Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. [15:15] RESERVED Reserved [31:16] IE Interrupt enable register 0xFE4 read-only 0 0xFFFFFFFF INX_Int Indicates that an index pulse was detected. [0:0] TIM_Int Indicates that a velocity timer overflow occurred [1:1] VELC_Int Indicates that captured velocity is less than compare velocity. [2:2] DIR_Int Indicates that a change of direction was detected. [3:3] ERR_Int Indicates that an encoder phase error was detected. [4:4] ENCLK_Int Indicates that and encoder clock pulse was detected. [5:5] POS0_Int Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_Int Indicates that the position 1compare value is equal to the current position. [7:7] POS2_Int Indicates that the position 2 compare value is equal to the current position. [8:8] REV_Int Indicates that the index compare value is equal to the current index count. [9:9] POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. [10:10] POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. [11:11] POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set. [12:12] REV1_Int Indicates that the index 1 compare value is equal to the current index count. [13:13] REV2_Int Indicates that the index 2 compare value is equal to the current index count. [14:14] MAXPOS_Int Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. [15:15] RESERVED Reserved [31:16] CLR Interrupt status clear register 0xFE8 write-only 0 0xFFFFFFFF INX_Int Indicates that an index pulse was detected. [0:0] TIM_Int Indicates that a velocity timer overflow occurred [1:1] VELC_Int Indicates that captured velocity is less than compare velocity. [2:2] DIR_Int Indicates that a change of direction was detected. [3:3] ERR_Int Indicates that an encoder phase error was detected. [4:4] ENCLK_Int Indicates that and encoder clock pulse was detected. [5:5] POS0_Int Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_Int Indicates that the position 1compare value is equal to the current position. [7:7] POS2_Int Indicates that the position 2 compare value is equal to the current position. [8:8] REV_Int Indicates that the index compare value is equal to the current index count. [9:9] POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. [10:10] POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. [11:11] REV1_Int Indicates that the index 1 compare value is equal to the current index count. [13:13] REV2_Int Indicates that the index 2 compare value is equal to the current index count. [14:14] MAXPOS_Int Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. [15:15] RESERVED Reserved [31:16] SET Interrupt status set register 0xFEC write-only 0 0xFFFFFFFF INX_Int Indicates that an index pulse was detected. [0:0] TIM_Int Indicates that a velocity timer overflow occurred [1:1] VELC_Int Indicates that captured velocity is less than compare velocity. [2:2] DIR_Int Indicates that a change of direction was detected. [3:3] ERR_Int Indicates that an encoder phase error was detected. [4:4] ENCLK_Int Indicates that and encoder clock pulse was detected. [5:5] POS0_Int Indicates that the position 0 compare value is equal to the current position. [6:6] POS1_Int Indicates that the position 1compare value is equal to the current position. [7:7] POS2_Int Indicates that the position 2 compare value is equal to the current position. [8:8] REV_Int Indicates that the index compare value is equal to the current index count. [9:9] POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set. [10:10] POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set. [11:11] POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set. [12:12] REV1_Int Indicates that the index 1 compare value is equal to the current index count. [13:13] REV2_Int Indicates that the index 2 compare value is equal to the current index count. [14:14] MAXPOS_Int Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction. [15:15] RESERVED Reserved [31:16] GIMA Global Input Multiplexer Array (GIMA) GIMA 0x400C7000 0x0 0xFFF registers CAP0_0_IN Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) 0x000 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTIN_0 CTIN_0 0x0 SGPIO3 SGPIO3 0x1 T0_CAP0 T0_CAP0 0x2 RESERVED Reserved [31:8] CAP0_1_IN Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) 0x004 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTIN_1 CTIN_1 0x0 USART2_TX_ACTIVE USART2 TX active 0x1 T0_CAP1 T0_CAP1 0x2 RESERVED Reserved [31:8] CAP0_2_IN Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) 0x008 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTIN_2 CTIN_2 0x0 SGPIO3_DIV SGPIO3_DIV 0x1 T0_CAP2 T0_CAP2 0x2 RESERVED Reserved [31:8] CAP0_3_IN Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) 0x00C read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTOUT_15_OR_T3_MAT3 CTOUT_15 or T3_MAT3 0x0 T0_CAP3 T0_CAP3 0x1 T3_MAT3 T3_MAT3 0x2 RESERVED Reserved [31:8] CAP1_0_IN Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) 0x010 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTIN_0 CTIN_0 0x0 SGPIO12 SGPIO12 0x1 T1_CAP0 T1_CAP0 0x2 RESERVED Reserved [31:8] CAP1_1_IN Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) 0x014 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTIN_3 CTIN_3 0x0 USART0_TX_ACTIVE USART0 TX active 0x1 T1_CAP1 T1_CAP1 0x2 RESERVED Reserved [31:8] CAP1_2_IN Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) 0x018 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTIN_4 CTIN_4 0x0 USART0_RX_ACTIVE USART0 RX active 0x1 T1_CAP2 T1_CAP2 0x2 RESERVED Reserved [31:8] CAP1_3_IN Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) 0x01C read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTOUT_3_OR_T0_MAT3 CTOUT_3 or T0_MAT3 0x0 T1_CAP3 T1_CAP3 0x1 T0_MAT3 T0_MAT3 0x2 RESERVED Reserved [31:8] CAP2_0_IN Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) 0x020 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x4 to 0xF are reserved. [7:4] ENUM CTIN_0 CTIN_0 0x0 SGPIO12_DIV SGPIO12_DIV 0x1 T2_CAP0 T2_CAP0 0x2 RESERVED Reserved [31:8] CAP2_1_IN Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) 0x024 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x4 to 0xF are reserved. [7:4] ENUM CTIN_1 CTIN_1 0x0 USART2_TX_ACTIVE USART2 TX active 0x1 _I2S1_RX_MWS - I2S1_RX_MWS 0x2 T2_CAP1 T2_CAP1 0x3 RESERVED Reserved [31:8] CAP2_2_IN Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) 0x028 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x4 to 0xF are reserved. [7:4] ENUM CTIN_5 CTIN_5 0x0 USART2_RX_ACTIVE USART2 RX active 0x1 _I2S1_TX_MWS - I2S1_TX_MWS 0x2 T2_CAP2 T2_CAP2 0x3 RESERVED Reserved [31:8] CAP2_3_IN Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) 0x02C read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTOUT_7_OR_T1_MAT3 CTOUT_7 or T1_MAT3 0x0 T2_CAP3 T2_CAP3 0x1 T1_MAT3 T1_MAT3 0x2 RESERVED Reserved [31:8] CAP3_0_IN Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) 0x030 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTIN_0 CTIN_0 0x0 I2S0_RX_MWS I2S0_RX_MWS 0x1 T3_CAP0 T3_CAP0 0x2 RESERVED Reserved [31:8] CAP3_1_IN Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) 0x034 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x4 to 0xF are reserved. [7:4] ENUM CTIN_6 CTIN_6 0x0 USART3_TX_ACTIVE USART3 TX active 0x1 TBD__I2S0_TX_MWS TBD - I2S0_TX_MWS 0x2 T3_CAP1 T3_CAP1 0x3 RESERVED Reserved [31:8] CAP3_2_IN Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) 0x038 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x4 to 0xF are reserved. [7:4] ENUM CTIN_7 CTIN_7 0x0 USART3_RX_ACTIVE USART3 RX active 0x1 SOF0_START_OF_FRAME SOF0 (Start-Of-Frame USB0) 0x2 T3_CAP2 T3_CAP2 0x3 RESERVED Reserved [31:8] CAP3_3_IN Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) 0x03C read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x4 to 0xF are reserved. [7:4] ENUM CTOUT11_OR_T2_MAT3 CTOUT11 or T2_MAT3 0x0 SOF1_START_OF_FRAME SOF1 (Start-Of-Frame USB1) 0x1 T3_CAP3 T3_CAP3 0x2 T2_MAT3 T2_MAT3 0x3 RESERVED Reserved [31:8] CTIN_0_IN SCT CTIN_0 capture input multiplexer (GIMA output 16) 0x040 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTIN_0 CTIN_0 0x0 SGPIO3 SGPIO3 0x1 SGPIO3_DIV SGPIO3_DIV 0x2 RESERVED Reserved [31:8] CTIN_1_IN SCT CTIN_1 capture input multiplexer (GIMA output 17) 0x044 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTIN_1 CTIN_1 0x0 USART2_TX_ACTIVE USART2 TX active 0x1 SGPIO12 SGPIO12 0x2 RESERVED Reserved [31:8] CTIN_2_IN SCT CTIN_2 capture input multiplexer (GIMA output 18) 0x048 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTIN_2 CTIN_2 0x0 SGPIO12 SGPIO12 0x1 SGPIO12_DIV SGPIO12_DIV 0x2 RESERVED Reserved [31:8] CTIN_3_IN SCT CTIN_3 capture input multiplexer (GIMA output 19) 0x04C read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x4 to 0xF are reserved. [7:4] ENUM CTIN_3 CTIN_3 0x0 USART0_TX_ACTIVE USART0 TX active 0x1 RESERVED Reserved 0x2 RESERVED Reserved 0x3 RESERVED Reserved [31:8] CTIN_4_IN SCT CTIN_4 capture input multiplexer (GIMA output 20) 0x050 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x4 to 0xF are reserved. [7:4] ENUM CTIN_4 CTIN_4 0x0 USART0_RX_ACTIVE USART0 RX active 0x1 _I2S1_RX_MWS1 - I2S1_RX_MWS1 0x2 _I2S1_TX_MWS1 - I2S1_TX_MWS1 0x3 RESERVED Reserved [31:8] CTIN_5_IN SCT CTIN_5 capture input multiplexer (GIMA output 21) 0x054 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTIN_5 CTIN_5 0x0 USART2_RX_ACTIVE USART2 RX active 0x1 SGPIO12_DIV SGPIO12_DIV 0x2 RESERVED Reserved [31:8] CTIN_6_IN SCT CTIN_6 capture input multiplexer (GIMA output 22) 0x058 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x4 to 0xF are reserved. [7:4] ENUM CTIN_6 CTIN_6 0x0 USART3_TX_ACTIVE USART3 TX active 0x1 I2S0_RX_MWS I2S0_RX_MWS 0x2 I2S0_TX_MWS I2S0_TX_MWS 0x3 RESERVED Reserved [31:8] CTIN_7_IN SCT CTIN_7 capture input multiplexer (GIMA output 23) 0x05C read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x4 to 0xF are reserved. [7:4] ENUM CTIN_7 CTIN_7 0x0 USART3_RX_ACTIVE USART3 RX active 0x1 SOF0_START_OF_FRAME SOF0 (Start-Of-Frame USB0) 0x2 SOF1_START_OF_FRAME SOF1 (Start-Of-Frame USB1) 0x3 RESERVED Reserved [31:8] ADCHS_TRIGGER_IN ADCHS trigger input multiplexer (GIMA output 24) 0x060 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0xA to 0xF are reserved. [7:4] ENUM GPIO6_28 GPIO6[28] 0x0 GPIO5_3 GPIO5[3] 0x1 SGPIO10 SGPIO10 0x2 SGPIO12 SGPIO12 0x3 RESERVED Reserved 0x4 MCOB2 MCOB2 0x5 CTOUT_0_OR_T0_MAT0 CTOUT_0 or T0_MAT0 0x6 CTOUT_8_OR_T2_MAT0 CTOUT_8 or T2_MAT0 0x7 T0_MAT0 T0_MAT0 0x8 T2_MAT0 T2_MAT0 0x9 RESERVED Reserved [31:8] EVENTROUTER_13_IN Event router input 13 multiplexer (GIMA output 25) 0x064 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTOUT_2_OR_T0_MAT2 CTOUT_2 or T0_MAT2 0x0 SGPIO3 SGPIO3 0x1 T0_MAT2 T0_MAT2 0x2 RESERVED Reserved [31:8] EVENTROUTER_14_IN Event router input 14 multiplexer (GIMA output 26) 0x068 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x3 to 0xF are reserved. [7:4] ENUM CTOUT_6_OR_T1_MAT2 CTOUT_6 or T1_MAT2 0x0 SGPIO12 SGPIO12 0x1 T1_MAT2 T1_MAT2 0x2 RESERVED Reserved [31:8] EVENTROUTER_16_IN Event router input 16 multiplexer (GIMA output 27) 0x06C read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x2 to 0xF are reserved. [7:4] ENUM CTOUT_14_OR_T3_MAT2 CTOUT_14 or T3_MAT2 0x0 T3_MAT2 T3_MAT2 0x1 RESERVED Reserved [31:8] ADCSTART0_IN ADC start0 input multiplexer (GIMA output 28) 0x070 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x2 to 0xF are reserved. [7:4] ENUM CTOUT_15_OR_T3_MAT3 CTOUT_15 or T3_MAT3 0x0 T0_MAT0 T0_MAT0 0x1 RESERVED Reserved [31:8] ADCSTART1_IN ADC start1 input multiplexer (GIMA output 29) 0x074 read-write 0 0xFFFFFFFF INV Invert input [0:0] ENUM NOT_INVERTED Not inverted. 0 INPUT_INVERTED Input inverted. 1 EDGE Enable rising edge detection [1:1] ENUM NO_EDGE_DETECTION No edge detection. 0 RISING_EDGE_DETECTIO Rising edge detection enabled. 1 SYNCH Enable synchronization [2:2] ENUM DISABLE__SYNCHRONIZ Disable synchronization. 0 ENABLE__SYNCHRONIZA Enable synchronization. 1 PULSE Enable single pulse generation. [3:3] ENUM DISABLE_SINGLE_PULSE Disable single pulse generation. 0 ENABLE_SINGLE_PULSE Enable single pulse generation. 1 SELECT Select input. Values 0x2 to 0xF are reserved. [7:4] ENUM CTOUT_8_OR_T2_MAT0 CTOUT_8 or T2_MAT0 0x0 T2_MAT0 T2_MAT0 0x1 RESERVED Reserved [31:8] DAC Digital-to-Analog Converter (DAC) DAC 0x400E1000 0 0xFFF registers DAC 0 CR DAC register. Holds the conversion data. 0x000 read-write 0 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [5:0] VALUE After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA. [15:6] BIAS Settling time [16:16] ENUM SHORT The settling time of the DAC is 1 micros max, and the maximum current is 700 microA. 0 LONG The settling time of the DAC is 2.5 micros and the maximum current is 350 microA. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:17] CTRL DAC control register. 0x004 read-write 0 0xFFFFFFFF INT_DMA_REQ DMA request [0:0] ENUM CLR This bit is cleared on any write to the DACR register. 0 SET This bit is set by hardware when the timer times out. 1 DBLBUF_ENA DMA double-buffering [1:1] ENUM DISABLED DACR double-buffering is disabled. 0 ENABLED When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter. 1 CNT_ENA DMA time-out [2:2] ENUM DISABLED Time-out counter operation is disabled. 0 ENABLED Time-out counter operation is enabled. 1 DMA_ENA DMA enable [3:3] ENUM DISABLED DMA access is disabled. 0 ENABLED DMA Burst Request Input 15 is enabled for the DAC (see Table 136). 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:4] CNTVAL DAC counter value register. 0x008 read-write 0 0xFFFFFFFF VALUE 16-bit reload value for the DAC interrupt/DMA timer. [15:0] RESERVED Reserved. [31:16] C_CAN0 0x400E2000 0 0xFFF registers C_CAN0 51 ADC0 10-bit Analog-to-Digital Converter (ADC) ADC 0x400E3000 0 0xFFF registers ADC0 17 CR A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. 0x000 read-write 0x00000000 0xFFFFFFFF SEL Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01. [7:0] CLKDIV The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. [15:8] BURST Burst mode [16:16] ENUM SOFTWARE Conversions are software controlled and require 11 clocks. 0 BURST The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start. 1 CLKS This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). [19:17] ENUM 11_CLOCKS_10_BITS 11 clocks / 10 bits 0x0 10_CLOCKS_9_BITS 10 clocks / 9 bits 0x1 9_CLOCKS_8_BITS 9 clocks / 8 bits 0x2 8_CLOCKS_7_BITS 8 clocks / 7 bits 0x3 7_CLOCKS_6_BITS 7 clocks / 6 bits 0x4 6_CLOCKS_5_BITS 6 clocks / 5 bits 0x5 5_CLOCKS_4_BITS 5 clocks / 4 bits 0x6 4_CLOCKS_3_BITS 4 clocks / 3 bits 0x7 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [20:20] PDN Power mode [21:21] ENUM POWERDOWN The A/D converter is in Power-down mode. 0 RUNNING The A/D converter is operational. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [23:22] START When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56): [26:24] ENUM NO_START No start (this value should be used when clearing PDN to 0). 0x0 START_CONVERSION_NOW Start conversion now. 0x1 CTOUT_15 Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15). 0x2 CTOUT_8 Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8). 0x3 ADCTRIG0 Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input. 0x4 ADCTRIG1 Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input. 0x5 MCOA2 Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2. 0x6 RESERVED_ Reserved. 0x7 EDGE This bit is significant only when the START field contains 0x2 -0x6. In these cases: [27:27] ENUM RISING Start conversion on a rising edge on the selected signal. 0 FALLING Start conversion on a falling edge on the selected signal. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:28] GDR A/D Global Data Register. Contains the result of the most recent A/D conversion. 0x004 read-only 0 0x00000000 RESERVED Reserved. These bits always read as zeroes. [5:0] V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA. [15:6] RESERVED Reserved. These bits always read as zeroes. [23:16] CHN These bits contain the channel from which the LS bits were converted. [26:24] RESERVED Reserved. These bits always read as zeroes. [29:27] OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits. [30:30] DONE This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started. [31:31] INTEN A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. 0x00C read-write 0x00000100 0xFFFFFFFF ADINTEN These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. [7:0] ADGINTEN When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. [8:8] RESERVED Reserved. Always 0. [31:9] 8 0x04 0-7 DR[%s] A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. 0x010 read-only 0 0xFFFFFFFF RESERVED Reserved. Always 0. [5:0] V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA. [15:6] RESERVED Reserved. Always 0. [29:16] OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register. [30:30] DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. [31:31] STAT A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. 0x030 read-only 0 0xFFFFFFFF DONE These bits mirror the DONE status flags that appear in the result register for each A/D channel. [7:0] OVERUN These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously. [15:8] ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. [16:16] RESERVED Reserved. Always 0. [31:17] ADC1 0x400E4000 ADC1 21 ADCHS 12-bit Analog-to-Digital Converter High-Speed (ADCHS) ADCHS 0x400F0000 0x0 0xFFF registers ADCHS 45 FLUSH Flushes FIFO 0x0000 write-only 0x00000000 0xFFFFFFFF FIFO_FLUSH 1= fifo is cleared [0:0] RESERVED Reserved. [31:1] DMA_REQ Set or clear DMA write request 0x0004 read-write 0x00000001 0xFFFFFFFF DMA_REQ_WR 1 = Dma_req_wr is set (initially used to fill second table), 0 = Dma_req_wr is cleared [0:0] RESERVED Reserved. [31:1] FIFO_STS Indicates FIFO fill level status 0x0008 read-only 0x00000000 0xFFFFFFFF LEVEL 0 = FIFO is empty 1...15 = FIFO is partially full 16 = FIFO is full [4:0] RESERVED Reserved. [31:5] FIFO_CFG Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word. 0x000C read-write 0x00000010 0xFFFFFFFF PACKED_READ 0 = one sample is packed in one 32-bit read cycle 1 = two samples are packed in one 32-bit read cycle [0:0] LEVEL When the FIFO contains more or equal than FIFO_LEVEL samples interrupt flag FIFO_FULL interrupt will be set and DMA_Read_Req will be raised. [5:1] RESERVED Reserved [31:6] TRIGGER Enable software trigger to start descriptor processing 0x0010 write-only 0x00000000 0xFFFFFFFF SW_TRIGGER Auto cleared [0:0] RESERVED Reserved [31:1] DSCR_STS Indicates active descriptor table and descriptor entry 0x0014 read-write 0x00000000 0xFFFFFFFF ACT_TABLE 0 = table 0 is active 1 = table 1 is active. [0:0] ACT_DESCRIPTOR ID of the descriptor that is active. [3:1] RESERVED Reserved [31:4] POWER_DOWN Set or clear power down mode 0x0018 read-write 0x00000001 0xFFFFFFFF PD_CTRL 0 = disable power down mode. Register holds value until set by writing 1 to this bit or by descriptor processor when descriptor field POWER_DOWN is set. 1 = enable power down mode. Register holds value until cleared by writing 0 to this bit or by descriptor processor when waking up RECOVERY_TIME before a conversion. [0:0] RESERVED Reserved [31:1] CONFIG Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down. 0x001C read-write 0x00002400 0xFFFFFFFF TRIGGER__MASK 00 = triggers off 01 = software trigger only 10 = external trigger only 11 = both triggers allowed [1:0] TRIGGER_MODE 00 = rising external trigger 01 = falling external trigger 10 = low external trigger 11 = high external trigger [3:2] TRIGGER_SYNC 0 = do not synchronize external trigger input 1 = synchronize external trigger input [4:4] CHANNEL_ID_EN 0 = do not add channel ID to FIFO output data 1 = add channel ID to FIFO output data [5:5] RECOVERY_TIME ADC recovery time from power down [13:6] RESERVED Reserved [31:14] THR_A Configures window comparator A levels. 0x0020 read-write 0x0FFF0000 0xFFFFFFFF THR_LOW_A Low Compare Threshold Register A: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A. [11:0] THR_HIGH_A High Compare Threshold Register A: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A. [27:16] RESERVED Reserved. [31:28] THR_B Configures window comparator B levels. 0x0024 read-write 0x0FFF0000 0xFFFFFFFF THR_LOW_B Low Compare Threshold Register B: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair A. [11:0] THR_HIGH_B High Compare Threshold Register B: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair A. [27:16] RESERVED Reserved. [31:28] 6 0x4 0-5 LAST_SAMPLE[%s] Contains last converted sample of input M [M=0..5) and result of window comparator. 0x0028 read-only 0x00000000 0xFFFFFFFF DONE This bit is set to 1 when an A/D conversion on this channel completes. This bit is cleared whenever this register is read. [0:0] OVERRUN This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read. This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled. [1:1] THCMP_RANGE Threshold Range Comparison result 00: In Range 01: Below Range 10: Above Range 11: Reserved [3:2] THCMP_CROSS Threshold Crossing Comparison result 00: No Threshold Crossing detected 01: Downward Threshold Crossing detected 10: Upward Threshold Crossing detected 11: Reserved [5:4] SAMPLE 12-Bit value of last converted sample for this channel [17:6] RESERVED Reserved [20:17] RESERVED Reserved [31:21] ADC_SPEED ADC speed control 0x0104 read-write 0x00000000 0xFFFFFFFF DGEC0 Speed0 [3:0] DGEC1 Speed1 [7:4] DGEC2 Speed2 [11:8] DGEC3 Speed3 [15:12] DGEC4 Speed4 [19:16] DGEC5 Speed5 [23:20] RESERVED Reserved [31:24] POWER_CONTROL Configures ADC power vs. speed, DC-in biasing, output format and power gating. 0x0108 read-write 0x00000000 0xFFFFFFFF CRS current setting for power versus speed programming [3:0] DCINNEG AC-DC coupling selection 0 = No dc bias 1 = DC bias on vin_neg side [9:4] DCINPOS AC-DC coupling selection 0 = No dc bias 1 = DC bias on vin_pos side [15:10] TWOS Output data format selection 0 = offset binary 1 = two's complement [16:16] POWER_SWITCH 0 = ADC is powered down 1 = ADC is active [17:17] BGAP_SWITCH 0 = ADC band gap reference is powered down 1 = ADC band gap reference is active [18:18] RESERVED Reserved [31:19] 16 0x4 0-15 FIFO_OUTPUT[%s] FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples 0x0200 read-only 0x00008000 0xFFFFFFFF SAMPLE Value of first converted sample [11:0] CHAN_ID Channel number of first converted sample: 000: channel _0 or CHANNEL_ID_EN =0 001: channel _1 010: channel _2 011: channel _3 100: channel _4 101: channel _5 110: reserved 111: recovery_ error [14:12] EMPTY 0: FIFO not empty 1: FIFO empty [15:15] SAMPLE2 Value of second converted sample. This field is only valid if PACKED_READ is set else it is 0x0 [27:16] CHAN_ID2 Channel number of second converted sample This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0 [30:28] EMPTY2 0: FIFO not empty 1: FIFO empty and PACKED_READ is set [31:31] 8 0x4 0-7 DESCRIPTOR0_[%s] Table 0 descriptor n, n= 0 to 7 0x0300 read-write 0x000090E0 0xFFFFFFFF CHANNEL_NR 0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved [2:0] HALT 0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger. [3:3] INTERRUPT 1: Raise interrupt when ADC result is available [4:4] POWER_DOWN 1: Power down after this conversion. [5:5] BRANCH 00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top). [7:6] MATCH_VALUE Evaluate this descriptor when descriptor timer value is equal to match value. [21:8] THRESHOLD_SEL Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved [23:22] RESET_TIMER 1: reset descriptor timer. [24:24] RESERVED Reserved [30:25] UPDATE_TABLE 1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0. [31:31] 8 0x4 0-7 DESCRIPTOR1_[%s] Table 1 descriptors n, n=0 to 7 0x0320 read-write 0x000090E0 0xFFFFFFFF CHANNEL_NR 0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved [2:0] HALT 0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger. [3:3] INTERRUPT 1: Raise interrupt when ADC result is available [4:4] POWER_DOWN 1: Power down after this conversion. [5:5] BRANCH 00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top). [7:6] MATCH_VALUE Evaluate this descriptor when descriptor timer value is equal to match value. [21:8] THRESHOLD_SEL Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved [23:22] RESET_TIMER 1: reset descriptor timer. [24:24] RESERVED Reserved [30:25] UPDATE_TABLE 1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0. [31:31] CLR_EN0 Interrupt 0 clear mask 0x0F00 write-only 0x00000000 0xFFFFFFFF CEN0 Interrupt clear enable [6:0] RESERVED Reserved [31:7] SET_EN0 Interrupt 0 set mask 0x0F04 write-only 0x00000000 0xFFFFFFFF SEN0 Interrupt set enable [6:0] RESERVED Reserved [31:7] MASK0 Interrupt 0 mask 0x0F08 read-only 0x00000000 0xFFFFFFFF M0 Interrupt enable [6:0] RESERVED Reserved [31:7] STATUS0 Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow 0x0F0C read-only 0x00000000 0xFFFFFFFF FIFO_FULL 0: number of samples in FIFO less than or equal to FIFO_LEVEL 1: number of samples in FIFO is more than FIFO_LEVEL [0:0] FIFO_EMPTY 0: FIFO is not empty 1: FIFO is empty [1:1] FIFO_OVERFLOW FIFO was full; conversion sample is not stored and lost [2:2] DSCR_DONE The descriptor INTERRUPT field was enabled and its sample is converted. [3:3] DSCR_ERROR The ADC was not fully woken up when a sample was converted and the conversion results is unreliable [4:4] ADC_OVF Converted sample value was over range of the 12 bit output code. [5:5] ADC_UNF Converted sample value was under range of the 12 bit output code. [6:6] RESERVED Reserved [31:7] CLR_STAT0 Interrupt 0 clear status 0x0F10 write-only 0x00000000 0xFFFFFFFF CSTAT0 Interrupt clear status [6:0] RESERVED Reserved [31:7] SET_STAT0 Interrupt 0 set status 0x0F14 write-only 0x00000000 0xFFFFFFFF SSTAT0 Interrupt set status [6:0] RESERVED Reserved [31:7] CLR_EN1 Interrupt 1 mask clear enable. 0x0F20 write-only 0x00000000 0xFFFFFFFF CEN1 Interrupt clear enable [29:0] RESERVED Reserved [31:30] SET_EN1 Interrupt 1 mask set enable 0x0F24 write-only 0x00000000 0xFFFFFFFF SEN1 Interrupt set enable [29:0] RESERVED Reserved [31:30] MASK1 Interrupt 1 mask 0x0F28 read-only 0x00000000 0xFFFFFFFF M1 Interrupt enable [29:0] RESERVED Reserved [31:30] STATUS1 Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun. 0x0F2C read-only 0x00000000 0xFFFFFFFF THCMP_BRANGE0 Input channel 0 result below range [0:0] THCMP_ARANGE0 Input channel 0 result above range [1:1] THCMP_DCROSS0 Input channel 0 result downward threshold crossing detected [2:2] THCMP_UCROSS0 Input channel 0 result upward threshold crossing detected [3:3] OVERRUN_0 A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [0] before it has been read [4:4] THCMP_BRANGE1 Input channel 1 result below range [5:5] THCMP_ARANGE1 Input channel 1 result above range [6:6] THCMP_DCROSS1 Input channel 1 result downward threshold crossing detected [7:7] THCMP_UCROSS1 Input channel 1 result upward threshold crossing detected [8:8] OVERRUN_1 A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [1] before it has been read [9:9] THCMP_BRANGE2 Input channel 2 result below range [10:10] THCMP_ARANGE2 Input channel 2 result above range [11:11] THCMP_DCROSS2 Input channel 2 result downward threshold crossing detected [12:12] THCMP_UCROSS2 Input channel 2 result upward threshold crossing detected [13:13] OVERRUN_2 A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [2] before it has been read [14:14] THCMP_BRANGE3 Input channel 3 result below range [15:15] THCMP_ARANGE3 Input channel 3 result above range [16:16] THCMP_DCROSS3 Input channel 3 result downward threshold crossing detected [17:17] THCMP_UCROSS3 Input channel 3 result upward threshold crossing detected [18:18] OVERRUN_3 A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [3] before it has been read [19:19] THCMP_BRANGE4 Input channel 4 result below range [20:20] THCMP_ARANGE4 Input channel 4 result above range [21:21] THCMP_DCROSS4 Input channel 4 result downward threshold crossing detected [22:22] THCMP_UCROSS4 Input channel 4 result upward threshold crossing detected [23:23] OVERRUN_4 A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [4] before it has been read [24:24] THCMP_BRANGE5 Input channel 5 result below range [25:25] THCMP_ARANGE5 Input channel 5 result above range [26:26] THCMP_DCROSS5 Input channel 5 result downward threshold crossing detected [27:27] THCMP_UCROSS5 Input channel 5 result upward threshold crossing detected [28:28] OVERRUN_5 A new conversion on channel m completed and has overwritten the previous contents of register LAST_SAMPLE [5] before it has been read [29:29] RESERVED Reserved. [31:30] CLR_STAT1 Interrupt 1 clear status 0x0F30 write-only 0x00000000 0xFFFFFFFF CSTAT1 Interrupt clear status [29:0] RESERVED Reserved. [31:30] SET_STAT1 Interrupt 1 set status 0x0F34 write-only 0x00000000 0xFFFFFFFF SSTAT1 Interrupt set status [29:0] RESERVED Reserved. [31:30] GPIO_PORT GPIO port GPIO_PORT 0x400F4000 0 0xFfFFF registers 256 0x1 0-255 B[%s] Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 0x0000 8 read-write 0 0xFF PBYTE Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit. [0:0] 256 0x4 0-255 W[%s] Word pin registers port 0 to 5 0x1000 read-write 0 0xFFFFFFFF PWORD Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. [31:0] 8 0x4 0-7 DIR%s Direction registers port m 0x2000 read-write 0 0xFFFFFFFF DIRP0 Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [0:0] DIRP1 Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [1:1] DIRP2 Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [2:2] DIRP3 Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [3:3] DIRP4 Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [4:4] DIRP5 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [5:5] DIRP6 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [6:6] DIRP7 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [7:7] DIRP8 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [8:8] DIRP9 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [9:9] DIRP10 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [10:10] DIRP11 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [11:11] DIRP12 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [12:12] DIRP13 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [13:13] DIRP14 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [14:14] DIRP15 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [15:15] DIRP16 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [16:16] DIRP17 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [17:17] DIRP18 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [18:18] DIRP19 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [19:19] DIRP20 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [20:20] DIRP21 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [21:21] DIRP22 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [22:22] DIRP23 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [23:23] DIRP24 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [24:24] DIRP25 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [25:25] DIRP26 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [26:26] DIRP27 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [27:27] DIRP28 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [28:28] DIRP29 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [29:29] DIRP30 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [30:30] DIRP31 Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output. [31:31] 8 0x4 0-7 MASK%s Mask register port m 0x2080 read-write 0 0xFFFFFFFF MASKP0 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [0:0] MASKP1 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [1:1] MASKP2 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [2:2] MASKP3 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [3:3] MASKP4 Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [4:4] MASKP5 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [5:5] MASKP6 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [6:6] MASKP7 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [7:7] MASKP8 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [8:8] MASKP9 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [9:9] MASKP10 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [10:10] MASKP11 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [11:11] MASKP12 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [12:12] MASKP13 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [13:13] MASKP14 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [14:14] MASKP15 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [15:15] MASKP16 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [16:16] MASKP17 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [17:17] MASKP18 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [18:18] MASKP19 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [19:19] MASKP20 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [20:20] MASKP21 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [21:21] MASKP22 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [22:22] MASKP23 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [23:23] MASKP24 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [24:24] MASKP25 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [25:25] MASKP26 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [26:26] MASKP27 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [27:27] MASKP28 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [28:28] MASKP29 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [29:29] MASKP30 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [30:30] MASKP31 Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. [31:31] 8 0x4 0-7 PIN%s Port pin register port m 0x2100 read-write 0 0xFFFFFFFF PORT0 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [0:0] PORT1 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [1:1] PORT2 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [2:2] PORT3 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [3:3] PORT4 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [4:4] PORT5 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [5:5] PORT6 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [6:6] PORT7 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [7:7] PORT8 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [8:8] PORT9 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [9:9] PORT10 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [10:10] PORT11 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [11:11] PORT12 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [12:12] PORT13 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [13:13] PORT14 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [14:14] PORT15 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [15:15] PORT16 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [16:16] PORT17 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [17:17] PORT18 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [18:18] PORT19 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [19:19] PORT20 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [20:20] PORT21 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [21:21] PORT22 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [22:22] PORT23 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [23:23] PORT24 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [24:24] PORT25 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [25:25] PORT26 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [26:26] PORT27 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [27:27] PORT28 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [28:28] PORT29 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [29:29] PORT30 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [30:30] PORT31 Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. [31:31] 8 0x4 0-7 MPIN%s Masked port register port m 0x2180 read-write 0 0xFFFFFFFF MPORTP0 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [0:0] MPORTP1 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [1:1] MPORTP2 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [2:2] MPORTP3 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [3:3] MPORTP4 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [4:4] MPORTP5 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [5:5] MPORTP6 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [6:6] MPORTP7 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [7:7] MPORTP8 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [8:8] MPORTP9 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [9:9] MPORTP10 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [10:10] MPORTP11 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [11:11] MPORTP12 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [12:12] MPORTP13 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [13:13] MPORTP14 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [14:14] MPORTP15 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [15:15] MPORTP16 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [16:16] MPORTP17 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [17:17] MPORTP18 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [18:18] MPORTP19 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [19:19] MPORTP20 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [20:20] MPORTP21 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [21:21] MPORTP22 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [22:22] MPORTP23 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [23:23] MPORTP24 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [24:24] MPORTP25 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [25:25] MPORTP26 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [26:26] MPORTP27 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [27:27] MPORTP28 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [28:28] MPORTP29 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [29:29] MPORTP30 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [30:30] MPORTP31 Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. [31:31] 8 0x4 0-7 SET%s Write: Set register for port m Read: output bits for port m 0x2200 read-write 0 0xFFFFFFFF SETP0 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [0:0] SETP1 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [1:1] SETP2 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [2:2] SETP3 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [3:3] SETP4 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [4:4] SETP5 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [5:5] SETP6 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [6:6] SETP7 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [7:7] SETP8 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [8:8] SETP9 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [9:9] SETP10 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [10:10] SETP11 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [11:11] SETP12 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [12:12] SETP13 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [13:13] SETP14 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [14:14] SETP15 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [15:15] SETP16 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [16:16] SETP17 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [17:17] SETP18 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [18:18] SETP19 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [19:19] SETP20 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [20:20] SETP21 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [21:21] SETP22 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [22:22] SETP23 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [23:23] SETP24 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [24:24] SETP25 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [25:25] SETP26 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [26:26] SETP27 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [27:27] SETP28 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [28:28] SETP29 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [29:29] SETP30 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [30:30] SETP31 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. [31:31] 8 0x4 0-7 CLR%s Clear port m 0x2280 write-only 0 0x00000000 CLRP00 Clear output bits: 0 = No operation. 1 = Clear output bit. [0:0] CLRP01 Clear output bits: 0 = No operation. 1 = Clear output bit. [1:1] CLRP02 Clear output bits: 0 = No operation. 1 = Clear output bit. [2:2] CLRP03 Clear output bits: 0 = No operation. 1 = Clear output bit. [3:3] CLRP04 Clear output bits: 0 = No operation. 1 = Clear output bit. [4:4] CLRP05 Clear output bits: 0 = No operation. 1 = Clear output bit. [5:5] CLRP06 Clear output bits: 0 = No operation. 1 = Clear output bit. [6:6] CLRP07 Clear output bits: 0 = No operation. 1 = Clear output bit. [7:7] CLRP08 Clear output bits: 0 = No operation. 1 = Clear output bit. [8:8] CLRP09 Clear output bits: 0 = No operation. 1 = Clear output bit. [9:9] CLRP010 Clear output bits: 0 = No operation. 1 = Clear output bit. [10:10] CLRP011 Clear output bits: 0 = No operation. 1 = Clear output bit. [11:11] CLRP012 Clear output bits: 0 = No operation. 1 = Clear output bit. [12:12] CLRP013 Clear output bits: 0 = No operation. 1 = Clear output bit. [13:13] CLRP014 Clear output bits: 0 = No operation. 1 = Clear output bit. [14:14] CLRP015 Clear output bits: 0 = No operation. 1 = Clear output bit. [15:15] CLRP016 Clear output bits: 0 = No operation. 1 = Clear output bit. [16:16] CLRP017 Clear output bits: 0 = No operation. 1 = Clear output bit. [17:17] CLRP018 Clear output bits: 0 = No operation. 1 = Clear output bit. [18:18] CLRP019 Clear output bits: 0 = No operation. 1 = Clear output bit. [19:19] CLRP020 Clear output bits: 0 = No operation. 1 = Clear output bit. [20:20] CLRP021 Clear output bits: 0 = No operation. 1 = Clear output bit. [21:21] CLRP022 Clear output bits: 0 = No operation. 1 = Clear output bit. [22:22] CLRP023 Clear output bits: 0 = No operation. 1 = Clear output bit. [23:23] CLRP024 Clear output bits: 0 = No operation. 1 = Clear output bit. [24:24] CLRP025 Clear output bits: 0 = No operation. 1 = Clear output bit. [25:25] CLRP026 Clear output bits: 0 = No operation. 1 = Clear output bit. [26:26] CLRP027 Clear output bits: 0 = No operation. 1 = Clear output bit. [27:27] CLRP028 Clear output bits: 0 = No operation. 1 = Clear output bit. [28:28] CLRP029 Clear output bits: 0 = No operation. 1 = Clear output bit. [29:29] CLRP030 Clear output bits: 0 = No operation. 1 = Clear output bit. [30:30] CLRP031 Clear output bits: 0 = No operation. 1 = Clear output bit. [31:31] 8 0x4 0-7 NOT%s Toggle port m 0x2300 write-only 0 0x00000000 NOTP0 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [0:0] NOTP1 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [1:1] NOTP2 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [2:2] NOTP3 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [3:3] NOTP4 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [4:4] NOTP5 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [5:5] NOTP6 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [6:6] NOTP7 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [7:7] NOTP8 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [8:8] NOTP9 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [9:9] NOTP10 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [10:10] NOTP11 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [11:11] NOTP12 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [12:12] NOTP13 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [13:13] NOTP14 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [14:14] NOTP15 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [15:15] NOTP16 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [16:16] NOTP17 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [17:17] NOTP18 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [18:18] NOTP19 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [19:19] NOTP20 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [20:20] NOTP21 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [21:21] NOTP22 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [22:22] NOTP23 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [23:23] NOTP24 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [24:24] NOTP25 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [25:25] NOTP26 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [26:26] NOTP27 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [27:27] NOTP28 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [28:28] NOTP29 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [29:29] NOTP30 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [30:30] NOTP31 Toggle output bits: 0 = no operation. 1 = Toggle output bit. [31:31] SPI SPI SPI 0x40100000 0x0 0xFFF registers SPI_INT 20 CR SPI Control Register. This register controls the operation of the SPI. 0x000 read-write 0x00 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [1:0] BITENABLE The SPI controller sends and receives 8 bits of data per transfer. [2:2] ENUM THE_SPI_CONTROLLER_S The SPI controller sends and receives the number of bits selected by bits 11:8. 1 CPHA Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending. [3:3] ENUM FIRST_EDGE Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal. 0 SECOND_EDGE Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active. 1 CPOL Clock polarity control. [4:4] ENUM SCK_IS_ACTIVE_HIGH_ SCK is active high. 0 SCK_IS_ACTIVE_LOW_ SCK is active low. 1 MSTR Master mode select. [5:5] ENUM SLAVE The SPI operates in Slave mode. 0 MASTER The SPI operates in Master mode. 1 LSBF LSB First controls which direction each byte is shifted when transferred. [6:6] ENUM MSB SPI data is transferred MSB (bit 7) first. 0 LSB SPI data is transferred LSB (bit 0) first. 1 SPIE Serial peripheral interrupt enable. [7:7] ENUM INTBLOCK SPI interrupts are inhibited. 0 HWINT A hardware interrupt is generated each time the SPIF or MODF bits are activated. 1 BITS When bit 2 of this register is 1, this field controls the number of bits per transfer: [11:8] ENUM 8_BITS_PER_TRANSFER 8 bits per transfer 0x8 9_BITS_PER_TRANSFER 9 bits per transfer 0x9 10_BITS_PER_TRANSFER 10 bits per transfer 0xA 11_BITS_PER_TRANSFER 11 bits per transfer 0xB 12_BITS_PER_TRANSFER 12 bits per transfer 0xC 13_BITS_PER_TRANSFER 13 bits per transfer 0xD 14_BITS_PER_TRANSFER 14 bits per transfer 0xE 15_BITS_PER_TRANSFER 15 bits per transfer 0xF 16_BITS_PER_TRANSFER 16 bits per transfer 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:12] SR SPI Status Register. This register shows the status of the SPI. 0x004 read-only 0x00 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [2:0] ABRT Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register. [3:3] MODF Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register. [4:4] ROVR Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register. [5:5] WCOL Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register. [6:6] SPIF SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register. [7:7] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] DR SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. 0x008 read-write 0x00 0xFFFFFFFF modify DATALOW SPI Bi-directional data port. [7:0] DATAHIGH If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes. [15:8] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:16] CCR SPI Clock Counter Register. This register controls the frequency of a master's SCK0. 0x00C read-write 0x00 0xFFFFFFFF COUNTER SPI0 Clock counter setting. [7:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] TCR SPI Test Control register. For functional testing only. 0x010 read-write 0x00 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [0:0] TEST SPI test mode. When 0, the SPI operates normally. When 1, SCK will always be on, independent of master mode select and data availability setting. [7:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] TSR SPI Test Status register. For functional testing only. 0x014 read-write 0x00 0xFFFFFFFF RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [2:0] ABRT Slave abort. [3:3] MODF Mode fault. [4:4] ROVR Read overrun. [5:5] WCOL Write collision. [6:6] SPIF SPI transfer complete flag. [7:7] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] INT SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. 0x01C read-write 0x00 0xFFFFFFFF SPIF SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software. [0:0] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [7:1] RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. [31:8] SGPIO Serial GPIO (SGPIO) SGPIO 0x40101000 0x0 0xFFF registers SGPIO_IINT 31 16 0x4 0-15 OUT_MUX_CFG[%s] Pin multiplexer configuration registers. 0x0000 read-write 0 0xFFFFFFFF P_OUT_CFG Output control of output SGPIOn. All other values are reserved. [3:0] ENUM DOUT_DOUTM1 dout_doutm1 (1-bit mode) 0x0 DOUT_DOUTM2A dout_doutm2a (2-bit mode 2a) 0x1 DOUT_DOUTM2B dout_doutm2b (2-bit mode 2b) 0x2 DOUT_DOUTM2C dout_doutm2c (2-bit mode 2c) 0x3 GPIO_OUT_LEVEL_SET gpio_out (level set by GPIO_OUTREG) 0x4 DOUT_DOUTM4A dout_doutm4a (4-bit mode 4a) 0x5 DOUT_DOUTM4B dout_doutm4b (4-bit mode 4b) 0x6 DOUT_DOUTM4C dout_doutm4c (4-bit mode 4c) 0x7 CLK_OUT clk_out 0x8 DOUT_DOUTM8A dout_doutm8a (8-bit mode 8a) 0x9 DOUT_DOUTM8B dout_doutm8b (8-bit mode 8b) 0xA DOUT_DOUTM8C dout_doutm8c (8-bit mode 8c) 0xB P_OE_CFG Output enable source. All other values are reserved. [6:4] ENUM GPIO_OE_STATE_SET_B gpio_oe (state set by GPIO_OEREG) 0x0 DOUT_OEM1_1_BIT_MOD dout_oem1 (1-bit mode) 0x4 DOUT_OEM2_2_BIT_MOD dout_oem2 (2-bit mode) 0x5 DOUT_OEM4_4_BIT_MOD dout_oem4 (4-bit mode) 0x6 DOUT_OEM8_8_BIT_MOD dout_oem8 (8-bit mode) 0x7 RESERVED Reserved. [31:7] 16 0x4 0-15 SGPIO_MUX_CFG[%s] SGPIO multiplexer configuration registers. 0x0040 read-write 0 0xFFFFFFFF EXT_CLK_ENABLE Select clock signal. [0:0] ENUM INTERNAL_CLOCK_SIGNA Internal clock signal (slice) 0x0 EXTERNAL_CLOCK_SIGNA External clock signal (pin) 0x1 CLK_SOURCE_PIN_MODE Select source clock pin. [2:1] ENUM SGPIO8 SGPIO8 0x0 SGPIO9 SGPIO9 0x1 SGPIO10 SGPIO10 0x2 SGPIO11 SGPIO11 0x3 CLK_SOURCE_SLICE_MODE Select clock source slice. Note that slices D, H, O and P do not support this mode. [4:3] ENUM SLICE_D Slice D 0x0 SLICE_H Slice H 0x1 SLICE_O Slice O 0x2 SLICE_P Slice P 0x3 QUALIFIER_MODE Select qualifier mode. [6:5] ENUM ENABLE Enable 0x0 DISABLE Disable 0x1 SLICE_SEE_BITS_QUAL Slice (see bits QUALIFIER_SLICE_MODE in this register) 0x2 EXTERNAL_SGPIO_PIN External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11) 0x3 QUALIFIER_PIN_MODE Select qualifier pin. [8:7] ENUM SGPIO8 SGPIO8 0x0 SGPIO9 SGPIO9 0x1 SGPIO10 SGPIO10 0x2 SGPIO11 SGPIO11 0x3 QUALIFIER_SLICE_MODE Select qualifier slice. [10:9] ENUM SLICE_A Slice A, but for slice A slice D is used. 0x0 SLICE_H Slice H, but for slice H slice O is used. 0x1 SLICE_I Slice I, but for slice I slice D is used. 0x2 SLICE_P Slice P, but for slice P slice O is used. 0x3 CONCAT_ENABLE Enable concatenation. [11:11] ENUM EXTERNAL_DATA_PIN External data pin 0x0 CONCATENATE_DATA Concatenate data 0x1 CONCAT_ORDER Select concatenation order [13:12] ENUM SELF_LOOP Self-loop 0x0 2_SLICES 2 slices 0x1 4_SLICES 4 slices 0x2 8_SLICES 8 slices 0x3 RESERVED Reserved [31:14] 16 0x4 0-15 SLICE_MUX_CFG[%s] Slice multiplexer configuration registers. 0x0080 read-write 0 0xFFFFFFFF MATCH_MODE Match mode. Selects whether the match filter is active or whether data is captured. [0:0] ENUM DO_NOT_MATCH_DATA Do not match data. 0x0 MATCH_DATA Match data. 0x1 CLK_CAPTURE_MODE Capture clock mode [1:1] ENUM USE_RISING_CLOCK_EDG Use rising clock edge. 0x0 USE_FALLING_CLOCK_ED Use falling clock edge. 0x1 CLKGEN_MODE Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock. [2:2] ENUM USE_CLOCK_INTERNALLY Use clock internally generated by COUNTER. 0x0 USE_EXTERNAL_CLOCK_F Use external clock from a pin or other slice. 0x1 INV_OUT_CLK Invert output clock [3:3] ENUM NORMAL_CLOCK Normal clock. 0x0 INVERTED_CLOCK Inverted clock. 0x1 DATA_CAPTURE_MODE Condition for input bit match interrupt [5:4] ENUM DETECT_RISING_EDGE Detect rising edge. 0x0 DETECT_FALLING_EDGE Detect falling edge. 0x1 DETECT_LOW_LEVEL Detect LOW level. 0x2 DETECT_HIGH_LEVEL Detect HIGH level. 0x3 PARALLEL_MODE Parallel mode [7:6] ENUM SHIFT_1_BIT_PER_CLOC Shift 1 bit per clock. 0x0 SHIFT_2_BITS_PER_CLO Shift 2 bits per clock. 0x1 SHIFT_4_BITS_PER_CLO Shift 4 bits per clock. 0x2 SHIFT_1_BYTE_PER_CLO Shift 1 byte per clock. 0x3 INV_QUALIFIER Inversion qualifier [8:8] ENUM USE_NORMAL_QUALIFIER Use normal qualifier. 0x0 USE_INVERTED_QUALIFI Use inverted qualifier. 0x1 RESERVED Reserved. [31:9] 16 0x4 0-15 REG[%s] Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0) 0x00C0 read-write 0 0xFFFFFFFF REG At each active shift clock the register shifts right; loading REG(31) with data captured from DIN(n) and DOUT(n) is set to REG(0). [31:0] 16 0x4 0-15 REG_SS[%s] Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG 0x0100 read-write 0 0xFFFFFFFF REG_SS Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG. [31:0] 16 0x4 0-15 PRESET[%s] Reload value of COUNT0, loaded when COUNT0 reaches 0x0 0x0140 read-write 0 0xFFFFFFFF PRESET Counter reload value; loaded when COUNT reaches 0x0. [11:0] RESERVED Reserved. [31:12] 16 0x4 0-15 COUNT[%s] Down counter, counts down each clock cycle. 0x0180 read-write 0 0xFFFFFFFF COUNT Down counter, counts down each shift clock cycle. Next count after 0x0 is PRESET. [11:0] RESERVED Reserved. [31:12] 16 0x4 0-15 POS[%s] Each time COUNT0 reaches 0x0 POS counts down. 0x01C0 read-write 0 0xFFFFFFFF POS Each time COUNT reaches 0x0 POS counts down. [7:0] POS_RESET Reload value for POS after POS reaches 0x0. [15:8] RESERVED Reserved. [31:16] MASK_A Mask for pattern match function of slice A 0x0200 read-write 0 0xFFFFFFFF MASK_A Mask for pattern match function of slice A 0 = No effect. 1 = Mask this bit. [31:0] MASK_H Mask for pattern match function of slice H 0x0204 read-write 0 0xFFFFFFFF MASK_H Mask for pattern match function of slice H 0 = No effect. 1 = Mask this bit. [31:0] MASK_I Mask for pattern match function of slice I 0x0208 read-write 0 0xFFFFFFFF MASK_I Mask for pattern match function of slice I 0 = No effect . 1 = Mask this bit. [31:0] MASK_P Mask for pattern match function of slice P 0x020C read-write 0 0xFFFFFFFF MASK_P Mask for pattern match function of slice P 0 = No effect. 1 = Mask this bit. [31:0] GPIO_INREG GPIO input status register 0x0210 read-only 0 0xFFFFFFFF GPIO_INi Bit i reflects the input state of SGPIO pin i . 0 = LOW 1 = HIGH [15:0] RESERVED Reserved. [31:16] GPIO_OUTREG GPIO output control register 0x0214 read-write 0 0xFFFFFFFF GPIO_OUT GPIO output register. Bit i sets the output of SGPIO pin i. 0 = LOW 1 = HIGH [15:0] RESERVED Reserved. [31:16] GPIO_OENREG GPIO OE control register 0x0218 read-write 0 0xFFFFFFFF GPIO_OE Bit i selects the output enable state of SGPIO pin i. 0 = GPIO output i is tri-stated . 1 = GPIO output i is active. [15:0] RESERVED Reserved. [31:16] CTRL_ENABLE Enables the slice COUNT counter 0x021C read-write 0 0xFFFFFFFF CTRL_EN Slice count enable. Bit n controls slice n (0 = slice A, ..., 15 = slice P). 0 = Disables slice shift clock. 1 = Starts COUNTn or external shift clock. [15:0] RESERVED Reserved. [31:16] CTRL_DISABLE Disables the slice POS counter 0x0220 read-write 0 0xFFFFFFFF CTRL_DIS Slice count disable. Bit n controls slice n, (0 = slice A, ..., 15 = slice P). 0 = Enables COUNT and POS counters. The counters start counting when the CTRL_EN bit or bits are set in the CTRL_ENABLED register. 1 = Disables POS counter of slice n. [15:0] RESERVED Reserved. [31:16] CLR_EN_0 Shift clock interrupt clear mask 0x0F00 write-only 0 0xFFFFFFFF CLR_SCI 1 = Shift clock interrupt clear mask of slice n. [15:0] RESERVED Reserved. [31:16] SET_EN_0 Shift clock interrupt set mask 0x0F04 write-only 0 0xFFFFFFFF SET_SCI 1 = Shift clock interrupt set mask of slice n. [15:0] RESERVED Reserved. [31:16] ENABLE_0 Shift clock interrupt enable 0x0F08 read-only 0 0xFFFFFFFF ENABLE_SCI 1 = Shift clock interrupt enable of slice n. [15:0] RESERVED Reserved. [31:16] STATUS_0 Shift clock interrupt status 0x0F0C read-only 0 0xFFFFFFFF STATUS_SCI Shift clock interrupt status of slice n. [15:0] RESERVED Reserved. [31:16] CLR_STATUS_0 Shift clock interrupt clear status 0x0F10 write-only 0 0xFFFFFFFF CLR_STATUS_SCI Shift clock interrupt clear status of slice n. [15:0] RESERVED Reserved. [31:16] SET_STATUS_0 Shift clock interrupt set status 0x0F14 write-only 0 0xFFFFFFFF SET_STATUS_SCI Shift clock interrupt set status of slice n. [15:0] RESERVED Reserved. [31:16] CLR_EN_1 Exchange clock interrupt clear mask 0x0F20 write-only 0 0xFFFFFFFF CLR_EN_CCI 1 = Exchange clock interrupt clear mask of slice n. [15:0] RESERVED Reserved. [31:16] SET_EN_1 Exchange clock interrupt set mask 0x0F24 write-only 0 0xFFFFFFFF SET_EN_CCI 1 = Exchange clock interrupt set mask of slice n. [15:0] RESERVED Reserved. [31:16] ENABLE_1 Exchange clock interrupt enable 0x0F28 read-only 0 0xFFFFFFFF ENABLE_CCI Exchange clock interrupt enable of slice n. [15:0] RESERVED Reserved. [31:16] STATUS_1 Exchange clock interrupt status 0x0F2C read-only 0 0xFFFFFFFF STATUS_CCI Exchange clock interrupt status of slice n. [15:0] RESERVED Reserved. [31:16] CLR_STATUS_1 Exchange clock interrupt clear status 0x0F30 write-only 0 0xFFFFFFFF CLR_STATUS_CCI Exchange clock interrupt clear status of slice n. [15:0] RESERVED Reserved. [31:16] SET_STATUS_1 Exchange clock interrupt set status 0x0F34 write-only 0 0xFFFFFFFF SET_STATUS_CCI Exchange clock interrupt set status of slice n. [15:0] RESERVED Reserved. [31:16] CLR_EN_2 Pattern match interrupt clear mask 0x0F40 write-only 0 0xFFFFFFFF CLR_EN2_PMI 1 = Match interrupt clear mask of slice n. [15:0] RESERVED Reserved. [31:16] SET_EN_2 Pattern match interrupt set mask 0x0F44 write-only 0 0xFFFFFFFF SET_EN_PMI 1 = Match interrupt set mask of slice n. [15:0] RESERVED Reserved. [31:16] ENABLE_2 Pattern match interrupt enable 0x0F48 read-only 0 0xFFFFFFFF ENABLE_PMI Match interrupt enable of slice n. [15:0] RESERVED Reserved. [31:16] STATUS_2 Pattern match interrupt status 0x0F4C read-only 0 0xFFFFFFFF STATUS_PMI Match interrupt status of slice n. [15:0] RESERVED Reserved. [31:16] CLR_STATUS_2 Pattern match interrupt clear status 0x0F50 write-only 0 0xFFFFFFFF CLR_STATUS_PMI Match interrupt clear status of slice n. [15:0] RESERVED Reserved. [31:16] SET_STATUS_2 Pattern match interrupt set status 0x0F54 write-only 0 0xFFFFFFFF SET_STATUS_PMI Match interrupt set status of slice n. [15:0] RESERVED Reserved. [31:16] CLR_EN_3 Input interrupt clear mask 0x0F60 write-only 0 0xFFFFFFFF CLR_EN_INPI 1 = Input interrupt clear mask of slice n. [15:0] RESERVED Reserved. [31:16] SET_EN_3 Input bit match interrupt set mask 0x0F64 write-only 0 0xFFFFFFFF SET_EN_INPI 1 = Input interrupt set mask of slice n. [15:0] RESERVED Reserved. [31:16] ENABLE_3 Input bit match interrupt enable 0x0F68 read-only 0 0xFFFFFFFF ENABLE3_INPI Input interrupt enable of slice n. [15:0] RESERVED Reserved. [31:16] STATUS_3 Input bit match interrupt status 0x0F6C read-only 0 0xFFFFFFFF STATUS_INPI Input interrupt status of slice n. [15:0] RESERVED Reserved. [31:16] CLR_STATUS_3 Input bit match interrupt clear status 0x0F70 write-only 0 0xFFFFFFFF CLR_STATUS_INPI Input interrupt clear status of slice n. [15:0] RESERVED Reserved. [31:16] SET_STATUS_3 Input bit match interrupt set status 0x0F74 write-only 0 0xFFFFFFFF SET_STATUS_INPI Shift interrupt set status of slice n. [15:0] RESERVED Reserved. [31:16]